A single-path level-controlled RF tri-state switch circuit

Abstract

The application discloses a single-path level control radio frequency tri-state switch circuit, and belongs to the technical field of radio frequency microwave switch and PIN diode bias control. The scheme is as follows: three states of conduction, matching absorption off and high resistance isolation are selected by one analog control voltage; the main path adopts PIN diodes in common cathode reverse series, double constant current power supply, independent forward backflow and fast discharge clamping; the terminal path adopts port terminal PIN diode and terminal isolation PIN diode and applies hierarchical reverse bias; the main path, terminal port and terminal isolation recovery current are detected through three sampling channels, and recovery signal reconstruction, displacement current compensation, trend discrimination and continuous confirmation are combined to control each branch to be off first and then on. The application realizes the technical effects of reducing control ports, improving tri-state switching speed and recovery judgment accuracy, and withdrawing forward driving when the control end is open circuit, under-voltage, illegal code or timeout, and improving safety in abnormal state.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microwave switch and PIN diode bias control technology, specifically involving a single-channel level controlled radio frequency three-state switch circuit. It uses one analog control voltage to select three states: radio frequency conduction, matching absorption turn-off, and reflective high-impedance isolation, and determines the conduction time of the target branch based on the actual reverse recovery current of the original conduction PIN branch. Background Technology

[0002] Existing PIN diode RF switches typically utilize series-connected PIN diodes to form the switching path, or combine series and parallel PIN diodes to improve isolation. Documents such as US4883984A disclose series or parallel PIN diodes, RF choke inductors, bias resistors, and DC blocking capacitors; window comparators have also been used to identify input voltage ranges based on two threshold values. Therefore, simply connecting a standard window comparator to a standard PIN diode switch usually only reduces the number of control ports.

[0003] Traditional absorption switches typically connect the RF port to the matching terminal when off, while reflective switches present a high impedance port when off. Existing solutions usually only provide one type of turn-off impedance, or require multiple digital control terminals to select the state separately. Meanwhile, when a PIN diode switches from forward conduction to reverse cutoff, it needs to extract the stored charge in its I-region; the recovery time varies with forward current, carrier lifetime, temperature, and device variability. A fixed RC dead time that is too short will cause overlapping conduction between the main path and the terminal path, while a time that is too long will reduce the switching speed.

[0004] Furthermore, if the reverse current is measured directly in the RFC bias circuit, the RFC charging / discharging and PIN junction capacitance displacement currents will be superimposed on the carrier recovery current. If the main and terminal branches share a differential input, the measured current difference may be the result. Especially in the terminal branch, the reverse recovery currents of the port terminal PIN diodes 185 and 186 and the terminal isolation PIN diode 187 may be in opposite directions on the terminal common return path. When only one sampling resistor is set, the two cancel each other out, which may cause the detection signal to exceed the recovery threshold prematurely. If the existing recovery detection only uses a uniform empirical threshold, it is difficult to take into account the zero point, reverse leakage current, and gain dispersion of each detection channel. If a calibration current is injected into the sampling circuit during operation, a calibration current source, channel selection, and interlocking deactivation are required, increasing circuit complexity and potentially interfering with state switching. Therefore, an RF tri-state switching circuit with a clear forward bias return current and fast discharge topology, separate terminal ports and terminal isolation sampling, a safe recovery threshold set based on preset or factory debugging parameters, and recovery current reconstruction and fault safety control is needed. Summary of the Invention

[0005] The technical problem to be solved by this invention is: to enable the same PIN diode RF network to select RF conduction, matched absorption turn-off and reflective high-impedance isolation states when using only one analog control voltage, to adaptively end the non-overlapping period according to the actual reverse recovery state of the original conducting PIN branch, to avoid RFC displacement current, detection channel zero point and gain dispersion, mutual cancellation of different recovery currents at the terminal and false authorization caused by abnormal control, and to form a clear recovery threshold constrained by safe recovery current without setting a calibration branch during operation.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A single-channel level-controlled radio frequency tri-state switch circuit includes a single-channel control input and protection unit, a dual-threshold reference unit, a window code unit, a fault-safe interlock unit, an adaptive non-overlapping control unit, a main branch bipolar drive unit, a terminal branch bipolar drive unit, a PIN diode radio frequency network, and a radio frequency DC blocking choke network. The PIN diode RF network includes a first series PIN diode, a second series PIN diode, an input terminal PIN diode, an output terminal PIN diode, a terminal isolation PIN diode, an input matching terminal, and an output matching terminal; The first and second series PIN diodes are connected in reverse series between the RF input node and the RF output node in a common cathode manner to form a common cathode node; the main branch forward constant current source includes two restricted constant current output branches that are respectively connected to the two RF nodes, and the common cathode node is connected to the main forward return terminal via the main branch forward return switch; the two RF nodes are respectively connected to the first RF bypass node and the second RF bypass node via corresponding matching terminals and port terminal PIN diodes, and the two RF bypass nodes are respectively connected to RF ground through the first absorption capacitor and the second absorption capacitor and converge to the terminal common return node through mutually isolated DC return branches; the anode of the terminal isolation PIN diode is connected to the terminal common return node, and the cathode is connected to the switchable terminal isolation drive terminal; The window code unit outputs mutually exclusive on-state requests, matched absorption off-state requests, and high-impedance isolation state requests based on one analog control voltage output. In the on state, the two main constant current output branches supply current to the two RF nodes respectively. The main branch forward return switch connects the common cathode node to the main forward return terminal, and the two series PIN diodes respectively obtain the specified forward current. At the same time, the terminal common return node and the terminal isolation drive terminal are respectively placed at the first terminal reverse bias potential and the higher second terminal reverse bias potential, so that all three terminal PIN diodes are reverse biased. In the matched absorption off state, the two RF nodes are continuously connected to the main reverse bias low potential return terminal by the main branch fast discharge clamping switch network, and the common cathode node is given a higher main reverse bias potential by the main branch reverse bias switch, thereby reversing the two series PIN diodes; the terminal branch forward constant current unit draws a limited constant current from the cathode side of the two port terminal PIN diodes through the terminal isolation PIN diode, so that the three terminal PIN diodes are forward biased, and the two RF nodes are respectively connected to the RF ground through the corresponding matched terminals; In the high-impedance isolation state, the main branch maintains the aforementioned main reverse bias, the terminal common return node is placed at the first terminal reverse bias potential, and the terminal isolation drive terminal is placed at the second terminal reverse bias potential higher than the first terminal reverse bias potential, so that all five PIN diodes are reverse biased; the main reverse bias satisfies VRS-V0S-ΔV_S,path≥VREV_S,min, the port terminal branch reverse bias satisfies VRA1-max(VNA_DC,VNC_DC)-ΔV_AP,path≥VREV_AP,min, and the terminal isolation branch reverse bias satisfies VRA2-VRA1-ΔV_AI,path≥VREV_AI,min; where ΔV_S,path, ΔV_AP,path and ΔV_AI,path are the worst-case path voltage drops of the corresponding switches, sampling resistors, damping resistors and choke inductors, and each actual reverse bias voltage is also lower than the minimum reverse breakdown voltage of the corresponding PIN diode minus the safety margin; The adaptive non-overlapping control unit includes a main branch sampling resistor, a terminal branch sampling resistor group consisting of a terminal port recovery sampling resistor and a terminal isolation recovery sampling resistor, a three-channel differential detection and recovery reconstruction circuit, a baseline correction threshold circuit, a recovery comparison circuit, a confirmation timer, and a drive permission gate. The baseline correction threshold circuit sets the recovery thresholds for the main branch, terminal port, and terminal isolation respectively based on the zero current baseline obtained or preset by each detection channel in the high-impedance isolation state, the effective transimpedance coefficient preset or determined by factory debugging, and the corresponding safe recovery current. The remaining recovery current corresponding to each threshold does not exceed the corresponding maximum allowable overlap current, and there is no need to inject calibration current into the sampling resistor during operation. The main branch sampling resistor is used to obtain the original detection voltage VS of the main branch; the terminal port recovery sampling resistor is located in the path from the first terminal reverse bias power supply to the terminal common return node and outputs VAP; the terminal isolation recovery sampling resistor is located in the path from the second terminal reverse bias power supply to the cathode of the terminal isolation PIN diode and outputs VAI. VAP and VAI are added after polarity and gain normalization to form VA_PORT, which is used to characterize the remaining recovery current of the two port terminal PIN diodes. VAI is normalized to form VA_ISO, which is used to characterize the remaining recovery current of the terminal isolation PIN diode, thereby avoiding the reverse component caused by the terminal isolation recovery current on the common return path from canceling the port terminal recovery current. When the state before the transition is the on state, the recovery blanking and compensation network subtracts the corresponding displacement current reference from the main branch detection signal. Recovery permission is only generated after the main branch compensation recovery signal continuously meets the recovery threshold condition. When the state before the transition is the matched absorption off state, the recovery blanking and compensation network compensates the terminal port path and the terminal isolation path respectively. Recovery permission is only generated after the reconstructed port compensation recovery signal and the independent isolation compensation recovery signal continuously meet their respective threshold conditions. When setting the recovery trend discrimination circuit, the corresponding trend result is also hardware ANDed with the real-time threshold result. When the state before the transition is high-impedance isolation, the target branch is allowed to sequentially cancel reverse bias, pass through the commutation dead zone, and establish positive bias only after the VS, VAP, and VAI without recovery compensation are all in their respective zero-current baseline windows and have been continuously maintained for the confirmation time. When the control terminal is open, the control input node enters the middle zone between the lower threshold and the upper threshold and requests high-impedance isolation. When the bias power supply is undervoltage, the code signal is illegal, or the recovery wait timeout occurs, the main branch and the terminal branch are prohibited from establishing positive bias.

[0007] As a further improvement to the above solution, the single-channel control input and protection unit includes control terminals, input current limiting resistors, low-capacitance clamping networks, and open-circuit bias resistors. The co-source dual threshold reference unit includes a reference source, a lower threshold voltage divider network, an upper threshold voltage divider network, a lower threshold buffer, and an upper threshold buffer; an open-circuit bias resistor is connected between the control input node and the intermediate bias node jointly generated by the lower threshold voltage divider network and the upper threshold voltage divider network, so that when the control terminal is open, the control input node is stably between the lower threshold and the upper threshold; the resistance value of the open-circuit bias resistor is at least twenty times the resistance value of the input current limiting resistor.

[0008] As a further improvement to the above scheme, the window code unit includes a lower threshold comparator, an upper threshold comparator, a lower threshold hysteresis network, an upper threshold hysteresis network, a mutex code, and acknowledgment logic. The fail-safe interlock unit includes a power monitor, a fault latch, and a mutual exclusion gate. The mutex code and confirmation logic include a combination code unit and a code confirmation timing unit. It outputs the corresponding status request only when the output combination of the two comparators is a valid combination in the low zone, a valid combination in the middle zone, or a valid combination in the high zone and is continuously maintained until the code confirmation time is reached. Other output combinations are judged as illegal code combinations. The mutex forcibly cancels the positive drive requests of the main branch and the terminal branch when the power monitor output is invalid, the fault latch is set, or two positive drive requests are valid at the same time.

[0009] As a further improvement to the above scheme, the main branch bipolar drive unit includes a main branch forward constant current source, a main branch reverse bias switch, a main branch fast discharge clamping switch network, a main branch current limiting resistor group, and a main branch forward return switch. The main branch forward constant current source includes a first constant current output branch and a second constant current output branch. These two branches supply forward current to the RF input node and RF output node respectively via the first main branch current-limiting resistor, the second main branch current-limiting resistor, the first RF choke inductor, and the fourth RF choke inductor. The common cathode node is connected to the main forward return terminal via the second RF choke inductor and the main branch forward return switch. The main branch reverse bias switch applies a main reverse bias voltage to the common cathode node via the second RF choke inductor. The main branch fast discharge clamping switch network connects the two RF nodes to the main reverse bias low-potential return terminal via the first RF choke inductor and the fourth RF choke inductor. The main branch forward constant current source and the main branch forward return switch are interlocked with the main branch reverse bias switch and the main branch fast discharge clamping switch network using a first-off-then-on interlock. The terminal branch bipolar drive unit includes a terminal branch forward constant current unit, a terminal branch reverse bias switch, a terminal branch fast discharge commutation switch, and a terminal branch current limiting resistor. The anode of the terminal isolation PIN diode is connected to the terminal common return node, and the cathode is connected to the common terminal of the commutation switch via a third damping resistor. In the matched absorption off state, the terminal branch reverse bias switch is open, and the commutation switch selects the negative power supply constant current absorption terminal connected via the terminal branch current limiting resistor and the terminal branch forward constant current unit, so that the current from the two RF nodes converges from the matched terminal, the port terminal PIN diode, and their respective DC return branches to the terminal common return node, and then flows to the negative power supply via the terminal isolation PIN diode. In the non-absorption state, the terminal branch forward constant current unit is open, the terminal branch reverse bias switch places the terminal common return node at the first terminal reverse bias potential, and the commutation switch places the cathode of the terminal isolation PIN diode at a higher second terminal reverse bias potential. The two connections are switched by first disconnecting and then turning on. The terminal common return node is connected to the main reverse bias low potential return terminal via the first passive discharge resistor, and the terminal isolation drive terminal is connected to the terminal common return node via the second passive discharge resistor, so that the two nodes are not floating in the commutation dead zone when the commutation switch is fully open; the resistance values ​​of the two passive discharge resistors are set so that their steady-state shunt current is much smaller than the terminal forward constant current and allowable recovery current.

[0010] As a further improvement to the above scheme, the radio frequency DC blocking choke network includes an input DC blocking capacitor, an output DC blocking capacitor, and first to sixth radio frequency choke inductors (193 to 198). An input DC blocking capacitor, a first series PIN diode, a second series PIN diode, and an output DC blocking capacitor are connected in series between the RF input port and the RF output port. One end of the input matching terminal is connected to the RF input node, and the other end is connected to the anode of the input terminal PIN diode. The cathode of the input terminal PIN diode is connected to the first RF bypass node. One end of the output matching terminal is connected to the RF output node, and the other end is connected to the anode of the output terminal PIN diode. The cathode of the output terminal PIN diode is connected to the second RF bypass node. The first RF bypass node is connected to the terminal common return node via a first damping resistor and a fifth RF choke inductor. The second RF bypass node is connected to the terminal common return node via a second damping resistor and a sixth RF choke inductor. The two RF bypass nodes are connected to RF ground via a first absorption capacitor and a second absorption capacitor, respectively. The terminal common return node is connected to the terminal common drive terminal via a third RF choke inductor and to the terminal isolation drive terminal, which can switch between the terminal forward constant current absorption terminal and the second terminal reverse bias voltage, via the terminal isolation PIN diode and the third damping resistor. The first passive discharge resistor connects the terminal common return node to the main reverse bias low potential return terminal, and the second passive discharge resistor bridges the terminal isolation drive terminal and the terminal common return node.

[0011] As a further improvement to the above scheme, the main branch sampling resistor is connected in series in the main branch reverse bias circuit; the terminal port recovery sampling resistor is connected in series between the first terminal reverse bias power supply and the terminal common return node, and the terminal isolation recovery sampling resistor is connected in series between the second terminal reverse bias power supply and the terminal isolation PIN diode cathode. Three independent differential detection channels output VS, VAP, and VAI respectively; VAP and VAI are reconstructed after normalization according to preset or factory-determined polarity and gain coefficients, and an independent VA_ISO is retained. When exiting the matched absorption turn-off state, VA_PORT and VA_ISO must respectively meet the corresponding recovery criteria; when entering the target state from the high-impedance state and during fault reset, VS, VAP, and VAI must simultaneously meet their respective baseline window criteria.

[0012] As a further improvement to the above scheme, the adaptive non-overlapping control unit also includes a timeout timer, and the fault-safe interlock unit includes a power monitor and a fault latch. When transitioning from the on-state or matched absorption off-state, the timeout timer starts counting from the moment the original on-branch is removed. When entering the target state from the high-impedance isolation state, the timeout timer starts counting from the moment the target state request is latched. The fault latch is set when no recovery permission signal is received within the maximum waiting time. The fault latch is reset only when the control voltage is in the middle zone, the power monitoring is normal, the timeout signal is invalid, VS, VAP, and VAI are all continuously within their respective zero-current baseline windows for the reset confirmation time, and the reset trigger signal RESET_TRIG is valid. RESET_TRIG is generated by the internal power-on reset or power monitoring circuit, or provided by the maintenance reset terminal that does not participate in the three-state selection.

[0013] As a further improvement to the above scheme, the restoration blanking and compensation network is configured with three sets of displacement current replication branches: a main branch, a terminal port path, and a terminal isolation path. Each replication branch is driven by a control signal synchronized with the corresponding actual reverse bias step, and is matched with the reverse bias step amplitude, source impedance, RF choke inductance, equivalent junction capacitance, and parasitic capacitance. After subtracting the corresponding displacement current reference from the normalized actual detection signal, VCOMP_S, VCOMP_AP, and VCOMP_AI are formed respectively. When exiting the matched absorption turn-off state, VCOMP_AP is formed by adding the compensated terminal port path signal and the compensated terminal isolation path signal, while VCOMP_AI is retained as an independent criterion for the terminal isolation PIN diode. The acknowledgment timer is prohibited from counting during the blanking time.

[0014] As a further improvement to the above scheme, a trend recovery discrimination circuit is also included. This circuit performs dual-time sampling and trend judgment on VCOMP_S when exiting the on-state, and VCOMP_AP and VCOMP_AI when exiting the matched absorption off-state. When the second sampled value is not higher than the sum of the first sampled value and the preset trend hysteresis voltage, and is lower than the corresponding recovery threshold, the corresponding trend valid result is output. When exiting the matched absorption off-state, the comparison results of the two terminal trend valid results and the two terminal real-time thresholds are hardware-based, and a confirmation timer is started or maintained. The confirmation timer is reset when any compensation recovery signal crosses its threshold again. The compensation recovery signals can be sampled in parallel by separately configured sample-and-hold circuits, or they can be sampled time-divisionally by the same group of sample-and-hold circuits under the condition of satisfying the sampling timing via a channel selector.

[0015] Compared with the prior art, the present invention has at least the following beneficial effects: This invention employs a single-channel control input and protection unit, a dual-threshold reference unit, and a window code unit to form three mutually exclusive states—on-state, matched absorption off-state, and high-impedance isolation state—based on a single analog control voltage. This reduces the number of external control ports and control lines, avoids state conflicts caused by asynchronous control signals, and improves the compatibility of the RF switch with existing analog control systems.

[0016] This invention configures the first and second series-connected PIN diodes as a common cathode reverse-connected structure, and sets independent matching absorption branches at the two RF nodes, enabling the same RF network to provide three different RF states: low-loss on, matched absorption off, and high-impedance isolation. Compared with existing RF switches that only have on and a single off state, this invention can select between absorption-type off and reflection-type high-impedance off according to different application scenarios.

[0017] This invention provides a main branch bipolar drive unit and a terminal branch bipolar drive unit, which can apply controlled forward constant current and reverse bias to the main PIN diodes and the terminal PIN diodes, respectively. This structure ensures that the forward conduction circuit, reverse recovery circuit, and reverse cutoff potential of each PIN diode have a defined connection relationship, which helps to reduce the impact of on-resistance and reverse bias junction capacitance on RF performance and avoids state uncertainty caused by floating bias nodes.

[0018] This invention employs two mutually isolated DC return branches at the terminals, and forms RF grounding loops through a first absorption capacitor and a second absorption capacitor, respectively. In the matched absorption off state, the two RF ports can be connected to their respective matched terminals; in the on state and high-impedance isolation state, the terminal branches are reverse-biased in stages, preventing the formation of a continuous DC path from the RF node to the reverse-biased power supply. This achieves a balance between port impedance matching, terminal branch isolation, and DC power consumption control.

[0019] This invention uses the main branch sampling resistor to detect the main branch reverse recovery current, and uses the terminal port recovery sampling resistor and the terminal isolation recovery sampling resistor to obtain the current information of the terminal common return path and the isolation PIN path, respectively. Through polarity and gain normalization and additive reconstruction, the actual recovery current of the two port terminal PIN diodes is recovered, while retaining the independent recovery criterion of the terminal isolation PIN diode, avoiding premature permission due to the cancellation of opposite currents on a single sampling resistor. Compared with switching methods using fixed delay or single-point terminal detection, this invention can determine the target branch conduction time based on the actual recovery state of all previously conducting PIN devices.

[0020] This invention incorporates a baseline correction threshold circuit into the threshold settings. This circuit uses a zero-current baseline obtained or pre-set in a high-impedance isolation state for the three physical detection channels, along with the effective transimpedance coefficient determined by preset or factory debugging, and the corresponding safe recovery current. It also limits the remaining recovery current corresponding to each recovery threshold to not exceeding the maximum allowable overlap current. This solution eliminates the need for a calibration current source and channel selection switch during operation. It simplifies circuitry and state control while reducing the impact of channel offset, reverse leakage, and gain dispersion on recovery determination, and avoids interference from online calibration current injection during normal switching.

[0021] This invention sets up a three-path recovery blanking and compensation network, where each replicated branch is synchronized with the corresponding actual reverse bias step and matched with the step amplitude, source impedance, RF choke inductance, and equivalent capacitance. Thus, the displacement current components in the main branch, terminal port path, and terminal isolation path are respectively deducted, and then the terminal port recovery signal is reconstructed, reducing the interference of compensation mismatch and RFC charging and discharging on the determination of the real carrier recovery.

[0022] The present invention sets up a recovery trend discrimination circuit to sample the main branch compensation recovery signal or the two terminal compensation recovery signals at two time moments respectively; when the matched absorption is turned off, the port terminal recovery trend, the isolation PIN recovery trend and the two real-time amplitude conditions jointly participate in the authorization, thereby eliminating premature conduction caused by ringing, secondary recovery peak or instantaneous threshold overrun of any device.

[0023] This invention uses a confirmation timer to continuously confirm the recovery completion signal, instead of immediately establishing a target positive bias when the detection signal first falls below the threshold. When the detection signal recovers during the confirmation period, the confirmation timer is reset to zero, thereby suppressing false clearances caused by noise spikes, comparator jitter, and recovery tail current fluctuations, and improving the stability of the state transition process.

[0024] This invention uses only one analog control voltage as the control input for three-state selection; the reset trigger signal RESET_TRIG does not participate in the three-state selection and is provided by the internal power-on reset, power monitoring circuit, or maintenance reset terminal. When the control terminal is open-circuited, open-circuit bias is used to put the control input into the middle zone and select the high-impedance isolation state, while setting the power monitor, fault latch, mutex gate, and timeout timer; when the code combination is illegal, the recovery wait timeout occurs, or two positive drive requests occur simultaneously, the circuit cancels the positive drive and enters the active reverse bias high-impedance isolation state when the reverse bias power supply is normal; when the reverse bias power supply is undervoltage, the circuit cancels at least all positive drives and uses passive discharge to put the drive node into a fail-safe state without forward bias. This can avoid simultaneous forward bias of the main branch and the terminal branch and shoot-through between the bias power supplies, improving safety under abnormal control and device failure conditions.

[0025] In summary, this invention, through the coordinated use of a single-channel analog level tri-state code, a PIN diode RF network with two types of turn-off impedances, a complete forward bias return and fast discharge connection, a graded reverse bias relationship, a three-physical-channel reverse recovery detection, a safety threshold setting based on preset or factory-set parameters, terminal recovery current reconstruction, displacement current compensation, trend discrimination, and fault safety interlocking, reduces the number of control ports and improves RF state selection capability, switching speed, recovery detection accuracy, and safety under abnormal conditions without increasing the number of calibration branches injected during operation. Attached Figure Description

[0026] Figure 1 This is a connection diagram of the overall circuit structure of the present invention; Figure 2 for Figure 1 Circuit diagram of single-channel control input and protection unit and dual-threshold reference unit; Figure 3 for Figure 1 Circuit diagram of the middle window code unit and the fault-safe interlock unit; Figure 4 for Figure 1 Circuit diagrams of the main branch bipolar drive unit and the terminal branch bipolar drive unit; Figure 5 for Figure 1 Circuit diagram of PIN diode RF network, RF DC blocking choke network and absorption decoupling network; Figure 6 for Figure 1 Circuit diagram of three physical channels reverse recovery detection, terminal recovery reconstruction and threshold comparison of adaptive non-overlapping control unit; Figure 7 for Figure 1 Circuit diagram of the recovery continuous confirmation, switching timeout and fault reset interlock circuit of the fault-safe interlock unit and the adaptive non-overlapping control unit; Figure 8 for Figure 1 Diagram of a three-path displacement current replication compensation and recovery detection blanking circuit for a recovery blanking and compensation network; Figure 9 for Figure 1 Diagram of the main single-channel and terminal dual-channel trend discrimination circuit of the recovery trend discrimination circuit; In the diagram: 110, Single-channel control input and protection unit; 111, Control terminal; 112, Input current limiting resistor; 113, Low-capacitance clamping network; 114, Open-circuit bias resistor; 120, Same-source dual-threshold reference unit; 121, Reference source; 122, Lower threshold voltage divider network; 123, Upper threshold voltage divider network; 124, Lower threshold buffer; 125, Upper threshold buffer; 130, Window code unit; 131, Lower threshold comparator; 132, Upper threshold comparator; 133, Lower threshold hysteresis network; 134, Upper threshold hysteresis network; 135, Mutex code and confirmation logic; 140, Fail-safe interlock unit; 141, Power supply monitor; 142, Fault latch; 143, Mutex gate; 150, Adaptive... Non-overlapping control unit; 151. Main branch sampling resistor; 152. Terminal branch sampling resistor group; 152a. Terminal port recovery sampling resistor; 152b. Terminal isolation recovery sampling resistor; 153. Three-channel differential detection and recovery reconstruction circuit; 154. Baseline correction threshold circuit; 155. Recovery comparison circuit; 156. Confirmation timer; 157. Timeout timer; 158. Drive permission gate; 159. Recovery blanking and compensation network; 160. Main branch bipolar drive unit; 161. Main branch forward constant current source; 162. Main branch reverse bias switch; 163. Main branch fast discharge clamping switch network; 164. Main branch current limiting resistor group; 164a. First main branch current limiting resistor; 164b. 165. Main branch current-limiting resistor; 170. Main branch forward return switch; 171. Terminal branch bipolar drive unit; 172. Terminal branch forward constant current unit; 173. Terminal branch reverse bias switch; 174. Terminal branch fast discharge reversing switch; 175. Terminal branch current-limiting resistor; 176. First passive bleeder resistor; 180. Second passive bleeder resistor; 181. PIN diode RF network; 182. RF input port; 183. RF output port; 184. First series PIN diode; 185. Second series PIN diode; 186. Input terminal PIN diode; 187. Output terminal PIN diode; 188. Terminal isolation PIN diode; 189. Input matching terminal. ; 189. Output matching terminal; 190. RF DC blocking choke network; 191. Input DC blocking capacitor; 192. Output DC blocking capacitor; 193. First RF choke inductor; 194. Second RF choke inductor; 195. Third RF choke inductor; 196. Fourth RF choke inductor; 197. Fifth RF choke inductor; 198. Sixth RF choke inductor; 210. Absorption decoupling network; 211. First absorption capacitor; 212. Second absorption capacitor; 213. First damping resistor; 214. Second damping resistor; 215. Third damping resistor; 220. Trend recovery discrimination circuit; 221. First sample-and-hold circuit; 222. Second sample-and-hold circuit; 223. Trend comparator; 224. Trend permission gate. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0028] like Figure 1 The diagram shown is a connection diagram of the overall circuit structure of the present invention, illustrating the overall connection relationships between various functional units, main control signals, detection signals, and the radio frequency network. The radio frequency tri-state switch circuit includes a single-channel control input and protection unit 110, a dual-threshold reference unit 120, a window code unit 130, a fault-safe interlock unit 140, an adaptive non-overlapping control unit 150, a main branch bipolar drive unit 160, a terminal branch bipolar drive unit 170, a PIN diode radio frequency network 180, a radio frequency DC blocking choke network 190, an absorption decoupling network 210, and a recovery trend discrimination circuit 220.

[0029] The control input node VIN of the single-channel control input and protection unit 110 is connected to the two comparison input terminals of the window code unit 130, and the homogeneous dual threshold reference unit 120 provides the lower threshold VL and the upper threshold VH. The three status requests REQ_A, REQ_Z and REQ_S of the window code unit 130 are connected to the fault-safe interlock unit 140, and the status permission output is connected to the adaptive non-overlapping control unit 150. The adaptive non-overlapping control unit 150 outputs EN_S, REV_S, EN_A, and REV_A: EN_S controls the main branch forward constant current source 161 and the main branch forward return switch 165; REV_S controls the main branch reverse bias switch 162 and the main branch fast discharge clamping switch network 163; EN_A controls the terminal branch forward constant current unit 171 and the terminal branch fast discharge reversing switch 173 to select the negative power supply constant current absorption terminal; REV_A controls the terminal branch reverse bias switch 172 and the terminal branch fast discharge reversing switch 173 to select the second terminal reverse bias potential. EN_S and REV_S, and EN_A and REV_A, respectively employ a first-off-then-on interlock.

[0030] like Figure 2 The diagram shows the circuit diagram of the single-channel control input and protection unit 110 and the dual-threshold reference unit 120. Control terminal 111 is connected to the control input node VIN via input current-limiting resistor 112. Low-capacitance clamping network 113 is connected between VIN and analog ground. Open-circuit bias resistor 114 is connected between VIN and the intermediate level Vmid. VIN serves as... Figure 2 The control signal output node is connected to Figure 3 The window code unit 130 is shown.

[0031] Reference source 121 is connected between the reference power supply and analog ground, and its output is connected to a five-segment equivalent resistor ladder network. This ladder network simultaneously forms the lower threshold voltage divider network 122 and the upper threshold voltage divider network 123. The second, third, and fourth voltage divider nodes counting upwards from analog ground form VL, Vmid, and VH, respectively. VL is connected to the non-inverting input of the lower threshold buffer 124, and VH is connected to the non-inverting input of the upper threshold buffer 125. The outputs of the two buffers are respectively fed back to their respective inverting inputs, and the buffered VL and VH are respectively sent to... Figure 3 The lower threshold comparator 131 and the upper threshold comparator 132 are in the middle. Vmid is connected to VIN only through the open-circuit bias resistor 114, so that VIN is biased to the middle level region when the control terminal 111 is open.

[0032] like Figure 3 The diagram shown is a circuit diagram of the window code unit 130 and the fail-safe interlock unit 140. Figure 2 The output VIN is connected to the signal input terminals of both the lower threshold comparator 131 and the upper threshold comparator 132. VL and VH are connected to the reference input terminals of the two comparators, respectively. The lower threshold hysteresis network 133 and the upper threshold hysteresis network 134 are connected across the output terminals and signal input terminals of their respective comparators. The output terminals of the two comparators are connected to the mutex and acknowledgment logic 135, which outputs REQ_A, REQ_Z, and REQ_S.

[0033] The UV_OK output of power monitor 141, the FAULT output of fault latch 142, and REQ_A, REQ_Z, and REQ_S are connected to mutex 143. The status clearance output of mutex 143 is connected to... Figure 1 The adaptive non-overlapping control unit 150 in the middle; undervoltage signal, illegal code signal, Figure 7 The output TIMEOUT and positive permission conflict signal are connected to the set terminal of fault latch 142. Figure 7 The output reset confirmation signal is connected to the reset terminal of fault latch 142. RESET_TRIG is generated by the internal power-on reset or power monitoring circuit, or provided by the maintenance reset terminal that does not participate in the tri-state selection. Therefore, Figure 2 Complete analog level generation and protection. Figure 3 Complete the three-state code and fault access. Figure 1 Based on this, the valid status request is sent to the subsequent switching control.

[0034] like Figure 4The diagram shows the circuit diagram of the main branch bipolar drive unit 160 and the terminal branch bipolar drive unit 170. The first RF choke inductor 193 connects NA and BSO1, the fourth RF choke inductor 196 connects NC and BSO2, and the second RF choke inductor 194 connects NB and BSC. The main branch forward constant current source 161 includes independent first and second constant current output branches, connected to BSO1 and BSO2 respectively via first and second main branch current limiting resistors 164a and 164b; BSC is connected to the main forward return terminal BSR via the main branch forward return switch 165. The two controlled contacts of the main branch fast discharge clamping switch network 163 are connected to BSO1 and BSO2 respectively, and the other end is connected to the main reverse bias low-potential return terminal VOS; +VRS is connected to BSC sequentially via the main branch sampling resistor 151 and the main branch reverse bias switch 162. When EN_S is active, the two constant current output branches flow to NB via the first series PIN diode 183 and the second series PIN diode 184, respectively, and then return to BSR via BSC and the main branch forward return switch 165, forming two closed forward loops. When REV_S is active, BSO1 and BSO2 are clamped to V0S while BSC is set to +VRS, forming a main reverse recovery and reverse bias loop from +VRS through the main branch sampling resistor 151, the main branch reverse bias switch 162, and the second RF choke inductor 194 to NB, and then return to V0S via the first series PIN diode 183, the first RF choke inductor 193, the second series PIN diode 184, the fourth RF choke inductor 196, and the main branch fast discharge clamp switch network 163.

[0035] The third RF choke inductor 195 connects the terminal common return node NGC and the terminal common drive terminal BAG. +VRA1 is connected to NGC sequentially via the terminal port recovery sampling resistor 152a, the terminal branch reverse bias switch 172, and the third RF choke inductor 195. The anode of the terminal isolation PIN diode 187 is connected to the terminal common return node NGC, and the cathode is connected to the terminal isolation drive terminal BID via the third damping resistor 215. The terminal isolation drive terminal BID is connected to the common terminal of the terminal branch fast discharge commutator switch 173. The first switching terminal of the terminal branch fast discharge commutator switch 173 is connected to the negative power supply -VSS via the terminal branch current limiting resistor 174 and the terminal branch positive constant current unit 171, and the second switching terminal is connected to +VRA2 via the terminal isolation recovery sampling resistor 152b. When EN_A is valid, the terminal branch reverse bias switch 172 is open and the terminal branch fast discharge commutation switch 173 selects the negative power supply constant current absorption terminal; when REV_A is valid, the terminal branch forward constant current unit 171 is open, the terminal branch reverse bias switch 172 is closed, and the terminal branch fast discharge commutation switch 173 selects +VRA2; during commutation, the terminal branch fast discharge commutation switch 173 first opens both switching terminals, and then closes the target switching terminal to prevent +VRA2 from being directly connected to -VSS. The terminal port recovery sampling resistor 152a detects the net current of the terminal common return path, and the terminal isolation recovery sampling resistor 152b independently detects the reverse recovery current of the terminal isolation PIN diode 187. The detection results of the two are used to reconstruct the port terminal recovery current of the input terminal PIN diode 185 and the output terminal PIN diode 186. The terminal common return node NGC is connected to VOS via a first passive bleeder resistor 175, and BID is connected to NGC via a second passive bleeder resistor 176. During the commutation dead zone when the terminal branch reverse bias switch 172 is open and the terminal branch fast discharge commutation switch 173 is fully open, the first passive bleeder resistor 175 and the second passive bleeder resistor 176 return NGC and BID to their respective predetermined non-positive bias potentials. The first passive bleeder resistor 175 and the second passive bleeder resistor 176 employ high resistance values, and their steady-state shunt current is much smaller than the terminal forward constant current and safety recovery current.

[0036] like Figure 5 The diagram shown is a circuit diagram of the PIN diode RF network 180, the RF DC blocking choke network 190, and the absorption decoupling network 210, and illustrates the relationship between the above modules and... Figure 4Connections between the bias drive nodes. The RF input port 181 is connected to NA via the input DC blocking capacitor 191, and the RF output node NC is connected to the RF output port 182 via the output DC blocking capacitor 192. The anode of the first series PIN diode 183 is connected to NA, and the cathode is connected to NB. The anode of the second series PIN diode 184 is connected to NC, and the cathode is connected to NB, thus forming a series transmission branch with a common cathode. The first RF choke inductor 193, the second RF choke inductor 194, and the fourth RF choke inductor 196 connect NA, NB, and NC respectively. Figure 4 BSO1, BSC, and BSO2.

[0037] The input absorption branch is formed by sequentially connecting the input matching terminal 188 of NA, the input terminal PIN diode 185, and the first RF bypass node NG1. The anode of the input terminal PIN diode 185 is connected to the input matching terminal 188, and the cathode is connected to NG1. The output absorption branch is formed by sequentially connecting the output matching terminal 189 of NC, the output terminal PIN diode 186, and the second RF bypass node NG2. The anode of the output terminal PIN diode 186 is connected to the output matching terminal 189, and the cathode is connected to NG2. NG1 is connected to RF ground via the first absorption capacitor 211, and to NGC via the first damping resistor 213 and the fifth RF choke inductor 197. NG2 is connected to RF ground via the second absorption capacitor 212, and to NGC via the second damping resistor 214 and the sixth RF choke inductor 198. The anode of the terminal isolation PIN diode 187 is connected to NGC, and the cathode is connected via the third damping resistor 215. Figure 4 The terminal branch fast discharge reversing switch 173 is in the middle. The first passive bleeder resistor 175 is connected to NGC and VOS, and the second passive bleeder resistor 176 is connected to BID and NGC.

[0038] like Figure 6 The diagram shows the three-physical-channel reverse recovery detection, terminal recovery reconstruction, and threshold comparison circuit of the adaptive non-overlapping control unit 150. Three independent differential amplification channels are connected across the main branch sampling resistor 151, the terminal port recovery sampling resistor 152a, and the terminal isolation recovery sampling resistor 152b, respectively, and output VS, VAP, and VAI. The polarity and gain normalization circuit outputs VAP_N and VAI_N according to preset or factory-determined polarity and gain coefficients, ensuring that both are positively correlated with the increase of the corresponding reverse recovery current. The additive reconstruction node outputs VA_PORT = VAP_N + VAI_N, and the isolation channel outputs VA_ISO = VAI_N. This additive relationship is used to cancel out the opposite-direction component of the reverse recovery current generated by the terminal isolation PIN diode 187 across the terminal port recovery sampling resistor 152a, so that VA_PORT represents the total recovery current of the input terminal PIN diode 185 and the output terminal PIN diode 186.

[0039] VS, VAP, and VAI are also connected to the zero-current baseline window comparators of the main branch, terminal port path, and terminal isolation path, respectively. The hardware of the three and the result form BASE_DONE, which is used to enter the target state from the high-impedance isolation state and to reset the fault. Figure 8 The baseline correction threshold circuit 154 outputs VTH_S, VTH_AP, and VTH_AI. The recovery comparison circuit 155 compares VCOMP_S with VTH_S when exiting the on state, and compares VCOMP_AP with VTH_AP and VCOMP_AI with VTH_AI when exiting the matched absorption off state. The latter two comparison results are then ANDed in hardware. Therefore, REC_DONE will not be generated if any terminal recovery object fails to complete recovery.

[0040] like Figure 7 The diagram shown is a circuit diagram of the recovery continuity confirmation, conversion timeout, and fault reset interlock circuit of the fail-safe interlock unit 140 and the adaptive non-overlapping control unit 150. Figure 6 The output REC_DONE, Figure 9 The output TREND_OK and the three-channel BASE_DONE are connected to the confirmation timer 156 via the state selection logic; Figure 8 The output blanking signal is connected to the reset terminal of the confirmation timer 156. The confirmation timer 156 outputs REC_OK only when all the conditions required for the current state remain valid for the confirmation time; it is reset to zero if any condition is interrupted.

[0041] REQ_A, REQ_Z, and REQ_S are connected to the timeout timer 157 and the drive permission gate 158 via the target state latch branch. The TIMEOUT output of the timeout timer 157 is connected to the set terminal of the fault latch 142. The fault latch 142 adopts a set-priority structure, and its FAULT output is connected to the disable terminal of the drive permission gate 158. The VIN mid-zone signal, UV_OK, TIMEOUT invalid signal, VS baseline window signal, VAP baseline window signal, VAI baseline window signal, and reset trigger signal RESET_TRIG are connected to the reset confirmation branch. RESET_TRIG does not participate in the generation of REQ_A, REQ_Z, and REQ_S. The fault latch 142 is allowed to be reset only if all three physical detection channels are continuously in the baseline window for the reset confirmation time, and the other reset conditions are valid at the same time.

[0042] like Figure 8 The diagram shows the three-path displacement current replication compensation and recovery detection blanking circuit diagram for the restoration blanking and compensation network 159, connected to... Figure 6 The original detection or normalized detection output and Figure 6 , Figure 9 The recovery determination inputs are connected. The main branch replication branch corresponds to the reverse bias path from +VRS to NB via the main branch sampling resistor 151, the main branch reverse bias switch 162, and the second RF choke inductor 194; the terminal port replication branch corresponds to the reverse bias path from +VRA1 to NGC via the terminal port recovery sampling resistor 152a, the terminal branch reverse bias switch 172, and the third RF choke inductor 195, and then shunted via the fifth RF choke inductor 197 and the sixth RF choke inductor 198; the terminal isolation replication branch corresponds to the reverse bias path from +VRA2 to the cathode of the terminal isolation PIN diode 187 via the terminal isolation recovery sampling resistor 152b, the terminal branch fast discharge commutation switch 173, and the third damping resistor 215. The three replication branches are synchronized with the actual reverse bias control edge and are respectively matched with the actual reverse bias step amplitude, source impedance, related RF choke inductor, equivalent junction capacitance, and wiring parasitic capacitance.

[0043] The normalized main branch detection signal is subtracted from the main branch displacement current reference to form VCOMP_S; VAP_N, after subtracting the terminal port displacement current reference, is added to VAI_N after subtracting the terminal isolation displacement current reference to form VCOMP_AP; VAI_N, after subtracting the terminal isolation displacement current reference, forms VCOMP_AI. VCOMP_S, VCOMP_AP, and VCOMP_AI are simultaneously sent to... Figure 6 The recovery comparator circuit 155 and Figure 9 The trend judgment input is as follows. The valid edges of REV_S and REV_A trigger the corresponding blanking pulse. During the blanking period, the corresponding REC_DONE is forcibly invalidated and the confirmation timer 156 is cleared. After the blanking is completed, any selected compensation recovery signal that crosses the corresponding threshold again will immediately clear the confirmation timer 156.

[0044] like Figure 9 The diagram shown is a circuit diagram of the main single-channel and terminal dual-channel trend discrimination circuit of the recovery trend discrimination circuit 220, and it also supports... Figure 8 The signal selection and parallel discrimination branch selects VCOMP_S when exiting the on state and selects VCOMP_AP and VCOMP_AI in parallel when exiting the matched absorption off state. Each selected signal is sampled sequentially by the corresponding first sample-and-hold circuit 221 and second sample-and-hold circuit 222 at the first and second sampling times after blanking. The three monitored signals can be configured with three sets of corresponding sample-and-hold circuits for parallel sampling, or they can be time-division multiplexed by one set of sample-and-hold circuits via a channel selector. In time-division multiplexing, the first and second sampling times and holding times of each channel meet the corresponding trend discrimination requirements.

[0045] Each first sampled value V1 and second sampled value V2 is connected to a trend comparator 223. The trend comparator 223 determines whether V2 is not higher than the sum of V1 and the trend hysteresis voltage. The comparison result of the real-time compensation recovery signal and the corresponding threshold is connected to a trend permission gate 224. When exiting the on state, the trend result of the main branch and the real-time comparison result of the main branch form TREND_OK. When exiting the matched absorption off state, the trend results of VCOMP_AP and VCOMP_AI and the real-time comparison results are all hardware ANDed to form TREND_OK. After the second sampling time, if any selected compensation recovery signal exceeds the threshold again, the real-time comparison result is immediately invalidated and the confirmation timer 156 is cleared.

[0046] At this point, Figure 1 This illustrates the overall circuit structure and connection relationships of each functional unit in this invention. Figures 2 to 9 They represent Figure 1 The specific circuits of the corresponding functional modules are used to form a complete closed loop through VIN, VL, VH, status request, drive permission, reverse bias control, VS, VAP, VAI, terminal recovery and reconstruction signal, three-way compensation recovery signal, recovery result, trend result, threshold and baseline confirmation signal.

[0047] Based on the above connection relationships, the overall working principle and state transition process of the present invention are as follows: Control level via Figure 2 VIN is formed after current limiting, clamping, and open-circuit biasing. Figure 3 VIN is compared with VL and VH. Once the comparison result stabilizes and reaches the specified code confirmation time, the low, middle, and high regions respectively form a matched absorption turn-off request REQ_A, a high-impedance isolation request REQ_Z, and a conduction request REQ_S. If the comparison result is an illegal combination, an unstable valid combination, an undervoltage supply, or a valid fault latch, the mutex 143 will not issue a positive drive permission to the subsequent stage.

[0048] In the on-state, EN_S is active, REV_S is inactive, EN_A is inactive while REV_A is active. The two constant current output branches of the main branch forward constant current source 161 supply the specified current to NA and NC respectively. The main branch forward return switch 165 connects the return current from BSC to BSR, so that the first series PIN diode 183 and the second series PIN diode 184 form closed forward loops respectively. The terminal common return node NGC is raised from +VRA1, and the cathode of the terminal isolation PIN diode 187 is further raised from +VRA2, so that the input terminal PIN diode 185, the output terminal PIN diode 186 and the terminal isolation PIN diode 187 are all reverse biased, and the RF signal is transmitted from the RF input port 181 to the RF output port 182.

[0049] In the matched absorption off state, EN_S is invalid, REV_S is valid, EN_A is valid, and REV_A is invalid. The main branch forward constant current source 161 and the main branch forward return switch 165 are disconnected. The main branch fast discharge clamping switch network 163 continuously clamps NA and NC near V0S. The main branch reverse bias switch 162 sets NB to +VRS, causing the first series PIN diode 183 and the second series PIN diode 184 to be reverse biased. The terminal branch fast discharge reversing switch 173 selects the negative power supply constant current absorption terminal. The terminal branch forward constant current unit 171 draws current from NGC. The current flows from NA and NC through the input matching terminal 188, the output matching terminal 189, the input terminal PIN diode 185, and the output terminal PIN diode 186 to NGC, and then through the terminal isolation PIN diode 187 to -VSS, causing the input terminal PIN diode 185, the output terminal PIN diode 186, and the terminal isolation PIN diode 187 to be forward biased. In high-impedance isolation mode, EN_S and EN_A are both invalid, while REV_S and REV_A are both valid, and both the main path and the terminal path maintain the specified reverse bias.

[0050] When exiting the on state, the adaptive non-overlapping control unit 150 first cancels EN_S and the main branch forward return switch 165, and establishes REV_S after the forward bias switch is turned off; VS is compensated for the displacement of the main branch to form VCOMP_S, and the recovery comparator circuit 155, the recovery trend discrimination circuit 220 and the confirmation timer 156 jointly generate the main branch REC_OK. When exiting the matched absorption off state, EN_A is first canceled and the terminal branch fast discharge commutator switch 173 is disconnected from the negative power supply absorption terminal, and then REV_A is established; VAP and VAI are normalized and compensated for three paths to form VCOMP_AP and VCOMP_AI. Only when the real-time threshold conditions and trend conditions of both are continuously valid and reach the confirmation time will the terminal branch REC_OK be generated. After obtaining REC_OK, the target branch reverse bias is first canceled, and after a commutation dead zone tCOM of not less than the sum of the reverse bias switch turn-off time and the forward bias switch on time, the target forward bias is established; the non-target branch always maintains reverse bias.

[0051] When transitioning from a high-impedance isolation state to a conduction state or a matched absorption turn-off state, VS, VAP, and VAI without recovery compensation must simultaneously be within their respective zero-current baseline windows and continuously maintained until the confirmation time. After obtaining BASE_DONE, the target branch reverse bias is first removed, and after passing through the commutation dead zone tCOM, the target forward bias is established. When transitioning from a conduction state or a matched absorption turn-off state to a high-impedance isolation state, EN_S and EN_A remain invalid, while REV_S and REV_A remain valid after REC_OK in the original conduction branch. The fault latch is reset only when VIN is in the middle zone, power supply monitoring is normal, TIMEOUT is invalid, BASE_DONE of the three physical detection channels is continuously valid, and RESET_TRIG is valid. RESET_TRIG does not participate in the three-state selection. A fault state with normal reverse bias power supply is forced into an active reverse bias high-impedance state. When the reverse bias power supply is undervoltage, at least all forward drives are removed, and the drive node is returned to the non-forward bias state through a passive bleeder resistor.

[0052] In this embodiment, the zero-current baselines of VS, VAP, and VAI are obtained in a high-impedance isolation state when EN_S and EN_A are both invalid, or are preset according to device parameters and factory debugging results. The baseline correction threshold circuit 154 sets VTH_S, VTH_AP, and VTH_AI respectively based on the baselines of the three detection channels, the preset transimpedance gain, and the allowable safe recovery current; the remaining recovery current corresponding to the threshold does not exceed the corresponding maximum allowable overlap current. During power-on or fault reset, normal state transition is only allowed if VS, VAP, and VAI are all continuously within their respective zero-current baseline windows for the confirmation time.

[0053] The following is a specific embodiment. This embodiment operates in the 400MHz to 800MHz frequency band, with a port impedance of 50Ω. The input DC blocking capacitor 191, output DC blocking capacitor 192, first absorption capacitor 211, and second absorption capacitor 212 are all 100pF; the first to sixth RF choke inductors are all 150nH with a self-resonant frequency higher than 1.2GHz; the input matching terminal 188 and output matching terminal 189 are both 49.9Ω; the two constant current output branches of the main branch are each provided with a 10mA forward current and are connected in series with a 22Ω first main branch current-limiting resistor 164a and a 22Ω second main branch current-limiting resistor 164b; the terminal branch forward constant current unit 171 is provided with a 20mA total absorption current, so that the two port terminals... Each branch receives approximately 10mA of forward current, while the terminal isolation PIN diode 187 and the terminal branch forward constant current unit 171 bear a total current of approximately 20mA; the main branch forward return switch 165 also bears a total return current of approximately 20mA; the first damping resistor 213 and the second damping resistor 214 are both 2.2Ω, and the third damping resistor 215 is 4.7Ω; the main branch sampling resistor 151, the terminal port recovery sampling resistor 152a, and the terminal isolation recovery sampling resistor 152b are all 2Ω; the first passive discharge resistor 175 and the second passive discharge resistor 176 are both 100kΩ.

[0054] In this embodiment, the reference source 121 outputs 5.0V, and the five-segment equivalent resistor ladder network generates VL=2.0V, Vmid=3.0V, and VH=4.0V. When the control terminal inputs 0V, 3.0V, or open circuit and 6.0V, it requests a matched absorption turn-off state, a high-impedance isolation state, and a conduction state, respectively. V0S and BSR are both 0V, +VRS is +5V, +VRA1 is +5V, +VRA2 is +10V, and -VSS is -5V. After considering the worst-case path voltage drop, the main reverse bias satisfies VRS-V0S-ΔV_S,path≥VREV_S,min; the reverse bias of the input terminal PIN diode 185 and the output terminal PIN diode 186 satisfies VRA1-max(VNA_DC, VNC_DC)-ΔV_AP,path≥VREV_AP,min. When the main path is on and the main path PIN forward voltage drop is approximately 0.6V to 0.9V, the actual reverse bias of the input terminal PIN diode 185 and the output terminal PIN diode 186 is approximately 4.0V to 4.4V instead of a fixed 5V; the reverse bias of the terminal isolation PIN diode 187 satisfies VRA2-VRA1-ΔV_AI,path≥VREV_AI,min, which in this embodiment is approximately 4.8V to 5.0V. Each actual reverse bias voltage is simultaneously lower than the minimum reverse breakdown voltage of the corresponding PIN diode minus at least 20% of the safety margin.

[0055] Taking the control level switching from 6.0V to 0V as an example, the circuit first cancels EN_S, disconnecting the two main constant current output branches and the main branch forward return switch 165. After the turn-off protection time, REV_S is made valid, and the main branch fast discharge clamping switch network 163 clamps NA and NC to V0S. +VRS establishes reverse bias to NB through the main branch sampling resistor 151 and the main branch reverse bias switch 162. The main channel VS is reduced by the main branch displacement current reference to form VCOMP_S. The comparator circuit 155 compares VCOMP_S and VTH_S. REC_OK is generated after satisfying the real-time amplitude, dual-time trend and 200ns continuous confirmation conditions. Then REV_A is canceled, and EN_A is made valid after tCOM. The terminal branch forward constant current unit 171 establishes the absorption state. The blanking time is 50ns, the two trend sampling times are 80ns and 120ns after blanking, and the trend hysteresis voltage is 10mV.

[0056] When the control level switches from 0V to 6.0V, EN_A is first deactivated and the terminal branch fast discharge commutator 173 is disconnected from the negative power supply constant current absorption terminal. Then, REV_A is activated: +VRA1 is applied to the terminal common return node NGC via the terminal port recovery sampling resistor 152a, the terminal branch reverse bias switch 172, and the third RF choke inductor 195. +VRA2 is applied to the cathode of the terminal isolation PIN diode 187 via the terminal isolation recovery sampling resistor 152b and the terminal branch fast discharge commutator 173. The differential detection channel obtains VAP and VAI, and generates VAP_N and VAI_N according to the preset or factory-determined polarity and gain coefficient. After displacement compensation, VCOMP_AP and VCOMP_AI are formed. Only when VCOMP_AP≤VTH_AP, VCOMP_AI≤VTH_AI, and both trend results are valid and continuously maintained for 200ns, is REC_OK obtained. Then, REV_S is deactivated, and EN_S is activated again via tCOM. When the control level switches from 3.0V to 0V or 6.0V, the uncompensated VS, VAP, and VAI must simultaneously be within their respective zero-current baseline windows and remain continuously for 200ns. After obtaining BASE_DONE, the target reverse bias is canceled, tCOM is waited for, and the target forward bias is established in sequence. The maximum recovery wait time is 10μs, tCOM is not less than the sum of the worst-case turn-off time and turn-on time of the selected drive switch, and a design margin of not less than 20ns is added.

[0057] In this embodiment, the polarity and gain coefficients of the three detection channels are preset based on the sampling resistor value, differential amplifier gain, and factory debugging results. The main branch baseline, terminal port reconstruction baseline, and terminal isolation baseline are denoted as VBL_S, VBL_PORT, and VBL_AI, respectively, and their corresponding effective transimpedance coefficients are denoted as K_S, K_PORT, and K_AI, respectively. The baseline correction threshold circuit 154 sets the thresholds according to VTH_S=VBL_S+K_S×ISAFE_S, VTH_AP=VBL_PORT+K_PORT×ISAFE_AP, and VTH_AI=VBL_AI+K_AI×ISAFE_AI, where ISAFE_S and ISAFE_AP are both 1mA, and ISAFE_AI is 0.5mA. The zero-current baseline windows for VS, VAP, and VAI are each ±10mV of the corresponding baseline, and BASE_DONE is formed when the three conditions are continuously maintained for 200ns.

[0058] When verifying this embodiment, S21, S11 and S22 were measured under three control levels, and NA, NB, NC, NGC, BID, VS, VAP, VAI, VCOMP_S, VCOMP_AP, VCOMP_AI, VTH_S, VTH_AP, VTH_AI, REC_DONE, TREND_OK, REC_OK, EN_S, REV_S, EN_A and REV_A were observed simultaneously. The verification results should meet the following requirements: In the on-state, both main PIN diodes receive the specified forward current; in the matched absorption off-state, the impedances of both ports are close to 50Ω and the forward currents of the three terminating PIN diodes are within the specified range; in the high-impedance isolation state, the reverse bias of all five PIN diodes satisfies the above-mentioned reverse bias relationship including the worst-case path voltage drop; NGC and BID are not floating in the commutation dead zone; the measured currents of the main branch forward return switch 165 and the terminating isolation PIN diode 187 do not exceed their rated values ​​selected based on a total current of approximately 20mA; EN_S and REV_S are not valid simultaneously, EN_A and REV_A are not valid simultaneously, and EN_S and EN_A are not valid simultaneously; when exiting the absorption state, the port termination recovery signal is reconstructed from the detection results of the terminal port recovery sampling resistor 152a and the terminal isolation recovery sampling resistor 152b, and the terminating isolation PIN diode 187 has an independent recovery criterion; the establishment of the target branch forward current is later than the original branch recovery confirmation and the commutation dead zone; in case of an anomaly or timeout, both forward permissions are revoked.

[0059] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.

Claims

1. A single-channel level-controlled radio frequency tri-state switch circuit, comprising a single-channel control input and protection unit (110), a dual-threshold reference unit (120), a window code unit (130), a fault-safe interlock unit (140), an adaptive non-overlapping control unit (150), a main branch bipolar drive unit (160), a terminal branch bipolar drive unit (170), a PIN diode radio frequency network (180), and a radio frequency DC blocking choke network (190); characterized in that: The PIN diode RF network (180) includes a first series PIN diode (183) and a second series PIN diode (184) connected in reverse series between the RF input node and the RF output node in a common cathode manner, an input terminal PIN diode (185) and an output terminal PIN diode (186) connected to the two RF nodes via an input matching terminal (188) and an output matching terminal (189) respectively, and a terminal isolation PIN diode (187) connected to the terminal common return node and the terminal isolation drive terminal. The main branch bipolar drive unit (160) includes two constant current output branches that supply limited forward current to the two radio frequency nodes respectively, a main branch forward return switch (165) that connects the common cathode node to the main forward return terminal, and a main branch fast discharge clamping switch network (163) and a main branch reverse bias switch (162) that connect the two radio frequency nodes to the main reverse bias low potential return terminal and apply a higher reverse bias potential to the common cathode node when the main branch is not conducting. The terminal branch bipolar drive unit (170) draws restricted forward current from the terminal common return node through the terminal isolation PIN diode (187) in the matched absorption turn-off state, and applies a first terminal reverse bias potential and a second terminal reverse bias potential higher than the first terminal reverse bias potential to the terminal common return node and the cathode of the terminal isolation PIN diode (187) respectively in the non-absorption state. The window code unit (130) outputs a mutually exclusive on state request, a matched absorption off state request, and a high-impedance isolation state request based on a single analog control voltage output. In the on state, the main branch is forward biased and the terminal branch is reverse biased. In the matched absorption off state, the main branch is reverse biased and the terminal branch is forward biased. In the high-impedance isolation state, both branches are reverse biased. During state transition, the adaptive non-overlapping control unit (150) first cancels the forward bias of the original conducting branch and establishes its reverse bias. After confirming that the original conducting branch has completed reverse recovery, or after confirming that each recovery detection channel is in the zero current baseline window when transitioning from the high-impedance isolation state, the transition is performed in the order of canceling the reverse bias of the target branch, passing through the commutation dead zone, and then establishing the forward bias of the target branch. The fault-safe interlock unit (140) prohibits the main branch and the terminal branch from being forward biased at the same time.

2. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 1, characterized in that: The single-channel control input and protection unit (110) includes a control terminal (111), an input current limiting resistor (112), a low-capacitance clamping network (113), and an open-circuit bias resistor (114). The co-source dual threshold reference unit (120) includes a reference source (121), a lower threshold voltage divider network (122), an upper threshold voltage divider network (123), a lower threshold buffer (124), and an upper threshold buffer (125); an open-circuit bias resistor (114) is connected between the control input node and the intermediate bias node jointly generated by the lower threshold voltage divider network (122) and the upper threshold voltage divider network (123), so that when the control terminal (111) is open, the control input node is stably between the lower threshold and the upper threshold; the resistance value of the open-circuit bias resistor (114) is at least twenty times the resistance value of the input current limiting resistor (112).

3. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 1, characterized in that: The window code unit (130) includes a lower threshold comparator (131), an upper threshold comparator (132), a lower threshold hysteresis network (133), an upper threshold hysteresis network (134), and a mutex code and confirmation logic (135). The failsafe interlock unit (140) includes a power monitor (141), a fault latch (142), and a mutex gate (143). The mutex code and confirmation logic (135) includes a combination code unit and a code confirmation timing unit. It outputs the corresponding status request only when the output combination of the two comparators is a low-zone valid combination, a middle-zone valid combination, or a high-zone valid combination and is continuously maintained until the code confirmation time is reached. Other output combinations are judged as illegal code combinations. The mutex (143) forcibly cancels the two forward drive requests when the output of the power monitor (141) is invalid, the fault latch (142) is set, or the main branch forward drive request and the terminal branch forward drive request are both valid.

4. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 1, characterized in that: The first and second constant current output branches of the main branch forward constant current source (161) are connected to the two RF nodes via the first main branch current limiting resistor (164a), the second main branch current limiting resistor (164b), the first RF choke inductor (193), and the fourth RF choke inductor (196), respectively. The common cathode node is connected to the main forward return terminal via the second RF choke inductor (194) and the main branch forward return switch (165). The main branch reverse bias power supply is connected to the main branch sampling resistor (151) and the main branch reverse bias switch in sequence. The first terminal common cathode node is connected to the second RF choke inductor (194) via the first RF choke inductor (162) and the second RF choke inductor (194). The main branch fast discharge clamping switch network (163) is connected to the two RF nodes via the first RF choke inductor (193) and the fourth RF choke inductor (196). The terminal common return node is connected to the terminal common drive terminal via the third RF choke inductor (195). The first terminal reverse bias power supply is connected to the terminal common drive terminal via the terminal port recovery sampling resistor (152a), the terminal branch reverse bias switch (172), and the third RF choke inductor (195). In the common return node, the anode of the terminal isolation PIN diode (187) is connected to the terminal common return node, and the cathode is connected to the common terminal of the terminal branch fast discharge commutator (173) via the third damping resistor (215). The first switching terminal of the commutator is connected to the terminal forward constant current absorption terminal, and the second terminal reverse bias power supply is connected to the second switching terminal of the commutator via the terminal isolation recovery sampling resistor (152b). The terminal port recovery sampling resistor (152a) and the terminal isolation recovery sampling resistor (152b) constitute the terminal branch sampling resistor. Group (152); The terminal common return node is connected to the main reverse bias low potential return terminal via the first passive discharge resistor (175), and the terminal isolation drive terminal is connected to the terminal common return node via the second passive discharge resistor (176), so that the two nodes have a defined non-positive bias potential during the period when the commutation switch (173) is fully off; the rated current of the main branch forward return switch (165) is not less than the sum of the currents of the two constant current output branches, and the rated current of the terminal isolation PIN diode (187) and its forward absorption path is not less than the sum of the currents of the two port terminal branches.

5. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 4, characterized in that: The radio frequency DC blocking choke network (190) includes an input DC blocking capacitor (191), an output DC blocking capacitor (192), and first to sixth radio frequency choke inductors (193 to 198); the circuit also includes an absorption decoupling network (210), which includes a first absorption capacitor (211), a second absorption capacitor (212), a first damping resistor (213), a second damping resistor (214), and a third damping resistor (215); An input DC blocking capacitor (191), a first series PIN diode (183), a second series PIN diode (184), and an output DC blocking capacitor (192) are connected in series between the RF input port (181) and the RF output port (182); an input matching terminal (188) is connected between the RF input node and the anode of the input terminal PIN diode (185), and the cathode of the input terminal PIN diode (185) is connected to the first RF bypass node; an output matching terminal (189) is connected between the RF output node and the anode of the output terminal PIN diode (186), and the cathode of the output terminal PIN diode (186) is connected to the first RF bypass node. The first RF bypass node is connected to the terminal common return node via a first damping resistor (213) and a fifth RF choke inductor (197). The second RF bypass node is connected to the terminal common return node via a second damping resistor (214) and a sixth RF choke inductor (198). The two RF bypass nodes are also connected to RF ground via a first absorption capacitor (211) and a second absorption capacitor (212). The terminal common return node is connected to the terminal common drive terminal via a third RF choke inductor (195) and connected to the terminal isolation drive terminal via a terminal isolation PIN diode (187) and a third damping resistor (215).

6. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 1, characterized in that: The adaptive non-overlapping control unit (150) includes a main branch sampling resistor (151) connected in series in the main branch reverse bias circuit, a terminal port recovery sampling resistor (152a) connected in series in the path from the first terminal reverse bias power supply to the terminal common return node, a terminal isolation recovery sampling resistor (152b) connected in series in the path from the second terminal reverse bias power supply to the cathode path of the terminal isolation PIN diode (187), and three differential detection channels connected across the above three sampling resistors respectively; the three differential detection channels output the main branch original detection voltage VS, the terminal port path original detection voltage VAP, and the terminal isolation path original detection voltage VAI respectively; the polarity and gain normalization circuit converts VAP and VAI into values ​​where the increase of the corresponding reverse recovery current is the positive direction. VAP_N and VAI_N, the terminal port recovery signal VA_PORT is formed by adding VAP_N and VAI_N, and the terminal isolation recovery signal VA_ISO is formed by VAI_N to compensate for the reverse component generated by the reverse recovery current of the terminal isolation PIN diode (187) on the terminal port recovery sampling resistor (152a); when exiting the matched absorption turn-off state, the terminal branch recovery completion signal is generated only if VA_PORT and VA_ISO meet the corresponding recovery completion conditions respectively; when entering the target state from the high-impedance isolation state and when resetting the fault, the uncompensated VS, VAP and VAI are connected to their respective zero-current baseline window comparators, and the baseline completion signal is generated only when the comparison results of the three zero-current baseline windows are all valid.

7. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 6, characterized in that: The adaptive non-overlapping control unit (150) further includes an acknowledgment timer (156) and a timeout timer (157). The fault-safe interlock unit (140) includes a power monitor (141) and a set-priority fault latch (142). The acknowledgment timer (156) is cleared when the selected recovery completion condition or the hardware and result of the three zero-current baseline windows are interrupted, and outputs a recovery permission signal when the corresponding condition is continuously valid for the acknowledgment time. The timeout timer (157) starts counting from the positive bias of the original conducting branch when the conduction state or matched absorption turn-off state is switched, and is high. When the isolation state enters the target state, the timer starts from the latch target state request. If the recovery permission signal is not obtained within the maximum waiting time, the fault latch (142) is set. The fault latch (142) is only reset when the analog control voltage is in the middle zone, the power supply monitoring is normal, the timeout signal is invalid, VS, VAP and VAI are all continuously in their respective zero current baseline windows until the reset confirmation time is reached and the reset trigger signal RESET_TRIG is valid. RESET_TRIG is generated by the internal power-on reset circuit or the power supply monitoring circuit, or provided by the maintenance reset terminal that does not participate in the three-state selection.

8. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 6, characterized in that: The adaptive non-overlapping control unit (150) further includes a recovery blanking and compensation network (159) and an acknowledgment timer (156). The recovery blanking and compensation network (159) is provided with three sets of displacement current replication branches corresponding to the main branch reverse bias path, the terminal port reverse bias path, and the terminal isolation reverse bias path, respectively. Each displacement current replication branch generates a displacement current reference signal from a replication network that is synchronously driven with the actual reverse bias step and matches the reverse bias step amplitude, source impedance, RF choke inductance, and equivalent capacitance of the corresponding actual path. The main branch compensation recovery signal VCOMP_S is formed by subtracting the main branch displacement current reference signal from VS, and the terminal port compensation recovery signal VCOMP_AP is formed by subtracting the terminal port displacement current reference signal from VAP_N. The result is added to the result obtained by subtracting the terminal isolation displacement current reference signal from VAI_N to form the terminal isolation compensation recovery signal VCOMP_AI. The terminal isolation compensation recovery signal VCOMP_AI is formed by subtracting the terminal isolation displacement current reference signal from VAI_N. The recovery comparison circuit compares VCOMP_S, VCOMP_AP and VCOMP_AI with the corresponding recovery thresholds VTH_S, VTH_AP and VTH_AI respectively. When exiting the conduction state, the comparison result of VCOMP_S is selected. When exiting the matched absorption turn-off state, the comparison results of VCOMP_AP and VCOMP_AI are performed by hardware AND. The recovery blanking and compensation network (159) forces the corresponding comparison result to be invalid and clears the confirmation timer (156) within the blanking time after the reverse bias is established.

9. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 8, characterized in that: It also includes a trend recovery discrimination circuit (220), which performs dual-time sampling on VCOMP_S when exiting the on state and VCOMP_AP and VCOMP_AI when exiting the matched absorption off state. The first and second sampling times of each monitored compensation recovery signal after blanking are collected by the corresponding first sample-and-hold circuit (221) and second sample-and-hold circuit (222), or by the two sample-and-hold circuits in a time-division manner via a channel selector. The trend comparator (223) determines whether the second sample value is not higher than the sum of the first sample value and the trend hysteresis voltage. When exiting the matching absorption shutdown state, the valid trend results of VCOMP_AP and VCOMP_AI and their respective real-time threshold comparison results are compared by hardware to form a terminal trend permission signal; the confirmation timer (156) only counts when the corresponding trend permission signal and the real-time threshold comparison result are valid, and the confirmation timer (156) is immediately cleared when any monitored compensation recovery signal crosses its recovery threshold again.

10. The single-channel level-controlled radio frequency tri-state switch circuit according to claim 8, characterized in that: The baseline correction threshold circuit (154) sets recovery thresholds VTH_S, VTH_AP, and VTH_AI respectively based on the zero-current baseline of the main branch, the terminal port path, and the terminal isolation path, the effective transimpedance coefficient determined by preset or factory debugging, and the corresponding safe recovery current; the zero-current baseline is obtained in the high-impedance isolation state when both the main branch forward drive permission EN_S and the terminal branch forward drive permission EN_A are invalid, or is preset; the three recovery thresholds respectively satisfy: VTH_S = VBL_S + K_S × ISAFE_S; VTH_AP=VBL_PORT+K_PORT×ISAFE_AP; VTH_AI=VBL_AI+K_AI×ISAFE_AI; Among them, ISAFE_S, ISAFE_AP and ISAFE_AI do not exceed the maximum allowable overlapping current of the corresponding branch.

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