A reset synchronization circuit for a multi-phase clock

Abstract

The embodiment of the application discloses a reset synchronization circuit for a multi-phase clock, comprising: a plurality of phase clock reset synchronization modules and a multi-phase synchronization reset alignment module, the phase clock reset synchronization module is used for outputting a first asynchronous reset synchronization release signal according to an enable signal of an enable input end, an accessed clock signal and an asynchronous reset asynchronous release signal, and the phases of a plurality of first asynchronous reset synchronization release signals are different; the multi-phase synchronization reset alignment module is used for outputting a plurality of second asynchronous reset synchronization release signals with different phases according to a plurality of clock signals with different phases, an asynchronous reset asynchronous release signal and a plurality of first asynchronous reset synchronization release signals, so that the phase difference of the plurality of second asynchronous reset synchronization release signals matches the phase difference of the plurality of clock signals. The application guarantees the reset release consistency of the multi-phase clock and guarantees the normal work of subsequent circuits.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a reset synchronization circuit for a multi-phase clock. Background Technology

[0002] In integrated circuit design, especially in high-speed SerDes design (where a clock cycle in a high-speed clock is on the order of tens to hundreds of ps), the chip usually integrates multiple clocks with different frequencies and phases, dividing them into multiple clock domains. Each clock domain circuit requires a matching reset signal to complete the power-on initialization.

[0003] Current multi-clock domain reset handling schemes suffer from asynchronous reset and release across multiple phase clock domains, fixed time delays between phases, and misaligned operating timings across multiple phase clock domains, failing to guarantee consistent reset and release across all phases. Asynchronous reset states across different phase clock domains can easily lead to logic chaos in subsequent circuits. Summary of the Invention

[0004] The invention provides a reset synchronization circuit for multi-phase clocks to ensure the consistency of reset and release of multi-phase clocks and to ensure the normal operation of subsequent circuits.

[0005] According to one aspect of the present invention, a reset synchronization circuit for a multi-phase clock is provided, comprising:

[0006] Multiple phase clock reset synchronization modules are provided, with the clock terminals of different phase clock reset synchronization modules connected to clock signals of different phases, and the reset terminals of multiple phase clock reset synchronization modules connected to the same asynchronous reset and asynchronous release signal.

[0007] Multiple phase clock reset synchronization modules are cascaded together. The enable input of the first-stage phase clock reset synchronization module is connected to an enable level. The enable input of the next-stage phase clock reset synchronization module is connected to the output of the previous-stage phase clock reset synchronization module. The phase clock reset synchronization module is used to output a first asynchronous reset synchronization release signal according to the enable signal of the enable input, the input clock signal, and the asynchronous reset and asynchronous release signal. The phases of the multiple first asynchronous reset synchronization release signals are different.

[0008] A multi-phase synchronous reset alignment module is provided, wherein the multi-phase synchronous reset alignment module is connected to the output terminals of multiple phase clock reset synchronization modules and receives multiple clock signals of different phases. The reset terminal of the multi-phase synchronous reset alignment module is connected to the asynchronous reset and asynchronous release signal. The multi-phase synchronous reset alignment module is used to output multiple second asynchronous reset and synchronous release signals of different phases according to the multiple clock signals of different phases, the asynchronous reset and asynchronous release signal, and multiple first asynchronous reset and synchronous release signals, so that the phase difference of the multiple second asynchronous reset and synchronous release signals matches the phase difference of the multiple clock signals.

[0009] Optionally, multiple clock signals with different phases can be sequentially separated by the same angle.

[0010] Optionally, the phase difference between the second-level phase clock reset synchronization module and the first-level phase clock reset synchronization module is the first phase difference, and the phase difference between the (N+1)th-level phase clock reset synchronization module and the first-level phase clock reset synchronization module is the Nth phase difference; wherein, N is greater than or equal to 2, and the first phase difference to the Nth phase difference decreases sequentially.

[0011] Optionally, the number of multiple clock signals with different phases is four, and the four clock signals with different phases are a first clock signal, a second clock signal, a third clock signal and a fourth clock signal with phases differing by 90° in sequence;

[0012] The number of the plurality of phase clock reset synchronization modules is four. The four phase clock reset synchronization modules are a first phase clock reset synchronization module, a second phase clock reset synchronization module, a third phase clock reset synchronization module, and a fourth phase clock reset synchronization module. The first phase clock reset synchronization module, the second phase clock reset synchronization module, the third phase clock reset synchronization module, and the fourth phase clock reset synchronization module are respectively connected to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal.

[0013] Optionally, the phase of the second clock signal lags behind the first clock signal by 90°, the phase of the third clock signal lags behind the second clock signal by 90°, and the phase of the fourth clock signal lags behind the third clock signal by 90°.

[0014] The output terminal of the first phase clock reset synchronization module is connected to the enable input terminal of the fourth phase clock reset synchronization module, the output terminal of the fourth phase clock reset synchronization module is connected to the enable input terminal of the third phase clock reset synchronization module, and the output terminal of the third phase clock reset synchronization module is connected to the enable input terminal of the second phase clock reset synchronization module.

[0015] Optionally, the phase clock reset synchronization module includes at least two cascaded trigger units.

[0016] Optionally, the multi-phase synchronous reset alignment module includes multiple signal alignment units, each of which is electrically connected to a corresponding phase clock reset synchronization module. The input terminal of each signal alignment unit is electrically connected to the output terminal of the corresponding phase clock reset synchronization module and is connected to the corresponding clock signal. The reset terminal of each signal alignment unit is connected to the asynchronous reset and asynchronous release signal. Each signal alignment unit is used to output a corresponding second asynchronous reset and synchronous release signal based on the connected clock signal, the asynchronous reset and asynchronous release signal, and the connected first asynchronous reset and synchronous release signal.

[0017] Optionally, at least one of the signal alignment units includes a trigger unit, and / or, at least one of the signal alignment units includes at least two cascaded trigger units.

[0018] Optionally, the triggering unit includes a D trigger.

[0019] Optionally, the first phase clock reset synchronization module includes three cascaded trigger units, and the second phase clock reset synchronization module, the third phase clock reset synchronization module and the fourth phase clock reset synchronization module include two cascaded trigger units.

[0020] The multi-phase synchronous reset alignment module includes a first signal alignment unit, a second signal alignment unit, a third signal alignment unit, and a fourth signal alignment unit; the first signal alignment unit includes a six-level cascaded trigger unit, the second signal alignment unit includes a single-level trigger unit, the third signal alignment unit includes a three-level cascaded trigger unit, and the fourth signal alignment unit includes a five-level cascaded trigger unit.

[0021] The technical solution of this invention employs multiple cascaded phase clock reset synchronization modules, which receive the same asynchronous reset and release signal and multiple clock signals of different phases. This converts a single asynchronous reset and release signal into multiple first asynchronous reset and release signals under multiple clock domains. A multi-phase synchronous reset alignment module performs phase alignment processing on the multiple first asynchronous reset and release signals based on the multiple clock signals of different phases and the asynchronous reset and release signals. This ensures that the phase difference of the final output second asynchronous reset and release signal is consistent with the phase difference of the multiple clock signals, guaranteeing the consistency of reset and release across the multi-phase clocks and ensuring the normal operation of subsequent circuits.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a reset circuit for multiple clocks provided by existing technology;

[0025] Figure 2 This is a schematic diagram of a reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of another reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of a first-phase clock reset synchronization module provided in an embodiment of the present invention;

[0028] Figure 5 This is a timing diagram of the first phase clock reset synchronization module provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the structure of a fourth-phase clock reset synchronization module provided in an embodiment of the present invention;

[0030] Figure 7 This is a timing diagram of the operation of the fourth phase clock reset synchronization module provided in an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of another reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of the structure of a multi-phase synchronous reset alignment module provided in an embodiment of the present invention;

[0033] Figure 10 This is a timing diagram of the multi-phase synchronous reset alignment module provided in an embodiment of the present invention;

[0034] Figure 11This is an input / output waveform diagram of a reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Figure 1 This is a schematic diagram of a prior art reset circuit for multiple clocks. The circuit includes at least two stages of asynchronous reset synchronous release circuits. The output of the first-stage asynchronous reset synchronous release circuit is connected to the reset terminal of the second-stage asynchronous reset synchronous release circuit. The reset terminal of the first stage is connected to the reset signal `reset_bus_n`, and the clock terminal of the first stage is connected to the clock signal `PCLK`. The clock terminal of the second stage is connected to the clock signal `HCLK`. Driven by clock signals `PCLK` and `HCLK` respectively, the signal `RSTAHB_n` is ultimately generated. The next clock domain is only allowed to perform reset synchronous release after the asynchronous reset synchronous release of the previous clock domain is completed. There is a fixed time delay between reset releases of different clock domains, and there is no simultaneous release mechanism. This technical solution cannot guarantee the phase relationship between the reset signal and different clock domains, and reset timing violations may occur in the next clock domain.

[0038] In multi-phase clock systems, there are usually multiple clocks with different phases. Traditional asynchronous reset and synchronous release circuits can only handle the reset synchronization of a single clock domain and cannot guarantee that the reset and release signals of multiple phase clock domains are correctly aligned with their respective clocks in phase. This may lead to metastability or timing violations in data transmission across phase clock domains.

[0039] In view of this, embodiments of the present invention provide a reset synchronization circuit for a multi-phase clock. Figure 2 This is a schematic diagram of a reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention. This embodiment is applicable to high-speed integrated circuits with multi-phase clocks, and is particularly suitable for systems containing multi-phase clock domains such as SerDes and high-speed interfaces. Figure 2 As shown, the circuit includes:

[0040] Multiple phase clock reset synchronization modules 110 are provided. The clock terminals of different phase clock reset synchronization modules 110 are connected to clock signals of different phases. The reset terminals of multiple phase clock reset synchronization modules 110 are connected to the same asynchronous reset and asynchronous release signal IRST_BA. The multiple phase clock reset synchronization modules 110 are cascaded. The enable input terminal of the first-stage phase clock reset synchronization module 110 is connected to the enable level IENA_0. The enable input terminal of the next-stage phase clock reset synchronization module 110 is connected to the output terminal of the previous-stage phase clock reset synchronization module 110. The phase clock reset synchronization module 110 is used to output a first asynchronous reset synchronization release signal according to the enable signal of the enable input terminal, the connected clock signal, and the asynchronous reset and asynchronous release signal. The phases of the multiple first asynchronous reset synchronization release signals are different.

[0041] A multi-phase synchronous reset alignment module 120 is connected to the output terminals of multiple phase clock reset synchronization modules 110 and receives multiple clock signals of different phases. The reset terminal of the multi-phase synchronous reset alignment module 120 is connected to an asynchronous reset and asynchronous release signal IRST_BA. The multi-phase synchronous reset alignment module 120 is used to output multiple second asynchronous reset and synchronous release signals of different phases according to the clock signals of different phases, the asynchronous reset and asynchronous release signals, and multiple first asynchronous reset and synchronous release signals, so that the phase difference of the multiple second asynchronous reset and synchronous release signals matches the phase difference of the multiple clock signals.

[0042] The reset synchronization circuit for multi-phase clocks of the present invention includes multiple phase clock reset synchronization modules 110 and a multi-phase synchronization reset alignment module 120. The number of phase clock reset synchronization modules 110 corresponds to the number of clock signals. For example, if there are four clock signals with different phases, there are four corresponding phase clock reset synchronization modules. Each phase clock reset synchronization module 110 is connected to one clock signal, and the clock signals connected to different phase clock reset synchronization modules 110 have different phases.

[0043] Asynchronous reset means the reset signal is independent of the clock; register reset does not require waiting for a clock edge. Asynchronous release means the reset cancellation action is independent of the clock. Synchronous release means that when the reset is cancelled, it must wait for a clock edge, such as the rising edge of the clock, before the register exits the reset state.

[0044] Multiple clock signals with different phases refer to a set of clock signals with the same frequency but different phases, typically operating at high frequencies (e.g., above GHz). When clock signals operate at high frequencies, reset timing challenges arise. Firstly, the clock cycle itself is extremely short, and the release edge of the external asynchronous reset signal can easily fall within the setup-hold time window of any two phase clocks. Cross-phase clock domains can easily trigger metastability, causing unpredictable flip-flop outputs. Secondly, each phase clock has its own phase offset. If the same asynchronous reset signal is directly applied to each clock domain, the reset release time will have random deviations in different phase clock domains. The reset signals cannot follow the multi-phase clocks to achieve orderly release, resulting in reset timing misalignment. In severe cases, this can cause some modules to prematurely exit the reset state while others remain in the reset state, leading to circuit malfunctions and operational errors. In multiple clock signals with different phases, the phases can differ by the same angle or different angles. For example, a four-phase clock includes four phase clocks: 0°, 90°, 180°, and 270°, with each phase differing by 90°; another example is a four-phase clock including four phase clocks: 0°, 60°, 180°, and 240°.

[0045] Each phase clock reset synchronization module's clock input receives a clock signal of a different phase, such as... Figure 2 As shown, clock signals of different phases can be ICK_1, ICK_2…ICK_n, where n is an integer greater than or equal to 3. The reset terminal is connected to the same asynchronous reset / release signal IRST_BA. Multiple phase clock reset synchronization modules 110 are cascaded. The enable input of the first-stage phase clock reset synchronization module 110 is connected to the enable level IENA_0, for example, the enable level IENA_0 can be high. Starting from the second stage, the enable input of the next-stage phase clock reset synchronization module 110 is connected to the output of the previous-stage phase clock reset synchronization module 110. Each stage of the phase clock reset synchronization module 110, driven by the input clock signal, converts the asynchronous reset / release signal IRST_BA into a first asynchronous reset / release signal. Multiple phase clock reset synchronization modules 110 output multiple first asynchronous reset / release signals, namely IENA_1, IENA_2…IENA_n. The multiple first asynchronous reset / release signals have different phases, but the phase difference may differ from the phase difference between the input clock signals of different phases.

[0046] The multi-phase synchronous reset alignment module 120 receives multiple clock signals of different phases and multiple first asynchronous reset synchronous release signals at its input terminal, and an asynchronous reset synchronous release signal IRST_BA at its reset terminal. The multi-phase synchronous reset alignment module 120 can align the multiple first asynchronous reset synchronous releases and output multiple second asynchronous reset synchronous release signals, namely ORST_B_1, ORST_B_2…ORST_B_n. The phase difference between the multiple second asynchronous reset synchronous release signals matches the phase difference of the clock signals. For example, the phases of the four clock signals are 0°, 90°, 180°, and 270° respectively, and the phase difference between the different phase clock signals is 90°. The phase difference between the four second asynchronous reset synchronous release signals is also 90°.

[0047] Specifically, the externally input asynchronous reset and asynchronous release signal IRST_BA is sent to all phase clock reset synchronization modules 110 and multi-phase synchronous reset alignment module 120. Each phase clock reset synchronization module 110 is cascaded and generates multiple first synchronous release and reset signals with different phases based on its own phase clock. These multiple first synchronous release and reset signals with different phases are sent to the multi-phase synchronous reset alignment module 120. The multi-phase synchronous reset alignment module 120 aligns the multiple first asynchronous reset and synchronous release signals according to the multiple clock signals with different phases and the asynchronous reset and asynchronous release signal IRST_BA, and outputs multiple second asynchronous reset and synchronous release signals with different phases, while ensuring that the phase difference between each signal is consistent with the phase difference of the multiple clock signals.

[0048] The technical solution of this invention employs multiple cascaded phase clock reset synchronization modules, which receive the same asynchronous reset and release signal and multiple clock signals of different phases, thereby converting a single asynchronous reset and release signal into multiple first asynchronous reset and release signals under multiple clock domains. A multi-phase synchronous reset alignment module aligns the multiple first asynchronous reset and release signals based on the multiple clock signals of different phases and the asynchronous reset and release signals, ensuring that the phase difference of the final output second asynchronous reset and release signal is consistent with the phase difference of the multiple clock signals. This guarantees the consistency of reset and release across multiple phase clocks and ensures the normal operation of subsequent circuits. Furthermore, this invention avoids the reset timing problems caused by the phase interleaving of multiple phase clocks in a single external asynchronous reset and release signal, eliminating the metastability problem of cross-phase reset. This invention can be directly ported to other circuit modules, such as PLLs, high-speed ADCs, and multi-phase clock interfaces, which contain multi-phase clocks.

[0049] In some optional embodiments of the present invention, the phases of multiple clock signals with different phases are sequentially separated by the same angle.

[0050] In this system, multiple clock signals have the same frequency, and the phase interval between adjacent clock signals is equal. For example, four-phase clock signals are 0°, 90°, 180°, and 270° phase clocks, with adjacent clocks differing by 90°; three-phase clock signals are 0°, 120°, and 240° phase clocks, with adjacent phases fixed at a difference of 120°.

[0051] In some optional embodiments of the present invention, the phase difference between the second-stage phase clock reset synchronization module and the first-stage phase clock reset synchronization module is the first phase difference, and the phase difference between the (N+1)th-stage phase clock reset synchronization module and the first-stage phase clock reset synchronization module is the Nth phase difference; wherein, N is greater than or equal to 2, and the phase difference from the first phase difference to the Nth phase difference decreases sequentially.

[0052] Multiple phase clock reset synchronization modules are cascaded, with each stage sequentially numbered as Stage 1, Stage 2, Stage 3... Stage N+1. Lag refers to the time when the edge of the signal in the next stage appears later than the corresponding edge of the signal in the previous stage. Phase difference is a angular measure of the time interval between two stages of signals, where 360° corresponds to one complete clock cycle, and the lag angle is the magnitude of the phase difference. The lag angle of Stage 2 relative to Stage 1 is the first phase difference, the lag angle of Stage 3 relative to Stage 1 is the second phase difference, and so on, with the lag angle of Stage N+1 relative to Stage 1 being the Nth phase difference, decreasing sequentially from the first to the Nth phase difference. Taking a four-phase clock (0°, 90°, 180°, 270°) as an example, the phase difference between adjacent clocks is 90°. The four phase clocks are connected to the corresponding phase clock reset synchronization modules. The first-level phase clock reset synchronization module is connected to the 0° phase clock, the second-level phase clock reset synchronization module is connected to the 270° phase clock, the third-level phase clock reset synchronization module is connected to the 180° phase clock, and the fourth-level phase clock reset synchronization module is connected to the 90° phase clock. The second level lags the first level by 270°, the third level lags the first level by 180°, and the fourth level lags the first level by 90°, satisfying the requirement that the phase difference decreases sequentially from the first to the third phase difference.

[0053] Figure 3 This is a schematic diagram of another reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 3 As shown, there are four clock signals with different phases. The four clock signals with different phases are the first clock signal ICK_D0, the second clock signal ICK_D90, the third clock signal ICK_D180 and the fourth clock signal ICK_D270, which are 90° apart in sequence.

[0054] The number of multiple phase clock reset synchronization modules is four. The four phase clock reset synchronization modules are the first phase clock reset synchronization module 111, the second phase clock reset synchronization module 112, the third phase clock reset synchronization module 113, and the fourth phase clock reset synchronization module 114. The first phase clock reset synchronization module 111, the second phase clock reset synchronization module 112, the third phase clock reset synchronization module 113, and the fourth phase clock reset synchronization module 114 are respectively connected to the first clock signal ICK_D0, the second clock signal ICK_D90, the third clock signal ICK_D180, and the fourth clock signal ICK_D270.

[0055] There are four clock signals with different phases. A complete clock cycle is 360°, and the phase difference between adjacent clock signals is 90°. Assume the first clock signal ICK_D0 has a phase of 0°, the second clock signal ICK_D90 has a phase of 90° (lagging behind the first clock signal ICK_D0 by 90°), the third clock signal ICK_D180 has a phase of 180° (lagging behind the second clock signal ICK_D90 by 90° and the first clock signal ICK_D0 by 180°), and the fourth clock signal ICK_D270 has a phase of 270° (lagging behind the third clock signal ICK_D180 by 90° and the first clock signal ICK_D0 by 270°). All four clock signals have the same frequency.

[0056] There are four phase clock reset synchronization modules, each connected to one of four clock signals. The clock input of the first phase clock reset synchronization module 111 is connected to the first clock signal ICK_D0; the clock input of the second phase clock reset synchronization module 112 is connected to the second clock signal ICK_D90; the clock input of the third phase clock reset synchronization module 113 is connected to the third clock signal ICK_D180; and the clock input of the fourth phase clock reset synchronization module 114 is connected to the fourth clock signal ICK_D270. All phase clock reset synchronization modules share the same asynchronous reset and asynchronous release signal IRST_BA. The four phase clock reset synchronization modules are cascaded according to a set rule: the first-stage enable input is connected to the enable level IENA_0; the second-stage enable input is connected to the first-stage output; the third-stage enable input is connected to the second-stage output; and the fourth-stage enable input is connected to the third-stage output. Each phase clock reset synchronization module generates its own first asynchronous reset and synchronous release signal. The output of each phase clock reset synchronization module is sent to the multi-phase synchronization reset alignment module 120. The multi-phase synchronization reset alignment module 120 outputs four second asynchronous reset synchronization release signals based on the four clock signals, four first asynchronous reset synchronization release signals and asynchronous reset synchronization release signal IRST_BA. The adjacent phase difference between the four second asynchronous reset synchronization release signals is 90°, which is consistent with the phase difference of the four clock signals.

[0057] In some alternative embodiments of the present invention, reference continues to be made. Figure 3 The phase of the second clock signal lags behind the phase of the first clock signal by 90°, the phase of the third clock signal lags behind the phase of the second clock signal by 90°, and the phase of the fourth clock signal lags behind the phase of the third clock signal by 90°.

[0058] The output of the first phase clock reset synchronization module 111 is connected to the enable input of the fourth phase clock reset synchronization module 114. The output of the fourth phase clock reset synchronization module 114 is connected to the enable input of the third phase clock reset synchronization module 113. The output of the third phase clock reset synchronization module 113 is connected to the enable input of the second phase clock reset synchronization module 112.

[0059] The four clock signals have the same frequency. The second clock signal ICK_D90 lags behind the first clock signal ICK_D0 by 90°; the third clock signal ICK_D180 lags behind the second clock signal ICK_D90 by 90°; and the fourth clock signal ICK_D270 lags behind the third clock signal ICK_D180 by 90°. The enable input of the first phase clock reset synchronization module 111 is connected to the enable level IENA_0. The output of the first phase clock reset synchronization module 111 is connected to the enable input of the fourth phase clock reset synchronization module 114. The output of the fourth phase clock reset synchronization module 114 is connected to the enable input of the third phase clock reset synchronization module 113. The output of the third phase clock reset synchronization module 113 is connected to the enable input of the second phase clock reset synchronization module 112. The cascaded sequence of the multiple phase clock reset synchronization modules is: first phase clock reset synchronization module 111, fourth phase clock reset synchronization module 114, third phase clock reset synchronization module 113, and second phase clock reset synchronization module 112. The fourth-phase clock reset synchronization module 114, the third-phase clock reset synchronization module 113, and the second-phase clock reset synchronization module 112 must wait for the output of the previous stage to be valid before they can output the first asynchronous reset synchronization release signal. The four first asynchronous reset synchronization release signals are IENA_D0, IENA_D90, IENA_180, and IENA_270, respectively. After being aligned by the multi-phase synchronous reset alignment module 120, the first asynchronous reset synchronization release signals output four second asynchronous reset synchronization release signals, ORST_B_D0, ORST_B_90, ORST_B_180, and ORST_B_270, respectively. The adjacent phases of the four second asynchronous reset synchronization release signals differ by 90°, consistent with the phase difference of the four clock signals. Under low-speed clock conditions, the connection order of the four phase clock reset synchronization modules can change while meeting the timing requirements of the preceding and following circuits.

[0060] In some optional embodiments of the present invention, the phase clock reset synchronization module includes at least two cascaded trigger units.

[0061] Each phase clock reset synchronization module includes at least two cascaded trigger units. These trigger units can be clock flip-flops, with the output of the preceding flip-flop connected to the input of the following flip-flop. If the release timing of the asynchronous reset coincides with a valid clock transition edge (e.g., the rising edge), metastability will occur. Each phase clock reset synchronization module includes at least two trigger units, ensuring that the valid level of the first asynchronous reset synchronization release signal output by the phase clock reset synchronization module appears at least two clock cycles after the valid level of the asynchronous reset synchronization release signal, preventing the release timing from coinciding with a valid clock transition edge and eliminating metastability. For example, the second phase clock reset synchronization module includes two trigger units. The clock inputs of both trigger units are connected to a second clock signal, and the reset inputs of both trigger units are connected to the asynchronous reset synchronization release signal. The input of the first trigger unit is connected to the output of the third phase clock reset synchronization module, and the output of the first trigger unit is connected to the input of the second trigger unit. The second trigger unit outputs the first asynchronous reset synchronization release signal.

[0062] Figure 4 This is a schematic diagram of the structure of a first-phase clock reset synchronization module provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the first-phase clock reset synchronization module is a cascaded three-stage D flip-flops (DFFs). Taking the phase of the first clock signal as 0°, the first-phase clock reset synchronization module is a 0° phase clock reset synchronization circuit. For the first-stage DFF, the input terminal D is connected to the enable level, i.e. Figure 3 The enable level is IENA_0, which can be high. The reset terminal RST_BA is connected to the asynchronous reset and release signal IRST_BA, the clock terminal CK is connected to the first clock signal ICK_D0, and the output terminal Q is connected to the input terminal D of the second-stage DFF. For the second-stage DFF, the input terminal D is connected to the output terminal Q of the first-stage DFF, the reset terminal RST_BA is connected to the asynchronous reset and release signal IRST_BA, the clock terminal CK is connected to the first clock signal ICK_D0, and the output terminal Q is connected to the input terminal D of the third-stage DFF. For the third-stage DFF, the input terminal D is connected to the output terminal Q of the second-stage DFF, the reset terminal RST_BA is connected to the asynchronous reset and release signal IRST_BA, the clock terminal CK is connected to the first clock signal ICK_D0, and the output terminal Q is connected to the enable input terminal of the fourth-phase clock reset synchronization module and the input terminal of the multi-phase synchronization reset alignment module.

[0063] Figure 5 This is a timing diagram of the first phase clock reset synchronization module provided in an embodiment of the present invention, as shown below. Figure 5As shown, ICK_D0 is the first clock signal, IRST_BA is the asynchronous reset and asynchronous release signal, Q1 is the output signal of the first-stage DFF output Q, Q2 is the output signal of the second-stage DFF output Q, and Q3 is the output signal of the third-stage DFF output Q, which is the output signal ORST_B_D0 of the first-phase clock reset synchronization module. When the asynchronous reset and asynchronous release signal IRST_BA goes high, the reset enable is disabled, and the first-stage DFF ends the reset state. Since its input D is always connected to a high level, after the asynchronous reset and asynchronous release signal IRST_BA goes high, after the next rising edge of the first clock signal ICK_D0 arrives, the output signal Q1 of the first-stage DFF output Q goes high. After the output signal Q1 of the first-stage DFF passes through the second-stage DFF and the third-stage DFF, and is delayed for a total of 2 clock cycles, the output signal Q3 of the third-stage DFF output Q goes high, completing the synchronous release processing of the reset signal in the clock domain of the first clock signal.

[0064] Figure 6 This is a schematic diagram of a fourth-phase clock reset synchronization module provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the fourth phase clock reset synchronization module is a cascaded two-stage D flip-flops (DFFs). With the first clock signal having a phase of 0°, the second clock signal having a phase of 90°, the third clock signal having a phase of 180°, and the fourth clock signal having a phase of 270°, the fourth phase clock reset synchronization module is a 270° phase clock reset synchronization circuit. For the first-stage DFF, the input terminal D is connected to the output signal IENA of the previous-stage phase clock reset synchronization module, which is the first asynchronous reset synchronization release ORST_B_ output of the first-stage phase clock reset synchronization module. D0, the reset terminal RST_BA is connected to the asynchronous reset and asynchronous release signal IRST_BA, the clock terminal CK is connected to the fourth clock signal ICK_D270, and the output terminal Q is connected to the input terminal D of the second-stage DFF; for the second-stage DFF, the input terminal D is connected to the output terminal Q of the first-stage DFF, the reset terminal RST_BA is connected to the asynchronous reset and asynchronous release signal IRST_BA, the clock terminal CK is connected to the fourth clock signal ICK_D270, and the output terminal Q is connected to the enable input terminal of the next-stage phase clock reset synchronization circuit and the input terminal of the multi-phase synchronization reset alignment module.

[0065] When the asynchronous reset / release signal IRST_BA is pulled low, both DFF stages enter the reset state without waiting for a valid edge of the clock signal (such as a rising edge). At this time, the output Q of both DFF stages is low. When the asynchronous reset / release signal IRST_BA is pulled high, there are two cases. Case 1: The enable input of the fourth phase clock reset synchronization module (i.e., the input D of the first-stage DFF) is low. After the rising edge of the fourth clock signal ICK_D270 arrives, the output Q of the first-stage DFF remains low. At this time, the second-stage DFF also ends the reset state. Since the input D is still low, the output Q remains low. Scenario 2: After the asynchronous reset and release signal IRST_BA goes high, the enable input of the fourth-phase clock reset synchronization module switches from low to high. After the rising edge of the fourth clock signal ICK_D270 arrives, the output Q of the first-stage DFF is pulled from low to high. At this time, the second-stage DFF also ends its reset state. Since the input D is still low, the output Q remains low. After the next rising edge of the fourth clock signal ICK_D270 arrives, since the input D of the second-stage DFF has been pulled from low to high, the output Q will be pulled from low to high, completing the synchronous release function of the reset signal. At this time, the synchronous release function of the asynchronous reset signal will be jointly determined by the signal connected to the enable input of the fourth-phase clock reset synchronization module and the asynchronous reset and release signal IRST_BA.

[0066] Figure 7 This is a timing diagram of the fourth phase clock reset synchronization module provided in an embodiment of the present invention, as shown below. Figure 7 As shown in the diagram, the connection relationship indicates that IENA is the output signal of the first phase clock reset synchronization module, i.e., the first asynchronous reset synchronization release signal ORST_B_D0, located in the ICK_D0 clock domain. It can be seen that the first clock signal ICK_D0 and the fourth clock signal ICK_D270 have a phase difference of 270°. Q1 is the output signal of the first-stage DFF output Q, and Q2 is the output signal of the second-stage DFF output Q, i.e., the output signal ORST_B of the fourth phase clock reset synchronization module. After the asynchronous reset and release signal IRST_BA goes high, the reset enable of the first-stage DFF is disabled. Since the input D is low when the asynchronous reset and release signal IRST_BA goes high, the circuit will not experience metastability. After the output signal IENA of the first-phase clock reset synchronization module goes high, after the next rising edge of the fourth clock signal ICK_D270 arrives, the output signal Q1 of the first-stage DFF output Q goes from low to high. After a delay of one clock cycle by the second-stage DFF, the output signal Q2 of the second-stage DFF output Q goes high, completing the synchronous release of the reset signal under the clock domain of the fourth clock signal ICK_D270.

[0067] Figure 8 This is a schematic diagram of another reset synchronization circuit for a multi-phase clock provided by an embodiment of the present invention. In some optional embodiments of the present invention, such as... Figure 8 As shown, the multi-phase synchronous reset alignment module 120 includes multiple signal alignment units. Each signal alignment unit is electrically connected to a phase clock reset synchronization module. The input terminal of the signal alignment unit is electrically connected to the output terminal of the corresponding phase clock reset synchronization module and receives the corresponding clock signal. The reset terminal of the signal alignment unit receives an asynchronous reset and asynchronous release signal. Each signal alignment unit is used to output a corresponding second asynchronous reset and synchronous release signal according to the received clock signal, asynchronous reset and asynchronous release signal and the received first asynchronous reset and synchronous release signal.

[0068] The multi-phase synchronous reset alignment module 120 includes multiple signal alignment units, the number of which is the same as the number of phase clock reset synchronization modules, and they are electrically connected one-to-one. There are four clock signals of different phases, four phase clock reset synchronization modules, and four signal alignment units. The signal alignment units are sequentially designated as a first signal alignment unit 121, a second signal alignment unit 122, a third signal alignment unit 123, and a fourth signal alignment unit 124. The first signal alignment unit 121 is connected to the first phase clock reset synchronization module 111, the second signal alignment unit 122 is connected to the second phase clock reset synchronization module 112, the third signal alignment unit 123 is connected to the third phase clock reset synchronization module 113, and the fourth signal alignment unit 124 is connected to the fourth phase clock reset synchronization module 114. The signal input terminal of each signal alignment unit is connected to the output terminal of the corresponding phase clock reset synchronization module, receiving the corresponding first asynchronous reset synchronization release signal. The clock terminal of each signal alignment unit receives the same clock signal as the corresponding phase clock reset synchronization module. For example, the signal input terminal of the first signal alignment unit 121 is connected to the output terminal of the first phase clock reset synchronization module 111. The clock terminal of the first phase clock reset synchronization module 111 is connected to the first clock signal ICK_D0, and thus the clock terminal of the first signal alignment unit 121 is also connected to the first clock signal ICK_D0. The reset terminal of each signal alignment unit is connected to the same asynchronous reset / asynchronous release signal IRST_BA. Each signal alignment unit outputs a corresponding second asynchronous reset / asynchronous release signal based on the input clock signal, the first asynchronous reset / asynchronous release signal, and the asynchronous reset / asynchronous release signal IRST_BA. Multiple signal alignment units perform alignment processing on their respective received first asynchronous reset / asynchronous release signals according to their corresponding clocks, ensuring that the adjacent phase difference between the four second asynchronous reset / asynchronous release signals is consistent with the phase difference of the four clock signals.

[0069] In some alternative embodiments of the present invention, at least one signal alignment unit includes a trigger unit, and / or, at least one signal alignment unit includes at least two cascaded trigger units.

[0070] The signal alignment unit includes a trigger unit. Some signal alignment units may use only a single trigger unit, while others may employ two or more cascaded trigger units. The number of trigger units included in different signal alignment units can vary. The number of triggers can be determined based on the characteristics of the incoming clock signal and the first asynchronous reset synchronous release signal, thereby ensuring that the phase difference between the four second asynchronous reset and asynchronous release signals remains consistent with the phase difference of the four clock signals. For example, the first signal alignment unit may include six cascaded trigger units, the second signal alignment unit may include one trigger unit, the third signal alignment unit may include three cascaded trigger units, and the fourth signal alignment unit may include five cascaded trigger units.

[0071] In some alternative embodiments of the present invention, the triggering unit includes a D flip-flop.

[0072] The phase clock reset synchronization module and the signal alignment unit both use D flip-flops. Each D flip-flop includes a clock input, a signal input, and a reset input. The clock input receives the corresponding clock signal, the signal input receives the input signal to be registered, and the reset input receives an asynchronous reset / asynchronous release signal. The D flip-flop is a clock-rising-edge triggered flip-flop with asynchronous reset functionality. The asynchronous reset / asynchronous release signal is enabled when low, and the output of the D flip-flop is low in the reset state.

[0073] Figure 9 This is a schematic diagram of the structure of a multi-phase synchronous reset alignment module provided in an embodiment of the present invention. Figure 10 This is a timing diagram of a multi-phase synchronous reset alignment module provided in an embodiment of the present invention. In some optional embodiments of the present invention, refer to... Figure 4 , Figure 6 , Figure 8 and Figure 9 The first phase clock reset synchronization module 111 includes three cascaded trigger units, and the second phase clock reset synchronization module 112, the third phase clock reset synchronization module 113 and the fourth phase clock reset synchronization module 114 include two cascaded trigger units.

[0074] The multi-phase synchronous reset alignment module 120 includes a first signal alignment unit 121, a second signal alignment unit 122, a third signal alignment unit 123, and a fourth signal alignment unit 124; the first signal alignment unit 121 includes a six-level cascaded trigger unit, the second signal alignment unit 122 includes a single-level trigger unit, the third signal alignment unit 123 includes a three-level cascaded trigger unit, and the fourth signal alignment unit 124 includes a five-level cascaded trigger unit.

[0075] The clock terminals of the four phase clock reset synchronization modules are respectively connected to four clock signals: ICK_D0, ICK_D90, ICK_D180, and ICK_D270. The phases of the four clock signals ICK_D0, ICK_D90, ICK_D180, and ICK_D270 are 0°, 90°, 180°, and 270°, respectively. Figure 4 As shown, the first phase clock reset synchronization module 111 includes three cascaded D flip-flops, and the asynchronous reset and asynchronous release signal IRST_BA is connected to the reset terminals of all flip-flops. Figure 6 As shown, the second phase clock reset synchronization module 112, the third phase clock reset synchronization module 113, and the fourth phase clock reset synchronization module 114 include two cascaded D flip-flops. The output of the first phase clock reset synchronization module 111 is given to the enable input of the fourth phase clock reset synchronization module 114, the output of the fourth phase clock reset synchronization module 114 is given to the enable input of the third phase clock reset synchronization module 113, and the output of the third phase clock reset synchronization module 113 is given to the enable input of the second phase clock reset synchronization module 112.

[0076] The multi-phase synchronous reset alignment module 120 includes four signal alignment units, which are connected one-to-one with four phase clock reset synchronization modules. The first signal alignment unit 121 is connected to the first phase clock reset synchronization module 111, the second signal alignment unit 122 is connected to the second phase clock reset synchronization module 112, the third signal alignment unit 123 is connected to the third phase clock reset synchronization module 113, and the fourth signal alignment unit 124 is connected to the fourth phase clock reset synchronization module 114. Each signal alignment unit outputs a second asynchronous reset synchronization release signal based on the corresponding clock signal, the asynchronous reset and asynchronous release signal IRST_BA, and the corresponding first asynchronous reset synchronization release signal.

[0077] The four signal alignment units have different numbers of flip-flop stages, such as... Figure 9As shown, the first signal alignment unit 121 includes a six-stage cascaded D flip-flop, the second signal alignment unit 122 includes a single-stage D flip-flop, the third signal alignment unit 123 includes a three-stage cascaded D flip-flop, and the fourth signal alignment unit 124 includes a five-stage cascaded D flip-flop. The asynchronous reset / asynchronous release signal RST_BA is enabled when low, and the D flip-flop output Q is low in the reset state. The more cascaded D flip-flops there are, the longer the clock cycle delay for the signal is registered. Different signal alignment units use different numbers of flip-flops, and timing adjustments are made by delaying the clock cycle of the flip-flops to ensure that the adjacent phase difference of the four second asynchronous reset / synchronous release signals is 90°, consistent with the phase difference of the four clocks.

[0078] Each signal alignment unit receives an enable signal with different clock phases (i.e., the first asynchronous reset synchronous release signal), a clock signal with different phases, and the same asynchronous reset asynchronous release signal, and then outputs a second asynchronous reset synchronous release signal. The first signal alignment unit 121, the second signal alignment unit 122, the third signal alignment unit 123, and the fourth signal alignment unit 124 are respectively connected to the first clock signal ICK_D0, the second clock signal ICK_D90, the third clock signal ICK_D180, and the fourth clock signal ICK_D270. The first signal alignment unit includes 6 cascaded DFFs, the second signal alignment unit includes 1 DFF, the third signal alignment unit includes 3 cascaded DFFs, and the fourth signal alignment unit includes 5 cascaded DFFs.

[0079] The first-stage DFF input terminal of the first signal alignment unit 121 is connected to the output signal of the first phase clock reset synchronization module 111, namely the first asynchronous reset and asynchronous release signal IENA_D0. The clock terminal is connected to the first clock signal ICK_D0, the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal is connected to the input terminal of the next stage DFF. The intermediate-stage DFF input terminal is connected to the output terminal of the previous stage DFF. The clock terminal is connected to the first clock signal ICK_D0, the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal is connected to the input terminal of the next stage DFF. The output-stage DFF input terminal is connected to the output terminal of the previous stage DFF. The clock terminal is connected to the first clock signal ICK_D0, the reset terminal RST_BA is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal outputs the second asynchronous reset and synchronous release signal ORST_B_D0.

[0080] The DFF input terminal of the second signal alignment unit 122 is connected to the output signal of the second phase clock reset synchronization module 112, namely the first asynchronous reset asynchronous release signal IENA_D90, the clock terminal is connected to the second clock signal ICK_D90, the reset terminal is connected to the asynchronous reset asynchronous release signal IRST_BA, and the output terminal outputs the second asynchronous reset synchronization release signal ORST_B_D90.

[0081] The third signal alignment unit 123 has a three-stage cascaded DFF. The input of the first-stage DFF is connected to the output signal of the third phase clock reset synchronization module 113, namely the first asynchronous reset and asynchronous release signal IENA_D180. The clock terminal is connected to the third clock signal ICK_D180, and the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA. The output terminal is connected to the input of the second-stage DFF. The input of the second-stage DFF is connected to the output of the first-stage DFF. The clock terminal is connected to the third clock signal ICK_D180, and the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA. The output terminal is connected to the input of the third-stage DFF. The input of the third-stage DFF is connected to the output of the second-stage DFF. The clock terminal is connected to the third clock signal ICK_D180, and the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA. The output terminal outputs the second asynchronous reset and synchronous release signal ORST_B_D180.

[0082] In the five-stage cascaded DFF of the fourth signal alignment unit 124, the input terminal of the first-stage DFF is connected to the output signal of the fourth phase clock reset synchronization module 114, namely the first asynchronous reset and asynchronous release signal IENA_D270, the clock terminal is connected to the fourth clock signal ICK_D270, the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal is connected to the input terminal of the next stage DFF; the input terminal of the intermediate-stage DFF is connected to the output terminal of the previous stage DFF, the clock terminal is connected to the fourth clock signal ICK_D270, the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal is connected to the input terminal of the next stage DFF; the input terminal of the output-stage DFF is connected to the output terminal of the previous stage DFF, the clock terminal is connected to the fourth clock signal ICK_D270, the reset terminal is connected to the asynchronous reset and asynchronous release signal IRST_BA, and the output terminal outputs the second asynchronous reset and synchronous release signal ORST_B_D270.

[0083] like Figure 10 As shown, signal alignment units with different numbers of cascaded DFFs are used to perform signal alignment processing on the first asynchronous reset synchronous release signals IENA_D0, IENA_D90, IENA_D180 and IENA_D270 respectively, and then output the second asynchronous reset synchronous release signals, namely ORST_B_D0, ORST_B_D90, ORST_B_D180 and ORST_B_D270.

[0084] Each signal alignment unit aligns the first asynchronous reset synchronization release signals IENA_D0, IENA_D90, IENA_D180, and IENA_D270, obtained through processing by the different phase clock reset synchronization modules, as follows: Figure 10As shown, the first asynchronous reset synchronous release signal IENA_D0 is passed through a 6-stage D flip-flop in the first signal alignment unit to output the second asynchronous reset synchronous release signal ORST_B_D0. That is, the second asynchronous reset synchronous release signal ORST_B_D0 will be pulled high after the first asynchronous reset synchronous release signal IENA_D0 has been pulled high, and then pulled high after six rising edges of the first clock signal ICK_D0. Similarly, the second asynchronous reset synchronous release signal ORST_B_D90 will be pulled high after the first asynchronous reset synchronous release signal IENA_D90 has been pulled high, and then pulled high after one rising edge of the second clock signal ICK_D90. The second asynchronous reset synchronous release signal ORST_B_D180 will be pulled high after the first asynchronous reset synchronous release signal IENA_D180 has been pulled high, and then pulled high after three rising edges of the third clock signal ICK_D180. The second asynchronous reset synchronization release signal ORST_B_D270 is pulled high after the first asynchronous reset synchronization release signal IENA_D270 has been pulled high, and then pulled high again after five rising edges of the fourth clock signal ICK_D270. The rising edges of the second asynchronous reset synchronization release signals ORST_B_D0, ORST_B_D90, ORST_B_D180, and ORST_B_D270 output by the four signal alignment units are 90° out of phase. The number of cascaded DFFs in each signal alignment unit in the multi-phase synchronous reset alignment module can vary depending on the processing delay and connection order of the four-phase clock reset synchronization module.

[0085] Figure 11 This is an example of the input / output waveform diagram of a reset synchronization circuit for a multi-phase clock provided in an embodiment of the present invention. (Refer to...) Figure 8 and Figure 11The asynchronous reset and asynchronous release signal IRST_BA is synchronized to the first clock signal ICK_D0 clock domain after passing through the first phase clock reset synchronization module 111. The reset signal synchronized to the first clock signal ICK_D0 clock domain is synchronized to the fourth clock signal ICK_D270 clock domain through the fourth phase clock reset synchronization module 114. The reset signal synchronized to the fourth clock signal ICK_D270 clock domain is synchronized to the third clock signal ICK_D180 clock domain through the third phase clock reset synchronization module 113. The reset signal synchronized to the third clock signal ICK_D180 clock domain is synchronized to the second clock signal ICK_D90 clock domain through the second phase clock reset synchronization module. The four-phase clock reset synchronization module aligns the first asynchronous reset synchronization release signals of different clock domains through the multi-phase synchronous reset alignment module 120, and then outputs the second asynchronous reset and asynchronous release signals ORST_B_D0, ORST_B_D90, ORST_B_D180 and ORST_B_D270, completing the synchronization operation of the external asynchronous reset and asynchronous release signals, and the phase relationship of the output reset signals corresponds one-to-one with the four-phase clock.

[0086] Circuit operation process reference Figure 4 , 6 8 and 9, the reset synchronization circuit for the multi-phase clock includes a power-on or reset phase (i.e., T1 phase), a reset release phase (i.e., T2 phase), and a normal operation phase (i.e., T3 phase). In the T1 phase, the external asynchronous reset and asynchronous release signal IRST_BA is enabled. That is, when the asynchronous reset and asynchronous release signal IRST_BA is low, the DFF reset in all phase clock reset synchronization modules and multi-phase synchronous reset alignment module 120 is enabled, and the output Q is low. At this time, the first asynchronous reset and synchronous release signals output by all phase clock reset synchronization modules are low, and the second asynchronous reset and synchronous release signals ORST_B_D0, ORST_B_D90, ORST_B_D180, and ORST_B_D270 output by multi-phase synchronous reset alignment module 120 are all low.

[0087] During phase T2, when the external asynchronous reset and asynchronous release signal is pulled from low to high, the DFF reset enable in all phase clock reset synchronization modules and multi-phase synchronous reset alignment module 120 is invalid. Since the output of the first phase clock reset synchronization module 111 is still low, the outputs of the subsequent second phase clock reset synchronization module 112, third phase clock reset synchronization module 113, and fourth phase clock reset synchronization module 114 remain low. The second asynchronous reset synchronization release signals ORST_B_D0, ORST_B_D90, ORST_B_D180, and ORST_B_D270 output by the multi-phase synchronous reset alignment module 120 are all low and remain unchanged.

[0088] During phase T3, the external asynchronous reset and asynchronous release signal is disabled. That is, when the asynchronous reset and asynchronous release signal IRST_BA is high, the DFF reset enable in all phase clock reset synchronization modules and multi-phase synchronous reset alignment module 120 is disabled. The output of the first phase clock reset synchronization module 111 is high, and subsequently the outputs of the second phase clock reset synchronization module 112, the third phase clock reset synchronization module 113, and the fourth phase clock reset synchronization module 114 are high. The second asynchronous reset and synchronous release ORST_B_D0, ORST_B_D90, ORST_B_D180, and ORST_B_D270 output by the multi-phase synchronous reset alignment module 120 are all high.

[0089] The technical solution of this invention solves the alignment problem of asynchronous reset and synchronous release signals for each different clock domain using four-phase clocks. It converts a single external asynchronous reset and release signal into an asynchronous reset and synchronous release signal that resets sequentially according to 0°, 90°, 180°, and 270° phases. This avoids the reset timing problem caused by the phase interleaving of the four-phase clocks in a single external asynchronous reset and release signal. The 0°, 90°, 180°, and 270° phase clock reset synchronization circuit eliminates the metastability problem of cross-phase reset. Multiplexing the same asynchronous reset and synchronous release signal across different clock domains reduces signal delay and the number of registers, thereby reducing layout area and dynamic power consumption.

[0090] The technical solution of this invention is based on a unified reset and synchronous release architecture for four-phase clock domains. It constructs a synchronous release link for four clocks with fixed phase differences, achieving a globally unified reset and synchronous release function across multiple clock domains, thus solving the defects of inconsistent timing due to individual resets in multiple phase clocks. The reset signal passes through each clock domain sequentially in a specific order, exiting the reset state only after all four phase clock domains have completed reset and release. This avoids problems such as system timing errors and initialization mistakes caused by some phase clock domains resetting and exiting before others. The phase relationship of the output reset signal corresponds one-to-one with the four phase clocks, ensuring that the reset and release of each clock domain are synchronized with its respective clock. Asynchronous reset and asynchronous release signals pass through each clock domain sequentially in a specific order. The first asynchronous reset and synchronous release signal of the previous clock domain is sent to the next clock domain. The reset and release timing can effectively avoid clock edges, preventing metastability issues in D flip-flops.

[0091] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A reset synchronization circuit for a multi-phase clock, characterized in that, include: Multiple phase clock reset synchronization modules are provided, with the clock terminals of different phase clock reset synchronization modules connected to clock signals of different phases, and the reset terminals of multiple phase clock reset synchronization modules connected to the same asynchronous reset and asynchronous release signal. Multiple phase clock reset synchronization modules are cascaded together. The enable input of the first-stage phase clock reset synchronization module is connected to an enable level. The enable input of the next-stage phase clock reset synchronization module is connected to the output of the previous-stage phase clock reset synchronization module. The phase clock reset synchronization module is used to output a first asynchronous reset synchronization release signal according to the enable signal of the enable input, the input clock signal, and the asynchronous reset and asynchronous release signal. The phases of the multiple first asynchronous reset synchronization release signals are different. A multi-phase synchronous reset alignment module is provided, wherein the multi-phase synchronous reset alignment module is connected to the output terminals of multiple phase clock reset synchronization modules and receives multiple clock signals of different phases. The reset terminal of the multi-phase synchronous reset alignment module is connected to the asynchronous reset and asynchronous release signal. The multi-phase synchronous reset alignment module is used to output multiple second asynchronous reset and synchronous release signals of different phases according to the multiple clock signals of different phases, the asynchronous reset and asynchronous release signal, and multiple first asynchronous reset and synchronous release signals, so that the phase difference of the multiple second asynchronous reset and synchronous release signals matches the phase difference of the multiple clock signals.

2. The reset synchronization circuit for a multi-phase clock according to claim 1, characterized in that, The phases of multiple clock signals with different phases are successively separated by the same angle.

3. The reset synchronization circuit for a multi-phase clock according to claim 1 or 2, characterized in that, The phase difference between the phase clock reset synchronization module of the second stage and the phase clock reset synchronization module of the first stage is the first phase difference. The phase difference between the phase clock reset synchronization module of the (N+1)th stage and the phase clock reset synchronization module of the first stage is the Nth phase difference; wherein, N is greater than or equal to 2, and the phase difference from the first phase difference to the Nth phase difference decreases sequentially.

4. The reset synchronization circuit for a multi-phase clock according to claim 2, characterized in that, The number of clock signals with different phases is four. The four clock signals with different phases are the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, which are 90° apart in sequence. The number of the plurality of phase clock reset synchronization modules is four. The four phase clock reset synchronization modules are a first phase clock reset synchronization module, a second phase clock reset synchronization module, a third phase clock reset synchronization module, and a fourth phase clock reset synchronization module. The first phase clock reset synchronization module, the second phase clock reset synchronization module, the third phase clock reset synchronization module, and the fourth phase clock reset synchronization module are respectively connected to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal.

5. The reset synchronization circuit for a multi-phase clock according to claim 4, characterized in that, The phase of the second clock signal lags behind the first clock signal by 90°, the phase of the third clock signal lags behind the second clock signal by 90°, and the phase of the fourth clock signal lags behind the third clock signal by 90°. The output terminal of the first phase clock reset synchronization module is connected to the enable input terminal of the fourth phase clock reset synchronization module, the output terminal of the fourth phase clock reset synchronization module is connected to the enable input terminal of the third phase clock reset synchronization module, and the output terminal of the third phase clock reset synchronization module is connected to the enable input terminal of the second phase clock reset synchronization module.

6. The reset synchronization circuit for a multi-phase clock according to claim 1, characterized in that, The phase clock reset synchronization module includes at least two cascaded trigger units.

7. The reset synchronization circuit for a multi-phase clock according to claim 1, characterized in that, The multi-phase synchronous reset alignment module includes multiple signal alignment units, each of which is electrically connected to a corresponding phase clock reset synchronization module. The input terminal of each signal alignment unit is electrically connected to the output terminal of the corresponding phase clock reset synchronization module and receives the corresponding clock signal. The reset terminal of each signal alignment unit receives the asynchronous reset and asynchronous release signal. Each signal alignment unit is used to output a corresponding second asynchronous reset and synchronous release signal based on the received clock signal, the asynchronous reset and asynchronous release signal, and the received first asynchronous reset and synchronous release signal.

8. The reset synchronization circuit for a multi-phase clock according to claim 7, characterized in that, At least one of the signal alignment units includes a trigger unit, and / or, at least one of the signal alignment units includes at least two cascaded trigger units.

9. The reset synchronization circuit for a multi-phase clock according to claim 6 or 8, characterized in that, The triggering unit includes a D flip-flop.

10. The reset synchronization circuit for a multi-phase clock according to claim 4, characterized in that, The first phase clock reset synchronization module includes three cascaded trigger units, and the second phase clock reset synchronization module, the third phase clock reset synchronization module and the fourth phase clock reset synchronization module include two cascaded trigger units. The multi-phase synchronous reset alignment module includes a first signal alignment unit, a second signal alignment unit, a third signal alignment unit, and a fourth signal alignment unit; the first signal alignment unit includes a six-level cascaded trigger unit, the second signal alignment unit includes a single-level trigger unit, the third signal alignment unit includes a three-level cascaded trigger unit, and the fourth signal alignment unit includes a five-level cascaded trigger unit.

Images