A high-voltage direct series IGBT driving circuit and method

Abstract

The application relates to the field of power electronics, and discloses a driving circuit and method of a high-voltage straight string IGBT. The driving circuit comprises a gate side bridge arm, an emitter reference side bridge arm, a driving resistor network, a static voltage-sharing and dynamic sampling coordination circuit and a protection circuit. The gate side bridge arm adjusts the IGBT gate potential through an on branch and an off branch, the emitter reference side bridge arm adjusts the emitter reference node potential through a fault off branch with different resistances in stages, and the gate-emitter voltage required for normal on, normal off and fault soft off is formed. The static voltage-sharing resistor is used for improving the steady-state voltage division of the straight string IGBT, the dynamic sampling, DI / DT, desaturation, VGE and driving power supply detection are jointly input into a fault logic and latch feedback circuit, so that the driving stability and protection reliability of the high-voltage straight string IGBT are improved.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a driving circuit and method for a high-voltage direct-connect IGBT. Background Technology

[0002] In medium- and high-voltage power electronic devices, the withstand voltage of a single IGBT module is often insufficient to directly meet the requirements of the bus voltage or the peak voltage on the AC side. Therefore, multiple IGBTs are often used in series to withstand the voltage. While improving the equivalent withstand voltage, the series-connected IGBTs also make the gate drive state of each IGBT more susceptible to the effects of differences in device parameters, parasitic parameters, and switching transients.

[0003] Existing IGBT drive circuits are usually designed around the turn-on and turn-off of a single IGBT. In high-voltage direct-connect IGBT applications, the requirements for gate charging and discharging speed, turn-off process, and voltage change process under fault conditions are not the same under different operating conditions. If a relatively simple gate drive path is still used, it is difficult to take into account the drive stability during normal turn-on, normal turn-off, and fault turn-off processes, which can easily affect the reliable drive of high-voltage direct-connect IGBTs. Summary of the Invention

[0004] This invention provides a driving circuit and method for high-voltage direct-drive IGBTs to solve the problem that ordinary IGBT driving circuits are difficult to simultaneously achieve gate drive, emitter reference adjustment, dynamic voltage equalization detection, and fault-controlled shutdown in high-voltage direct-drive applications.

[0005] In a first aspect, the present invention provides a driving circuit for a high-voltage direct-connect IGBT, used to drive any IGBT in a high-voltage direct-connect branch, including a gate-side bridge arm, an emitter-reference-side bridge arm, and a driving resistor network. The driving resistor network includes an on branch, an off branch, a first fault off branch, a second fault off branch, and an emitter reference branch; The gate-side bridge arm includes a first switching device and a second switching device. The first connection terminal of the first switching device is connected to the positive drive power supply, and the second connection terminal of the first switching device is connected to the gate of the IGBT through the turn-on branch. The first connection terminal of the second switching device is connected to the gate through the turn-off branch, and the second connection terminal of the second switching device is connected to the low potential reference terminal. The emitter reference side bridge arm includes a third switching device, a fourth switching device, and a fifth switching device. The first connection terminals of the third and fourth switching devices are both connected to the forward drive power supply. The second connection terminal of the third switching device is connected to the emitter reference node of the IGBT through a first fault shutdown branch. The second connection terminal of the fourth switching device is connected to the emitter reference node through a second fault shutdown branch. The first connection terminal of the fifth switching device is connected to the emitter reference node through an emitter reference branch. The second connection terminal of the fifth switching device is connected to a low-potential reference terminal. The gate-side bridge arm is used to adjust the potential of the gate, and the emitter reference-side bridge arm is used to adjust the potential of the emitter reference node to form the gate-emitter drive voltage required for turn-on, turn-off, or fault turn-off between the gate and the emitter. The emitter reference node is a local reference node that is electrically connected to the auxiliary emitter terminal or emitter terminal of the IGBT through an independently set low-inductance connection conductor.

[0006] This invention features a gate-side bridge arm and an emitter reference-side bridge arm that work together to adjust the gate potential and emitter reference potential of the IGBT separately. These arms form the gate-emitter drive voltages required for normal turn-on, normal turn-off, and fault turn-off through different branches. This structure allows for more targeted control of the gate-emitter voltage under different operating conditions, enabling independent paths for normal drive and fault turn-off, reducing mutual interference between different drive states, and improving the controllability of the high-voltage direct-drive IGBT drive process and the reliability of fault turn-off.

[0007] In one alternative implementation, the open branch includes a first gate resistor, which is connected between the second connection terminal of the first switching device and the gate. The shutdown branch includes a second gate resistor, which is connected between the gate and the first connection terminal of the second switching device; The first fault shutdown branch includes a first emitter-side resistor, which is connected between the second connection terminal of the third switching device and the emitter reference node. The second fault shutdown branch includes a second emitter-side resistor, which is connected between the second connection terminal of the fourth switching device and the emitter reference node. The emitter reference branch includes a third emitter-side resistor, which is connected between the first connection terminal of the fifth switching device and the emitter reference node. The resistance value of the first emitter-side resistor is less than the resistance value of the second emitter-side resistor.

[0008] In one alternative implementation, in the normal on-state, the first and fifth switching devices are turned on, while the second, third, and fourth switching devices are turned off, so that the forward drive power supply charges the gate through the on-state branch and brings the emitter reference node close to the low-potential reference terminal. In the normal shutdown state, the first and fifth switching devices are turned off, while the second, third, and fourth switching devices are turned on, causing the gate to discharge through the shutdown branch and the emitter reference node to be adjusted to a relatively high potential. In the fault shutdown state, the first and fifth switching devices are turned off. When the second switching device was in the conducting state before entering the fault shutdown state, the second switching device remains conducting. When the second switching device was in the off state before entering the fault shutdown state, the second switching device turns on after the first switching device turns off and the gate dead time has elapsed. After the second switching device turns on, the first stage begins, with the third switching device turning on and the fourth switching device turning off to connect to the first fault shutdown branch. When the gate-emitter voltage of the IGBT drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device turns off, and after the emitter reference commutation dead time has elapsed, the fourth switching device turns on to connect to the second fault shutdown branch and enter the second stage, until the gate-emitter voltage reaches the shutdown threshold or the duration of the second stage reaches the second preset duration.

[0009] During normal turn-on, the first and fifth switching devices are turned on, charging the gate through the turn-on branch and bringing the emitter reference node close to the low-potential reference terminal, thus forming a positive VGE. During normal turn-off, the second switching device is turned on, discharging the gate through the turn-off branch. The emitter reference side bridge arm works together to adjust the emitter reference node to a relatively high potential, thereby causing VGE to change in the turn-off direction.

[0010] During fault shutdown, the emitter reference node potential is quickly adjusted through the first fault shutdown branch with a smaller resistance value to rapidly reduce VGE and suppress the continued rise of fault current. Subsequently, the second fault shutdown branch with a larger resistance value is used for limited adjustment to reduce the shutdown voltage spike and the dynamic voltage division impact of the direct-series IGBT.

[0011] In one alternative implementation, it further includes a command shaping interlock circuit and a fault logic and latch feedback circuit. The command shaping interlock circuit includes a command input circuit, a shaping logic circuit, an interlock logic circuit, and a delay circuit. The output terminal of the command input circuit is connected to the input terminal of the shaping logic circuit, the output terminal of the shaping logic circuit is connected to the input terminal of the interlock logic circuit, the delay circuit is connected to the interlock logic circuit, and the output terminal of the interlock logic circuit is connected to the control terminals of the first switching device, the second switching device, the third switching device, the fourth switching device, and the fifth switching device, respectively. The fault logic and latch feedback circuit includes a fault logic circuit and a latch logic circuit. The output of the fault logic circuit is connected to the input of the latch logic circuit, and the output of the latch logic circuit is connected to the interlock logic circuit to block the normal turn-on command and maintain the fault-off state after the fault signal is generated.

[0012] The command shaping interlock circuit shapes, interlocks, and delays the turn-on command, turn-off command, and fault turn-off command to prevent the upper and lower switching devices in the gate-side bridge arm or emitter-reference-side bridge arm from shoot-through; the fault logic and latching feedback circuit blocks the normal turn-on command and maintains the fault turn-off state after the protection signal is valid.

[0013] In one optional implementation, a static voltage equalization and dynamic sampling coordination circuit is also included, which includes a static voltage equalization resistor, a series resistor circuit, a series capacitor circuit, and a diode clamping circuit. A static voltage equalization resistor is connected in parallel between the collector and emitter of the IGBT; A series resistor circuit is connected between the collector of the IGBT and the collector-side sampling node. A series capacitor circuit is connected in parallel with the series resistor circuit. The collector-side sampling node is located on the low-voltage side away from the collector of the IGBT, where the series resistor circuit and the series capacitor circuit are located. This is used to form a sampling signal that characterizes the change in the collector potential of the IGBT. The diode clamping circuit is connected between the collector of the IGBT and the clamping sampling node. It is used to convert the dynamic changes of the IGBT collector-emitter voltage into a clamping sampling signal with a voltage amplitude within the allowable range of the subsequent protection circuit.

[0014] The static voltage equalization resistor is used to reduce the steady-state voltage deviation caused by leakage current differences; the series resistor circuit, series capacitor circuit and diode clamping circuit convert the dynamic changes of the IGBT collector-emitter voltage into a low-voltage sampling signal that can be processed by the subsequent protection circuit.

[0015] In an optional implementation, a DI / DT protection circuit is further included. The DI / DT protection circuit includes a DI / DT comparator and a DI / DT threshold voltage divider network. The emitter-side dynamic sampling node is connected to the emitter power terminal of the IGBT or its detection lead. The first input terminal of the DI / DT comparator is connected to the emitter-side dynamic sampling node, the second input terminal of the DI / DT comparator is connected to the emitter reference node and the DI / DT threshold voltage divider network, and the output terminal of the DI / DT comparator is connected to the input terminal of the fault logic circuit, so as to indirectly characterize the di / dt abnormality through the emitter-side dynamic potential difference.

[0016] In one optional embodiment, a desaturation protection circuit is further included, which includes a first desaturation protection branch, a second desaturation protection branch, and a third desaturation protection branch. The first desaturation protection branch includes a first input network and a first comparator. The input terminal of the first input network is connected to the collector-side sampling node, and the output terminal of the first input network forms a first sampling signal and is connected to the sampling-side input terminal of the first comparator. The first comparator forms a fast short-circuit or hard desaturation protection signal based on the first sampling signal. The second desaturation protection branch includes a second input network and a second comparator. The input terminal of the second input network is connected to the clamping sampling node, and the output terminal of the second input network forms a second sampling signal and is connected to the sampling side input terminal of the second comparator. After the blanking time ends, the second comparator forms a desaturation confirmation signal based on the second sampling signal. The third desaturation protection branch includes a third comparator. The sampling input of the third comparator is connected to the output of the second input network to share the second sampling signal with the second desaturation protection branch. The third desaturation protection branch has a comparison threshold or filtering time constant that is different from that of the second desaturation protection branch.

[0017] In one optional implementation, an auxiliary protection circuit is also included, which includes a gate voltage detection circuit and a drive power supply detection circuit. The gate voltage detection circuit includes a VGE sampling circuit and a VGE window comparator. The VGE sampling circuit is connected between the gate and the emitter, and the VGE window comparator is used to determine whether the gate-emitter voltage is within the allowable voltage window of the corresponding driving state. The drive power detection circuit includes a power divider circuit and a power window comparator. The power divider circuit is connected to the positive drive power supply, the logic power supply and the reference power supply respectively. The input terminal of the power window comparator is connected to the power divider circuit and the output terminal of the power window comparator is connected to the fault logic circuit.

[0018] The DI / DT protection circuit indirectly characterizes di / dt abnormalities through the dynamic potential difference on the emitter side; the desaturation protection circuit achieves layered protection through fast short circuit, desaturation confirmation after blanking, and auxiliary confirmation of slow overcurrent or dynamic voltage division abnormalities; the gate voltage detection circuit and the drive power supply detection circuit detect the VGE window and the drive power supply window, respectively.

[0019] Secondly, the present invention provides a driving method for a high-voltage direct-drive IGBT, applied to the driving circuit of the high-voltage direct-drive IGBT in the first aspect or any corresponding embodiment thereof, comprising: Receive drive commands and determine the target drive state of the IGBT based on the drive commands. The target drive state includes normal turn-on state, normal turn-off state, and fault turn-off state. When the target drive state is in the normal on state, control the first and fifth switching devices to turn on, and control the second, third and fourth switching devices to turn off; When the target drive state is the normal off state, the first and fifth switching devices are turned off, and the second, third and fourth switching devices are turned on. When the target drive state is fault shutdown state, the first and fifth switching devices are controlled to turn off; when the second switching device is in the conducting state before entering the fault shutdown state, the second switching device is controlled to remain conducting; when the second switching device is in the off state before entering the fault shutdown state, the second switching device is controlled to turn on after the first switching device is turned off and the gate dead time has elapsed; and the third and fourth switching devices are controlled to connect to the first fault shutdown branch and the second fault shutdown branch in stages.

[0020] In one optional implementation, the third and fourth switching devices are connected to the first fault shutdown branch and the second fault shutdown branch in stages, including: The first stage controls the third switching device to turn on and the fourth switching device to turn off, so that the emitter reference node is quickly adjusted through the first fault turn-off branch to quickly reduce the gate-emitter voltage. When the gate-emitter voltage drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device is controlled to turn off. After the commutation dead time on the emitter reference side, the fourth switching device is controlled to turn on and enter the second stage, so that the emitter reference node is restricted and regulated through the second fault turn-off branch to reduce the turn-off voltage spike and the dynamic voltage division impact of the direct-series IGBT. When the gate-emitter voltage reaches the turn-off threshold or the duration of the second stage reaches the second preset duration, the second stage ends and the fault turn-off state is maintained. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a structural block diagram of a high-voltage direct-connect IGBT drive circuit according to an embodiment of the present invention; Figure 2 This is a circuit diagram of the gate-side bridge arm, the emitter reference-side bridge arm, and the drive resistor network according to an embodiment of the present invention; Figure 3 This is another structural block diagram of the driving circuit of the high-voltage direct-series IGBT according to an embodiment of the present invention; Figure 4 This is a circuit diagram of the static voltage equalization and dynamic sampling coordinated circuit according to an embodiment of the present invention; Figure 5 This is a circuit diagram of the DI / DT protection circuit according to an embodiment of the present invention; Figure 6 This is a circuit diagram of a desaturation protection circuit according to an embodiment of the present invention; Figure 7 This is a circuit diagram of a gate voltage detection circuit according to an embodiment of the present invention; Figure 8 This is a circuit diagram of a drive power detection circuit according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the fault logic circuit according to an embodiment of the present invention.

[0023] Figure 10 This is a schematic diagram of the normal turn-on, normal turn-off, and fault turn-off current paths according to an embodiment of the present invention. Figure 11 This is a flowchart illustrating a driving method for a high-voltage direct-connect IGBT according to an embodiment of the present invention. Figure 12 This is a flowchart illustrating step S104 of the driving method for a high-voltage direct-connect IGBT according to an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures: 100. Gate-side bridge arm; 200. Emitter-reference-side bridge arm; 300. Drive resistor network; 310. Turn-on branch; 320. Turn-off branch; 331. First fault turn-off branch; 332. Second fault turn-off branch; 340. Emitter reference branch; 400. Static voltage equalization and dynamic sampling coordination circuit; 410. Series resistor circuit; 420. Series capacitor circuit; 430. Diode clamping circuit; 500. DI / DT protection circuit; 510. DI / DT comparator; 520. DI / DT threshold voltage divider network; 600. Desaturation protection circuit; 610. First desaturation protection branch; 620. Second desaturation protection branch; 630. Third desaturation protection branch; U3A. First comparator; U4C. Second comparator; U4D. Third comparator; 700. Command shaping interlock circuit; 710. Command Input circuit; 720, Shaping logic circuit; 730, Interlock logic circuit; 740, Delay circuit; 800, Fault logic and latch feedback circuit; 810, Fault logic circuit; 820, Latch logic circuit; 900, Auxiliary protection circuit; 910, Gate voltage detection circuit; 920, Drive power supply detection circuit; 911, VGE sampling circuit; 912, VGE window comparator; 921, Power supply voltage divider circuit; 922, Power supply window comparator; G, Gate; C, Collector; E, Emitter; Q1, First switching device; Q4, Second switching device; Q2, Third switching device; Q5, Fourth switching device; Q3, Fifth switching device; RG1, First gate resistor; RG2, Second gate resistor; RE1, First emitter-side resistor; RE2, Second emitter-side resistor; RE3, Third emitter-side resistor. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] In medium- and high-voltage power electronic devices, power switching devices need to withstand high DC bus voltages or AC peak voltages. Since the withstand voltage capability of a single IGBT module is limited, two or more IGBTs are typically connected in series in engineering to share the voltage and improve the overall withstand voltage capability of the switching unit. While direct-connected IGBTs can improve the equivalent withstand voltage, the IGBTs in series are in the same main power circuit. Differences in leakage current, switching speed, parasitic inductance, parasitic capacitance, and gate drive delay among the devices can easily lead to uneven voltage distribution during static voltage bearing and dynamic switching. Furthermore, when faults such as short circuits or overcurrents occur, the drive circuit needs to quickly identify abnormal states, avoid excessively high turn-off spikes caused by excessively fast turn-off, and reduce the risk of false turn-on due to abnormal gate voltage, insufficient negative voltage, or abnormal drive power supply. Existing conventional IGBT drive circuits are typically designed primarily for the turn-on, turn-off, undervoltage protection, and desaturation protection of a single IGBT. When applied to high-voltage direct-connect IGBTs, the coordination between drive action, voltage equalization requirements, fault detection, and controlled turn-off process is insufficient, making it difficult to meet the reliable drive requirements of direct-connect IGBTs under different operating conditions.

[0028] Therefore, embodiments of the present invention provide a driving circuit and method for high-voltage direct-connect IGBTs to improve the driving stability and protection reliability of high-voltage direct-connect IGBTs under complex operating conditions.

[0029] like Figure 1 As shown, this invention provides a driving circuit for a high-voltage direct-connect IGBT. This driving circuit can be configured separately for each IGBT in the direct-connect branch, enabling each IGBT to receive independent and timing-controllable driving and protection during turn-on, turn-off, fault turn-off, and voltage-bearing processes. The driving circuit includes a gate-side bridge arm 100, an emitter-reference-side bridge arm 200, and a driving resistor network 300. The driving resistor network 300 includes an on branch 310, an off branch 320, a first fault off branch 331, a second fault off branch 332, and an emitter reference branch 340. The gate-side bridge arm 100 includes a first switching device Q1 and a second switching device Q4. The first connection terminal of the first switching device Q1 is connected to the positive drive power supply VDD, and the second connection terminal of the first switching device Q1 is connected to the gate G of the IGBT through the turn-on branch 310. The first connection terminal of the second switching device Q4 is connected to the gate G through the turn-off branch 320, and the second connection terminal of the second switching device Q4 is connected to the low potential reference terminal. The emitter reference side bridge arm 200 includes a third switching device Q2, a fourth switching device Q5, and a fifth switching device Q3. The first connection terminals of the third switching device Q2 and the fourth switching device Q5 are both connected to the forward drive power supply VDD. The second connection terminal of the third switching device Q2 is connected to the emitter reference node of the IGBT through the first fault shutdown branch 331. The second connection terminal of the fourth switching device Q5 is connected to the emitter reference node through the second fault shutdown branch 332. The first connection terminal of the fifth switching device Q3 is connected to the emitter reference node through the emitter reference branch 340. The second connection terminal of the fifth switching device Q3 is connected to the low potential reference terminal. The gate-side bridge arm 100 is used to adjust the potential of the gate, and the emitter reference-side bridge arm 200 is used to adjust the potential of the emitter reference node to form the gate-emitter drive voltage required for turn-on, turn-off or fault turn-off between the gate G and the emitter E. The emitter reference node is a local reference node that is electrically connected to the auxiliary emitter terminal or emitter terminal of the IGBT through an independently set low-inductance connection conductor.

[0030] Specifically, the gate-side bridge arm 100 and the emitter-reference-side bridge arm 200 act on the gate side and emitter-reference side of the IGBT, respectively. The drive circuit controls the corresponding switching devices to turn on or off according to the target operating state of the IGBT, thus forming a corresponding current path between the forward drive power supply VDD, the low-potential reference terminal, the drive resistor network 300, the gate G, and the emitter E.

[0031] The emitter reference node can be connected to the auxiliary emitter terminal or emitter terminal of the IGBT via a separately configured low-inductance connecting conductor, serving as a common reference for the gate-emitter drive voltage and emitter-side protection signals. The emitter reference node and the emitter power terminal carrying the main current have a potential relationship determined by the parasitic impedance of the connecting conductor or a predetermined sampling impedance. The low-inductance connecting conductor can be formed using a separately led-out short-distance wire, for example, a wire with a cross-sectional area of ​​6 square millimeters, and the low-inductance connecting conductor is not shared with the emitter circuit carrying the IGBT's main power current. Since the low-inductance connecting conductor is only used to establish a reference connection between the emitter reference node and the IGBT emitter and does not carry the main power circuit current, it can reduce the impact of parasitic inductance voltage drop caused by changes in the power circuit current on the emitter reference potential. For example, Figure 5The VE-R (Voltage - Emitter Reference) shown is the emitter reference node, and IGBT-E is the emitter power terminal or its detection lead. When the IGBT module has an auxiliary emitter terminal or a Kelvin emitter terminal, VE-R is preferably connected to the auxiliary emitter terminal; when no auxiliary emitter terminal is provided, VE-R is connected to the emitter terminal through an independent low-inductance conductor. VE-R serves as a local reference for driving and sensing, and is not equivalent to the low-potential reference terminal 0V / GND of the drive power supply. IGBT-E and VE-R are two different sampling locations on the same emitter connection path, and their steady-state potentials are basically the same; during switching transients, the parasitic inductance, parasitic resistance, or predetermined sampling impedance of the connection section generates a transient potential difference, which the DI / DT comparator uses to indirectly characterize the abnormal rate of change of current.

[0032] During normal turn-on, the gate-side bridge arm 100 provides drive current to the gate G through the turn-on branch 310. At the same time, the emitter reference-side bridge arm 200 makes the emitter reference node at the reference potential required for turn-on, thereby establishing a positive gate-emitter drive voltage between the gate G and the emitter E, and turning on the IGBT.

[0033] During normal turn-off, the gate-side bridge arm 100 releases the charge on the gate G through the turn-off branch 320 and adjusts the potential of the gate G towards the low potential reference terminal; the emitter reference-side bridge arm 200 adjusts the potential of the emitter reference node accordingly, so that the gate-emitter drive voltage drops to the turn-off range, thereby causing the IGBT to exit the conduction state.

[0034] During fault shutdown, the emitter reference side bridge arm 200 first adjusts the potential of the emitter reference node through the first fault shutdown branch 331 and then through the second fault shutdown branch 332, so that the drive voltage between the gate G and the emitter E changes according to the fault shutdown requirements. The emitter reference branch 340 is used to form a clamping / discharge path between the emitter reference node and the low-potential reference terminal.

[0035] This invention, through the configuration of a gate-side bridge arm 100 and an emitter reference-side bridge arm 200 that cooperate with each other, can adjust the gate potential and emitter reference potential of the IGBT separately, and form the gate-emitter drive voltage required for normal turn-on, normal turn-off, and fault turn-off through different branches. This structure can more effectively control the gate-emitter voltage under different operating conditions, enabling normal drive and fault turn-off to use independent paths, reducing the mutual influence between different drive states, and improving the controllability of the high-voltage direct-drive IGBT drive process and the reliability of fault turn-off.

[0036] like Figure 2As shown, the open branch 310 includes a first gate resistor RG1, which is connected between the second connection terminal of the first switching device Q1 and the gate G. The shutdown branch 320 includes a second gate resistor RG2, which is connected between the gate G and the first connection terminal of the second switching device Q4. The first fault shutdown branch 331 includes a first emitter-side resistor RE1, which is connected between the second connection terminal of the third switching device Q2 and the emitter reference node. The second fault shutdown branch 332 includes a second emitter-side resistor RE2, which is connected between the second connection terminal of the fourth switching device Q5 and the emitter reference node. The emitter reference branch 340 includes a third emitter-side resistor RE3, which is connected between the first connection terminal of the fifth switching device Q3 and the emitter reference node. The resistance value of the first emitter-side resistor RE1 is less than the resistance value of the second emitter-side resistor RE2.

[0037] like Figure 10 As shown, in the normal on-state, the first switching device Q1 and the fifth switching device Q3 are turned on, and the second switching device Q4, the third switching device Q2 and the fourth switching device Q5 are turned off, so that the positive drive power supply VDD charges the gate G through the on-state branch 310 and brings the emitter reference node close to the low potential reference terminal. In the normal off state, the first switching device Q1 and the fifth switching device Q3 are off, and the second switching device Q4, the third switching device Q2, and the fourth switching device Q5 are on, so that the gate G is discharged through the off branch 320 and the emitter reference node is adjusted to a relatively high potential. In the fault shutdown state, the first switching device Q1 and the fifth switching device Q3 are turned off. When the second switching device Q4 is in the conducting state before entering the fault shutdown state, the second switching device Q4 remains conducting. When the second switching device Q4 is in the off state before entering the fault shutdown state, the second switching device Q4 turns on after the first switching device Q1 is turned off and the gate dead time has elapsed. After the second switching device Q4 turns on, the first stage begins, the third switching device Q2 turns on and the fourth switching device turns off, so as to connect to the first fault shutdown branch 331. When the gate-emitter voltage of the IGBT drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device Q2 turns off, and after the emitter reference side commutation dead time has elapsed, the fourth switching device Q5 turns on, so as to connect to the second fault shutdown branch 332 and enter the second stage, until the gate-emitter voltage reaches the shutdown threshold or the duration of the second stage reaches the second preset duration.

[0038] Specifically, the first gate resistor RG1 in the turn-on branch 310 is connected between the output terminal of Q1 and the gate G of the IGBT, and the second gate resistor RG2 in the turn-off branch 320 is connected between the gate G of the IGBT and the input terminal of Q4. Thus, RG1 is used to limit the gate charging current, and RG2 is used to limit the gate discharging current. They correspond to the turn-on and normal turn-off processes, respectively, and should not be written as the same branch from the output terminal to the gate.

[0039] The output of Q2 is connected to the emitter reference node through the first emitter-side resistor RE1 in the first fault shutdown branch 331, and the output of Q5 is connected to the emitter reference node through the second emitter-side resistor RE2 in the second fault shutdown branch 332. Q3 is connected between the emitter reference node and the low-potential reference terminal, and the third emitter-side resistor RE3 in the emitter reference branch 340 is used to provide emitter reference, bleed, or clamping impedance.

[0040] It should be noted that RE1 and RE2 are fault-shutdown graded resistors on the emitter reference side, used to change VGE by adjusting the emitter reference node potential, rather than directly serving as discharge resistors from the gate to the low potential end. RG1 and RG2 have different functions than RE1 and RE2: RG1 and RG2 mainly limit the charging and discharging rate of the gate charge, while RE1 and RE2 mainly limit the rate of adjustment of the emitter reference side potential during fault shutdown.

[0041] The gate-side dead time TdG and emitter-reference-side commutation dead time TdE are determined based on the worst-case propagation delay difference of the corresponding upper and lower bridge arm control paths, the turn-off / turn-on delay of the switching devices, and the safety margin, respectively, to ensure that the next switching device is allowed to turn on only after the previous switching device has been reliably turned off. The first preset duration T1 and the second preset duration T2 can be preset by the delay circuit, or they can be used as early termination conditions when VGE reaches the first switching threshold and the turn-off threshold, respectively.

[0042] The first switching threshold is a preset gate-emitter voltage threshold used to determine the transition from the first stage to the second stage; the first preset duration is the maximum allowed duration of the first stage. The first stage ends when the gate-emitter voltage drops to the first switching threshold, or when the duration of the first stage reaches the first preset duration. The turn-off threshold is a preset gate-emitter voltage threshold used to determine when the IGBT meets the turn-off requirement; the second preset duration is the maximum allowed duration of the second stage. The second stage ends when the gate-emitter voltage reaches the turn-off threshold, or when the duration of the second stage reaches the second preset duration, and the drive circuit remains in a turn-off state adapted to fault turn-off.

[0043] During normal turn-on, Q1 is on, Q4 is off, Q2 and Q5 are off, and Q3 is on. At this time, VDD charges the gate G through Q1 and RG1, and the emitter reference node approaches the low-potential reference terminal through Q3. The gate establishes a positive VGE relative to the emitter, and the IGBT enters the turn-on state.

[0044] During normal turn-off, Q1 is off, Q4 is on, Q3 is off, and Q2 and Q5 are on simultaneously. At this time, the gate G releases charge to the low-potential reference terminal through RG2 and Q4, and the emitter reference node is adjusted to a relatively high potential through Q2, Q5 and the corresponding emitter-side resistors. The gate-emitter voltage changes from the turn-on voltage to the low voltage or negative voltage required for turn-off.

[0045] During fault shutdown, the normal turn-on path is first blocked, i.e., Q1 remains off; Q3 is off, and Q4 remains on depending on its conduction state before entering the fault shutdown state, or turns on after Q1 is off and the gate dead time has passed, allowing the gate G to discharge to the low potential reference terminal through the shutdown branch 320; in the first stage, Q2 is controlled to turn on, so that the emitter reference node is quickly adjusted through the small resistance RE1, thereby quickly reducing VGE and suppressing the fault current from continuing to rise; in the second stage, Q5 is controlled to turn on, so that the emitter reference node is restricted and adjusted through the large resistance RE2, thereby reducing the turn-off voltage spike and the dynamic voltage drop impact between series IGBTs.

[0046] Since the resistance of RE1 is less than that of RE2, the equivalent resistance of the first fault shutdown branch 331 is less than that of the second fault shutdown branch 332. This allows the fault shutdown process to accommodate both rapid VGE reduction and soft shutdown requirements. Furthermore, the third emitter-side resistor RE3, after turn-on, turn-off, or fault shutdown, can provide discharge and clamping relationships for the emitter reference node, reducing the risk of false turn-on caused by parasitic capacitive coupling.

[0047] In some embodiments, such as Figure 3 As shown, it also includes a command shaping interlock circuit 700 and a fault logic and latch feedback circuit 800; The command shaping interlock circuit 700 includes a command input circuit 710, a shaping logic circuit 720, an interlock logic circuit 730, and a delay circuit 740. The output terminal of the command input circuit 710 is connected to the input terminal of the shaping logic circuit 720, the output terminal of the shaping logic circuit 720 is connected to the input terminal of the interlock logic circuit 730, the delay circuit 740 is connected to the interlock logic circuit 730, and the output terminal of the interlock logic circuit 730 is connected to the control terminals of the first switching device Q1, the second switching device Q4, the third switching device Q2, the fourth switching device Q5, and the fifth switching device Q3, respectively. The fault logic and latch feedback circuit 800 includes a fault logic circuit 810 and a latch logic circuit 820. The output of the fault logic circuit 810 is connected to the input of the latch logic circuit 820, and the output of the latch logic circuit 820 is connected to the interlock logic circuit 730 to block the normal turn-on command and maintain the fault turn-off state after the fault signal is generated.

[0048] Specifically, the command input circuit 710 can be an optical fiber input circuit or an electrically isolated input circuit, used to receive the turn-on and turn-off commands sent by the upper-level controller, and generate the turn-on command signal C_ON and the turn-off command signal C_OFF respectively. Using isolated input of drive commands ensures electrical isolation between the upper-level controller and the high-voltage side drive circuit.

[0049] The shaping logic circuit 720 may include an inverter and connected resistors, capacitors, and diodes. After the ON command signal C_ON and OFF command signal C_OFF enter the shaping logic circuit 720, they are converted into signals whose levels and edges meet the requirements of subsequent logic stages. During the shaping process, input pulses with excessively short durations can also be suppressed to prevent transient changes at the input terminals from directly causing the bridge arm switches to operate.

[0050] The interlock logic circuit 730 may include inverters, NAND gates, and NOR gates. The shaped turn-on and turn-off command signals are respectively input to the interlock logic circuit 730. The interlock logic circuit 730 generates control signals for each switching transistor based on the level combination of the two commands. The output control signals are sent to the control terminals of each switching transistor to control each transistor to operate according to the corresponding turn-on or turn-off sequence. When the turn-on command is valid, the interlock logic circuit 730 outputs a control signal corresponding to the IGBT's turn-on state; when the turn-off command is valid, the interlock logic circuit 730 outputs a control signal corresponding to the IGBT's turn-off state. The interlock logic circuit 730 performs logical restrictions on C_ON and C_OFF to prevent the turn-on control signal and the turn-off control signal from being valid simultaneously.

[0051] The delay circuit 740 can be formed by an RC delay network consisting of resistors and capacitors, and is set in the transmission path of the turn-on control signal and the turn-off control signal. When the drive state switches from turn-on to turn-off, or from turn-off to turn-on, the RC delay network first disables the control signal of the original conducting switch, and then outputs the control signal of another set of switches after a preset delay time, thereby forming a dead time between the two sets of control signals. This dead time is formed between the first switch Q1 and the second switch Q4 on the gate side bridge arm, and between the third switch Q2, the fourth switch Q5 and the fifth switch Q3 on the emitter reference side bridge arm, preventing the pull-up switch and the pull-down switch on the same bridge arm from being turned on simultaneously and forming a direct path from the positive drive power supply to the low potential reference terminal.

[0052] The fault logic circuit 810 is used to receive the fault level and the current drive command status. Since different protection signals may be active high or active low, the fault logic circuit 810 can first unify the effective polarity of each input signal using an inverter, and then logically combine the enable judgment condition, drive command status, and fault status using AND and OR gates. In one example, such as... Figure 9 As shown, the fault logic circuit 810 includes multiple logic gate devices U8A, U8B, U8C, U9B, U9C, U10C, U6D, U6E, U6F, and U10D. The input signals of the fault logic circuit 810 can include desaturation protection signals OC1, OC2, OC3, DI / DT protection signal, VGE protection signal, and drive power supply abnormality signal BGV / FLT-POW. The desaturation protection signals OC1, OC2, and OC3 are combined and processed by the logic gate devices. The DI / DT protection signal, VGE protection signal, and drive power supply abnormality protection signal BGV are combined and processed by their respective logic gate devices. Simultaneously, the validity of the signals is determined by combining the drive status signals PWM and P_OFF, ultimately generating the fault trigger signal FAULT.

[0053] After the FAULT signal is input to the latching logic circuit 820, the latching logic circuit 820 is set and outputs the FLT signal. Even if the transient abnormality causing the FAULT signal subsequently disappears, the FLT signal remains in a fault state to prevent the drive circuit from immediately resuming normal operation. After the FLT signal is fed back to the interlocking logic circuit 730, it prevents C_ON from continuing to be transmitted to the gate-side bridge arm 100 and the emitter-reference-side bridge arm 200, and keeps the interlocking logic circuit 730 in a control state adapted to fault shutdown.

[0054] During normal operation, C_ON or C_OFF is processed sequentially by the shaping logic circuit 720, the interlocking logic circuit 730, and the delay circuit 740 to form the control signals for each switching transistor. In the event of a fault, the fault logic circuit 810 outputs a FAULT signal, which is converted into a continuously valid FLT signal by the latching logic circuit 820. The FLT signal returns to the interlocking logic circuit 730 and blocks the normal turn-on command, preventing the IGBT from being re-triggered due to a brief recovery of the protection signal during a momentary fault.

[0055] In this embodiment of the invention, by setting a command shaping interlock circuit 700, the drive command can be shaped, interlocked, and delayed, so that the control process of each switching transistor meets the timing constraints and reduces the risk of conflicting drive signals occurring simultaneously. By setting a fault logic and latch feedback circuit 800, the fault state output by the fault logic circuit 810 can be maintained, and the latch result can be fed back to the interlock logic circuit 730, so that the normal drive process can be continuously suppressed after a fault occurs, avoiding repeated triggering of the turn-on action under fault conditions and improving the safety of the drive circuit.

[0056] In some embodiments, such as Figure 4 As shown, the driving circuit of the high voltage direct-series IGBT also includes a static voltage equalization and dynamic sampling coordination circuit 400. The static voltage equalization and dynamic sampling coordination circuit 400 includes a static voltage equalization resistor R1, a series resistor circuit 410, a series capacitor circuit 420, and a diode clamping circuit 430. The static voltage equalization resistor R1 is connected in parallel between the collector and emitter of the IGBT; The series resistor circuit 410 is connected between the collector of the IGBT and the collector-side sampling node. The series capacitor circuit 420 is connected in parallel with the series resistor circuit 410. The collector-side sampling node is located on the low-voltage side away from the collector of the IGBT by the series resistor circuit 410 and the series capacitor circuit 420, and is used to form a sampling signal characterizing the change of the collector potential of the IGBT. The diode clamping circuit 430 is connected between the collector of the IGBT and the clamping sampling node, and is used to convert the dynamic change of the IGBT collector-emitter voltage into a clamping sampling signal with a voltage amplitude within the allowable range of the subsequent protection circuit.

[0057] Specifically, the static voltage equalization resistor R1 can be a resistor whose voltage rating and power rating meet the requirements of the direct-connected IGBTs. The static voltage equalization resistor R1 is connected in parallel between the collector and emitter of each IGBT, providing a parallel shunt path for the corresponding IGBT. When the resistance values ​​of all static voltage equalization resistors are the same or close, the current flowing through the static voltage equalization resistor R1 is greater than the voltage division error current caused by the leakage current dispersion of the devices, making the bus voltage approximately uniformly distributed among the series-connected IGBTs.

[0058] The series resistor circuit 410 and the series capacitor circuit 420 constitute a dynamic sampling chain. The voltage change on the collector side of the IGBT is processed by the dynamic sampling chain and a VC sampling signal is formed at the collector-side sampling node VC (Voltage-Collector). The diode clamping circuit 430 clamps the dynamic voltage on the collector side of the IGBT and forms a clamping sampling signal at the clamping sampling node V-CE2 (Voltage-Collector-Emitter 2). V-CE1 is a gate-side auxiliary sampling node, formed by the gate-side auxiliary clamping and sampling network.

[0059] The series resistor circuit 410 and series capacitor circuit 420 perform current limiting, voltage division, and dynamic coupling on the collector-side voltage of the IGBT, forming the VC signal at the collector-side sampling node. The diode clamping circuit 430 clamps the dynamic voltage on the collector side of the IGBT, forming the V-CE2 signal at the clamped sampling node. V-CE1 is formed by the gate-side auxiliary clamping and sampling network. VC, V-CE1, and V-CE2 are formed by their respective branches, and there is no sequential conversion of VC to V-CE1 and V-CE2. When the IGBT is turned on, each sampling signal responds to the decrease of VCE according to the transmission relationship of its corresponding branch; when the IGBT is turned off, each sampling signal responds to the increase of VCE according to the transmission relationship of its corresponding branch.

[0060] By setting up a static voltage equalization and dynamic sampling coordination circuit 400, the present invention can reduce the steady-state voltage division deviation caused by the difference in leakage current of the device using the static voltage equalization resistor R1. Through the series resistor circuit 410, the series capacitor circuit 420 and the diode clamping circuit 430, the change of VCE on the high-voltage side is converted into a low-voltage sampling signal that can be processed by the subsequent detection circuit, so as to identify the asynchronous dynamic response or abnormal dynamic voltage division of the series IGBT.

[0061] In some embodiments, such as Figure 3 and Figure 5 As shown, the driving circuit of the high-voltage direct-series IGBT also includes a DI / DT protection circuit 500. The DI / DT protection circuit 500 includes a DI / DT comparator 510 and a DI / DT threshold voltage divider network 520. The emitter-side dynamic sampling node is connected to the emitter power terminal of the IGBT or its detection lead. The first input terminal of the DI / DT comparator 510 is connected to the emitter-side dynamic sampling node, the second input terminal of the DI / DT comparator 510 is connected to the emitter reference node and the DI / DT threshold voltage divider network 520, and the output terminal of the DI / DT comparator 510 is connected to the input terminal of the fault logic circuit 810, so as to indirectly characterize the di / dt abnormality through the emitter-side dynamic potential difference.

[0062] Specifically, the DI / DT protection circuit 500 is used to determine the threshold of the transient potential difference between the IGBT-E (emitter power terminal detection point) and the emitter reference node VE-R. This transient potential difference is generated by the parasitic inductance, parasitic resistance, or predetermined sampling impedance of the connecting conductor when the current changes rapidly, and does not use the VC or V-CE2 signal of the static voltage equalization and dynamic sampling coordination circuit 400 as input. The DI / DT threshold voltage divider network 520 is used to establish a comparison threshold. A preset comparison threshold is formed by the reference voltage and the voltage divider resistors, and the reference node is filtered and clamped by corresponding capacitors and diodes. When the dynamic potential difference between the IGBT-E side sampling signal and the VE-R side reference signal reaches the comparison threshold, the output state of the DI / DT comparator 510 changes, forming a DI / DT abnormality detection signal.

[0063] The DI / DT comparator 510 compares the emitter-side dynamic sampling signal with the emitter reference signal and a comparison threshold. The emitter-side dynamic sampling signal is formed by the IGBT-E terminal of the IGBT through an input resistor, and the emitter reference signal is formed by the emitter reference node VE-R and the DI / DT threshold voltage divider network 520. The DI / DT protection circuit 500 does not directly measure the rate of change of the main circuit current, but compares the dynamic potential difference between the corresponding signals of IGBT-E and VE-R. The dynamic potential difference changes rapidly with the current during the IGBT's turn-on or turn-off process, and can be used to indirectly characterize di / dt anomalies.

[0064] The comparator's operating state is controlled by C_ON, C_OFF, and blanking signals to avoid misjudging normal switching transients as faults. After the IGBT starts to turn on or off, the control logic starts the blanking timer according to the corresponding switch control signal. During the blanking time, the DI / DT comparison results caused by normal switching transients are masked. After the blanking time ends, the output of the DI / DT comparator 510 is used to determine whether the dynamic potential change on the emitter side is abnormal, in order to reduce misjudgments caused by normal switching transients.

[0065] In one example, the output node of the DI / DT comparator 510 is pulled up by a resistor connected to the positive power supply. When the DI / DT comparator 510 operates, its output node is pulled low; therefore, the DI / DT fault detection signal is an active low signal. After indication and filtering, the DI / DT fault detection signal is sent to the fault logic circuit 810, which, in conjunction with drive commands and other protection signals, determines whether to execute fault blocking or fault shutdown.

[0066] This invention, by setting up a DI / DT protection circuit 500 and enabling the DI / DT comparator 510 to receive the emitter-side dynamic sampling signal, the emitter reference signal, and the threshold signal formed by the DI / DT threshold voltage divider network 520, can compare and judge the dynamic potential difference on the emitter side. When a switching transient or fault transient causes the dynamic potential difference on the emitter side to exceed the comparison threshold, the DI / DT comparator 510 can output a corresponding signal to the fault logic circuit 810, enabling the drive circuit to respond to rapidly changing abnormal states in a timely manner and improving the response speed to fault transients.

[0067] In some embodiments, such as Figure 6 As shown, the driving circuit of the high voltage direct-series IGBT also includes a desaturation protection circuit 600, which includes a first desaturation protection branch, a second desaturation protection branch and a third desaturation protection branch. The first desaturation protection branch 610 includes a first input network and a first comparator U3A. The input terminal of the first input network is connected to the collector-side sampling node, and the output terminal of the first input network forms a first sampling signal and is connected to the sampling-side input terminal of the first comparator U3A. The first comparator U3A forms a fast short-circuit or hard desaturation protection signal based on the first sampling signal. The second desaturation protection branch 620 includes a second input network and a second comparator U4C. The input terminal of the second input network is connected to the clamping sampling node, and the output terminal of the second input network forms a second sampling signal and is connected to the sampling side input terminal of the second comparator U4C. After the blanking time ends, the second comparator U4C forms a desaturation confirmation signal based on the second sampling signal. The third desaturation protection branch 630 includes a third comparator U4D. The sampling input terminal of the third comparator U4D is connected to the output terminal of the second input network to share the second sampling signal with the second desaturation protection branch 620. The third desaturation protection branch 630 has a comparison threshold or filtering time constant that is different from that of the second desaturation protection branch 620.

[0068] Specifically, the first input network includes an input resistor R4 and a filter capacitor C1. The VC signal is processed by the first input network to form a first sampling signal, which is then sent to the first comparator U3A. The second input network includes an input resistor R38, a voltage divider resistor R35, and a filter capacitor C32. The V-CE2 signal is processed by the second input network to form a second sampling signal, which is simultaneously sent to the second comparator U4C and the third comparator U4D. The second comparator U4C and the third comparator U4D each use different threshold voltage divider networks to form different decision conditions.

[0069] Both the first sampling signal and the second sampling signal can be analog voltage signals relative to the low potential reference terminal of the driving circuit. The first sampling signal is formed by processing the sampling signal of the collector-side sampling node through the first input network, and the second sampling signal is formed by processing the clamping sampling signal of the clamping sampling node through the second input network.

[0070] The first desaturation protection branch compares the first sampled signal with the first comparison threshold and improves the response speed through a shorter filtering time or a faster comparison path. When VCE remains at a high level after the IGBT is turned on and the judgment conditions corresponding to severe short circuit or hard desaturation are met, the first comparator U3A outputs the OC1 signal.

[0071] The second desaturation protection branch compares the second sampled signal with the second comparison threshold. After the blanking is completed, if the second sampled signal corresponding to V-CE2 still does not enter the range corresponding to the normal saturation conduction state, the second comparator U4C outputs the OC2 signal to confirm the desaturation after blanking.

[0072] The third desaturation protection branch shares the second sampling signal with the second desaturation protection branch, and compares this second sampling signal with the third comparison threshold. The threshold setting and RC parameters corresponding to the third comparator U4D can form a comparison threshold or time constant that is different from that of the second desaturation protection branch, so that the third comparator U4D can assist in confirming slow overcurrent, VCE continuously high or dynamic voltage division abnormality, and output the OC3 signal.

[0073] OC1, OC2, and OC3 are fed into the fault logic circuit 810. OC1 is used to generate a fast short-circuit or hard desaturation protection request, OC2 is used for desaturation confirmation after blanking, and OC3 is used for auxiliary confirmation of slower overcurrent or dynamic voltage division anomalies. It can also be combined with the DI / DT protection signal, gate voltage detection signal, or drive command status for judgment, to reduce the possibility of malfunctions caused by transient noise. In one example, the outputs of OC1, OC2, and OC3 are all equipped with pull-up circuits, and the corresponding protection signals are active low.

[0074] This invention employs a three-stage desaturation protection branch. The first and second desaturation protection branches each include an input network and a comparator, while the third desaturation protection branch includes a third comparator and shares a second input network with the second desaturation protection branch. The second and third comparators use different comparison thresholds or filtering time constants. These different desaturation protection branches can correspond to different degrees or different judgment conditions of desaturation, avoiding the problem of overly simplistic protection responses caused by relying solely on a single threshold. This achieves a better balance between response speed and resistance to false triggering in the desaturation protection.

[0075] In some embodiments, such as Figure 3 , Figure 7 and Figure 8 As shown, it also includes an auxiliary protection circuit 900, which includes a gate voltage detection circuit 910 and a drive power supply detection circuit 920. The gate voltage detection circuit 910 includes a VGE sampling circuit 911 and a VGE window comparator 912. The VGE sampling circuit 911 is connected between the gate and the emitter, and the VGE window comparator 912 is used to determine whether the gate-emitter voltage is within the allowable voltage window of the corresponding driving state. The drive power detection circuit 920 includes a power divider circuit 921 and a power window comparator 922. The power divider circuit 921 is connected to the positive drive power supply, the logic power supply and the reference power supply respectively. The input terminal of the power window comparator 922 is connected to the power divider circuit 921 and the output terminal of the power window comparator 922 is connected to the fault logic circuit 810.

[0076] Specifically, the gate voltage detection circuit 910 is used to detect the VGE state between the IGBT gate and emitter. The VGE sampling circuit 911 consists of IGBT-G, IGBT-E, and an emitter reference branch. The gate signal and emitter signal are fed into the VGE window comparator 912 after current limiting, voltage division, RC filtering, and diode clamping. The VGE window comparator 912 includes an upper limit comparator U1A and a lower limit comparator U1B. The upper limit comparator U1A compares the VGE sampled signal with the VGE upper limit threshold, and the lower limit comparator U1B compares the VGE sampled signal with the VGE lower limit threshold to form a VGE allowable voltage window. When the turn-on command is valid, the VGE allowable voltage window is used to determine whether VGE has reached the minimum voltage required for turn-on and whether it has exceeded the maximum allowable positive voltage. When the turn-off command is valid, the lower limit comparison result is used to determine whether VGE has reached the negative voltage range required for turn-off. When VGE is lower than the lower threshold of the corresponding driving state or higher than the upper threshold, the upper limit comparator U1A or the lower limit comparator U1B will activate, causing the common output node to form a VGE fault signal that is active low, and the VGE fault signal will be sent to the fault logic circuit 810.

[0077] The gate voltage detection circuit 910 also generates a BGV signal based on the fault signal FLT / and the IGBT gate state signal. Specifically, the fault signal FLT / and the gate state signal corresponding to IGBT-G are processed by logic devices U1C and U1D to determine whether the fault state is consistent with the gate voltage state. When the gate is still in a state that does not meet the turn-off requirements under the fault state, or when the gate state is inconsistent with the expected drive state, a low-level active BGV fault signal is output. The BGV fault signal is sent to the fault logic circuit 810 for auxiliary confirmation of the gate drive state.

[0078] The drive power supply detection circuit 920 is used to detect the power supply status of the drive circuit itself. The power supply voltage divider circuit 921 divides the voltage of each detected drive power supply and filters out high-frequency fluctuations in the power supply sampling signal through an RC network. The power supply window comparator 922 compares each divided voltage signal with its corresponding upper and lower limit reference voltages; when any detected power supply exceeds its corresponding predetermined window, the power supply window comparator 922 outputs an FLT-POW fault signal. This fault signal is sent to the fault logic circuit 810 and interlocked with C_ON and C_OFF to keep the bridge arm in a defined off state during power supply abnormalities, preventing the IGBT from being in a half-on state due to insufficient drive voltage. The power supply window comparator 922 includes window comparison branches corresponding to the +17V and +5V power supplies, respectively. For the +17V power supply, U5A and U5B perform upper and lower limit comparisons, respectively; for the +5V power supply, U5C performs a lower limit comparison, and U5D performs an upper limit comparison. The outputs of all comparators are connected to a common output node and pulled up to +5V via R109. When any detected power supply is higher than the corresponding upper threshold or lower than the corresponding lower threshold, the corresponding comparator activates, pulling the common output node low and generating a low-level active FLT-POW fault signal.

[0079] This invention, by setting up an auxiliary protection circuit 900, can detect the gate-emitter voltage state and the drive power supply state separately; the VGE sampling circuit 911, in conjunction with the VGE window comparator 912, can determine whether the gate drive voltage is within the allowable voltage window of the corresponding drive state; the power supply voltage divider circuit 921, in conjunction with the power supply window comparator 922, can determine whether each detected drive power supply is within its corresponding allowable voltage window. After the above detection results enter the fault logic circuit 810, the risk of continuing to drive the IGBT under conditions of insufficient gate voltage or abnormal drive power supply can be reduced, improving the protection integrity of the drive circuit.

[0080] This invention provides a driving method for a high-voltage direct-drive IGBT, such as... Figure 11 As shown, the driving circuit applicable to the high-voltage direct-series IGBT in the above embodiments includes: Step S101: Receive the drive command and determine the target drive state of the IGBT according to the drive command. The target drive state includes normal turn-on state, normal turn-off state and fault turn-off state.

[0081] In one example, the normal on state corresponds to the C_ON signal, the normal off state corresponds to the C_OFF signal, and the fault off state corresponds to the FLT signal.

[0082] Step S102: When the target drive state is in the normal on state, control the first switch device Q1 and the fifth switch device Q3 to be turned on, and control the second switch device Q4, the third switch device Q2 and the fourth switch device Q5 to be turned off.

[0083] Step S103: When the target drive state is in the normal off state, control the first switch Q1 and the fifth switch Q3 to turn off, and control the second switch Q4, the third switch Q2 and the fourth switch Q5 to turn on.

[0084] Step S104: When the target drive state is in the fault shutdown state, control the first switch Q1 and the fifth switch Q3 to turn off; when the second switch Q4 is in the on state before entering the fault shutdown state, control the second switch Q4 to remain on; when the second switch Q4 is in the off state before entering the fault shutdown state, control the second switch Q4 to turn on after the first switch Q1 is turned off and the gate dead time has elapsed; and control the third switch Q2 and the fourth switch Q5 to connect to the first fault shutdown branch 331 and the second fault shutdown branch 332 in stages.

[0085] During normal turn-on, control Q1 and Q3 are turned on, while Q4, Q2, and Q5 are turned off, and VGE is established as a positive drive voltage. During normal turn-off, control Q1 and Q3 are turned off, while Q4, Q2, and Q5 are turned on, and VGE switches to a low voltage or negative drive voltage. During fault turn-off, Q1 and Q3 are turned off, and Q4 remains on depending on its conduction state before entering the fault turn-off state, or turns on after Q1 is turned off and the gate dead time has elapsed. Q2 and Q5 are turned on in stages according to a predetermined timing sequence, and VGE first drops rapidly and then drops with limitation.

[0086] In some embodiments, such as Figure 12 As shown, in step S104 above, the first fault shutdown branch 331 and the second fault shutdown branch 332 are connected in stages by controlling the third switching device Q2 and the fourth switching device Q5, including: In step S1041, the third switching device Q2 is turned on and the fourth switching device Q5 is turned off in the first stage, so that the emitter reference node is quickly adjusted through the first fault turn-off branch 331 to quickly reduce the gate-emitter voltage. In step S1042, when the gate-emitter voltage drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device Q2 is controlled to turn off. After the commutation dead time on the emitter reference side, the fourth switching device Q5 is controlled to turn on and enter the second stage, so that the emitter reference node is restricted and regulated through the second fault shutdown branch 332 to reduce the shutdown voltage spike and the dynamic voltage division impact of the direct-series IGBT. When the gate-emitter voltage reaches the shutdown threshold or the duration of the second stage reaches the second preset duration, the second stage ends and the fault shutdown state is maintained.

[0087] Specifically, the fault shutdown process includes two stages. In the first stage, the third switching device Q2 is turned on, and the fourth switching device Q5 is turned off, selecting the first fault shutdown branch where RE1 is located. This utilizes a smaller resistance value to quickly adjust the emitter reference node potential, thereby reducing VGE as quickly as possible. In the second stage, the third switching device Q2 is turned off, and the fourth switching device Q5 is turned on, selecting the second fault shutdown branch where RE2 is located. This utilizes a larger resistance value to limit the rate of change of the emitter reference node potential, thereby reducing the risk of shutdown spike voltage and abnormal dynamic voltage division of the direct-series IGBTs. The fault shutdown state is that Q1, Q2, and Q3 are off, and Q4 and Q5 are on.

[0088] In the above method, DI / DT protection, OC1, OC2, OC3, VGE detection, and drive power detection can all be used as inputs to the fault logic circuit 810. After the fault logic circuit 810 outputs the FAULT signal, the latching logic circuit 820 maintains the fault state and feeds it back to the interlocking logic circuit 730, thus blocking the normal turn-on command and preventing the IGBT from restarting after the fault signal is briefly restored.

[0089] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A driving circuit for a high-voltage direct-connect IGBT, used to drive any IGBT in a high-voltage direct-connect branch, characterized in that, This includes the gate-side bridge arm, the emitter-reference-side bridge arm, and the drive resistor network; The driving resistor network includes an on branch, an off branch, a first fault off branch, a second fault off branch, and an emitter reference branch. The gate-side bridge arm includes a first switching device and a second switching device. The first connection terminal of the first switching device is connected to the forward drive power supply, and the second connection terminal of the first switching device is connected to the gate of the IGBT through the turn-on branch. The first connection terminal of the second switching device is connected to the gate through the turn-off branch, and the second connection terminal of the second switching device is connected to a low-potential reference terminal. The emitter reference side bridge arm includes a third switching device, a fourth switching device, and a fifth switching device. The first connection terminals of the third switching device and the fourth switching device are both connected to the forward drive power supply. The second connection terminal of the third switching device is connected to the emitter reference node of the IGBT through the first fault shutdown branch. The second connection terminal of the fourth switching device is connected to the emitter reference node through the second fault shutdown branch. The first connection terminal of the fifth switching device is connected to the emitter reference node through the emitter reference branch. The second connection terminal of the fifth switching device is connected to the low potential reference terminal. The gate-side bridge arm is used to adjust the potential of the gate, and the emitter reference-side bridge arm is used to adjust the potential of the emitter reference node, so as to form the gate-emitter drive voltage required for turn-on, turn-off or fault turn-off between the gate and the emitter. The emitter reference node is a local reference node that is electrically connected to the auxiliary emitter end or emitter end of the IGBT through an independently set low-inductance connection conductor.

2. The driving circuit for a high-voltage direct-drive IGBT according to claim 1, characterized in that, The open branch includes a first gate resistor, which is connected between the second connection terminal of the first switching device and the gate. The shutdown branch includes a second gate resistor, which is connected between the gate and the first connection terminal of the second switching device; The first fault shutdown branch includes a first emitter-side resistor, which is connected between the second connection terminal of the third switching device and the emitter reference node. The second fault shutdown branch includes a second emitter-side resistor, which is connected between the second connection terminal of the fourth switching device and the emitter reference node; The emitter reference branch includes a third emitter-side resistor, which is connected between the first connection terminal of the fifth switching device and the emitter reference node. The resistance value of the first emitter-side resistor is less than the resistance value of the second emitter-side resistor.

3. The driving circuit for a high-voltage direct-drive IGBT according to claim 2, characterized in that, In the normal on-state, the first and fifth switching devices are turned on, while the second, third, and fourth switching devices are turned off, so that the forward drive power supply charges the gate through the on-state branch and brings the emitter reference node close to the low-potential reference terminal. In the normal shutdown state, the first and fifth switching devices are turned off, while the second, third, and fourth switching devices are turned on, causing the gate to discharge through the shutdown branch and the emitter reference node to be adjusted to a relatively high potential. In the fault shutdown state, the first switching device and the fifth switching device are turned off; When the second switching device is in the on state before entering the fault shutdown state, the second switching device remains on. When the second switching device is in the off state before entering the fault shutdown state, the second switching device turns on after the first switching device turns off and the gate dead time has elapsed. After the second switching device turns on, the first stage is entered, where the third switching device turns on and the fourth switching device turns off to connect to the first fault shutdown branch. When the gate-emitter voltage of the IGBT drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device is turned off, and after the commutation dead time on the emitter reference side, the fourth switching device is turned on to connect to the second fault shutdown branch and enter the second stage, until the gate-emitter voltage reaches the shutdown threshold or the duration of the second stage reaches the second preset duration.

4. The driving circuit for a high-voltage direct-drive IGBT according to any one of claims 1 to 3, characterized in that, It also includes command shaping interlock circuitry and fault logic and latch feedback circuitry; The command shaping interlock circuit includes a command input circuit, a shaping logic circuit, an interlock logic circuit, and a delay circuit. The output terminal of the command input circuit is connected to the input terminal of the shaping logic circuit, the output terminal of the shaping logic circuit is connected to the input terminal of the interlock logic circuit, the delay circuit is connected to the interlock logic circuit, and the output terminal of the interlock logic circuit is connected to the control terminals of the first switching device, the second switching device, the third switching device, the fourth switching device, and the fifth switching device, respectively. The fault logic and latch feedback circuit includes a fault logic circuit and a latch logic circuit. The output of the fault logic circuit is connected to the input of the latch logic circuit, and the output of the latch logic circuit is connected to the interlock logic circuit, so as to block the normal turn-on command and maintain the fault-off state after the fault signal is generated.

5. The driving circuit for a high-voltage direct-drive IGBT according to claim 4, characterized in that, It also includes a static voltage equalization and dynamic sampling coordination circuit, which includes a static voltage equalization resistor, a series resistor circuit, a series capacitor circuit, and a diode clamping circuit. The static voltage equalization resistor is connected in parallel between the collector and emitter of the IGBT; The series resistor circuit is connected between the collector of the IGBT and the collector-side sampling node. The series capacitor circuit is connected in parallel with the series resistor circuit. The collector-side sampling node is located on the low-voltage side of the series resistor circuit and the series capacitor circuit, away from the collector of the IGBT, and is used to form a sampling signal characterizing the change of the collector potential of the IGBT. The diode clamping circuit is connected between the collector of the IGBT and the clamping sampling node, and is used to convert the dynamic change of the IGBT collector-emitter voltage into a clamping sampling signal with a voltage amplitude within the allowable range of the subsequent protection circuit.

6. The driving circuit for a high-voltage direct-drive IGBT according to claim 5, characterized in that, It also includes a DI / DT protection circuit, which includes a DI / DT comparator and a DI / DT threshold voltage divider network. The emitter-side dynamic sampling node is connected to the emitter power terminal of the IGBT or its detection lead. The first input terminal of the DI / DT comparator is connected to the emitter-side dynamic sampling node, the second input terminal of the DI / DT comparator is connected to the emitter reference node and the DI / DT threshold voltage divider network, and the output terminal of the DI / DT comparator is connected to the input terminal of the fault logic circuit, so as to indirectly characterize the di / dt abnormality through the emitter-side dynamic potential difference.

7. The driving circuit for a high-voltage direct-drive IGBT according to claim 5, characterized in that, It also includes a desaturation protection circuit, which includes a first desaturation protection branch, a second desaturation protection branch, and a third desaturation protection branch; The first desaturation protection branch includes a first input network and a first comparator. The input terminal of the first input network is connected to the collector-side sampling node. The output terminal of the first input network forms a first sampling signal and is connected to the sampling-side input terminal of the first comparator. The first comparator forms a fast short-circuit or hard desaturation protection signal based on the first sampling signal. The second desaturation protection branch includes a second input network and a second comparator. The input terminal of the second input network is connected to the clamping sampling node, and the output terminal of the second input network forms a second sampling signal and is connected to the sampling side input terminal of the second comparator. After the blanking time ends, the second comparator forms a desaturation confirmation signal based on the second sampling signal. The third desaturation protection branch includes a third comparator, the sampling input of which is connected to the output of the second input network to share the second sampling signal with the second desaturation protection branch, and the third desaturation protection branch has a comparison threshold or filtering time constant different from that of the second desaturation protection branch.

8. The driving circuit for a high-voltage direct-drive IGBT according to claim 4, characterized in that, It also includes an auxiliary protection circuit, which includes a gate voltage detection circuit and a drive power supply detection circuit; The gate voltage detection circuit includes a VGE sampling circuit and a VGE window comparator. The VGE sampling circuit is connected between the gate and the emitter, and the VGE window comparator is used to determine whether the gate-emitter voltage is within the allowable voltage window of the corresponding driving state. The drive power detection circuit includes a power divider circuit and a power window comparator. The power divider circuit is connected to the positive drive power supply, the logic power supply and the reference power supply respectively. The input terminal of the power window comparator is connected to the power divider circuit and the output terminal of the power window comparator is connected to the fault logic circuit.

9. A driving method for a high-voltage direct-drive IGBT, characterized in that, A drive circuit for a high-voltage direct-drive IGBT according to any one of claims 1 to 8, comprising: Receive a drive command and determine the target drive state of the IGBT based on the drive command. The target drive state includes a normal turn-on state, a normal turn-off state, and a fault turn-off state. When the target drive state is in the normal on state, the first switch device and the fifth switch device are controlled to be turned on, and the second switch device, the third switch device and the fourth switch device are controlled to be turned off. When the target drive state is in the normal off state, the first switch device and the fifth switch device are controlled to turn off, and the second switch device, the third switch device and the fourth switch device are controlled to turn on. When the target drive state is a fault shutdown state, the first and fifth switching devices are controlled to turn off; when the second switching device is in the on state before entering the fault shutdown state, the second switching device is controlled to remain on; when the second switching device is in the off state before entering the fault shutdown state, the second switching device is controlled to turn on after the first switching device is turned off and the gate dead time has elapsed; and the third and fourth switching devices are controlled to connect to the first fault shutdown branch and the second fault shutdown branch in stages.

10. The driving method for a high-voltage direct-drive IGBT according to claim 9, characterized in that, The step of controlling the third and fourth switching devices to connect to the first fault shutdown branch and the second fault shutdown branch in stages includes: In the first stage, the third switching device is turned on and the fourth switching device is turned off, so that the emitter reference node is quickly adjusted through the first fault shutdown branch to quickly reduce the gate-emitter voltage. When the gate-emitter voltage drops to the first switching threshold or the duration of the first stage reaches the first preset duration, the third switching device is controlled to turn off. After the commutation dead time on the emitter reference side, the fourth switching device is controlled to turn on and enter the second stage, so that the emitter reference node is restricted and regulated through the second fault shutdown branch to reduce the shutdown voltage spike and the dynamic voltage division impact of the direct-series IGBT. When the gate-emitter voltage reaches the shutdown threshold or the duration of the second stage reaches the second preset duration, the second stage ends and the fault shutdown state is maintained.

Images