Circuit structures and methods having a resistor and multiple discharge circuits for reducing the clamping voltage released at a device control node

Abstract

Embodiments of the present disclosure provide circuit structures and methods having a resistor and multiple discharge circuits for reducing a pad voltage discharged at a device control node. The structures of the present disclosure include a first trigger circuit connected between a pad and a ground node. A first discharge circuit is connected between the pad and the ground node, where the first discharge circuit is connected to an output node of the first trigger circuit. A second trigger circuit can be connected in parallel with the first trigger circuit between the pad and the ground node. A resistor has a first end connected to the pad and a second end opposite the first end. A second discharge circuit is connected between the second end of the resistor and the ground node. The second discharge circuit is connected to an output node of the first trigger circuit or the second trigger circuit. Related methods are provided.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to electronic circuits. More specifically, various embodiments of this disclosure provide circuit structures and methods that affect the pad voltage of a release. Background Technology

[0002] Circuitry including integrated circuits (ICs) may include discharge elements to protect device hardware from events such as electrostatic discharge (ESD) voltages, which can cause short circuits, dielectric breakdown, and / or other failure modes. In an ideal setup, the ESD element has no effect on device operation until an ESD event occurs at a pin on the IC, where the ESD event turns on the ESD element and releases current to the power or ground rail. The ESD element is not used for any operational purpose until a trigger voltage is applied to activate it.

[0003] As device dimensions continue to shrink, the operating parameters of discharge elements, such as those in ESD protection circuits, are becoming increasingly sensitive. For example, for all operations below a predetermined maximum operating voltage, the discharge element needs to remain in an "off" state. However, at voltages above the predetermined maximum operating voltage but below the device's breakdown voltage level, the discharge element needs to become active. Conventional configurations of discharge elements can no longer provide a stable maximum operating voltage sufficiently below the breakdown voltage, potentially posing a risk of negatively impacting some devices even when the discharge element operates as intended. Summary of the Invention

[0004] Some aspects of this disclosure provide a structure comprising: a first trigger circuit connected between a pad and a ground node; a first discharge circuit connected between the pad and the ground node, wherein the first discharge circuit is connected to an output node of the first trigger circuit; a second trigger circuit connected in parallel with the first trigger circuit between the pad and the ground node; a resistor having a first end connected to the pad and a second end opposite to the first end; and a second discharge circuit connected between the second end of the resistor and the ground node, wherein the second discharge circuit is connected to an output node of the second trigger circuit.

[0005] Another aspect of this disclosure provides a structure comprising: a trigger circuit connected between a pad and a ground node; a first discharge circuit connected between the pad and the ground node, wherein the first discharge circuit is connected to an output node of the trigger circuit; a resistor having a first end connected to the pad and a second end opposite to the first end; and a second discharge circuit connected between the second end of the resistor and the ground node, wherein the second discharge circuit is connected to the output node of the trigger circuit.

[0006] An additional aspect of this disclosure provides a method comprising: providing a structure including: a pad; a first discharge circuit connected between the pad and a ground node; a resistor having a first end connected to the pad and a second end opposite to the first end; and a second discharge circuit connected between the second end of the resistor and the ground node; activating the first discharge circuit when the pad voltage on the pad is higher than a first predetermined operating voltage; and simultaneously activating the second discharge circuit when the pad voltage on the pad is higher than a second predetermined operating voltage. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood through a detailed description of various aspects of the present disclosure in conjunction with the accompanying drawings, which depict various embodiments thereof, in which:

[0008] Figure 1 A schematic diagram of a circuit structure having multiple discharge circuits and resistors according to embodiments of the present disclosure is provided.

[0009] Figure 2 Enlarged schematic diagrams of circuit structures and devices according to embodiments of the present disclosure are provided.

[0010] Figure 3 A cross-sectional view of a high electron mobility transistor (HEMT) configured to be implemented within a discharge circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A schematic diagram of an example implementation of a circuit structure having a trigger circuit and a discharge circuit according to embodiments of the present disclosure is provided.

[0012] Figure 5 A schematic diagram of a circuit structure having multiple discharge circuits and resistors according to another embodiment of the present disclosure is provided.

[0013] Figure 6 A schematic diagram of an example implementation of a circuit structure having a trigger circuit and a discharge circuit according to another embodiment of the present disclosure is provided.

[0014] Figure 7 An example graph is shown showing the current (I) within the device relative to the pad voltage (VA) during operation with different resistances according to an embodiment of the present disclosure.

[0015] Figure 8 An illustrative flowchart is provided for a method of operating a circuit structure having multiple discharge circuits and resistors according to embodiments of the present disclosure.

[0016] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure. In the drawings, the same reference numerals denote the same elements between the figures. Detailed Implementation

[0017] In this description, reference is made to the accompanying drawings, which form a part thereof, illustrating specific exemplary embodiments in which the present teachings may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made within the scope of the present teachings. Therefore, the description herein is merely illustrative.

[0018] As device dimensions continue to shrink, the operating parameters of discharge elements, such as those in ESD protection circuits, are becoming increasingly sensitive. For example, for all operations below a predetermined maximum operating voltage, the discharge element needs to remain in an "off" state. However, at voltages above the predetermined maximum operating voltage but below the device's breakdown voltage level, the discharge element needs to become active. Conventional configurations of discharge elements can no longer provide a stable maximum operating voltage sufficiently below the breakdown voltage, potentially posing a risk of negatively impacting certain devices even when the discharge element operates as intended.

[0019] Embodiments of this disclosure provide a circuit structure and method having a resistor for reducing the release pad voltage and multiple discharge circuits. The structure includes a first trigger circuit connected between the pad and a ground node. A first discharge circuit is connected between the pad and the ground node, wherein the first discharge circuit is connected to the output node of the first trigger circuit. A second trigger circuit may be connected in parallel with the first trigger circuit between the pad and the ground node. The resistor has a first end connected to the pad and a second end opposite to the first end. The second discharge circuit is connected between the second end of the resistor and the ground node. The second discharge circuit is connected to the output node of either the first or second trigger circuit. Related methods are also provided.

[0020] refer to Figure 1This illustration shows a schematic diagram of a circuit structure (hereinafter referred to as "structure") 100 according to an embodiment of the present disclosure. Structure 100 can be embodied as any type of electronic circuit and, in various embodiments, can be provided as an integrated circuit (IC) structure or included as part of an integrated circuit (IC) structure. Structure 100 may include a pad 101. Pad 101 may be, for example, an input / output ("I / O") pad, a power supply pad, etc., which is at risk of being subjected to high-voltage operating conditions such as electrostatic discharge (ESD) events. Pad 101 may be further electrically connected to a device 110 for performing various functions of operating circuitry 111 (e.g., a transceiver front end or other circuitry). According to one example, such as... Figure 2 As shown, device 110 may be a transistor 105 (e.g., a "ground transistor") or any other electrically controllable device configured to operate in response to a signal from pad 101. Transistor 105 may have a first source / drain (S / D) terminal coupled to at least one other component of device 110, coupled to a ground pad (GND, e.g., via terminal V). SS The second S / D terminal of the pad 101 and the gate coupled to the pad 101 (via resistor 116, as discussed in more detail below). As discussed in more detail below, structure 100 can be configured to protect device 110 from adverse effects caused by ESD events at pad 101, including possible damage.

[0021] Structure 100 includes a first node A connected to pad 101 and several other components (e.g., three components connected in parallel as shown). The gate (or alternatively, a switching terminal) of device 110 is coupled to a second node B within structure 100. Resistor 116 has a first end coupled to the first node A and a second end coupled to the second node B opposite to the first end. As discussed herein, one S / D terminal (or other input terminal) of device 110 is coupled to other devices (not shown) within the operating circuit 101, and another S / D terminal (or output terminal) is coupled to terminal V via a third node C. SS The device 110 is coupled to ground (GND). Specifically, the first node A may be coupled to a first trigger circuit 112a, a first discharge circuit 114a, and a second trigger circuit 112b, all of which are connected in parallel between nodes A and C. Device 110 may also include a gate terminal coupled to a second node B (or another voltage-controlled node for enabling or disabling current through device 110). Node B is also connected to node C via the second discharge circuit 114b. Although device 110 is... Figure 2The device 110, indicated as a single transistor (e.g., a protective transistor or ground transistor as discussed herein), may be coupled to and / or may include more complex circuitry having several electrically active elements, including several resistors, capacitors, diodes, and / or other devices. Additional components and / or circuitry can be connected via the input line V. in They are coupled to structure 100, but the nature and operation of such components are not important to the configuration and operation of structure 100, so they will not be discussed in further detail.

[0022] In the configuration shown, the first node A can be set to the level of the input or "high voltage" input terminal of structure 100, and the third node C can be set to the "ground" or "output" (V) of structure 100. SS The second node B can specify the junction between the gate terminal (or other control terminal) of device 110 and the second discharge circuit 114b of structure 100, as discussed herein. The second node B can be used to control the operation of device 110, but is susceptible to current spikes during ESD events, as discussed herein. Structure 100 is configured to respond to excess charge and current originating from ESD events by establishing a short circuit to bypass device 110, while simultaneously reducing the voltage amplitude applied to device 110. During operation, by establishing one or more intentional electrical short circuits through structure 100 (e.g., using the first trigger circuit 112a and the first discharge circuit 114a and / or the second trigger circuit 112b and the second discharge circuit 114b), the resistor 116 of structure 100 simultaneously reduces the voltage applied to device 110 ground (V). SS The voltage of the gate (or other control terminal) of the device from an ESD event.

[0023] Structure 100 can be in the form of a clamp, which is configured to establish a ground V from the input pad 101 to the output terminal. SSThe structure 100 is designed to prevent electrical short circuits without decoupling device 110 from input pad 101. Structure 100 can also be configured to operate under non-ESD conditions with voltage variations, for example, by including a connection from input pad 101 to device 110 in the operating circuit 111. However, structure 100 includes additional components configured to be inactive during non-ESD scenarios or within predetermined voltage limits. Trigger circuits 112a, 112b are electrically configured to activate discharge circuits 114a, 114b only when the pad voltage VPAD reaches a predetermined amplitude. Trigger circuits 112a, 112b will prevent current from flowing through discharge circuits 114a, 114b, as long as such voltage fluctuations are insufficient to trigger the transistor gates of trigger circuits 112a, 112b. Therefore, structure 100 is designed to establish a connection from input pad 101 to ground V only when an ESD event is detected. SS Electrical short circuit. In addition, structure 100 may include multiple trigger circuits 112a, 112b with different predetermined voltages to activate corresponding discharge circuits 114a, 114b to prevent excessive voltage (e.g., breakdown voltage or higher voltage levels) from being applied to device 110, but without requiring large resistive elements and / or being overly sensitive to non-ESD voltage spikes.

[0024] The first set of ESD elements 120 and the second set of ESD elements 130 can both couple the first node A to the third node C in parallel with any connection to device 110. Resistor 116 also couples the first node A to the gate terminal (or other control terminal) of device 110 at the second node B. Structure 100 is connected to a ground node (or ground terminal) at the third node C. SS ESD components 120 and 130 can be activated under different conditions during an ESD event in response to a voltage or current on pad 101 exceeding a predetermined amplitude of device 110 and / or the operating circuit 111 connected thereto, to establish a connection from input pad 101 to ground terminal V. SS The electrical short circuit. A specific set or both sets of ESD elements 120, 130 can be configured to respond to the same or different voltage magnitudes on pad 101. For example, the threshold voltage of trigger circuit 112a in the first set of ESD elements 120 can be the same as or greater than the threshold voltage of trigger circuit 112b in the second set of ESD elements 130. ESD elements 120, 130 can be electrically inactive unless at least their predetermined voltage is applied to the trigger circuits 112a, 112b of the ESD elements 120, 130. In various other examples, additional circuitry and / or current paths can be located between device 110 and ESD elements 120, 130 to further control the situation where ESD elements 120, 130 become electrically active.

[0025] As this article is about Figure 4 As discussed in further detail, each trigger circuit 112a, 112b of structure 100 may include a plurality of interconnected transistors, each transistor being configured to detect, for example, only a predetermined high voltage amplitude at pad 101 during an ESD event. A transistor is an electrical component in which the flow of current between an input node and an output node (e.g., a source terminal and a drain terminal) is controlled by a voltage applied to a third “gate” terminal. Trigger circuits 112a, 112b may include one or more transistors having a gate coupled to terminal A of structure 100, such that a voltage at pad 101 with a predetermined amplitude controls whether each trigger circuit 112a, 112b is turned on or off. Each trigger circuit 112a, 112b may be coupled at its output to a corresponding discharge circuit 114a, 114b. A first trigger circuit 112a is coupled to a first discharge circuit 114a, and a second trigger circuit 112b is coupled to a second discharge circuit 114b. During operation, trigger circuits 112a and 112b remain inactive until a predetermined operating voltage (e.g., ESD voltage) is applied from pad 101 to trigger circuits 112a and 112b at node A. Each trigger circuit 112a and 112b may have a different predetermined operating voltage, for example, by having different numbers and / or arrangements of transistors therein. Upon receiving the predetermined operating voltage, trigger circuits 112a and 112b output trigger voltages (VTRIG1 from the first trigger circuit 112a and VTRIG2 from the second trigger circuit 112b) to discharge circuits 114a and 114b to achieve a protective interaction with device 110. Trigger voltages VTRIG1 and VTRIG2 may be the same or different. Each trigger circuit 112a and 112b allows current to flow through discharge circuits 114a and 114b to discharge the gate control terminal of device 110 to ground terminal V. SS .

[0026] Structure 100 includes a resistor 116 having a first end (at a first node A) coupled to pad 101 to receive a pad voltage (VPAD) and a second end (at a second node B) coupled to a second discharge circuit 114b and the gate terminal of device 110. The second node B at the second end of resistor 116 is not coupled to the first set of ESD elements 120. Resistor 116 is present in structure 100 to reduce the VPAD received at the first end to a lower amplitude intermediate voltage (VINT) output at the second end (e.g., output to device 110, as a gate voltage, for example, if device 110 is a transistor with a gate connected to pad 101). The voltage reduction across resistor 116 from the first node A to the second node B occurs by applying Ohm's law, generally understood in the relevant art. When activated by the second trigger circuit 112b, the second discharge circuit 114b selectively couples the second node B (i.e., the second end of resistor 116) to ground (VINT) at a third node C. SS The first discharge circuit 114a is similarly activated by the first trigger circuit 112a to selectively couple node A to ground (V). SS However, the predetermined voltage amplitude used to activate the first trigger circuit 112a is greater than the predetermined voltage amplitude used to activate the second trigger circuit 112b. In an alternative embodiment, the predetermined voltage amplitude used to activate the first trigger circuit 112a may be the same as or less than the predetermined voltage amplitude used to activate the second trigger circuit 112b, or, only the first trigger circuit 112a may exist (see the document). Figure 5 , 6 (8). During operation, the first trigger circuit 112a and the first discharge circuit 114a can electrically bypass resistor 116 to accommodate higher voltage ESD events.

[0027] When the first discharge circuit 114a and the second discharge circuit 114b are inactive (i.e., no trigger voltage is applied to them from the trigger circuits 112a, 112b), no current b will travel from the first node A or the second node B through the discharge circuits 114a, 114b to the third node C. In the case where structure 100 includes multiple trigger circuits 112a, 112b that apply trigger voltages VTRIG1, VTRIG2 to a discharge circuit 114a, 114b respectively (e.g., during an ESD event or other high-voltage operating scenario at a predetermined operating voltage), the discharge circuits 114a, 114b become active, establishing a current b from the first node A or the second node B to the third node C to ground (VTRIG1, VTRIG2). SSThe electrical short circuit of the device 110. Therefore, during an ESD event or other high-voltage operating scenario, a current path from pad 101 is from the first node A through resistor 116 to the second node B to the gate terminal of device 110, then through discharge circuit 114b (due to the trigger voltage applied to it from trigger circuit 112) to the third node C, and to terminal V. SS The ground (GND) is located at point G. An additional or alternative path is from the first node A through discharge circuit 114b to the third node C, and then to terminal V. SS The ground (GND) is located at pad 101. Under different voltage conditions at pad 101, one or both of these current paths can be enabled. During an ESD event in which the voltage at pad 101 is high enough to activate the second trigger circuit 112b but not the first trigger circuit 112a, resistor 116 is used to reduce the voltage applied to the gate terminal of device 110 to an intermediate voltage level (VINT) lower than the high voltage (VPAD) at pad 101.

[0028] Figure 3 Examples of high electron mobility transistors (HEMTs) 200 that can be implemented within the discharge circuits 114a and 114b of structure 100 are provided. Traditionally, resistive elements in ESD protection circuits pose a risk that ESD detection components may not be triggered when sufficiently high voltages occur. Resistor 116 can be incorporated into structure 100, partially without this risk, through the HEMT device architecture within the discharge elements 114a and 114b. It should be emphasized that... Figure 3 The HEMT 200 shown is an example of a specific device configuration; for the embodiment of the HEMT 200 shown herein, different devices with different polarities, doping distributions, electrical couplings, etc., can be substituted in the discharge elements 114a, 114b.

[0029] HEMT 200 can be provided using a stack of III-V semiconductor layers at substantially the same level above the substrate. More specifically, in the disclosed embodiments, the semiconductor structure may include a stack of III-V semiconductor layers. Therefore, HEMT 200 may include any conceivable HEMT III-V semiconductor device constructed on such a structure, such as another HEMT enhancement mode HEMT with or without raised III-V semiconductor source / drain regions, enhancement mode MISHEMT with or without raised III-V semiconductor source / drain regions, etc. As discussed herein, HEMT 200 can differ from other transistor architectures by including (among other components) a barrier layer located above and adjacent to the III-V semiconductor surface at the top of the stack in a first region. Various isolation materials (e.g., one or more isolation wells) may be located within the stack and adjacent to the III-V semiconductor surface, for example, to electrically isolate HEMT 200 from other transistors with different architectures.

[0030] Figure 3 A cross-sectional view illustrating an example embodiment of HEMT 200 is provided. HEMT 200 may include a substrate 201. Substrate 201 may be, for example, a silicon substrate or a silicon-based substrate (e.g., silicon carbide or silicon-germanium substrate), a sapphire substrate, a III-V semiconductor substrate (e.g., a gallium nitride substrate or other suitable III-V semiconductor substrate), or any other substrate suitable for III-V semiconductor processing. HEMT 200 may include a stack of III-V semiconductor layers located on substrate 201. Those skilled in the art will recognize that III-V semiconductors refer to compounds obtained by combining one or more group III elements (e.g., boron (B), aluminum (Al), gallium (Ga), or indium (in)) with one or more group V elements (e.g., nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)). Therefore, examples of III-V semiconductors include, but are not limited to, gallium nitride, indium phosphide, gallium arsenide, aluminum gallium nitride, indium gallium nitride, etc. The III-V semiconductor layer in the stack can be epitaxially grown on the substrate 201, and can include at least a buffer layer 202 and a channel layer 203 located on the buffer layer 202. For example, the buffer layer 202 can be located above and adjacent to the top surface of the substrate 201.

[0031] Buffer layer 202 can serve as an anchor to facilitate nucleation and replication of orientation in subsequently grown epitaxial layers. Buffer layer 202 can be, for example, a gallium nitride layer and / or one or more layers of any other group III-V semiconductor suitable for use as a buffer layer in HEMT or metal-insulator-semiconductor HEMT (MISHEMT). Optionally, buffer layer 202 can be carbon-doped or iron-doped. Channel layer 203 can be located above and immediately adjacent to the top surface of buffer layer 202. Channel layer 203 can be, for example, a gallium nitride layer and / or one or more layers of any other group III-V semiconductor suitable for use as a channel layer in HEMT or MISHEMT. In any case, the top surface of the stack, particularly the top surface of channel layer 203, can be a group III-V semiconductor surface 203t.

[0032] In addition to the other components discussed in more detail below, HEMT 200 may also include a barrier layer 204 (specifically, another III-V semiconductor layer) located above and adjacent to the III-V semiconductor surface 203t. HEMT 200 may also be located around and / or above various components of HEMT 200. DM layer 250 may include a first DM layer 251, specifically a silicon nitride layer. DM layers may optionally include, but are not limited to, one or more of a second DM layer 252, a third DM layer 253, a fourth DM layer 254, a fifth DM layer 255, and a sixth DM layer 256. Any of DM layers 252-156 may include a single DM layer (e.g., a silicon dioxide layer or some other suitable DM) or two or more DM sublayers (e.g., a conformal silicon nitride layer and some other suitable combination of a silicon dioxide layer or a dielectric material layer situated on the conformal silicon nitride layer).

[0033] HEMT 200 further includes source / drain terminals 232 located on channel layer 203 and gate terminals 235 laterally located on barrier layer 204 between source / drain terminals 232. HEMT 200 may include a barrier layer 204 located above and immediately adjacent to a III-V semiconductor surface 203t at the top of the stack. Barrier layer 204 may be another III-V semiconductor, different from channel layer 203, and having a wider bandgap than channel layer 203. Those skilled in the art will recognize that the channel and barrier III-V semiconductor materials can be selected to form a heterojunction at the interface between the two layers, resulting in the formation of a two-dimensional electron gas (2DEG) in channel layer 203. This 2DEG in channel layer 203 can provide a conduction path for charge drift between source / drain terminals. In the case of E-mode HEMT, the minimum voltage amplitude at gate terminal 235 used to generate 2DEG in channel layer 203 is also referred to as the "threshold voltage". The barrier layer 204 may be a layer of aluminum gallium nitride, aluminum nitride, or any other III-V semiconductor material suitable for use as a barrier layer (e.g., depending on the III-V semiconductor material of the channel layer 203). In any case, the aforementioned layer may be epitaxially grown by metal-organic chemical vapor deposition (MOCVD) or any other suitable technique (e.g., molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc.). For illustrative purposes, the above figures and description depict the barrier layer 204 as comprising a single layer of III-V semiconductor material. However, it should be understood that the figures and description are not intended to be limiting, and alternatively, the barrier layer 204 may comprise two or more sublayers of III-V semiconductor material. A first DM layer 251 (which, as described above, may be a silicon nitride layer) may be located above and immediately adjacent to the top surface of the barrier layer 204.

[0034] HEMT 200 can be configured as an enhancement-mode (E-mode) HEMT. Those skilled in the art will recognize that an E-mode HEMT refers to a HEMT that remains in an "off" (i.e., non-conductive) state when no voltage is applied to its gate. In this case, HEMT 200 may require a threshold voltage (e.g., from trigger circuit 112 as discussed herein) to be applied to gate terminal 235. Figure 1The trigger voltage (VTRIG) is used to operate the device to the on state (i.e., to become conductive). In the case of an E-mode HEMT, the HEMT 200 includes a P-type III-V semiconductor layer 236 stacked in a gate terminal 235 between a barrier layer 204 and a gate conductor material 237. The P-type III-V semiconductor layer 236 may be, for example, a III-V semiconductor (e.g., gallium nitride), which is epitaxially grown on the barrier layer 204 and doped (e.g., with magnesium) to have P-type conductivity. In these embodiments of the HEMT 200, the gate conductor material 237 may include a metal gate conductor material such that the gate terminal 235 is a Schottky contact gate terminal.

[0035] Now for reference Figure 4 Another schematic diagram of structure 100 is shown, featuring example sub-components for implementing trigger circuits 112a, 112b and discharge circuits 114a, 114b. In some embodiments, discharge circuits 114a, 114b may simply include a HEMT 200, which is coupled from the drain to the source from a first node A (in the case of the first discharge circuit 114a) or a second node B (in the case of the second discharge circuit 114b) to a third node C, and coupled at its gate to the source terminal at one end of a transistor 302 connected in series within the trigger circuits 112a, 112b. As described herein, HEMT 200 may be an E-mode HEMT, such that while a trigger voltage is applied to the gate of HEMT 200, current flows only from the first node A or the second node B to the third node C via the first trigger circuit 112a or the second trigger circuit 112b (if applicable). In various alternative configurations, the discharge circuits 114a, 114b may include multiple interconnected HEMTs 200, for example, an array of interconnected HEMTs configured to function as larger transistors according to any now-known or later-developed "macro transistor" configuration, and / or other groups of interconnected transistors configured to approximate the function of HEMTs 200.

[0036] In contrast to discharge circuits 114a and 114b, trigger circuits 112a and 112b may include several conventional (e.g., non-HEMT) transistors interconnected as a plurality of diode-connected transistors 302. A diode-connected transistor is a transistor configuration in which the control terminal of the transistor is directly coupled to one of its input-output terminals, thus converting the transistor into a two-terminal diode structure. In the case of a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode-connected transistor may have a drain (or alternatively, source) terminal connected to its gate. According to one example, trigger circuits 112a and 112b may each include: a first diode-connected transistor 302, whose connected gate and drain terminals are coupled to a first node A (i.e., neither trigger circuit 112a nor 112b is coupled to a second node B) and a pad 101; a last diode-connected transistor coupled to one terminal of an additional resistor 304; and a plurality of intermediate diode-connected transistors 302 (e.g., two are shown) connected in series from drain to source between the first and last diode-connected transistors 302. Multiple diode-connected transistors 302 can be implemented in the trigger circuits 112a, 112b instead of a single transistor, for example, to reduce current leakage through the trigger circuits 112a, 112b when the discharge circuits 114a, 114b are not operating (i.e., when a high-voltage scenario (e.g., an ESD event) at the predetermined operating voltage does not occur).

[0037] Within each trigger circuit 112a, 112b, the junction between the source of a diode-connected transistor 302 and a terminal of an additional resistor 304 can be connected to the control terminal of the discharge circuit 114 (e.g., the gate terminal of the HEMT 200), such that the operating state of the diode-connected transistor 302 determines whether a trigger voltage is applied to the discharge circuit 114a, 114b coupled thereto. Therefore, the additional resistor 304 in the trigger circuits 112a, 112b prevents the control terminals of the respective discharge circuits 114a, 114b from being at terminal V. SS Grounding is achieved at the specified location. In an alternative configuration, the control terminals (i.e., the gates of the HEMT 200) of the discharge circuits 114a and 114b can be coupled to another node within the corresponding trigger circuits 112a and 112b, for example, where a different circuit configuration is used to perform a similar function. In other examples discussed herein (e.g., Figure 5 In the structure 100 shown, a trigger circuit 112 can be coupled to multiple discharge circuits 114a, 114b.

[0038] In the presence of multiple trigger circuits 112a, 112b, the diode-connected transistor 302 can have a sufficiently high threshold voltage such that the trigger circuits 112a, 112b do not operate until a predetermined high voltage amplitude (which is different for each trigger circuit 112a, 112b) is applied to the structure 100 at pad 101. The threshold voltage of the diode-connected transistor 302 in the trigger circuits 112a, 112b can be at least equal to the expected voltage during an ESD event or a similar event with an undesirably high voltage amplitude. Differences in the number of transistors and / or interconnections within each trigger circuit 112a, 112b may result in a different voltage (e.g., larger than the voltage used to activate the second trigger circuit 112b) than the voltage used to activate the first trigger circuit 112a. Both trigger voltages are greater than the actual voltage applied to the gate of device 110 and released from it through the HEMT 200 in the discharge circuits 114a, 114b. The combination of trigger circuits 112a and 112b (both configured to trigger at a pad voltage amplitude higher than the breakdown voltage of device 110) and resistor 116 (configured to reduce the pad voltage to an amplitude lower than the breakdown voltage of device 110 when only the second discharge circuit 114b is active) allows structure 100 to release a high voltage amplitude via discharge circuit 114 without overwhelming the control terminals of device 110.

[0039] Figure 5 and Figure 6 Another embodiment of structure 100 is shown, wherein, optionally, only the first trigger circuit 112a is configured to use a voltage (VTRIG) to control the first discharge circuit 114a and the second discharge circuit 114b. In this configuration, device 110 and operating circuit 111 can be any of the various forms and / or embodiments discussed elsewhere herein (e.g., transistor 105). Figure 2 The first group of ESD elements 120 may include a first trigger circuit 112a and a plurality of discharge circuits 114a, 114b. Each discharge circuit 114a, 114b may be coupled to different terminals of resistor 116. Similar to other embodiments herein, the first discharge circuit 114a may be electrically coupled at nodes A (set to pad voltage VPAD) and C (set to V). SS The second discharge circuit 114b can also be electrically coupled between node B (set to intermediate voltage VINT) and C (set to V). SSBetween (or ground). Therefore, the first discharge circuit 114a is configured to release the pad voltage VPAD, and the second discharge circuit 114b is configured to release the intermediate voltage VINT. However, in this arrangement, the first trigger circuit 112a includes an output node coupled in parallel with the control nodes of the first discharge circuit 114a and the second discharge circuit 114b.

[0040] Although the first trigger circuit 112a outputs only a single voltage VTRIG to electrically control the multiple discharge circuits 114a, 114b, each discharge circuit 114a, 114b can be activated in response to different voltage amplitudes. For example, the second discharge circuit 114b can be activated when VTRIG reaches an amplitude less than the trigger voltage required to activate the first discharge circuit 114a. The discharge circuits 114a, 114b can be activated in response to different voltage amplitudes, for example, by using a HEMT or other transistors having different threshold voltages due to physical and / or electrical differences. For example, the HEMT 200 in the second discharge circuit 114b can be approximately six times smaller than the HEMT 200 in the first discharge circuit 114a, or the size of the HEMT 200 can differ sufficiently to cause a substantial difference in its activation voltage. In another configuration, the voltage amplitude used to activate each discharge circuit 114a, 114b can be controlled by other components (e.g., resistors, capacitors, etc.) coupled between the first trigger circuit 112a and the discharge circuits 114a, 114b. For ESD events with lower voltage amplitudes, the second discharge circuit 114b can release the intermediate voltage VINT. For ESD events with higher voltage amplitudes, the first discharge circuit 114a can release the pad voltage VPAD. In this configuration, due to the presence of resistor 116 and multiple discharge circuits 114a, 114b, the first trigger circuit 112a can operatively release different voltages from the first node A or the second node B.

[0041] Let's refer to each other. Figure 1 , 5 Sections 1 and 7 further discuss in detail the technical benefits of structure 100 compared to conventional protection circuit structures. Regardless of the implementation... Figure 1 , 2 The technical benefits discussed herein can be achieved by any configuration of structure 100 shown in 4-6 and discussed herein, or by another embodiment of structure 100. Figure 7 A comparative voltage plot and corresponding current plot are provided for different amounts of pad voltage (VPAD) applied to structure 100. The left Y-axis indicates the total current (Itot) through structure 100, and the right Y-axis indicates the voltage (Vdevice) applied to device 110, i.e., the voltage at the second node B. The X-axis represents the input voltage applied at pad 101. Figure 7The example diagram also indicates the voltage at the control node of each discharge circuit ("Dis1" for the first discharge circuit 114a, "Dis2" for the second discharge circuit 112b) and the current through resistor 116 ("Rcurrent"). The dashed lines also indicate example values ​​for the voltage amplitude ("threshold 1") used to activate the first discharge circuit 114a and example values ​​for the voltage amplitude ("threshold 2") used to activate the second discharge circuit 114b. As discussed herein, each voltage can be applied by a single trigger circuit (112a, 112b, respectively) or only by the first trigger circuit 112a. Therefore, Figure 7 The example diagram illustrates how a change in the pad voltage applied at the first node A will affect the control terminal voltage at node B to device 110 (via Vdevice), and the subsequent current through discharge circuits 114a, 114b (via Dis1 and Dis2) when trigger circuit 112 is activated. In conventional ESD protection devices without resistor 116 or similar resistive elements, there is essentially no resistance between nodes A and B; therefore, conventional circuits have a resistance "R" value of zero ohms (Ω).

[0042] In an example embodiment of structure 100, the second discharge circuit 114b is activated by a voltage of at least about 10V, and the first discharge circuit 114a is activated by a voltage of at least about 14V. A voltage of at least about 10V can indicate an ESD event, while a voltage of at least about 14V can indicate a higher voltage ESD event in which structure 100 must release more potential to ground. For lower ESD voltages at pad 101, for example, voltages between about 10V and 14V, only the second discharge circuit 114b is activated and carries the ESD current to ground at an intermediate voltage VINT.

[0043] For higher ESD voltages at pad 101, such as those above approximately 14V, both the first discharge circuit 114a and the second discharge circuit 114b are activated, thus allowing multiple circuits 114a, 114b to discharge ESD current to ground. Resistor 116 (with a value of, for example, approximately 4Ω) will saturate for even greater voltages (e.g., pad 101 has a voltage of at least approximately 22V), so that no additional current is transported even if the voltage at pad 101 increases. Figure 7The current saturation is indicated; even as the pad voltage increases to above 22V, Rcurrent remains at approximately 0.25A. Therefore, by reducing the voltage at device 110 (i.e., node B) to VINT, structure 100 can accommodate higher voltages during ESD events. Thus, these aspects of structure 100 according to any embodiment herein cause the voltage (Vdevice) at device 110 to reach its maximum at approximately 17V, significantly below its breakdown voltage, and then decrease to approximately 6V, even as the total current (Itot) continues to increase along a linear distribution.

[0044] Let's refer to it together now. Figure 1 , 5 In accordance with 7, embodiments of this disclosure provide a method of operating structure 100 such that during an ESD event or other high-voltage operation, device 110 has an intermediate voltage at a second node B that is less than the voltage at a first node A used to activate trigger circuit 112, but during an ESD event of higher magnitude, the entire ESD voltage at pad 101 is released to ground. Process P1 in the method of this disclosure may include coupling resistor 116 between pad 101 (at first node A) and device 110 (at second node B) in structure 100. When the first trigger circuit 112a (e.g., in...) Figure 5 In the implementation of the second trigger circuit 112b (e.g., in the embodiment of the second trigger circuit 112b), the second trigger circuit 112b is used. Figure 1 In the embodiment, the second discharge circuit 114b is activated to pass through resistor 116 between pad 101 and ground (at terminal V). SS When a current path is established between nodes A and B, the resistor 116 at that location can operate to generate a voltage drop from the first node A to the second node B without disconnecting device 110 from pad 101. Therefore, in process P1, the coupling of resistor 116 between nodes A and B can produce structure 100 as discussed herein.

[0045] An ESD event or other high-voltage operation can generate a voltage high enough at the first node A to activate the trigger circuits 112a, 112b of structure 100. Due to the configuration of the trigger circuits 112a, 112b and the discharge circuits 114a, 114b in structure 100, process P2 includes detecting whether any predetermined operating voltage is received at pad 101. When the voltage at pad 101 is insufficient to activate the trigger circuits 112a, 112b, the method can terminate (“complete”), and structure 100 can remain inactive until one of the predetermined operating voltages is detected at pad 101. Alternatively, process P2 can simply include any process that applies a voltage sufficient to activate one or more of the trigger circuits 112a, 112b, for example, to transistors 302s connected to diodes within the trigger circuits 112a, 112b. Figure 4 ,6 Apply at least the predetermined operating voltage.

[0046] When the lower of two predetermined operating voltages (i.e., the "second operating voltage" in this example) is detected at pad 101, structure 100 uses trigger circuits 112a, 112b and a second discharge circuit 114b to implement processes P3 and P4. In process P3, trigger circuits 112a, 112b output trigger voltages (VTRIG or VTRIG2, respectively) in response to pad 101 being set to the second predetermined operating voltage. Thereafter, the trigger voltage (VTRIG from the first trigger circuit 112a or VTRIG2 from the second trigger circuit 112b, depending on the configuration) activates the second discharge circuit 114b.

[0047] Individual activation of trigger circuits 112a and 112b will not establish a connection from pad 101 to output pad V via structure 100. SS The electrical path. The second discharge circuit 114b is coupled between nodes B and C in structure 100 to transfer the intermediate voltage VINT to V. SS (Ground). When trigger circuits 112a and 112b activate the second discharge circuit 114b, in process P3, the second discharge circuit 114b establishes a current path from the second node B to the third node C. The second discharge circuit 114b includes one or more HEMT 200 ( Figure 4 , 6 In the case of a trigger circuit 112a, 112b, process P3 can simply involve outputting a trigger voltage with an amplitude equal to or greater than the threshold voltage to the gate terminal of the E-mode HEMT 200. Therefore, process P4 can include transferring the trigger voltage VTRIG or VTRIG2 (depending on the trigger circuits 112a, 112b connected thereto) to the second discharge circuit 114b in structure 100. As discussed herein, applying the trigger voltage VTRIG to the second discharge circuit 114b (e.g., at its HEMT 200) will allow current to travel from the drain to the source from the second node B (connected to the gate or control terminal of device 110) to the third node C. Because of the resistor 116 between the first node A and the second node B, the voltage drop across resistor 116 will give device 110 an intermediate voltage at the second node B that is less than the voltage at pad 101 (e.g., less than the high voltage generated during an ESD event), thus avoiding negative impacts on device 110.

[0048] When the higher of two predetermined operating voltages (i.e., the "first operating voltage" in this example) is detected at pad 101, structure 100 can provide an additional path to connect pad 101 to ground in parallel with resistor 116. Detection of the first operating voltage can initiate processes P5 and P6 of activating the first discharge circuit 114a using the first trigger circuit 112a. Regardless of how structure 100 is implemented, only the first trigger circuit 112a and the first discharge circuit 114a can be manipulated in processes P5 and P6. In process P5, the voltage detected at pad 101 is transmitted to the first trigger circuit 112a. The first trigger circuit 112a may have a gate or other control node with a predetermined voltage higher than that of the second trigger circuit 112b, for example, a voltage high enough to trigger both the first and second trigger circuits 112b. In an embodiment where the second trigger circuit 112b is absent, the voltage at the first trigger circuit 112a can increase the amplitude of VTRIG from the first trigger circuit 112a to a level sufficient to simultaneously activate the first discharge circuit 114a and the second discharge circuit 114b. In process P6, the first trigger circuit 112a transmits the trigger voltage VTRIG or VTRIG1 to the first discharge circuit 114a, thereby establishing an additional current path from the first node A to the third node C, which is connected in parallel with the path along resistor 116 through nodes A, B, and C. In this configuration, at higher amplitude ESD voltages, the current through resistor 116 will be at a predetermined voltage (e.g., as...). Figure 7 The example shown saturates at 22V to protect device 110. When implemented, these processes protect device 110 and other circuitry from high-voltage events, while preventing device 110 from operating above its breakdown voltage due to the presence of resistor 116. These technical benefits and associated advantages may be even more pronounced in embodiments where discharge circuits 114a, 114b include HEMT 200 but trigger circuits 112a, 112b do not include any HEMT device.

[0049] The embodiments of this disclosure can provide several technical and commercial advantages, some of which are discussed herein by way of example. Embodiments of structure 100, for example, provide a structure capable of responding to ESD events with a conventional trigger voltage amplitude without applying a voltage close to its breakdown voltage to device 110. During operation, structure 100, having multiple discharge circuits 114a, 114b and optionally multiple trigger circuits 112a, 112b, reduces current leakage through structure 100 during non-ESD operation and lowers the clamping voltage of structure 100 in various applications. Furthermore, structure 100 can implement resistors of lower amplitudes compared to conventional ESD protection circuits, thus occupying a smaller amount of surface area. Due to the inclusion of resistor 116, device 110 can remain coupled to pad 101 during such events and have an intermediate voltage applied thereto. Embodiments of this disclosure avoid the conventional penalties to size and performance associated with forming resistors in ESD protection circuits by using HEMT or similar architectures to provide a discharge path. These advantages, in turn, can provide lower leakage current regardless of the operating state of structure 100, and can provide greater protection against high-voltage events by adapting to a wider voltage range before the intermediate voltage approaches the breakdown voltage of device 110.

[0050] The description of various embodiments in this disclosure is presented for illustrative purposes and is not intended to be exhaustive and / or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art within the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, and / or technical improvements relative to technologies found in the market, and / or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: The first trigger circuit is connected between the pad and the ground node; A first discharge circuit is connected between the pad and the grounding node, wherein the first discharge circuit is connected to the output node of the first trigger circuit; A second trigger circuit is connected in parallel with the first trigger circuit between the pad and the grounding node; A resistor having a first end connected to the pad and a second end opposite to the first end; and A second discharge circuit is connected between the second terminal of the resistor and the grounding node, wherein the second discharge circuit is connected to the output node of the second trigger circuit.

2. The structure according to claim 1, wherein, The first trigger circuit, the second trigger circuit, and the first discharge circuit are connected to a shared node between the pad and the first terminal of the resistor, wherein both the first trigger circuit and the second trigger circuit are configured to output a trigger voltage in response to detecting a pad voltage higher than a predetermined operating voltage, wherein the predetermined operating voltage of the first trigger circuit is different from the predetermined operating voltage of the second trigger circuit.

3. The structure according to claim 2, wherein, The predetermined operating voltage of the first trigger circuit is less than the predetermined operating voltage of the second trigger circuit.

4. The structure according to claim 2, wherein, Each trigger circuit includes: Multiple diode-connected field-effect transistors are connected in series between the pad and the output node; and An additional resistor is connected between the output node and the ground node, wherein the trigger voltage is generated and output at the output node.

5. The structure according to claim 1, wherein, Each discharge circuit includes an enhancement-mode high electron mobility transistor (HEMT), wherein the HEMT of the first discharge circuit is larger than the HEMT of the second discharge circuit.

6. The structure according to claim 5, wherein, The first trigger circuit has more diode-connected field-effect transistors than the first trigger circuit.

7. The structure according to claim 1, wherein, The resistor reduces the voltage received from the pad at the first end to an intermediate voltage at the second end, and wherein the second discharge circuit is configured to receive a second trigger voltage from the second trigger circuit and release the intermediate voltage in response to the second trigger voltage.

8. A structure comprising: A trigger circuit is connected between the pad and the ground node; A first discharge circuit is connected between the pad and the grounding node, wherein the first discharge circuit is connected to the output node of the trigger circuit; A resistor having a first end connected to the pad and a second end opposite to the first end; and A second discharge circuit is connected between the second terminal of the resistor and the ground node, wherein the second discharge circuit is connected to the output node of the trigger circuit.

9. The structure according to claim 8, wherein, The first trigger circuit and the first discharge circuit are connected to a shared node between the pad and the first end of the resistor, and wherein the trigger circuit is configured to output a trigger voltage in response to detecting a pad voltage higher than a predetermined operating voltage.

10. The structure according to claim 8, wherein, Each discharge circuit includes an enhancement-mode high electron mobility transistor (HEMT), wherein the HEMT of the first discharge circuit is larger than the HEMT of the second discharge circuit.

11. The structure according to claim 8, wherein, The trigger circuit is configured to, in response to detecting a pad voltage higher than a predetermined operating voltage, output a trigger voltage as a first trigger voltage to the first discharge circuit and output a trigger voltage as a second trigger voltage to the second discharge circuit.

12. The structure according to claim 11, wherein, The trigger circuit includes: Multiple diode-connected field-effect transistors are connected in series between the pad and the output node; and An additional resistor is connected between the output node and the ground node, wherein the trigger voltage is generated and output at the output node.

13. The structure according to claim 8, wherein, The second discharge circuit is not directly electrically coupled to the gasket.

14. The structure according to claim 8, wherein, The resistor reduces the voltage received from the pad at the first end to an intermediate voltage at the second end, and wherein the second discharge circuit is configured to receive a second trigger voltage from the trigger circuit and release the intermediate voltage in response to the second trigger voltage.

15. A method comprising: A structure is provided, the structure comprising: a pad; a first discharge circuit connected between the pad and a ground node; a resistor having a first end connected to the pad and a second end opposite to the first end; and a second discharge circuit connected between the second end of the resistor and the ground node; When the voltage on the pad is higher than a first predetermined operating voltage, the first discharge circuit is activated; and When the voltage on the pad is higher than the second predetermined operating voltage, the second discharge circuit is activated.

16. The method according to claim 15, wherein, The first predetermined operating voltage is different from the second predetermined operating voltage.

17. The method according to claim 15, wherein, The first predetermined operating voltage is less than the second predetermined operating voltage.

18. The method according to claim 15, wherein, Each discharge circuit includes an enhancement-mode high electron mobility transistor (HEMT) having a gate coupled to the first or second trigger circuit, a first source / drain S / D terminal coupled to the second end of the resistor, and a second S / D terminal coupled to ground.

19. The method of claim 15, further comprising providing a first trigger circuit coupled between the pad and the first discharge circuit, and a second trigger circuit coupled between the pad and the second discharge circuit, wherein, Each trigger circuit includes: Multiple diode-connected field-effect transistors are connected in series between the I / O pad and the output node; and An additional resistor is connected between the output node and the ground, wherein the first trigger voltage or the second trigger voltage is generated and output at the output node.

20. The method according to claim 19, wherein, The first trigger circuit has more diode-connected field-effect transistors than the first trigger circuit.

Images