An integrated circuit and an output driver stage shoot-through current suppression circuit thereof

Abstract

The application discloses an integrated circuit and an output driving stage through current inhibition circuit thereof, and applies to the technical field of circuits, and comprises a preceding circuit, a gate driving circuit and an output driving circuit; the output driving circuit comprises pull-up and pull-down driving tubes; the gate driving circuit is used for generating first and second control signals for controlling the turn-on state of the pull-up and pull-down driving tubes respectively according to received pull-up and pull-down driving signals; the preceding circuit is used for generating the pull-up and pull-down driving signals according to an input data signal, and the pull-up and pull-down driving signals have non-overlapping delay in a signal flip process, so that in the process that the output of the output driving circuit is flipped to a high level, the pull-up driving tube is turned on after the pull-down driving tube is turned off, and in the process that the output is flipped to a low level, the pull-down driving tube is turned on after the pull-up driving tube is turned off. The application scheme can avoid through current and effectively inhibit turn-on noise without excessively increasing the complexity of the circuit structure.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to an integrated circuit and its output driver stage through-current suppression circuit. Background Technology

[0002] For digital I / O (Input and Output) circuits, the output driver circuit is the circuit module responsible for driving the external load. It is generally composed of a PMOS and an NMOS connected in series. The PMOS acts as a pull-up driver when the I / O circuit outputs a high level, and the NMOS acts as a pull-down driver when the I / O circuit outputs a low level. The main power consumption of the output driver circuit is the dynamic power consumption during the output signal switching process, including switching power consumption and short-circuit power consumption. Switching power consumption refers to the charging and discharging power consumption of the load capacitor and the parasitic capacitance of the internal nodes of the circuit when the circuit switches. Short-circuit power consumption is the power consumption formed by the shoot-through current when the PMOS and NMOS are simultaneously conducting during the circuit switching. The shoot-through current will cause voltage changes between the power supply and ground, which is called ground bounce noise or simultaneous conduction noise.

[0003] The larger the size of the MOSFET in the output drive circuit, the greater the output current it can provide, and the stronger its driving capability. However, as the size increases, the circuit will generate a larger shoot-through current when the signal is switched, resulting in greater noise, which will be more serious in high-frequency applications.

[0004] Currently, adding a fixed delay circuit can introduce a delay during the switching process to prevent simultaneous conduction. However, fixed delay circuits typically require a large number of logic gates or delay lines, which not only increases the circuit area but also places higher demands on chip layout and other aspects.

[0005] In summary, how to reduce the shoot-through current generated during the switching process of the output drive circuit without excessively increasing the complexity of the circuit structure, thereby suppressing conduction noise, is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an integrated circuit and its output driver stage shoot-through current suppression circuit, so as to reduce the shoot-through current generated during the switching process of the output driver circuit without excessively increasing the complexity of the circuit structure, thereby suppressing conduction noise.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides an output driver stage through-current suppression circuit, comprising a pre-driver circuit, a gate driver circuit, and an output driver circuit connected in sequence:

[0009] The output driving circuit includes a pull-up driving transistor connected between the power supply terminal and the output terminal for pulling up the output terminal, and a pull-down driving transistor connected between the output terminal and ground for pulling down the output terminal.

[0010] The gate driving circuit is used to generate a first control signal to control the conduction state of the pull-up driving transistor and a second control signal to control the conduction state of the pull-down driving transistor, respectively, based on the received pull-up driving signal and pull-down driving signal.

[0011] The pre-drive circuit is used to generate the pull-up drive signal and the pull-down drive signal according to the input data signal. The pull-up drive signal and the pull-down drive signal have a non-overlapping delay during the signal flipping process, so that during the process of the output of the output drive circuit flipping to a high level, the pull-down drive transistor is turned off and then turned on again. And during the process of the output of the output drive circuit flipping to a low level, the pull-up drive transistor is turned off and then turned on again.

[0012] In one embodiment, the precursor circuit includes at least one logic gate circuit composed of a pull-up network and a pull-down network, and the pull-up network and the pull-down network have different driving capabilities to form the non-overlapping delay.

[0013] In one embodiment, the pre-drive circuit includes: a first inverter, a second inverter, a third inverter, a three-input AND gate, and a three-input OR gate;

[0014] The input terminal of the first inverter is connected to the second input terminal of the three-input OR gate, and the connection terminal is used to receive the output enable signal; the output terminal of the first inverter is connected to the second input terminal of the three-input AND gate.

[0015] The first input terminal of the three-input AND gate is connected to the third input terminal of the three-input OR gate, and the connection terminal is used to receive the input data signal; the third input terminal of the three-input AND gate is connected to the output terminal of the three-input OR gate and the input terminal of the third inverter, and the first input terminal of the three-input OR gate is connected to the output terminal of the three-input AND gate and the input terminal of the second inverter.

[0016] The output terminal of the second inverter serves as the first output terminal of the pre-drive circuit to output the pull-up drive signal, and the output terminal of the third inverter serves as the second output terminal of the pre-drive circuit to output the pull-down drive signal.

[0017] In one embodiment, the three-input OR gate includes: a first pull-up switch, a second pull-up switch, a third pull-up switch, a first pull-down switch, a second pull-down switch, a third pull-down switch, and a first inverting unit composed of a fourth pull-up switch and a fourth pull-down switch;

[0018] The first end of the third pull-up switch is connected to the power supply end, the second end of the third pull-up switch is connected to the first end of the second pull-up switch, the second end of the second pull-up switch is connected to the first end of the first pull-up switch, and the second end of the first pull-up switch is connected to the first end of the first pull-down switch, the first end of the second pull-down switch, the first end of the third pull-down switch, the control end of the fourth pull-up switch, and the control end of the fourth pull-down switch, respectively.

[0019] The second ends of the first pull-down switch, the second pull-down switch, the third pull-down switch, and the fourth pull-down switch are all grounded. The first end of the fourth pull-up switch is connected to the power supply terminal. The second end of the fourth pull-up switch is connected to the first end of the fourth pull-down switch, and the connection terminal serves as the output terminal of the three-input OR gate.

[0020] The control terminals of the first pull-up switch and the first pull-down switch are both connected to the first input terminal of the three-input OR gate, the control terminals of the second pull-up switch and the second pull-down switch are both connected to the second input terminal of the three-input OR gate, and the control terminals of the third pull-up switch and the third pull-down switch are both connected to the third input terminal of the three-input OR gate.

[0021] In one embodiment, the three-input AND gate includes: a fifth pull-up switch, a sixth pull-up switch, a seventh pull-up switch, a fifth pull-down switch, a sixth pull-down switch, a seventh pull-down switch, and a second inverting unit composed of an eighth pull-up switch and an eighth pull-down switch;

[0022] The first ends of the fifth pull-up switch, the sixth pull-up switch, and the seventh pull-up switch are all connected to the power supply terminal; the second end of the fifth pull-up switch is connected to the second end of the sixth pull-up switch, the second end of the seventh pull-up switch, the first end of the fifth pull-down switch, the control terminal of the eighth pull-up switch, and the control terminal of the eighth pull-down switch, respectively.

[0023] The second end of the fifth pull-down switch is connected to the first end of the sixth pull-down switch, the second end of the sixth pull-down switch is connected to the first end of the seventh pull-down switch, and the second end of the seventh pull-down switch is grounded.

[0024] The first end of the eighth pull-up switch is connected to the power supply terminal, the second end of the eighth pull-up switch is connected to the first end of the eighth pull-down switch, and the connection terminal serves as the output terminal of the three-input AND gate. The second end of the eighth pull-down switch is grounded.

[0025] The control terminals of the fifth pull-up switch and the fifth pull-down switch are both connected to the first input terminal of the three-input AND gate, the control terminals of the sixth pull-up switch and the sixth pull-down switch are both connected to the second input terminal of the three-input AND gate, and the control terminals of the seventh pull-up switch and the seventh pull-down switch are both connected to the third input terminal of the three-input AND gate.

[0026] In one embodiment, the pre-drive circuit further includes: a first NOR gate, a first NAND gate, a fourth inverter, and a fifth inverter.

[0027] The output of the second inverter is connected to the first input of the first NOR gate, the second input of the first NOR gate is connected to the output of the fifth inverter, and the output of the first NOR gate is connected to the input of the fourth inverter.

[0028] The output of the third inverter is connected to the first input of the first NAND gate, the second input of the first NAND gate is connected to the output of the fourth inverter, and the output of the first NAND gate is connected to the input of the fifth inverter.

[0029] Accordingly, the output terminal of the fourth inverter serves as the first output terminal of the pre-drive circuit to output the pull-up drive signal, and the output terminal of the fifth inverter serves as the second output terminal of the pre-drive circuit to output the pull-down drive signal.

[0030] In one embodiment, the gate drive circuit includes a first control signal generation branch, a second control signal generation branch, a first enhancement branch, and a second enhancement branch.

[0031] The input terminal of the first control signal generation branch is used to receive the pull-up drive signal, and the output terminal is used to output the first control signal;

[0032] The input terminal of the second control signal generation branch is used to receive the pull-down drive signal, and the output terminal of the second control signal generation branch is used to output the second control signal;

[0033] The first enhancement branch is connected to the output terminal of the first control signal generation branch, and is used to enhance the output slew rate of the first control signal when the first slew rate control signal is effective;

[0034] The second enhancement branch is connected to the output terminal of the second control signal generation branch, and is used to enhance the output slew rate of the second control signal when the second slew rate control signal is effective.

[0035] In one embodiment, the second control signal generation branch includes a ninth pull-up switch, a tenth pull-up switch, a ninth pull-down switch, and a tenth pull-down switch; the first control signal generation branch includes an eleventh pull-up switch, a twelfth pull-up switch, an eleventh pull-down switch, and a twelfth pull-down switch.

[0036] The first terminal of the ninth pull-up switch is connected to the power supply terminal, and the second terminal of the ninth pull-up switch is connected to the first terminal of the ninth pull-down switch, the control terminal of the tenth pull-up switch, and the control terminal of the tenth pull-down switch, respectively; the control terminals of the ninth pull-up switch and the ninth pull-down switch are both used to receive the pull-down drive signal.

[0037] The first end of the tenth pull-up switch is connected to the power supply end, and the second end of the tenth pull-up switch is connected to the first end of the tenth pull-down switch, with the connection end used to output the second control signal.

[0038] The first terminal of the eleventh pull-up switch is connected to the power supply terminal, and the second terminal of the eleventh pull-up switch is connected to the first terminal of the eleventh pull-down switch, the control terminal of the twelfth pull-up switch, and the control terminal of the twelfth pull-down switch, respectively; the control terminals of the eleventh pull-up switch and the eleventh pull-down switch are both used to receive the pull-up drive signal.

[0039] The first end of the twelfth pull-up switch is connected to the power supply terminal, and the second end of the twelfth pull-up switch is connected to the first end of the twelfth pull-down switch, with the connection terminal used to output the first control signal.

[0040] The second terminals of the ninth pull-down switch, the tenth pull-down switch, the eleventh pull-down switch, and the twelfth pull-down switch are all grounded.

[0041] In one embodiment, the second reinforcement branch includes a thirteenth pull-up switch and a fourteenth pull-up switch, and the first reinforcement branch includes a thirteenth pull-down switch and a fourteenth pull-down switch.

[0042] The first terminal of the thirteenth pull-up switch is connected to the power supply terminal, and the second terminal of the thirteenth pull-up switch is connected to the first terminal of the fourteenth pull-up switch. The second terminal of the fourteenth pull-up switch is connected to the second terminal of the tenth pull-up switch and the first terminal of the tenth pull-down switch. The control terminal of the thirteenth pull-up switch is used to receive the second slew rate control signal, and the control terminal of the fourteenth pull-up switch is interconnected with the second terminal of the ninth pull-up switch, the first terminal of the ninth pull-down switch, the control terminal of the tenth pull-up switch, and the control terminal of the tenth pull-down switch.

[0043] The first terminal of the thirteenth pull-down switch is connected to the second terminal of the twelfth pull-up switch and the first terminal of the twelfth pull-down switch. The second terminal of the thirteenth pull-down switch is connected to the first terminal of the fourteenth pull-down switch, and the second terminal of the fourteenth pull-down switch is grounded. The control terminal of the thirteenth pull-down switch is interconnected with the second terminal of the eleventh pull-up switch, the first terminal of the eleventh pull-down switch, the control terminal of the twelfth pull-up switch, and the control terminal of the twelfth pull-down switch. The control terminal of the fourteenth pull-down switch is used to receive the first slew rate control signal.

[0044] The first slew rate control signal and the second slew rate control signal are opposite signals.

[0045] In a second aspect, the present invention provides an integrated circuit including the output drive stage through-current suppression circuit as described above.

[0046] The output drive stage current suppression circuit, using the technical solution provided in this embodiment of the invention, includes a pre-drive circuit, a gate drive circuit, and an output drive circuit connected in sequence. The output drive circuit includes a pull-up drive transistor and a pull-down drive transistor. The gate drive circuit can generate a first control signal controlling the conduction state of the pull-up drive transistor and a second control signal controlling the conduction state of the pull-down drive transistor based on the received pull-up drive signal and pull-down drive signal, respectively. In other words, the gate drive circuit can improve the driving capability. The pre-drive circuit can generate the pull-up drive signal and pull-down drive signal based on the input data signal, and the pull-up drive signal and pull-down drive signal have a non-overlapping delay during signal switching. It should also be noted that the pre-drive circuit of this application does not delay the two drive signals as a whole like a delay line. Instead, it uses the difference between the pull-up and pull-down capabilities of the pre-drive circuit itself to generate a directional delay. That is, according to the direction of the output level flip, the control signal corresponding to the drive transistor that needs to be turned off first changes faster, while the control signal corresponding to the drive transistor that needs to be turned on later changes slower, thus forming the required non-overlapping timing. Therefore, during the process of the output of the output drive circuit flipping to a high level, the pull-down drive transistor turns off and then the pull-up drive transistor turns on. Correspondingly, during the process of the output of the output drive circuit flipping to a low level, the pull-up drive transistor turns off and then the pull-down drive transistor turns on.

[0047] The pre-drive circuit only needs to ensure that the pull-up drive signal and the pull-down drive signal have non-overlapping delay during the signal switching process, so the structure is relatively simple. It can be seen that the solution of this application can effectively avoid shoot-through current. Therefore, the solution of this application can avoid shoot-through current without excessively increasing the complexity of the circuit structure, thereby effectively suppressing conduction noise. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the output drive stage through-current suppression circuit provided in a specific embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the structure of the pre-drive circuit in a specific embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of a three-input OR gate in a specific embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the structure of a three-input AND gate in a specific embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of the pre-driver circuit in another specific embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram illustrating the timing changes of the pull-up drive signal and the pull-down drive signal in a specific embodiment of the present invention;

[0055] Figure 7 This is a schematic diagram of the gate driving circuit in a specific embodiment of the present invention;

[0056] Figure 8 This is a waveform diagram of the first control signal and the second control signal in high-speed mode and low-speed mode, respectively, according to a specific embodiment of the present invention. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0058] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the output driver stage shoot-through current suppression circuit according to a specific embodiment of the present invention. The output driver stage shoot-through current suppression circuit may include a pre-drive circuit 10, a gate drive circuit 20, and an output drive circuit 30 connected in sequence.

[0060] The output drive circuit 30 includes a pull-up drive transistor MP0 connected between the power supply terminal and the output terminal for pulling up the output terminal, and a pull-down drive transistor MN0 connected between the output terminal and ground for pulling down the output terminal.

[0061] The gate drive circuit 20 is used to generate a first control signal to control the conduction state of the pull-up drive transistor MP0 and a second control signal to control the conduction state of the pull-down drive transistor MN0, respectively, based on the received pull-up drive signal and pull-down drive signal.

[0062] The pre-drive circuit 10 is used to generate pull-up drive signals and pull-down drive signals according to the input data signals. The pull-up drive signals and pull-down drive signals have non-overlapping delays during the signal switching process, so that when the output of the output drive circuit 30 switches to a high level, the pull-down drive transistor MN0 is turned off and then the pull-up drive transistor MP0 is turned on. And when the output of the output drive circuit 30 switches to a low level, the pull-up drive transistor MP0 is turned off and then the pull-down drive transistor MN0 is turned on.

[0063] Figure 1 In this circuit, the power supply terminal is denoted as VDD. The output drive circuit 30 includes a pull-up drive transistor MP0 for pulling up the output terminal and a pull-down drive transistor MN0 for pulling down the output terminal. In practical applications, the pull-up drive transistor MP0 can usually be a P-type MOS transistor, and the pull-down drive transistor MN0 can usually be an N-type MOS transistor. Figure 1 In the example, the first terminal of the pull-up driver MP0 is the source of the PMOS transistor and is connected to the power supply VDD. The second terminal of the pull-up driver MP0 is its drain and is connected to the output terminal. The first terminal of the pull-down driver MN0 is the drain of the NMOS transistor and is connected to the output terminal. The second terminal of the pull-down driver MN0 is its source and is grounded.

[0064] As can be seen, when the pull-up driver transistor MP0 is turned on and the pull-down driver transistor MN0 is turned off, the power supply terminal supplies power to the output terminal through the pull-up driver transistor MP0, thereby making the output terminal a high-level state. Correspondingly, when the pull-down driver transistor MN0 is turned on and the pull-up driver transistor MP0 is turned off, the output terminal is grounded through the pull-down driver transistor MN0, thereby making the output terminal a low-level state.

[0065] The gate drive circuit 20 is connected between the pre-drive circuit 10 and the output drive circuit 30. It receives the pull-up drive signal and pull-down drive signal output from the pre-drive circuit 10, and generates a first control signal to control the conduction state of the pull-up drive transistor MP0 based on the pull-up drive signal, and a second control signal to control the conduction state of the pull-down drive transistor MN0 based on the pull-down drive signal. For ease of description, the pull-up drive signal and pull-down drive signal output from the pre-drive circuit 10 will be denoted as Pdrive and Ndrive, respectively, and the first and second control signals output from the gate drive circuit 20 will be denoted as Pgate and Ngate, respectively. The gate drive circuit 20 enhances the drive capability; that is, it does not change the drive logic. The logic of Ndrive and Ngate is the same, only their drive capabilities differ. Ngate is responsible for the drive transistors in the output drive circuit 30, and due to its larger load, it requires a larger drive capability. Similarly, the logic of Pdrive and Pgate is the same, but Pgate has a greater drive capability.

[0066] In some embodiments, the gate drive circuit 20 can also decode the driving select signal to generate multiple Pgates (Ngates) that are logically identical to Pdrive (Ndrive).

[0067] Ideally, the pull-up drive transistor MP0 and pull-down drive transistor MN0 in the output drive circuit 30 should be turned on alternately according to a preset timing sequence. That is, when the output signal flips, one drive transistor turns off and the other turns on, thus avoiding the simultaneous conduction of the two drive transistors. However, in the actual application of traditional solutions, due to the influence of factors such as the drive signal transmission path, device response speed, and differences in process parameters, there may be an overlap between the control signals of the pull-up drive transistor MP0 and the pull-down drive transistor MN0, causing the pull-up drive transistor MP0 and the pull-down drive transistor MN0 to conduct simultaneously for a short period of time.

[0068] In this application, the pre-drive circuit 10 generates pull-up and pull-down drive signals based on the input data signal, ensuring a non-overlapping delay during the signal switching process. This non-overlapping delay refers to a certain time interval between the two control signals controlling the pull-up drive transistor MP0 and the pull-down drive transistor MN0, allowing the other drive transistor to turn on only after the currently conducting transistor has turned off, thus preventing the simultaneous conduction of both the pull-up drive transistor MP0 and the pull-down drive transistor MN0.

[0069] The pre-drive circuit 10 can receive input data signals, hereinafter referred to as I. In this application, the pre-drive circuit 10 is not only used to complete the logic conversion from the input data signal I to the pull-up drive signal Pdrive and the pull-down drive signal Ndrive, but also used to control the timing of the changes in the pull-up drive signal Pdrive and the pull-down drive signal Ndrive, so that the two drive signals form the required non-overlapping delay during the signal switching process.

[0070] Specifically, when the input data signal switches, for example, when the input data signal I switches from low level to high level, the output terminal of the output drive circuit 30 also needs to switch from low level to high level. Therefore, the pull-down drive transistor MN0, which is currently in the on state, needs to be turned off first, and then the pull-up drive transistor MP0 needs to be turned on. In order to achieve this process, the front-end circuit 10 needs to make the pull-down drive signal Ndrive change accordingly first, so that the second control signal Ngate is low through the gate drive circuit 20, thereby turning off the pull-down drive transistor MN0. After the corresponding non-overlapping delay, the pull-up drive signal Pdrive changes accordingly again, so that the first control signal Pgate is low through the gate drive circuit 20, thereby turning on the pull-up drive transistor MP0, and the output terminal of the output drive circuit 30 switches from low level to high level.

[0071] Correspondingly, when I switches from high level to low level, the output terminal of the output drive circuit 30 needs to switch from high level to low level. Therefore, the pull-up drive transistor MP0, which is currently in the conducting state, needs to be turned off first, and then the pull-down drive transistor MN0 needs to be turned on. In order to achieve this process, the front-end circuit 10 needs to make the pull-up drive signal Pdrive change accordingly, so that the first control signal Pgate is high through the gate drive circuit 20, thereby turning off the pull-up drive transistor MP0. After the corresponding non-overlapping delay, the pull-down drive signal Ndrive changes accordingly, so that the second control signal Ngate is high through the gate drive circuit 20, thereby turning on the pull-down drive transistor MN0, and the output terminal of the output drive circuit 30 switches from high level to low level.

[0072] It can be seen that regardless of whether the output of the output driving circuit 30 switches from low level to high level or from high level to low level, the pull-up driving transistor MP0 and pull-down driving transistor MN0 of the output driving circuit 30 can achieve the purpose of turning on the other driving transistor after the driving transistor that is currently in the conducting state is turned off, thus avoiding the situation where the two driving transistors are conducting at the same time during the switching process.

[0073] There are various ways to implement the pre-drive circuit 10. The goal is to ensure that the pull-up drive signal and the pull-down drive signal have the required non-overlapping delay during signal switching. This can typically be achieved using logic gate circuits. In one specific embodiment of the invention, the pre-drive circuit 10 includes at least one logic gate circuit composed of a pull-up network and a pull-down network, and the pull-up network and the pull-down network have different driving capabilities to form a non-overlapping delay.

[0074] This implementation takes into account that the pre-driver circuit 10 can be implemented by a single logic gate or by connecting multiple logic gates. The more logic gates used, the longer the non-overlapping delay. Therefore, in practical applications, the number of logic gates can be selected according to needs. Furthermore, in this implementation, the pull-up and pull-down networks of the logic gates are not set up in a completely symmetrical manner, but rather there is a difference in driving capability between the pull-up and pull-down networks, thereby achieving the required non-overlapping delay.

[0075] For example, in practical applications, when the input data signal I switches from low to high, the pull-down network's driving capability for the pull-down drive signal Ndrive is stronger than the pull-up network's driving capability for the pull-up drive signal Pdrive. This causes the pull-down drive signal Ndrive to change first, and after a corresponding non-overlapping delay, the pull-up drive signal Pdrive changes accordingly. Similarly, when the input data signal I switches from high to low, the pull-up network's driving capability for the pull-up drive signal Pdrive is stronger than the pull-down network's driving capability for the pull-down drive signal Ndrive. This causes the pull-up drive signal Pdrive to change first, and after a corresponding non-overlapping delay, the pull-down drive signal Ndrive changes accordingly.

[0076] It should also be noted that the driving capability of pull-up and pull-down networks is affected by various factors such as the size and number of related switching transistors and their series-parallel connection. In practical applications, the functional requirements of the logic gate circuit in this application can be achieved by reasonably setting the structure of the pull-up and pull-down networks and the size and number of related switching transistors.

[0077] In one specific embodiment of the present invention, see [reference needed]. Figure 2 The front-end circuit 10 includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a three-input AND gate AND3, and a three-input OR gate OR3;

[0078] The input terminal of the first inverter INV1 is connected to the second input terminal of the three-input OR gate OR3, and the connection terminal is used to receive the output enable signal OEB; the output terminal of the first inverter INV1 is connected to the second input terminal of the three-input AND gate AND3.

[0079] The first input of the three-input AND gate AND3 is connected to the third input of the three-input OR gate OR3, and the connection is used to receive input data signals; the third input of the three-input AND gate AND3 is connected to the output of the three-input OR gate OR3 and the input of the third inverter INV3; the first input of the three-input OR gate OR3 is connected to the output of the three-input AND gate AND3 and the input of the second inverter INV2.

[0080] The output of the second inverter INV2 serves as the first output of the pre-drive circuit 10 to output a pull-up drive signal, and the output of the third inverter INV3 serves as the second output of the pre-drive circuit 10 to output a pull-down drive signal.

[0081] Figure 2 In this context, the input data signal is denoted as I. The enable signal for a GPIO interface is typically represented by Output Enable, or OE. Generally, OE=1 (OEB=0) indicates an enabled state, meaning the IO can output data. Figure 2 In this diagram, the output enable signal is denoted as OEB. When OEB is enabled, it is low. In this state, the pre-driver circuit 10 can control the output terminal of the output driver circuit 30 to output the corresponding logic level based on the input data signal I. When OEB is disabled, it is high. In this state, the pre-driver circuit 10 can turn off both the pull-up driver transistor MP0 and the pull-down driver transistor MN0 of the output driver circuit 30, thus making the output terminal of the output driver circuit 30 high-impedance. The following descriptions will all be based on the condition that OEB is low, i.e., in the enabled state.

[0082] For ease of description, the output signal of the three-input AND gate AND3 is denoted as PB, and the output signal of the three-input OR gate OR3 is denoted as NB.

[0083] When the input data signal I is stable at a low level, the first input of the three-input AND gate AND3 is low, therefore PB is low. Meanwhile, the three input signals PB, OEB, and I of the three-input OR gate OR3 are all low, therefore NB is also low. Because of the second inverter INV2 and the third inverter INV3, both the pull-up drive signal Pdrive and the pull-down drive signal Ndrive are high. After passing through the gate drive circuit 20, the first control signal Pgate and the second control signal Ngate are also high. At this time, the pull-up drive transistor MP0 is off, the pull-down drive transistor MN0 is on, and the output is low.

[0084] When the input data signal I switches from low to high, the third input of the three-input OR gate OR3 receives a high level, allowing NB to switch to high. Furthermore, in the following embodiments, the three-input OR gate OR3 can be configured as an asymmetric three-input OR gate where the pull-up speed of the output signal NB is faster than its pull-down speed, allowing NB to switch from low to high more quickly. The third inverter INV3 inverts NB; therefore, when NB switches from low to high quickly, the pull-down drive signal Ndrive switches from high to low quickly, allowing the pull-down drive transistor MN0 to be turned off first.

[0085] After NB switches to a high level, the first, second, and third inputs of the three-input AND gate AND3 are all high, and only then does PB begin to switch from low to high. Furthermore, in the embodiments described later, the three-input AND gate AND3 can be configured as an asymmetric three-input AND gate AND3 where the pull-down speed of the output signal PB is faster than the pull-up speed (i.e., the pull-up speed of PB is slower than the pull-down speed). Therefore, the transition of PB from low to high can have a relatively large delay. Of course, even without this configuration, it can be seen that the level transition of PB at this time is still later than the level transition of NB. The second inverter INV2 inverts PB, so the pull-up drive signal Pdrive switches from high to low only after PB has completed its rise, ensuring that the pull-up drive transistor MP0 is turned on after the pull-down drive transistor MN0 has been turned off.

[0086] Correspondingly, when the input data signal I is stable at a high level, both NB and PB are high, and the pull-up drive signal Pdrive and the pull-down drive signal Ndrive are low. After passing through the gate drive circuit 20, the pull-down drive transistor MN0 is turned off, the pull-up drive transistor MP0 is turned on, and the output is driven to a high level.

[0087] When the input data signal I switches from high to low, the first input of the three-input AND gate AND3 receives a low level, allowing PB to switch to low. Furthermore, in the following embodiments, the three-input AND gate AND3 can be configured as an asymmetric three-input AND gate where the pull-down speed of the output signal PB is faster than the pull-up speed, allowing PB to switch from high to low more quickly. The second inverter INV2 inverts PB; therefore, when PB switches from high to low more quickly, the pull-up drive signal Pdrive switches from low to high more quickly, causing the pull-up drive transistor MP0 to turn off first.

[0088] After PB switches to low, all three input signals of the three-input OR gate OR3—PB, OEB, and I—are low, and only then does NB begin to switch from high to low. Furthermore, in the embodiments described later, the three-input OR gate OR3 can be configured as an asymmetric three-input OR gate OR3 where the pull-up speed of the output signal NB is faster than the pull-down speed (i.e., the pull-down speed of NB is slower than the pull-up speed). Therefore, the transition of NB from high to low can have a relatively large delay. Of course, even without this configuration, it can be seen that the level transition of NB at this time is still later than the level transition of PB. The third inverter INV3 inverts NB; therefore, the pull-down drive signal Ndrive switches from low to high only after NB has completed its fall, which means that the pull-down drive transistor MN0 is turned on after the pull-up drive transistor MP0 has been turned off.

[0089] It can be seen that this implementation method effectively achieves the functional requirements of the present application for the pre-driver circuit 10. The pre-driver circuit 10 is implemented by one logic gate circuit, and the structure of the logic gate circuit is very simple, which facilitates the implementation of the present application.

[0090] In one specific embodiment of the present invention, the three-input OR gate OR3 includes: a first pull-up switch MP1, a second pull-up switch MP2, a third pull-up switch MP3, a first pull-down switch MN1, a second pull-down switch MN2, a third pull-down switch MN3, and a first inverting unit composed of a fourth pull-up switch MP4 and a fourth pull-down switch MN4.

[0091] The first end of the third pull-up switch MP3 is connected to the power supply end. The second end of the third pull-up switch MP3 is connected to the first end of the second pull-up switch MP2. The second end of the second pull-up switch MP2 is connected to the first end of the first pull-up switch MP1. The second end of the first pull-up switch MP1 is connected to the first end of the first pull-down switch MN1, the first end of the second pull-down switch MN2, the first end of the third pull-down switch MN3, the control end of the fourth pull-up switch MP4, and the control end of the fourth pull-down switch MN4.

[0092] The second terminals of the first pull-down switch MN1, the second pull-down switch MN2, the third pull-down switch MN3, and the fourth pull-down switch MN4 are all grounded. The first terminal of the fourth pull-up switch MP4 is connected to the power supply terminal. The second terminal of the fourth pull-up switch MP4 is connected to the first terminal of the fourth pull-down switch MN4, and the connection terminal serves as the output terminal of the three-input OR gate OR3.

[0093] The control terminals of the first pull-up switch MP1 and the first pull-down switch MN1 are both connected to the first input terminal of the three-input OR gate OR3. The control terminals of the second pull-up switch MP2 and the second pull-down switch MN2 are both connected to the second input terminal of the three-input OR gate OR3. The control terminals of the third pull-up switch MP3 and the third pull-down switch MN3 are both connected to the third input terminal of the three-input OR gate OR3.

[0094] See also Figure 3 The three-input OR gate OR3 is a two-stage circuit. The first stage is a three-input NOR gate, consisting of a first pull-up switch MP1, a second pull-up switch MP2, a third pull-up switch MP3, a first pull-down switch MN1, a second pull-down switch MN2, and a third pull-down switch MN3. The second stage is an inverter, also known as the first inverting unit, consisting of a fourth pull-up switch MP4 and a fourth pull-down switch MN4. The first inverting unit and the second inverting unit in the following embodiments can usually adopt a symmetrical design. Therefore, the asymmetry of the asymmetrical three-input OR gate OR3 is reflected in the asymmetry of the pull-up and pull-down capabilities of the first stage.

[0095] Figure 3 The code also indicates the parasitic capacitances of some nodes, such as C1, C2, and CL1. C1 is the parasitic capacitance between the source of MP1 and the drain of MP2, C2 is the parasitic capacitance between the source of MP2 and the drain of MP3, and CL1 is the parasitic capacitance of the first-stage output node. In practical applications, Figure 3 Each pull-up transistor in the circuit can typically be a PMOS transistor, while each pull-down transistor can typically be an NMOS transistor. To simplify the setup, the dimensions (width-to-length ratio W / L) of each MOS transistor in the circuit can satisfy the following conditions:

[0096] (W / L) MP1 = (W / L) MP2 = (W / L) MP3 =Mp;

[0097] (W / L) MN1 = (W / L) MN2 = (W / L) MN3 =Mn.

[0098] The on-resistance of a MOSFET, RDS(on), can be expressed as:

[0099] .

[0100] Since the size (width-to-length ratio) of a MOSFET is approximately inversely proportional to its on-resistance, the on-resistances of each PMOS and NMOS transistor are equal, denoted as Rp and Rn respectively. With the same width-to-length ratio, due to the mobility difference between PMOS and NMOS transistors, the on-resistance of a PMOS is typically twice that of an NMOS, say twice. Therefore, if the pull-up and pull-down capabilities are symmetrical, the overall size of the pull-up network can typically be twice that of the pull-down network. Furthermore, for... Figure 3 In the structure, MN1 to MN3 are connected in parallel, and their combined size can be regarded as the size of a single tube, denoted as Mn=m. MP1 to MP3 are connected in series, so if the symmetry of the pull-up network and the pull-down network is to be ensured, the size can be set to Mp=6×m.

[0101] Furthermore, based on the above... Figure 2 As described above, both the three-input OR gate (OR3) and the three-input AND gate (AND3) can achieve non-overlapping delay regardless of whether an asymmetric setting is used. However, if an asymmetric setting is not used, the duration of the non-overlapping delay may be shorter. Therefore, in practical applications, in order to ensure sufficient non-overlapping delay, the three-input OR gate (OR3) is usually specifically set as an asymmetric three-input OR gate (OR3). Similarly, the three-input AND gate (AND3) is usually specifically set as an asymmetric three-input AND gate (AND3). The following text will use the asymmetric three-input OR gate (OR3) and the asymmetric three-input AND gate (AND3) as examples for explanation.

[0102] Because it is an asymmetric three-input OR gate OR3, the pull-up speed of the output signal NB is faster than the pull-down speed, allowing NB to switch from low level to high level more quickly. That is, the pull-up capability of the asymmetric three-input OR gate OR3 is stronger than its own pull-down capability. Therefore, for the first stage of the asymmetric three-input OR gate OR3, the pull-down capability is stronger than the pull-up capability. After passing through the first inverting unit, this can be reflected in the fact that the pull-up speed of the NB signal is faster than the pull-down speed.

[0103] To address this, the pull-up capability of the first-stage 3-input NOR gate can be weakened, i.e., Mp can be reduced, or the pull-down capability of the first-stage 3-input NOR gate can be strengthened, i.e., Mn can be increased. For example, in one specific implementation, Mp is reduced to be equal to m, at which point its pull-up capability becomes 1 / 6 of its original value.

[0104] The following section, in conjunction with the change process of the input data signal I, analyzes... Figure 3 The working process of the asymmetric three-input OR gate OR3 is explained.

[0105] When the input data signal I is a stable low level, PB is low. At this time, the first pull-up switch MP1, the second pull-up switch MP2, and the third pull-up switch MP3 are all turned on, while the first pull-down switch MN1, the second pull-down switch MN2, and the third pull-down switch MN3 are all turned off. At this time, V... C1 =V C2 =V CL1 =VDD, NB is low level.

[0106] When the input data signal I switches from low to high, PB remains low at this initial moment. The third pull-up switch MP3 is off and the third pull-down switch MN3 is on; therefore, CL1 discharges directly to ground through the third pull-down switch MN3. Because the third pull-down switch MN3 has a strong pull-down capability, CL1 can discharge quickly through MN3, causing the fourth pull-up switch MP4 to turn on and the fourth pull-down switch MN4 to turn off, thus causing NB to rise quickly to a high level. It can be seen that the output signal NB of the asymmetric three-input OR gate OR3 has a fast pull-up speed.

[0107] Furthermore, during the rapid discharge of CL1, C1 and C2 can also slowly discharge through the first pull-up switch MP1, the second pull-up switch MP2, and the third pull-down switch MN3, which are still in the on state. As NB rises, PB will then switch from low to high, turning off the first pull-up switch MP1 and turning on the first pull-down switch MN1, thereby ending the conduction path of C1 and C2. Ideally, V will eventually... C1 =V C2 =0.

[0108] When the input data signal I is a stable high level, PB is high. At this time, the first pull-up switch MP1 and the third pull-up switch MP3 are both off, and the first pull-down switch MN1 and the third pull-down switch MN3 are both on. The output node of the first stage remains low, therefore V C1 =V C2 =V CL1 =0, NB is high level.

[0109] When the input data signal I switches from high to low, PB remains high at this initial moment. The third pull-up switch MP3 is turned on and the third pull-down switch MN3 is turned off. However, since PB is still high, the first pull-up switch MP1 remains off and the first pull-down switch MN1 remains on. Therefore, the output node of the first stage is still held low by the first pull-down switch MN1. Only after the asymmetric three-input AND gate AND3 switches PB from high to low can the first pull-up switch MP1 be turned on and the first pull-down switch MN1 be turned off. At this time, the first pull-up switch MP1, the second pull-up switch MP2, and the third pull-up switch MP3 are all turned on, and the power supply charges the parasitic capacitors C1, C2, and CL1 through the three series-connected pull-up switches. Because the charging path includes three series-connected pull-up switches and needs to charge the parasitic capacitances of multiple internal nodes, the speed at which the output node of the first stage changes from low to high is relatively slow. The first inverting unit only switches NB from high to low after the output node of the first stage gradually rises to the corresponding toggling threshold. It can be seen that, due to the characteristic that the pull-down speed of the first-stage 3-input OR gate is faster than the pull-up speed, after being inverted by the first inverting unit, the entire asymmetric three-input OR gate OR3 exhibits that the pull-up speed of NB is faster than the pull-down speed.

[0110] In one specific embodiment of the present invention, see [reference needed]. Figure 4 The three-input AND gate AND3 includes: a fifth pull-up switch MP5, a sixth pull-up switch MP6, a seventh pull-up switch MP7, a fifth pull-down switch MN5, a sixth pull-down switch MN6, a seventh pull-down switch MN7, and a second inverting unit composed of an eighth pull-up switch MP8 and an eighth pull-down switch MN8;

[0111] The first terminals of the fifth pull-up switch MP5, the sixth pull-up switch MP6, and the seventh pull-up switch MP7 are all connected to the power supply terminal; the second terminal of the fifth pull-up switch MP5 is connected to the second terminal of the sixth pull-up switch MP6, the second terminal of the seventh pull-up switch MP7, the first terminal of the fifth pull-down switch MN5, the control terminal of the eighth pull-up switch MP8, and the control terminal of the eighth pull-down switch MN8, respectively.

[0112] The second end of the fifth pull-down switch MN5 is connected to the first end of the sixth pull-down switch MN6, the second end of the sixth pull-down switch MN6 is connected to the first end of the seventh pull-down switch MN7, and the second end of the seventh pull-down switch MN7 is grounded.

[0113] The first terminal of the eighth pull-up switch MP8 is connected to the power supply terminal, the second terminal of the eighth pull-up switch MP8 is connected to the first terminal of the eighth pull-down switch MN8, and the connection terminal serves as the output terminal of the three-input AND gate AND3. The second terminal of the eighth pull-down switch MN8 is grounded.

[0114] The control terminals of the fifth pull-up switch MP5 and the fifth pull-down switch MN5 are both connected to the first input terminal of the three-input AND gate AND3. The control terminals of the sixth pull-up switch MP6 and the sixth pull-down switch MN6 are both connected to the second input terminal of the three-input AND gate AND3. The control terminals of the seventh pull-up switch MP7 and the seventh pull-down switch MN7 are both connected to the third input terminal of the three-input AND gate AND3.

[0115] Figure 4 MP5 to MP7 are connected in parallel, and their combined size is the size of a single transistor, denoted as Mp=m. MN5 to MN7 are connected in series, similar to the above. To ensure symmetry, the size can be set to Mn=6m. Furthermore, as described above, to ensure sufficient non-overlapping delay, the three-input AND gate AND3 is usually specifically configured as an asymmetric three-input AND gate AND3, so that the pull-down speed of its output signal PB is faster than its pull-up speed, allowing PB to switch from high to low level more quickly. In other words, for an asymmetric three-input AND gate AND3, its pull-down capability can be stronger than its pull-up capability.

[0116] Figure 4 The asymmetric three-input AND gate AND3 also has a two-stage structure. The first stage is a 3-input NAND gate, consisting of the fifth pull-up switch MP5, the sixth pull-up switch MP6, the seventh pull-up switch MP7, the fifth pull-down switch MN5, the sixth pull-down switch MN6, and the seventh pull-down switch MN7. The second stage is an inverter, also known as the second inverting unit, consisting of the eighth pull-up switch MP8 and the eighth pull-down switch MN8. The asymmetry of the asymmetric three-input AND gate AND3 is reflected in the asymmetry of the pull-up and pull-down capabilities of the first stage.

[0117] Therefore, for the first stage of the asymmetric three-input AND gate AND3, the pull-up capability of the 3-input NAND gate can be made stronger than its pull-down capability. After passing through the second inverting unit, this manifests as the pull-down speed of the PB signal being faster than its pull-up speed. To address this, the pull-down capability of the first stage 3-input NAND gate can be weakened, i.e., Mn can be reduced, or the pull-up capability of the first stage 3-input NAND gate can be strengthened, i.e., Mp can be increased. For example, in one specific implementation, Mn can be reduced to be equal to m, at which point its pull-down capability becomes 1 / 6 of its original value.

[0118] The following section, in conjunction with the change process of the input data signal I, analyzes... Figure 4 The working process of the asymmetric three-input AND gate AND3 will be explained.

[0119] When the input data signal I is stable at a high level, NB is at a high level, and the fifth pull-up switch MP5, the sixth pull-up switch MP6, and the seventh pull-up switch MP7 are all turned off, while the fifth pull-down switch MN5, the sixth pull-down switch MN6, and the seventh pull-down switch MN7 are all turned on. The output node of the first-stage 3-input NAND gate is grounded through three series-connected pull-down switches, therefore V C3 =V C4 =V CL2 =0, the eighth pull-up switch MP8 is turned on, and PB is at a high level.

[0120] When the input data signal I switches from high to low, NB remains high at this initial moment. The fifth pull-up switch MP5 is turned on and the fifth pull-down switch MN5 is turned off. Therefore, CL2 is charged through the fifth pull-up switch MP5. Because this pull-up network has strong pull-up capability, the parasitic capacitance CL2 of the output node of the first-stage 3-input AND gate can be quickly charged through the fifth pull-up switch MP5. This causes the eighth pull-up switch MP8 to turn off and the eighth pull-down switch MN8 to turn on, allowing PB to quickly switch from high to low. Therefore, the output signal PB of the asymmetric three-input AND gate AND3 has a fast pull-down speed.

[0121] When the input data signal I is stably at a low level, NB is at a low level, the fifth pull-up switch MP5 and the seventh pull-up switch MP7 are both turned on, and the fifth pull-down switch MN5 and the seventh pull-down switch MN7 are both turned off. CL2 =VDD,V C3 =V C4 =0, PB is low level.

[0122] When the input data signal I switches from low to high, NB initially remains low, the fifth pull-up switch MP5 is off, and the fifth pull-down switch MN5 is on. However, since NB is still low, the seventh pull-up switch MP7 remains on, and the seventh pull-down switch MN7 remains off. Therefore, V CL2 The value remains VDD. Only after the asymmetric three-input OR gate OR3 switches NB from low to high is the seventh pull-up switch MP7 turned off and the seventh pull-down switch MN7 turned on. At this time, the fifth pull-down switch MN5, the sixth pull-down switch MN6, and the seventh pull-down switch MN7 are all turned on, and CL2 discharges to ground through the three series-connected pull-down switches. Because this discharge path involves three series-connected pull-down switches and requires discharging the parasitic capacitance of the corresponding internal nodes, VDD... CL2 The transition from high to low level is relatively slow. The second inverting unit at V... CL2After gradually decreasing to the corresponding toggling threshold, PB switches from low to high. It can be seen that the first-stage 3-input AND gate has the characteristic that the pull-up speed is faster than the pull-down speed. After being inverted by the second inverting unit, the entire asymmetric 3-input AND gate AND3 exhibits that the pull-down speed of PB is faster than the pull-up speed.

[0123] In one specific embodiment of the present invention, the pre-drive circuit 10 may further include: a first OR gate OR2, a first AND gate AND2, a fourth inverter INV4, and a fifth inverter INV5.

[0124] The output of the second inverter INV2 is connected to the first input of the first NOR gate OR2, the second input of the first NOR gate OR2 is connected to the output of the fifth inverter INV5, and the output of the first NOR gate OR2 is connected to the input of the fourth inverter INV4.

[0125] The output of the third inverter INV3 is connected to the first input of the first NAND gate AND2, the second input of the first NAND gate AND2 is connected to the output of the fourth inverter INV4, and the output of the first NAND gate AND2 is connected to the input of the fifth inverter INV5.

[0126] Correspondingly, the output of the fourth inverter INV4 serves as the first output of the pre-drive circuit 10 to output a pull-up drive signal, and the output of the fifth inverter INV5 serves as the second output of the pre-drive circuit 10 to output a pull-down drive signal.

[0127] As described above, the precursor circuit 10 can be implemented by a single logic gate or by connecting multiple logic gates. The more logic gates used, the longer the non-overlapping delay. (See also...) Figure 5 In this implementation, the first OR gate OR2, the first NAND gate AND2, the fourth inverter INV4, and the fifth inverter INV5 constitute the second logic gate circuit. Furthermore... Figure 5 For ease of distinction, the output signals of the first logic gate are denoted as Ndrive0 and Pdrive0.

[0128] In practical applications, the number of cascaded logic gates can be further increased according to actual needs to achieve the required non-overlapping delay. Furthermore, it is understood that the specific types and structures of the logic gates at each stage can be the same or different, as long as the final output pull-up drive signal Pdrive and pull-down drive signal Ndrive meet the required non-overlapping delay.

[0129] For example, for the first OR gate OR2 and the first AND gate AND2 in this implementation, the above methods can be used respectively. Figure 3 and Figure 4 The implementation method is as follows (the ports connecting OE and OEB are set to a fixed level, which can change the input from 3 inputs to 2 inputs), which will not be repeated here.

[0130] See also Figure 6 , Figure 6 This diagram illustrates the timing changes of the pull-up drive signal Pdrive and the pull-down drive signal Ndrive. In this application, the pre-driver circuit 10 ensures that when the input data signal I switches from low to high, the pull-down drive signal Ndrive first switches from high to low, thus turning off the pull-down drive transistor MN0. After a non-overlapping delay, the pull-up drive signal Pdrive then switches from high to low, thus turning on the pull-up drive transistor MP0. Correspondingly, when the input data signal I switches from high to low, the pull-up drive signal Pdrive first switches from low to high, thus turning off the pull-up drive transistor MP0. After a non-overlapping delay, the pull-down drive signal Ndrive then switches from low to high, thus turning on the pull-down drive transistor MN0. Figure 6 In this case, the high-level duty cycle of the pull-up drive signal Pdrive is greater than the high-level duty cycle of the pull-down drive signal Ndrive.

[0131] In one specific embodiment of the present invention, the gate driving circuit 20 includes a first control signal generation branch, a second control signal generation branch, a first enhancement branch, and a second enhancement branch;

[0132] The input terminal of the first control signal generation branch is used to receive the pull-up drive signal, and the output terminal is used to output the first control signal.

[0133] The input terminal of the second control signal generation branch is used to receive the pull-down drive signal, and the output terminal of the second control signal generation branch is used to output the second control signal.

[0134] The first enhancement branch is connected to the output terminal of the first control signal generation branch, and is used to enhance the output slew rate of the first control signal when the first slew rate control signal is effective.

[0135] The second enhancement branch is connected to the output of the second control signal generation branch and is used to enhance the output slew rate of the second control signal when the second slew rate control signal is effective.

[0136] In this embodiment, the first control signal generation branch and the second control signal generation branch output the first control signal and the second control signal, respectively, thereby realizing the function of the gate drive circuit 20. Furthermore, in this embodiment, the first enhancement branch and the second enhancement branch can enhance the output slew rate of the first control signal and the output slew rate of the second control signal, thereby further improving the driving capability of the gate drive circuit 20.

[0137] Output slew rate refers to dV / dt, which is the slope of the voltage change over time. It describes the driving capability of the output stage; a larger slope indicates a stronger driving force. In GPIO, the output slope is typically controlled by the control signal SL. The first enhancement branch enhances the output slew rate of the first control signal, i.e., increases the speed at which the first control signal Pgate changes from high to low, allowing the pull-up driver MP0 to turn on more quickly. The second enhancement branch increases the speed at which the second control signal Ngate changes from low to high, allowing the pull-down driver MN0 to turn on more quickly.

[0138] The specific structures of the first control signal generation branch, the second control signal generation branch, the first enhancement branch, and the second enhancement branch can be set according to actual needs. For example, in one specific embodiment of the present invention, see [reference needed]. Figure 7 The second control signal generation branch includes the ninth pull-up switch MP9, the tenth pull-up switch MP10, the ninth pull-down switch MN9, and the tenth pull-down switch MN10; the first control signal generation branch includes the eleventh pull-up switch MP11, the twelfth pull-up switch MP12, the eleventh pull-down switch MN11, and the twelfth pull-down switch MN12.

[0139] The first terminal of the ninth pull-up switch MP9 is connected to the power supply terminal, and the second terminal of the ninth pull-up switch MP9 is connected to the first terminal of the ninth pull-down switch MN9, the control terminal of the tenth pull-up switch MP10, and the control terminal of the tenth pull-down switch MN10, respectively. The control terminals of the ninth pull-up switch MP9 and the ninth pull-down switch MN9 are both used to receive pull-down drive signals.

[0140] The first terminal of the tenth pull-up switch MP10 is connected to the power supply terminal, and the second terminal of the tenth pull-up switch MP10 is connected to the first terminal of the tenth pull-down switch MN10, and the connection terminal is used to output the second control signal.

[0141] The first terminal of the eleventh pull-up switch MP11 is connected to the power supply terminal. The second terminal of the eleventh pull-up switch MP11 is connected to the first terminal of the eleventh pull-down switch MN11, the control terminal of the twelfth pull-up switch MP12, and the control terminal of the twelfth pull-down switch MN12, respectively. The control terminals of the eleventh pull-up switch MP11 and the eleventh pull-down switch MN11 are both used to receive pull-up drive signals.

[0142] The first terminal of the twelfth pull-up switch MP12 is connected to the power supply terminal, and the second terminal of the twelfth pull-up switch MP12 is connected to the first terminal of the twelfth pull-down switch MN12, and the connection terminal is used to output the first control signal.

[0143] The second terminal of the ninth pull-down switch MN9, the second terminal of the tenth pull-down switch MN10, the second terminal of the eleventh pull-down switch MN11, and the second terminal of the twelfth pull-down switch MN12 are all grounded.

[0144] In this embodiment, the second control signal generation branch includes a ninth pull-up switch MP9, a tenth pull-up switch MP10, a ninth pull-down switch MN9, and a tenth pull-down switch MN10. As can be seen from the circuit structure, the ninth pull-up switch MP9 and the ninth pull-down switch MN9 constitute the first-stage inverting unit, and the tenth pull-up switch MP10 and the tenth pull-down switch MN10 constitute the second-stage inverting unit. Through two stages of inversion, the second control signal Ngate and the pull-down drive signal Ndrive have the same logic state, and the second-stage inverting unit can provide a greater drive capability. Furthermore, the switch size in the second-stage inverting unit described here is typically larger than the switch size in the first-stage inverting unit, thereby progressively increasing the drive capability to meet the gate drive requirements of the pull-up drive MP0 and the pull-down drive MN0. In this embodiment, the first control signal generation branch also has this structure, and will not be described again.

[0145] The first and second control signal generation branches in this embodiment have simple structures and are easy to implement.

[0146] In one specific embodiment of the present invention, the second enhancement branch includes a thirteenth pull-up switch MP13 and a fourteenth pull-up switch MP14, and the first enhancement branch includes a thirteenth pull-down switch MN13 and a fourteenth pull-down switch MN14.

[0147] The first terminal of the thirteenth pull-up switch MP13 is connected to the power supply terminal, and the second terminal of the thirteenth pull-up switch MP13 is connected to the first terminal of the fourteenth pull-up switch MP14. The second terminal of the fourteenth pull-up switch MP14 is connected to the second terminal of the tenth pull-up switch MP10 and the first terminal of the tenth pull-down switch MN10, respectively. The control terminal of the thirteenth pull-up switch MP13 is used to receive the second slew rate control signal, and the control terminal of the fourteenth pull-up switch MP14 is interconnected with the second terminal of the ninth pull-up switch MP9, the first terminal of the ninth pull-down switch MN9, the control terminal of the tenth pull-up switch MP10, and the control terminal of the tenth pull-down switch MN10.

[0148] The first terminal of the thirteenth pull-down switch MN13 is connected to the second terminal of the twelfth pull-up switch MP12 and the first terminal of the twelfth pull-down switch MN12. The second terminal of the thirteenth pull-down switch MN13 is connected to the first terminal of the fourteenth pull-down switch MN14. The second terminal of the fourteenth pull-down switch MN14 is grounded. The control terminal of the thirteenth pull-down switch MN13 is interconnected with the second terminal of the eleventh pull-up switch MP11, the first terminal of the eleventh pull-down switch MN11, the control terminal of the twelfth pull-up switch MP12, and the control terminal of the twelfth pull-down switch MN12. The control terminal of the fourteenth pull-down switch MN14 is used to receive the first slew rate control signal.

[0149] Among them, the first slew rate control signal and the second slew rate control signal are opposite signals.

[0150] See also Figure 7 As can be seen from the circuit structure, when the second slew rate control signal SL is valid and the second control signal generation branch needs to pull up the second control signal Ngate, the thirteenth pull-up switch MP13 and the fourteenth pull-up switch MP14 are turned on, thereby forming an additional pull-up path between the power supply terminal and the output terminal of the second control signal Ngate. This additional pull-up path is connected in parallel with the pull-up path formed by the tenth pull-up switch MP10, thereby enhancing the pull-up capability of the second control signal Ngate, increasing the output slew rate when the second control signal Ngate changes from low level to high level, and enabling the pull-down drive transistor MN0 to turn on faster.

[0151] Accordingly, when the first slew rate control signal is valid and the first control signal generation branch needs to pull down the first control signal Pgate, the first enhancement branch can enhance the pull-down capability of the first control signal Pgate, improve the output slew rate when the first control signal Pgate changes from high level to low level, and enable the pull-up drive transistor MP0 to turn on faster.

[0152] Furthermore, it is understood that whether to activate the first and second enhancement branches can be selected as needed, thus ensuring the flexibility of the solution in this application. A schematic diagram of the output waveform can be found in the attached diagram. Figure 8 SL=0 (SLB=1) is the high-speed mode, and SL=1 (SLB=0) is the low-speed mode. Enabling the first and second enhancement branches via SL (SLB) enhances the pull-up (pull-down) capability of the Ngate (Pgate), allowing the output stage driver transistors to turn on faster and increasing the maximum transmission speed. This function can also be disabled; for example, in applications that do not require high-speed transmission, this function can be turned off to use the low-speed mode.

[0153] Furthermore, it is understandable that the adjustable range of the output slew rate is limited. Figure 6 The marker ① indicates the setting range of the Ngate rising slope, and the marker ② indicates the setting range of the Pgate falling slope.

[0154] Applying the technical solution provided in this embodiment of the invention, the output driver stage shoot-through current suppression circuit includes a pre-drive circuit 10, a gate drive circuit 20, and an output drive circuit 30 connected in sequence. The output drive circuit 30 includes a pull-up drive transistor MP0 and a pull-down drive transistor MN0. The gate drive circuit 20 can generate a first control signal controlling the conduction state of the pull-up drive transistor MP0 and a second control signal controlling the conduction state of the pull-down drive transistor MN0, respectively, based on the received pull-up drive signal and pull-down drive signal. In other words, the gate drive circuit 20 can improve the driving capability. The pre-drive circuit 10 can generate pull-up drive signal and pull-down drive signal based on the input data signal, and the pull-up drive signal and pull-down drive signal have a non-overlapping delay during signal switching. It should also be noted that the pre-drive circuit 10 of this application does not delay the two drive signals as a whole like a delay line. Instead, it uses the difference between the pull-up and pull-down capabilities of the pre-drive circuit 10 to generate a directional delay. That is, according to the direction of the output level flip, the control signal corresponding to the drive transistor that needs to be turned off first changes faster, while the control signal corresponding to the drive transistor that needs to be turned on later changes slower, thereby forming the required non-overlapping timing. Therefore, during the process of the output of the output drive circuit 30 flipping to a high level, the pull-down drive transistor MN0 is turned off and then the pull-up drive transistor MP0 is turned on. Correspondingly, during the process of the output of the output drive circuit 30 flipping to a low level, the pull-up drive transistor MP0 is turned off and then the pull-down drive transistor MN0 is turned on.

[0155] The pre-drive circuit 10 only needs to ensure that the pull-up drive signal and the pull-down drive signal have non-overlapping delay during the signal switching process. Therefore, the structure is relatively simple. It can be seen that the solution of this application can effectively avoid shoot-through current. Therefore, the solution of this application can avoid shoot-through current without excessively increasing the complexity of the circuit structure, thereby effectively suppressing conduction noise.

[0156] Corresponding to the above embodiments of the output driver stage shoot-through current suppression circuit, this embodiment of the invention also provides an integrated circuit that may include the output driver stage shoot-through current suppression circuit as described in any of the above embodiments, which can be referred to in correspondence with the above description and will not be repeated here.

[0157] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0158] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0159] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A through-current suppression circuit for an output driver stage, characterized in that, It includes a pre-drive circuit, a gate drive circuit, and an output drive circuit connected in sequence: The output driving circuit includes a pull-up driving transistor connected between the power supply terminal and the output terminal for pulling up the output terminal, and a pull-down driving transistor connected between the output terminal and ground for pulling down the output terminal. The gate driving circuit is used to generate a first control signal to control the conduction state of the pull-up driving transistor and a second control signal to control the conduction state of the pull-down driving transistor, respectively, based on the received pull-up driving signal and pull-down driving signal. The pre-drive circuit is used to generate the pull-up drive signal and the pull-down drive signal according to the input data signal. The pull-up drive signal and the pull-down drive signal have a non-overlapping delay during the signal flipping process, so that during the process of the output of the output drive circuit flipping to a high level, the pull-down drive transistor is turned off and then turned on again. And during the process of the output of the output drive circuit flipping to a low level, the pull-up drive transistor is turned off and then turned on again.

2. The output driver stage shoot-through current suppression circuit according to claim 1, characterized in that, The pre-drive circuit includes at least one logic gate circuit composed of a pull-up network and a pull-down network, and the pull-up network and the pull-down network have different driving capabilities to form the non-overlapping delay.

3. The output driver stage shoot-through current suppression circuit according to claim 2, characterized in that, The pre-drive circuit includes: a first inverter, a second inverter, a third inverter, a three-input AND gate, and a three-input OR gate; The input terminal of the first inverter is connected to the second input terminal of the three-input OR gate, and the connection terminal is used to receive the output enable signal; the output terminal of the first inverter is connected to the second input terminal of the three-input AND gate. The first input terminal of the three-input AND gate is connected to the third input terminal of the three-input OR gate, and the connection terminal is used to receive the input data signal; the third input terminal of the three-input AND gate is connected to the output terminal of the three-input OR gate and the input terminal of the third inverter, and the first input terminal of the three-input OR gate is connected to the output terminal of the three-input AND gate and the input terminal of the second inverter. The output terminal of the second inverter serves as the first output terminal of the pre-drive circuit to output the pull-up drive signal, and the output terminal of the third inverter serves as the second output terminal of the pre-drive circuit to output the pull-down drive signal.

4. The output driver stage shoot-through current suppression circuit according to claim 3, characterized in that, The three-input OR gate includes: a first pull-up switch, a second pull-up switch, a third pull-up switch, a first pull-down switch, a second pull-down switch, a third pull-down switch, and a first inverting unit composed of a fourth pull-up switch and a fourth pull-down switch; The first end of the third pull-up switch is connected to the power supply end, the second end of the third pull-up switch is connected to the first end of the second pull-up switch, the second end of the second pull-up switch is connected to the first end of the first pull-up switch, and the second end of the first pull-up switch is connected to the first end of the first pull-down switch, the first end of the second pull-down switch, the first end of the third pull-down switch, the control end of the fourth pull-up switch, and the control end of the fourth pull-down switch, respectively. The second ends of the first pull-down switch, the second pull-down switch, the third pull-down switch, and the fourth pull-down switch are all grounded. The first end of the fourth pull-up switch is connected to the power supply terminal. The second end of the fourth pull-up switch is connected to the first end of the fourth pull-down switch, and the connection terminal serves as the output terminal of the three-input OR gate. The control terminals of the first pull-up switch and the first pull-down switch are both connected to the first input terminal of the three-input OR gate, the control terminals of the second pull-up switch and the second pull-down switch are both connected to the second input terminal of the three-input OR gate, and the control terminals of the third pull-up switch and the third pull-down switch are both connected to the third input terminal of the three-input OR gate.

5. The output driver stage shoot-through current suppression circuit according to claim 3, characterized in that, The three-input AND gate includes: a fifth pull-up switch, a sixth pull-up switch, a seventh pull-up switch, a fifth pull-down switch, a sixth pull-down switch, a seventh pull-down switch, and a second inverting unit composed of an eighth pull-up switch and an eighth pull-down switch; The first ends of the fifth pull-up switch, the sixth pull-up switch, and the seventh pull-up switch are all connected to the power supply terminal; the second end of the fifth pull-up switch is connected to the second end of the sixth pull-up switch, the second end of the seventh pull-up switch, the first end of the fifth pull-down switch, the control terminal of the eighth pull-up switch, and the control terminal of the eighth pull-down switch, respectively. The second end of the fifth pull-down switch is connected to the first end of the sixth pull-down switch, the second end of the sixth pull-down switch is connected to the first end of the seventh pull-down switch, and the second end of the seventh pull-down switch is grounded. The first end of the eighth pull-up switch is connected to the power supply terminal, the second end of the eighth pull-up switch is connected to the first end of the eighth pull-down switch, and the connection terminal serves as the output terminal of the three-input AND gate. The second end of the eighth pull-down switch is grounded. The control terminals of the fifth pull-up switch and the fifth pull-down switch are both connected to the first input terminal of the three-input AND gate, the control terminals of the sixth pull-up switch and the sixth pull-down switch are both connected to the second input terminal of the three-input AND gate, and the control terminals of the seventh pull-up switch and the seventh pull-down switch are both connected to the third input terminal of the three-input AND gate.

6. The output driver stage shoot-through current suppression circuit according to claim 3, characterized in that, The pre-drive circuit further includes: a first NOR gate, a first NAND gate, a fourth inverter, and a fifth inverter; The output of the second inverter is connected to the first input of the first NOR gate, the second input of the first NOR gate is connected to the output of the fifth inverter, and the output of the first NOR gate is connected to the input of the fourth inverter. The output of the third inverter is connected to the first input of the first NAND gate, the second input of the first NAND gate is connected to the output of the fourth inverter, and the output of the first NAND gate is connected to the input of the fifth inverter. Accordingly, the output terminal of the fourth inverter serves as the first output terminal of the pre-drive circuit to output the pull-up drive signal, and the output terminal of the fifth inverter serves as the second output terminal of the pre-drive circuit to output the pull-down drive signal.

7. The output drive stage shoot-through current suppression circuit according to any one of claims 1 to 6, characterized in that, The gate drive circuit includes a first control signal generation branch, a second control signal generation branch, a first enhancement branch, and a second enhancement branch; The input terminal of the first control signal generation branch is used to receive the pull-up drive signal, and the output terminal is used to output the first control signal; The input terminal of the second control signal generation branch is used to receive the pull-down drive signal, and the output terminal of the second control signal generation branch is used to output the second control signal; The first enhancement branch is connected to the output terminal of the first control signal generation branch, and is used to enhance the output slew rate of the first control signal when the first slew rate control signal is effective; The second enhancement branch is connected to the output terminal of the second control signal generation branch, and is used to enhance the output slew rate of the second control signal when the second slew rate control signal is effective.

8. The output driver stage shoot-through current suppression circuit according to claim 7, characterized in that, The second control signal generation branch includes a ninth pull-up switch, a tenth pull-up switch, a ninth pull-down switch, and a tenth pull-down switch; the first control signal generation branch includes an eleventh pull-up switch, a twelfth pull-up switch, an eleventh pull-down switch, and a twelfth pull-down switch. The first terminal of the ninth pull-up switch is connected to the power supply terminal, and the second terminal of the ninth pull-up switch is connected to the first terminal of the ninth pull-down switch, the control terminal of the tenth pull-up switch, and the control terminal of the tenth pull-down switch, respectively; the control terminals of the ninth pull-up switch and the ninth pull-down switch are both used to receive the pull-down drive signal. The first end of the tenth pull-up switch is connected to the power supply end, and the second end of the tenth pull-up switch is connected to the first end of the tenth pull-down switch, with the connection end used to output the second control signal. The first terminal of the eleventh pull-up switch is connected to the power supply terminal, and the second terminal of the eleventh pull-up switch is connected to the first terminal of the eleventh pull-down switch, the control terminal of the twelfth pull-up switch, and the control terminal of the twelfth pull-down switch, respectively; the control terminals of the eleventh pull-up switch and the eleventh pull-down switch are both used to receive the pull-up drive signal. The first end of the twelfth pull-up switch is connected to the power supply terminal, and the second end of the twelfth pull-up switch is connected to the first end of the twelfth pull-down switch, with the connection terminal used to output the first control signal. The second terminals of the ninth pull-down switch, the tenth pull-down switch, the eleventh pull-down switch, and the twelfth pull-down switch are all grounded.

9. The output driver stage shoot-through current suppression circuit according to claim 8, characterized in that, The second enhancement branch includes a thirteenth pull-up switch and a fourteenth pull-up switch, and the first enhancement branch includes a thirteenth pull-down switch and a fourteenth pull-down switch; The first terminal of the thirteenth pull-up switch is connected to the power supply terminal, and the second terminal of the thirteenth pull-up switch is connected to the first terminal of the fourteenth pull-up switch. The second terminal of the fourteenth pull-up switch is connected to the second terminal of the tenth pull-up switch and the first terminal of the tenth pull-down switch. The control terminal of the thirteenth pull-up switch is used to receive the second slew rate control signal, and the control terminal of the fourteenth pull-up switch is interconnected with the second terminal of the ninth pull-up switch, the first terminal of the ninth pull-down switch, the control terminal of the tenth pull-up switch, and the control terminal of the tenth pull-down switch. The first terminal of the thirteenth pull-down switch is connected to the second terminal of the twelfth pull-up switch and the first terminal of the twelfth pull-down switch. The second terminal of the thirteenth pull-down switch is connected to the first terminal of the fourteenth pull-down switch, and the second terminal of the fourteenth pull-down switch is grounded. The control terminal of the thirteenth pull-down switch is interconnected with the second terminal of the eleventh pull-up switch, the first terminal of the eleventh pull-down switch, the control terminal of the twelfth pull-up switch, and the control terminal of the twelfth pull-down switch. The control terminal of the fourteenth pull-down switch is used to receive the first slew rate control signal. The first slew rate control signal and the second slew rate control signal are opposite signals.

10. An integrated circuit, characterized in that, Includes the output drive stage through-current suppression circuit as described in any one of claims 1 to 9.

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