High speed zero static current high to low level shift circuit

Abstract

The present application relates to the technical field of DC-DC converter, in particular to a high-speed zero quiescent current level shift circuit. It comprises a collection module, an amplification module and an output module, the collection module is adaptively connected with the amplification module, and the amplification module is adaptively connected with the output module. The collection module shifts the level of SW signal to a differential signal in low voltage domain, the amplification module is a current mirror circuit for amplifying the input differential signal and sending it to the output module, and the output module is used for converting the amplified differential signal into a logic level to form an output signal. The characteristic is that the lower end node A of the input side of the amplification module is grounded through a first discharge circuit, the lower end node B of the output side of the amplification module is grounded through a second discharge circuit, the first discharge circuit is turned on when the IN signal changes from low level to high level, and the second discharge circuit is turned on when the IN signal changes from high level to low level. The conversion speed of the circuit is fast.

Description

Technical Field

[0001] This invention relates to the field of DC-DC converter technology, specifically a high-speed zero quiescent current level shifting circuit. Background Technology

[0002] In DC-DC converters, different switching transistors require different turn-on and turn-off voltages, resulting in different voltage domains for the gate control signals of the power transistors. To achieve signal level transfer between different voltage domains, low-to-high and high-to-low level shifters are needed. Taking a buck regulator as an example, the voltage domain of the high-side power transistor is VBST-SW, which is the floating power rail, while the voltage domain of the low-side power transistor is VCC-GND. A traditional high-to-low level shifter circuit is shown in Figure 1 for transferring signals from the high-voltage domain to the low-voltage domain.

[0003] Figure 1 The circuit shown is a high-to-low level shifter based on differential cascaded voltage switches. MP3~MP4 and MN1~MN2 are high-voltage transistors, used to protect the constant-voltage transistors MP1~MP2 and MN3~MN4, respectively. MP5 and MP6 provide auxiliary protection for MN3~MN4. Due to the complementarity of the pull-up and pull-down networks, the power consumption of this level shifter is close to zero in standby mode. However, when it is operating, there is a severe competition between the pull-up and pull-down networks, making it difficult for NMOS transistors MN3 and MN4 to switch quickly between the cutoff and linear regions. Therefore, the switching speed is slow, especially when the VBST voltage is low. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-speed zero static current level shift circuit with fast switching speed.

[0005] To solve the above problems, the following technical solutions are provided: The high-speed, zero-static-current high-to-low level shift circuit of this invention includes a data acquisition module, an amplification module, and an output module. The data acquisition module and the amplification module are adapted and connected, and the amplification module and the output module are adapted and connected. The data acquisition module is controlled by the IN signal and, driven by VBST, acquires the high-side switch node SW signal and shifts the level of the SW signal to a differential signal in the low-voltage domain. The amplification module is a current mirror circuit controlled by VCC, used to amplify the input differential signal and send it to the output module. The output module is used to convert the amplified differential signal into a logic level to form an output signal. Its key feature is that the lower node A on the input side of the amplification module is grounded through a first bleeder circuit, and the lower node B on the output side of the amplification module is grounded through a second bleeder circuit. The first bleeder circuit conducts when the IN signal changes from low to high, and the second bleeder circuit conducts when the IN signal changes from high to low.

[0006] Node A is connected to the output of inverter INV1 and the input of inverter INV2, and the input of inverter INV1 is connected to node B, which is connected to the output of inverter INV2.

[0007] The first bleeder circuit includes a current mirror. The upper input side of the current mirror is connected to the drain of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to the drain of PMOS transistor MP9. The source of PMOS transistor MP9 is connected to the drain of PMOS transistor MP7. The source of PMOS transistor MP7 is connected to VBST. The gate of PMOS transistor MP11 is connected to the SW signal. The gate of PMOS transistor MP9 is connected to the IN_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the IN signal. The gate of PMOS transistor MP7 is connected to the INB signal, the phase of which is opposite to that of the IN signal. The upper output side of the current mirror is connected to node A, and the lower input and lower output sides of the current mirror are both grounded.

[0008] The second bleeder circuit includes a second current mirror. The upper input side of the second current mirror is connected to the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP10. The source of PMOS transistor MP10 is connected to the drain of PMOS transistor MP8. The source of PMOS transistor MP8 is connected to the VBST signal. The gate of PMOS transistor MP14 is connected to the SW signal. The gate of PMOS transistor MP10 is connected to the INB_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the INB signal. The gate of PMOS transistor MP8 is connected to the IN signal. The upper output side of the second current mirror is connected to node B, and the lower input and lower output sides of the second current mirror are both grounded.

[0009] The output module includes the output side of the first current mirror and the output side of the second current mirror.

[0010] The input delay signal generation circuit includes an inverter INV3, PMOS transistors MP1, MP2, and MP4. The sources of PMOS transistors MP1, MP2, and MP4 are all connected to VBST. The drain of PMOS transistor MP1 is connected to one end of resistor R1, the other end of which is at node IN_1. Node IN_1 is connected to one end of resistor R2, the other end of which is connected to the drain of NMOS transistor MN1. The source of NMOS transistor MN1 is connected to the SW signal. VBST is connected to one end of capacitor C1, the other end of which is connected to node IN_1 and one end of capacitor C2. The other end of capacitor C2 is connected to the SW signal. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is connected to node IN_1 and the drain of NMOS transistor MN3. The source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2. The source of NMOS transistor MN2 is connected to the SW signal. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4. The source of NMOS transistor MN4 is connected to the SW signal. The IN signal is connected to the input of inverter INV3. The output of inverter INV3 forms the INB signal. The output of inverter INV3 is connected to the gates of PMOS transistors MP1, MP2, MN1, and MN2. The ground IN_1 is connected to the gates of PMOS transistor MP4 and MN4. The drain of PMOS transistor MP4 is connected to the gates of PMOS transistor MP3 and MN3. The drain of the PMOS transistor MP4 is connected to the input of the inverter INV4, and the output of the inverter INV4 forms the IN_DLY signal. The output of the inverter INV4 is connected to the input of the inverter INV5, and the output of the inverter INV5 forms the INB_DLY signal.

[0011] The output signal is connected to the input terminal of inverter INV6, the output terminal of inverter INV6 is connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 forms the OUT signal.

[0012] The acquisition module includes PMOS transistors MP5, MP6, MP12, and MP13. The sources of PMOS transistors MP5 and MP6 are connected to the VBST. The drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP12, and the drain of PMOS transistor MP12 is connected to the amplification module. The drain of PMOS transistor MP6 is connected to the source of PMOS transistor MP13, and the drain of PMOS transistor MP13 is connected to the amplification module. The gate of PMOS transistor MP5 is connected to the IN signal, and the gate of PMOS transistor MP6 is connected to the INB signal, with the INB signal having the opposite phase to the IN signal. The gates of PMOS transistors MP12 and MP13 are connected to the SW signal.

[0013] The amplification module includes NMOS transistors MN5, MN6, MP15, and MP16. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP12, the source of PMOS transistor MP15 is connected to the gate of NMOS transistor MN5, and both the drain of PMOS transistor MP15 and the source of NMOS transistor MN5 are connected to node A. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP13, the source of PMOS transistor MP16 is connected to the gate of NMOS transistor MN6, and both the drain of PMOS transistor MP16 and the source of NMOS transistor MN6 are connected to node B. The SW signal is connected to the gates of PMOS transistors MP12 and MP13, respectively. The VCC signal is connected to the gates of PMOS transistors MP15, MP16, MN5, and MN6, respectively.

[0014] The above approach has the following advantages: Because the lower node A on the input side of the high-speed zero static current level shift circuit of this invention is grounded through a first bleeder circuit, and the lower node B on the output side of the amplifier module is grounded through a second bleeder circuit, the first bleeder circuit is turned on when the IN signal changes from low to high, and the second bleeder circuit is turned on when the IN signal changes from high to low. By using the two bleeder circuits to discharge the residual charge at node A or node B when the IN signal changes from high to low or from low to high, the corresponding pull-down network can be quickly cut off when the pull-up network is working, eliminating the competition between the pull-up and pull-down networks, and causing the corresponding node voltage to rise rapidly, so as to achieve high-speed output level conversion, unaffected by VBST. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of a high-to-low level shifter in the background technology; Figure 2 This is a schematic diagram of the high-speed zero static current level shifting circuit of the present invention; Figure 3 This is a schematic diagram of the input delay signal generation circuit in the high-speed zero static current level shift circuit of the present invention; Figure 4 This is a simulation diagram of the VBST of the present invention, showing the conversion delay and static current when the IN signal changes from low to high under high voltage conditions; Figure 5 This is a simulation diagram of the VBST of the present invention, showing the conversion delay and static current when the IN signal changes from high to low under high voltage conditions; Figure 6 This is a simulation diagram of the VBST of the present invention, showing the conversion delay and quiescent current when the IN signal changes from low to high under low voltage conditions; Figure 7 This is a simulation diagram of the VBST of the present invention, showing the transition delay and quiescent current when the IN signal changes from high to low under low voltage conditions. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to the accompanying drawings.

[0017] like Figure 2 As shown, the high-speed, zero-static-current high-to-low level shift circuit of the present invention includes a data acquisition module, an amplification module, and an output module. The data acquisition module and the amplification module are adapted and connected, and the amplification module and the output module are adapted and connected. The data acquisition module is controlled by the IN signal. Under the drive of VBST, it acquires the high-side switch node SW signal and shifts the level of the SW signal to a differential signal in the low-voltage domain. The amplification module is a current mirror circuit controlled by VCC. It is used to amplify the input differential signal and send it to the output module. The output module is used to convert the amplified differential signal into a logic level to form an output signal. The lower node A on the input side of the amplification module is grounded through a first bleeder circuit, and the lower node B on the output side of the amplification module is grounded through a second bleeder circuit. The first bleeder circuit is turned on when the IN signal changes from low to high, and the second bleeder circuit is turned on when the IN signal changes from high to low. By using two bleeder circuits to discharge the residual charge at node A or node B when the IN signal changes from high to low or from low to high, the level of the output signal can be quickly changed from high to low or from low to high, achieving fast switching that is unaffected by VBST.

[0018] In some possible implementations, such as Figure 2As shown, node A is connected to the output of inverter INV1 and the input of inverter INV2, and the input of inverter INV1 is connected to node B, the output of inverter INV2. The positive feedback formed by the two inverters can speed up the conversion, thereby further improving the switching speed.

[0019] like Figure 2 As shown in this embodiment, specifically, the acquisition module includes PMOS transistors MP5, MP6, MP12, and MP13. The sources of PMOS transistors MP5 and MP6 are connected to VBST. The drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP12, and the drain of PMOS transistor MP12 is connected to the amplification module. The drain of PMOS transistor MP6 is connected to the source of PMOS transistor MP13, and the drain of PMOS transistor MP13 is connected to the amplification module. The gate of PMOS transistor MP5 is connected to the IN signal, and the gate of PMOS transistor MP6 is connected to the INB signal, with the phase of the INB signal being opposite to that of the IN signal. The gates of PMOS transistors MP12 and MP13 are connected to the SW signal. The amplification module includes NMOS transistors MN5 and MN6, PMOS transistors MP15 and MP16. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP12. The source of PMOS transistor MP15 is connected to the gate of NMOS transistor MN5. The drains of PMOS transistor MP15 and the sources of NMOS transistor MN5 are connected to node A. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP13. The source of PMOS transistor MP16 is connected to the gate of NMOS transistor MN6. The drains of PMOS transistor MP16 and the sources of NMOS transistor MN6 are both connected to node B. The SW signal is connected to the gates of PMOS transistors MP12 and MP13, respectively. VCC is connected to the gates of PMOS transistors MP15, MP16, MN5, and MN6, respectively. The output module contains NMOS transistors MN8 and MN10. The drain of NMOS transistor MN8 is connected to node A, and the source of NMOS transistor MN8 is grounded. The drain of NMOS transistor MN10 is connected to node B, and the source of NMOS transistor MN10 is grounded.

[0020] like Figure 2As shown, in this embodiment, the first discharge circuit includes a current mirror. The upper end of the input side of the current mirror is connected to the drain of PMOS transistor MP11, and the source of PMOS transistor MP11 is connected to the drain of PMOS transistor MP9. Specifically, the current mirror includes NMOS transistors MN7 and MN8. The drain of NMOS transistor MN7 is connected to the drain of PMOS transistor MP11, and the gate of NMOS transistor MN7 is connected to the drain of NMOS transistor MN7 and the gate of NMOS transistor MN8, respectively. The source of PMOS transistor MP9 is connected to the drain of PMOS transistor MP7, and the source of PMOS transistor MP7 is connected to VBST. The gate of PMOS transistor MP11 is connected to the SW signal. The gate of PMOS transistor MP9 is connected to the IN_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the IN signal. The gate of PMOS transistor MP7 is connected to the INB signal, and the phase of the INB signal is opposite to that of the IN signal. The upper output side of current mirror 1 is connected to node A. The lower input and lower output sides of current mirror 1 are both grounded. That is, the drain of NMOS transistor MN8 is connected to node A, and the source of NMOS transistor MN8 and the source of NMOS transistor MN7 are grounded.

[0021] like Figure 2 As shown, in this embodiment, the second discharge circuit includes a second current mirror. The upper end of the input side of the second current mirror is connected to the drain of PMOS transistor MP14, and the source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP10. The second current mirror includes NMOS transistors MN9 and MN10. The drain of NMOS transistor MN9 is connected to the drain of PMOS transistor MP14, and the gate of NMOS transistor MN9 is connected to both the drain of NMOS transistor MN9 and the gate of NMOS transistor MN10. The source of PMOS transistor MP10 is connected to the drain of PMOS transistor MP8, and the source of PMOS transistor MP8 is connected to VBST. The gate of PMOS transistor MP14 is connected to the SW signal. The gate of PMOS transistor MP10 is connected to the INB_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the INB signal. The gate of PMOS transistor MP8 is connected to the IN signal. The upper output side of current mirror 2 is connected to node B. The lower input and lower output sides of current mirror 2 are both grounded. That is, the drain of NMOS transistor MN10 is connected to node A, and the source of NMOS transistor MN10 and the source of NMOS transistor MN9 are grounded.

[0022] like Figure 2 As shown, in this embodiment, the output side of current mirror one is NMOS transistor MN8, and the output side of current mirror two is NMOS transistor MN10. NMOS transistors MN8 and MN10 constitute the output module.

[0023] like Figure 3As shown, in some possible embodiments, the input delay signal generation circuit includes an inverter INV3, PMOS transistors MP1, MP2, and MP4. The sources of PMOS transistors MP1, MP2, and MP4 are all connected to VBST. The drain of PMOS transistor MP1 is connected to one end of resistor R1, the other end of which is at node IN_1. Node IN_1 is connected to one end of resistor R2, the other end of which is connected to the drain of NMOS transistor MN1. The source of NMOS transistor MN1 is connected to the SW signal. VBST is connected to one end of capacitor C1, the other end of which is connected to node IN_1 and one end of capacitor C2. The other end of capacitor C2 is connected to the SW signal. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3, the drain of PMOS transistor MP3 is connected to node IN_1 and the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN2 is connected to the SW signal. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4, and the source of NMOS transistor MN4 is connected to the SW signal. The IN signal is connected to the input of inverter INV3, and the output of inverter INV3 forms the INB signal. The output of inverter INV3 is connected to the gates of PMOS transistors MP1, MP2, MN1, and MN2, respectively. Ground IN_1 is connected to the gates of PMOS transistor MP4 and MN4, respectively. The drain of PMOS transistor MP4 is connected to the gates of PMOS transistor MP3 and MN3, respectively. The drain of PMOS transistor MP4 is connected to the input of inverter INV4, and the output of inverter INV4 forms the IN_DLY signal. The output of inverter INV4 is connected to the input of inverter INV5, and the output of inverter INV5 forms the INB_DLY signal. Two resistors, R1 and R2, are connected in series between MP1 and MN1, and capacitors C1 and C2 are connected in parallel to VBST and SW at the midpoint IN_1 of the two resistors, respectively. By using the charging and discharging of RC, a delayed signal can be generated when IN undergoes a level switch.

[0024] like Figure 2 As shown, in this embodiment, the output signal is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 is connected to the input terminal of inverter INV7. The output terminal of inverter INV7 forms the OUT signal. The output is buffered using two stages of inverters to achieve a delay in the output signal.

[0025] In operation, when the IN signal level changes from high to low, INB will rise after a short delay. During this time, MP8 and MP10 are simultaneously activated, and current mirrors MN9 and MN10 begin to operate. Residual charge on node B is rapidly discharged by MN10, causing its voltage to decrease, and the pull-down network for node A stops working. Once the voltage at node A rises to a certain level, the positive feedback formed by inverters INV1 and INV2 accelerates the switching speed. When the OUT level also decreases, INB_DLY will rise, MP10 will turn off, and the branch containing MN9 will have no current. The current mirrors will stop working, and the quiescent current will be zero. When IN changes from low to high, another current mirror, MN7 and MN8, begins to operate, rapidly pulling down the voltage at node A, achieving a fast switching of the output level from low to high.

[0026] To generate a delay signal when the IN signal changes from low to high and from high to low, this solution also includes an input delay signal generation circuit. Two resistors R1 and R2 are connected in series between MP1 and MN1, and capacitors C1 and C2 are connected in parallel to VBST and SW at the midpoint IN_1 of the two resistors. By utilizing the charging and discharging of RC, a delay signal can be generated when the IN signal changes level.

[0027] Specifically, taking Dongbu's 0.18um BCD process as an example, using four high-voltage P-channel transistors and two high-voltage N-channel transistors, with VBST at 41V, SW at 36V, and VCC at 5V, the transition delay and quiescent current when the IN signal transitions from low to high are as follows: Figure 4 As shown; when the IN signal transitions from high to low, its switching delay and quiescent current are as follows: Figure 5 As shown.

[0028] When VBST is 6V, SW is 3V, and VCC is 3V, the transition delay and quiescent current when the IN signal transitions from low to high are as follows: Figure 6 As shown; when the IN signal transitions from high to low, its switching delay and quiescent current are as follows: Figure 7 As shown In DC-DC converters, a novel high-to-low level shifter is proposed to address the challenge of balancing high switching speed and zero quiescent current in traditional high-to-low level shifters. This new shifter can simultaneously meet both speed and power consumption requirements. Moreover, compared to traditional level shifters, it not only significantly improves switching speed but also maintains a relatively fast switching speed even under low voltage conditions with minimal attenuation. It can be applied to buck DC-DC converters with a wide input voltage range.

Claims

1. A high-speed, zero-static-current high-to-low level shift circuit, comprising a data acquisition module, an amplification module, and an output module, wherein the data acquisition module is adapted to and connected to the amplification module, and the amplification module is adapted to and connected to the output module; the data acquisition module is controlled by an IN signal, and under VBST drive, acquires the high-side switching node SW signal, and shifts the level of the SW signal to a differential signal in the low-voltage domain; the amplification module is a current mirror circuit, controlled by VCC, used to amplify the input differential signal and send it to the output module; the output module is used to convert the amplified differential signal into a logic level to form an output signal; characterized in that... The lower node A on the input side of the amplification module is grounded through a first bleeder circuit, and the lower node B on the output side of the amplification module is grounded through a second bleeder circuit. The first bleeder circuit is turned on when the IN signal changes from low level to high level, and the second bleeder circuit is turned on when the IN signal changes from high level to low level.

2. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 1, characterized in that, Node A is connected to the output of inverter INV1 and the input of inverter INV2, and the input of inverter INV1 is connected to the output of inverter INV2 at node B.

3. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 1, characterized in that, The first bleeder circuit includes a current mirror. The upper input side of the current mirror is connected to the drain of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to the drain of PMOS transistor MP9. The source of PMOS transistor MP9 is connected to the drain of PMOS transistor MP7. The source of PMOS transistor MP7 is connected to VBST. The gate of PMOS transistor MP11 is connected to the SW signal. The gate of PMOS transistor MP9 is connected to the IN_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the IN signal. The gate of PMOS transistor MP7 is connected to the INB signal, and the phase of the INB signal is opposite to that of the IN signal. The upper output side of the current mirror is connected to node A. The lower input and lower output sides of the current mirror are both grounded.

4. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 3, characterized in that, The second bleeder circuit includes a second current mirror. The upper input side of the second current mirror is connected to the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the drain of PMOS transistor MP10. The source of PMOS transistor MP10 is connected to the drain of PMOS transistor MP8. The source of PMOS transistor MP8 is connected to the VBST signal. The gate of PMOS transistor MP14 is connected to the SW signal. The gate of PMOS transistor MP10 is connected to the INB_DLY signal, which is a delayed signal generated by the input delay signal generation circuit of the INB signal. The gate of PMOS transistor MP8 is connected to the IN signal. The upper output side of the second current mirror is connected to node B. The lower input and lower output sides of the second current mirror are both grounded.

5. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 4, characterized in that, The output module includes the output side of the first current mirror and the output side of the second current mirror.

6. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 4, characterized in that, The input delay signal generation circuit includes an inverter INV3, PMOS transistors MP1, MP2, and MP4. The sources of PMOS transistors MP1, MP2, and MP4 are all connected to VBST. The drain of PMOS transistor MP1 is connected to one end of resistor R1, the other end of which is node IN_1. Node IN_1 is connected to one end of resistor R2, the other end of which is connected to the drain of NMOS transistor MN1. The source of NMOS transistor MN1 is connected to the SW signal. VBST is connected to one end of capacitor C1, the other end of which is connected to node IN_1 and one end of capacitor C2. The other end of capacitor C2 is connected to the SW signal. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP3, the drain of PMOS transistor MP3 is connected to node IN_1 and the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2, and so on. The source of transistor 2 is connected to the SW signal; the drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4, and the source of NMOS transistor MN4 is connected to the SW signal; the IN signal is connected to the input of inverter INV3, the output of inverter INV3 forms the INB signal, and the output of inverter INV3 is connected to the gates of PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN1, and NMOS transistor MN2 respectively; the ground IN_1 is connected to the gates of PMOS transistor MP4 and NMOS transistor MN4 respectively; the drain of PMOS transistor MP4 is connected to the gates of PMOS transistor MP3 and NMOS transistor MN3 respectively; the drain of PMOS transistor MP4 is connected to the input of inverter INV4, the output of inverter INV4 forms the IN_DLY signal, the output of inverter INV4 is connected to the input of inverter INV5, and the output of inverter INV5 forms the INB_DLY signal.

7. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 1, characterized in that, The output signal is connected to the input terminal of inverter INV6, the output terminal of inverter INV6 is connected to the input terminal of inverter INV7, and the output terminal of inverter INV7 forms the OUT signal.

8. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 1, characterized in that, The acquisition module includes PMOS transistors MP5, MP6, MP12, and MP13. The sources of PMOS transistors MP5 and MP6 are connected to the VBST, the drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP12, and the drain of PMOS transistor MP12 is connected to the amplification module. The drain of PMOS transistor MP6 is connected to the source of PMOS transistor MP13, and the drain of PMOS transistor MP13 is connected to the amplification module. The gate of PMOS transistor MP5 is connected to the IN signal, and the gate of PMOS transistor MP6 is connected to the INB signal, with the phase of the INB signal being opposite to that of the IN signal. The gates of PMOS transistors MP12 and MP13 are connected to the SW signal.

9. The high-speed, zero-static-current high-to-low level shift circuit as described in claim 8, characterized in that, The amplification module includes NMOS transistors MN5, MN6, MP15, and MP16. The drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP12, the source of PMOS transistor MP15 is connected to the gate of NMOS transistor MN5, and both the drain of PMOS transistor MP15 and the source of NMOS transistor MN5 are connected to node A. The drain of NMOS transistor MN6 is connected to the drain of PMOS transistor MP13, the source of PMOS transistor MP16 is connected to the gate of NMOS transistor MN6, and both the drain of PMOS transistor MP16 and the source of NMOS transistor MN6 are connected to node B. The SW signal is connected to the gates of PMOS transistor MP12 and PMOS transistor MP13, respectively. The VCC signal is connected to the gates of PMOS transistor MP15, PMOS transistor MP16, NMOS transistor MN5, and NMOS transistor MN6, respectively.

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