Low power level shifter with feedback chopping mechanism

Abstract

The application discloses a low-power consumption level conversion circuit with a feedback cut-off mechanism and relates to the technical field of integrated circuits.The circuit comprises a low-voltage domain input control stage, a left-side pull-down control network, a middle driving stage, a right-side pull-up control network and a high-voltage domain output buffer stage.In order to solve the problems of strong logic competition, large flip delay and high transient through current of a traditional cross-coupled level converter under a wide voltage difference, the application introduces an asymmetric feedforward acceleration mechanism to realize rapid pull-down of a core node; meanwhile, a left-side state control network is combined with an output feedback signal to accurately cut off a direct current leakage path after state flip, thereby eliminating the logic confrontation of the pull-up and pull-down networks.The application significantly improves the flip speed and working robustness under a wide voltage difference, greatly reduces dynamic power consumption and layout area, and is suitable for low-power consumption, high-speed integrated circuit systems.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power level conversion circuit with a feedback cutoff mechanism. Background Technology

[0002] Level converters are crucial high-voltage generation and signal transmission interfaces in analog or mixed-signal circuits, affecting the signal integrity and dynamic efficiency of the entire circuit system. They are one of the most fundamental and critical modules in electronic system design. The technological development of level converters mainly focuses on wide voltage drop capability, high-frequency switching speed, and low dynamic power consumption. However, in practical applications, traditional cross-coupled level converters often face situations where the input low voltage and output high voltage have a significant voltage difference.

[0003] In related technologies, level shifting circuits using traditional cross-coupling structures primarily rely on a low-voltage driven N-type pull-down transistor and a high-voltage powered P-type pull-up transistor for competitive switching. Regarding operating voltage: when the input transitions from low to high, the large system voltage difference prevents the high-voltage P-type transistor from being completely turned off, resulting in persistent leakage current. This mechanism directly hinders the level shifting process, necessitating the pull-down transistor to forcibly extract and overcome this DC leakage current. Regarding dynamic leakage and area consumption: during the transient switching of clock states, the pull-up network's turn-off and pull-down network's turn-on actions often occur simultaneously in traditional level shifters, lacking timing and logic isolation. This easily leads to high-voltage power flowing directly to ground potential through the not-yet-completely-turned-off pull-up transistor, causing a large transient shoot-through short-circuit current, resulting in severe dynamic energy loss and deteriorating overall efficiency. These two defects prevent existing level shifters from operating normally under extremely large voltage differences while maintaining sufficient area, and severely limit their high-frequency switching capability. Summary of the Invention

[0004] To address the shortcomings of the aforementioned related technologies, this invention proposes a low-power level conversion circuit and electronic device with a feedback cutoff mechanism. This addresses the problems in the related technologies, such as logic competition failure caused by the transistor's inability to be completely turned off due to limited driving capability when the voltage difference is large, and the existence of huge shoot-through leakage current during state switching transients, resulting in severe deterioration of dynamic power consumption.

[0005] To address the aforementioned technical problems, in a first aspect, the present invention provides a low-power level conversion circuit with a feedback cutoff mechanism, comprising a low-voltage domain input control stage, a left-side pull-down control network, an intermediate drive stage, a right-side pull-up control network, and an output buffer stage; the low-voltage domain input control stage receives a low-voltage domain input signal and provides it with an inverted input signal; the intermediate drive stage is controlled by an intermediate control signal from the left-side pull-down control network and is used to drive an internal core node; the output buffer stage is connected to the internal core node and is used to output a final output signal with a high voltage swing; the left-side pull-down control network... The control network receives the inverted input signal and, driven by the high-voltage level signal at the circuit output, uses the output level of the previous state to preemptively cut off the DC power supply path; the right-side pull-up control network is connected between the low-voltage domain input signal and the internal core node, and, driven by the high-voltage level signal at the circuit output, combines a real-time status feedback loop to accurately cut off the transient short-circuit path; the left-side pull-down control network and the right-side pull-up control network, through feedback control of the high-voltage output signal, preemptively turn off the corresponding P-type transistors before the circuit enters the level flipping action to completely cut off the direct leakage path.

[0006] Preferably, the left-side pull-down control network includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; the source terminals of the first P-type transistor and the second P-type transistor are sequentially connected to a high-voltage power supply, and the drain terminal of the first P-type transistor is connected to the source terminal of the second P-type transistor; the drain terminal of the second P-type transistor is connected to the left-side output node; the source terminals of the first N-type transistor and the second N-type transistor are sequentially grounded, and the drain terminal of the first N-type transistor is connected to the source terminal of the second N-type transistor; the drain terminal of the second N-type transistor is connected to the left-side output node; the gate terminals of both the first P-type transistor and the first N-type transistor receive the inverted input signal; the gate terminals of both the second P-type transistor and the second N-type transistor are controlled by an internal inverted feedback signal related to the high-voltage level signal at the circuit output terminal.

[0007] Preferably, the right-side pull-up control network includes a fourth P-type transistor, a fifth P-type transistor, and a fourth N-type transistor; the source terminal of the fourth P-type transistor is connected to a high-voltage power supply, and its drain terminal is connected to the source terminal of the fifth P-type transistor; the drain terminal of the fifth P-type transistor is connected to an internal core node; the drain terminal of the fourth N-type transistor is connected to an internal core node, and its source terminal is grounded; the gate terminals of both the fifth P-type transistor and the fourth N-type transistor receive the low-voltage domain input signal; the gate terminal of the fourth P-type transistor is connected to the high-voltage level signal to form a feedback loop.

[0008] Compared with related technologies, the low-power level conversion circuit with feedback cutoff mechanism in this invention not only limits the topology of the left pull-down control network and the right pull-up control network, but also limits the timing connection method based on the previous state cutoff and real-time state feedback coordination mechanism. This not only breaks the logic competition caused by the inability of transistors to be completely turned off under large voltage difference conditions, realizing the pure capacitor charging and discharging of internal nodes without competition, but also has lower dynamic power consumption, better high-frequency switching speed and load capacity because the direct short-circuit leakage path is completely cut off in the state switching transient. Attached Figure Description

[0009] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings.

[0010] Figure 1 A circuit diagram of a level conversion circuit with a cross-coupled structure provided for related technologies;

[0011] Figure 2 The circuit diagram of a low-power level conversion circuit with a feedback cutoff mechanism provided in Embodiment 1 of the present invention;

[0012] Figure 3 The circuit diagram shows a low-power level conversion circuit with a Schmitt trigger structure provided in Embodiment 3 of the present invention.

[0013] In the attached figures, the following labels are used:

[0014] X: Internal core node

[0015] MP1~MP7: P-type transistors

[0016] MN1~MN5: N-type transistors

[0017] inv1~inv2: Inverters

[0018] ls_in: Input signal (low-voltage domain input signal)

[0019] ls_out: Output signal (high voltage output signal)

[0020] VDDL: Low-voltage power supply

[0021] VDDH: High voltage power supply Detailed Implementation

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Example 1

[0026] This invention provides a low-power level conversion circuit with a feedback cutoff mechanism. The circuit includes a low-voltage input control stage, a left pull-down control network, an intermediate drive stage, a right pull-up control network, and an output buffer stage.

[0027] The low-voltage domain input control stage includes an inverter inv1 powered by a low-voltage power supply VDDL, whose input terminal receives the input signal ls_in and whose output terminal is connected to the left-side pull-down control network.

[0028] The left-side pull-down control network includes a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor;

[0029] The source terminal of the first P-type transistor is connected to the high-voltage power supply VDDH, the gate terminal is connected to the output terminal of the inverter inv1, and the drain terminal is connected to the source terminal of the second P-type transistor.

[0030] The gate of the second P-type transistor is connected to the inverted feedback signal related to the high-voltage output signal ls_out, and the drain is connected to the left output node; the source of the first N-type transistor is grounded, the gate is connected to the output of the inverter inv1, and the drain is connected to the source of the second N-type transistor.

[0031] The gate of the second N-type transistor is connected to the aforementioned inverting feedback signal, and the drain is connected to the left output node;

[0032] The intermediate driving stage includes a third P-type transistor and a third N-type transistor that form an inverter structure. The gate terminals of the two transistors are connected to the left output node, and their drain terminals are connected to the internal core node X.

[0033] The right-side pull-up control network includes a fourth P-type transistor, a fifth P-type transistor, and a fourth N-type transistor;

[0034] The source terminal of the fourth P-type transistor is connected to the high-voltage power supply VDDH, the gate terminal is connected to the high-voltage output signal ls_out, and the drain terminal is connected to the source terminal of the fifth P-type transistor.

[0035] The gate of the fifth P-type transistor is connected to the input signal ls_in, and the drain is connected to the internal core node X.

[0036] The source terminal of the fourth N-type transistor is grounded, the gate terminal is connected to the input signal ls_in, and the drain terminal is connected to the internal core node X.

[0037] The output buffer stage includes an inverter inv2 powered by a high-voltage power supply VDDH, whose input is connected to the internal core node X, and whose output is a high-voltage output signal ls_out.

[0038] This embodiment, through the precise connection described above, strictly implements the control strategy of "cut off first, then flip," forming a perfect isolation barrier in the physical path and completely cutting off the short-circuit path from the high-voltage power supply to ground potential, which is very likely to occur during the transient state flip.

[0039] Example 2

[0040] Based on Embodiment 1, the P-type and N-type transistors used in this embodiment are not limited to traditional bulk silicon CMOS processes. In practical high-frequency mixed-signal systems or complex cross-voltage domain designs (such as high-frequency signal interfaces in RF front-end architectures or high-voltage power transistor drive modules in DC-DC power management chips), MOSFETs in the circuit can be equivalently replaced with advanced process devices such as silicon-on-insulator (SiI) devices and fin field-effect transistors. Alternatively, multi-threshold voltage process designs can be adopted (e.g., designing cut-off transistors as high-threshold devices to reduce leakage current, and pull-down transistors as low-threshold devices to improve speed). These device-level replacements do not deviate from the core idea of ​​this invention—breaking off the DC path through physical isolation—and are all equivalent substitutions of this technical solution.

[0041] Example 3

[0042] Based on Example 1, such as Figure 3 As shown, the intermediate driver stage can be replaced with a Schmitt trigger structure. In application scenarios facing extreme process, voltage, and temperature drift, or significant noise interference in the power supply network, the unique hysteresis voltage characteristic of the Schmitt trigger can effectively prevent multiple oscillations and false flips of the internal core level near the flip threshold, thereby further improving the robustness of the circuit under high-frequency operation.

[0043] In this embodiment, the specific connection relationship of replacing the intermediate driver stage with a Schmitt trigger is as follows:

[0044] The low-voltage input control stage includes an inverter inv1; the left pull-down control network includes a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2; the right pull-up control network includes a sixth P-type transistor MP6, a seventh P-type transistor MP7, and a fifth N-type transistor MN5; the output buffer stage includes an inverter inv2; the intermediate drive stage is a Schmitt trigger structure, including a third P-type transistor MP3, a fourth P-type transistor MP4, a fifth P-type transistor MP5 (a Schmitt feedback P-type transistor), a third N-type transistor MN3, a fourth N-type transistor MN4, and a Schmitt feedback N-type transistor.

[0045] The input terminal of the inverter inv1 receives the input signal ls_in, and the output terminal is connected to the gates of MP1 and MN1.

[0046] The source terminal of MP1 is connected to the high-voltage power supply VDDH, and the drain terminal is connected to the source terminal of MP2; the drain terminal of MP2 is connected to the left output node, and the gate terminal is connected to the internal inverting feedback signal.

[0047] The source terminal of MN1 is grounded, and its drain terminal is connected to the source terminal of MN2; the drain terminal of MN2 is connected to the left output node, and its gate terminal is connected to the internal inverting feedback signal.

[0048] The source terminal of the MP3 is connected to the high-voltage power supply VDDH, the gate terminal is connected to the left output node, and the drain terminal is connected to the source terminal of the MP4.

[0049] The gate of the MP4 is connected to the left output node, and the drain is connected to the internal core node X.

[0050] The drain of MN4 is connected to the internal core node X, the gate is connected to the left output node, and the source is connected to the drain of MN3.

[0051] The gate terminal of MN3 is connected to the left output node, and the source terminal is grounded;

[0052] The source terminal of MP5 is connected to the intermediate node between the drain terminal of MP3 and the source terminal of MP4, the gate terminal is connected to the internal core node X, and the drain terminal is grounded.

[0053] The drain of the Schmitt feedback N-type transistor is connected to the high-voltage power supply VDDH, the gate is connected to the internal core node X, and the source is connected to the intermediate node between the drain of MN3 and the source of MN4.

[0054] The source terminal of MP6 is connected to the high-voltage power supply VDDH, the gate terminal is connected to the high-voltage output signal ls_out, and the drain terminal is connected to the source terminal of MP7.

[0055] The drain of MP7 is connected to the internal core node X, and the gate is connected to the input signal ls_in;

[0056] The source terminal of MN5 is grounded, the drain terminal is connected to the internal core node X, and the gate terminal is connected to the input signal ls_in;

[0057] The input of the inverter inv2 is connected to the internal core node X, and the output of the high-voltage output signal ls_out is output.

[0058] Example 4

[0059] This embodiment provides an electronic device including a low-power level shifting circuit with a feedback cutoff mechanism from any one of the embodiments 1 to 3 described above. This low-power level shifting circuit with a feedback cutoff mechanism is used to provide cross-voltage domain signal interface control for the electronic device. The electronic device is any one of an RF front-end chip, a dynamic random access memory, an IoT terminal chip, and a power management chip.

[0060] Since the high-frequency interface of the electronic device in this embodiment is provided by the low-power level conversion circuit with feedback cutoff mechanism in any one of the embodiments 1 to 3 above, it can also achieve the technical effect achieved by the low-power level conversion circuit with feedback cutoff mechanism in any one of the embodiments 1 to 3 above, and will not be described in detail here.

[0061] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A low-power level conversion circuit with a feedback cutoff mechanism, characterized in that, include: The low-voltage domain input control stage receives the low-voltage domain input signal and outputs an inverted input signal; The left-side pull-down control network receives the inverted input signal and is controlled by the high-voltage output signal of the circuit to achieve state cutoff, and is used to output intermediate control signals; The intermediate drive stage, controlled by the intermediate control signal output by the left-side pull-down control network, is used to drive the internal core nodes; The right-side pull-up control network, controlled by the low-voltage domain input signal and the high-voltage output signal, is used to perform charging and discharging operations on the internal core node. The high-voltage output buffer stage is connected to the internal core node and is used to output the high-voltage output terminal signal with a high voltage swing. During the input signal state transition, the left pull-down control network uses the high-voltage output signal of the previous state to cut off the DC power supply path in advance, and the right pull-up control network physically cuts off the transient pass-through path through the real-time feedback of the high-voltage output signal, thus jointly achieving level transition without logic competition.

2. The low-power level conversion circuit with feedback cutoff mechanism according to claim 1, characterized in that, The right-side pull-up control network includes: a first P-type transistor, a second P-type transistor, and a first N-type transistor connected in series; The source terminal of the first P-type transistor is connected to a high-voltage power supply, the gate terminal is connected to the high-voltage output signal to form a feedback loop, and the drain terminal is connected to the source terminal of the second P-type transistor. The gate of the second P-type transistor is connected to the low-voltage domain input signal, and the drain is connected to the internal core node; The drain of the first N-type transistor is connected to the internal core node, the gate is connected to the low-voltage domain input signal, and the source is grounded.

3. The low-power level conversion circuit with feedback cutoff mechanism according to claim 2, characterized in that, The left-side pull-down control network includes: a third P-type transistor, a fourth P-type transistor, and a second N-type transistor and a third N-type transistor connected in series; The source terminal of the third P-type transistor is connected to a high-voltage power supply, and the drain terminal is connected to the source terminal of the fourth P-type transistor. The drain of the fourth P-type transistor is connected to the drain of the third N-type transistor to form the output terminal of the left-side pull-down control network. The source terminal of the second N-type transistor is grounded, and its drain terminal is connected to the source terminal of the third N-type transistor; The gate terminals of the third P-type transistor and the second N-type transistor are connected together to the inverting input signal; The fourth P-type transistor is interconnected with the gate of the third N-type transistor and is jointly controlled by an internal feedback signal related to the high-voltage output signal.

4. The low-power level shifting circuit with feedback cutoff mechanism according to any one of claims 1 to 3, characterized in that, The intermediate driving stage includes an inverter structure composed of a fifth P-type transistor and a fourth N-type transistor; The gate terminals of the fifth P-type transistor and the fourth N-type transistor are connected to the output terminal of the left-side pull-down control network, and their drain terminals are connected to the internal core node. The high-voltage output buffer stage includes an inverter powered by a high-voltage power supply, whose input is connected to the internal core node and whose output output is the high-voltage output signal.

5. The low-power level shifting circuit with feedback cutoff mechanism according to any one of claims 1 to 3, characterized in that, The specific working logic of the feedback and truncation mechanism is as follows: When the low-voltage domain input signal is at a low level, the high-voltage output signal is at a high level in the previous state. This high level will cut off the P-type transistor in the left pull-down control network and physically cut off the left DC path in advance. When the low-voltage input signal flips from low to high, the left DC path remains cut off and does not generate competing current. At the same time, the first N-type transistor in the right pull-up control network is turned on and capacitively pulls the internal core node low. After the node state is buffered, the high-voltage output signal flips. Then, the first P-type transistor is turned off through the right feedback loop to cut off the right transient pass-through path.

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