Multi-stage level shift circuit, driving chip and power semiconductor device

Abstract

The application relates to the technical field of integrated circuits, and discloses a multistage level displacement circuit, a driving chip and a power semiconductor device, wherein the circuit is integrated in a three-stage series connection architecture of a primary level displacement unit, a secondary level displacement unit, a tertiary level displacement unit and an output driving unit, voltage stress is shared in stages, each stage only bears part of the voltage difference, and the voltage conversion range from a low-voltage digital domain to a high-voltage power domain is greatly expanded; the level displacement units at all stages complete preliminary level lifting, signal shaping and final level matching in turn, noise interference in the signal transmission process is effectively avoided, the circuit anti-interference performance and signal response rate are significantly optimized, and the technical short board that a traditional cross-coupled level displacement circuit adopts a single topology structure and cannot simultaneously consider high-voltage isolation, low-power operation and high driving capacity is solved, and the technical defects of the traditional circuit, such as limited voltage conversion range, high static power consumption, weak working reliability and insufficient load driving capacity, are overcome.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-level level shifting circuit, a driver chip, and a power semiconductor device. Background Technology

[0002] As a key module connecting the low-voltage digital control domain and the high-voltage power drive domain, the level shifting circuit's core function is to convert the low-voltage control signals output by the microcontroller and digital logic circuit into high-voltage signals that can drive high-voltage power devices such as power MOSFETs and IGBTs, directly determining the operating efficiency, reliability, and stability of the power system.

[0003] Traditional cross-coupled level shifting circuits have been widely used in low-to-medium voltage and low-power applications due to their simple structure and ease of integration. A typical structure is shown below. Figure 6 As shown, the circuit mainly consists of two cross-connected PMOS transistors and two NMOS transistors. Two complementary input signals, IN and INB, control the gates of the two NMOS transistors respectively. The output terminal OUT is connected to the cross-coupled node through an inverter. This circuit relies on a positive feedback mechanism to achieve state switching. When the input signal IN is low and INB is high, the NMOS transistor used to receive the IN input signal is turned off, and the NMOS transistor used to receive the INB input signal is turned on. Node B is pulled low, causing the corresponding PMOS transistor to turn on, which in turn pulls node A high, causing the corresponding PMOS transistor to turn off, and finally outputting a low level; otherwise, it outputs a high level.

[0004] However, under the modern application requirements of high voltage, high precision, and low power consumption, the inherent defects of traditional cross-coupling structures have gradually become a bottleneck restricting system performance. Traditional cross-coupling structures are single-structure level shifting circuits, which are difficult to withstand high voltage stress, have limited voltage conversion range, and insufficient output driving capability. When driving high-power capacitive loads, multiple levels of buffer circuits must be added, which increases the complexity and cost of the system.

[0005] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a multi-level level shifting circuit that solves the technical problem that traditional cross-coupled level shifting circuits, which use a single topology, cannot simultaneously achieve high-voltage isolation, low-power operation, and high driving capability.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A multi-stage level shifting circuit includes a first-stage level shifting unit, a second-stage level shifting unit, a third-stage level shifting unit, and an output driving unit. The first-stage level shifting unit initially raises the received external low-voltage differential input signal into a first-stage high-voltage differential signal, and its output terminal is connected to the input terminal of the second-stage level shifting unit. The second-stage level shifting unit performs second-stage raising and signal shaping processing on the received first-stage high-voltage differential signal, and its output terminal is connected to the input terminal of the third-stage level shifting unit. The third-stage level shifting unit performs third-stage raising and signal matching processing on the received second-stage differential output signal, and its output terminal is connected to the input terminal of the output driving unit. The output terminal of the output driving unit outputs a high-voltage driving signal, which directly controls the on / off state of an external power transistor.

[0008] In the circuit described, the first-level level shifting unit includes a first power input section, a differential conversion section, and an input bias section. The power input terminal of the first power input section is used to connect to an external high-voltage power supply. The bias input terminal of the differential conversion section is used to connect to an external first bias voltage, and the bias input terminal of the input bias section is used to connect to an external second bias voltage. The signal input terminal of the input bias section is used to receive an external low-voltage differential input signal. The input terminal of the differential conversion section is connected to the output terminal of the input bias section and the output terminal of the first power input section, respectively. The output terminal of the differential conversion section is connected to the input terminal of the second-level level shifting unit.

[0009] In the circuit described, the first power input section includes a first diode D1, a second diode D2, a first resistor R1, and a second resistor R2; the differential conversion section includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third resistor R3, a fourth resistor R4, a first NMOS transistor NM1, a second NMOS transistor NM2, a fifth resistor R5, and a sixth resistor R6; the input bias section includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5; the cathode of the first diode D1, one end of the first resistor R1, and the second diode D2 are connected to the first resistor R1. The cathode of transistor 2, one end of the second resistor R2, the source of the first PMOS transistor PM1, and the source of the second PMOS transistor PM2 are respectively used to connect to an external high-voltage power supply; the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the anode of the first diode D1, the other end of the first resistor R1, and one end of the third resistor R3 are connected together as an output terminal of the differential conversion section; the drain of the second PMOS transistor PM2, the gate of the first PMOS transistor PM1, the anode of the second diode D2, and the source of the second resistor R2 are connected together as an external high-voltage power supply. The other end, and one end of the fourth resistor R4, are connected together as another output terminal of the differential conversion section; the other end of the third resistor R3 is connected to the drain of the first NMOS transistor NM1, and the other end of the fourth resistor R4 is connected to the drain of the second NMOS transistor NM2; the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are used to connect to an external first bias voltage; the source of the first NMOS transistor NM1 is connected to one end of the fifth resistor R5, and the source of the second NMOS transistor NM2 is connected to one end of the sixth resistor R6; The other end of the fifth resistor R5 is connected to the drain of the third NMOS transistor NM3, and the other end of the sixth resistor R6 is connected to the drain of the fourth NMOS transistor NM4. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are used to receive external low-voltage differential input signals. The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is used to connect to an external second bias voltage. The source of the fifth NMOS transistor NM5 is grounded.

[0010] In the circuit described, the second-level level shifting unit includes a high-voltage bias section, a differential switch section, and a load network section. The power supply terminal of the high-voltage bias section is used to connect to an external high-voltage power supply, the bias input terminal of the high-voltage bias section is used to connect to an external third bias voltage, and the bias input terminal of the differential switch section is used to connect to an external fourth bias voltage. The control input terminal of the differential switch section is used to connect to the output terminal of the first-level level shifting unit. The output terminal of the high-voltage bias section is connected to the common power supply terminal of the differential switch section, and the output terminal of the differential switch section is connected to the input terminal of the load network section. The output terminal of the load network section is used to connect to the input terminal of the third-level level shifting unit.

[0011] In the circuit described, the high-voltage bias section includes a third PMOS transistor PM3; the differential switch section includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7; the load network section includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM7; the source of the third PMOS transistor PM3 is connected to an external high-voltage power supply; the gate of the third PMOS transistor PM3 is connected to an external third bias voltage; the drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5, respectively; the gates of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are connected to the output terminal of the first-stage level shifting unit, respectively; the drain of the fourth PMOS transistor PM4 is connected to the sixth PMOS transistor PM6. The source terminals of the fifth PMOS transistor PM5 and the seventh PMOS transistor PM7 are connected. The gate terminals of the sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 are respectively used to connect to an external fourth bias voltage. The drain terminals of the sixth PMOS transistor PM6, the sixth NMOS transistor NM6, the gate terminal of the seventh NMOS transistor NM7, and one end of the eighth resistor R8 are connected together as one output terminal of the load network section. The drain terminals of the seventh PMOS transistor PM7, the seventh NMOS transistor NM7, the gate terminal of the sixth NMOS transistor NM6, one end of the seventh resistor R7, and one end of the ninth resistor R9 are connected together as another output terminal of the load network section. The other end of the eighth resistor R8, the other end of the ninth resistor R9, the source terminal of the sixth NMOS transistor NM6, and the source terminal of the seventh NMOS transistor NM7 are respectively grounded.

[0012] In the circuit described, the three-level level shifting unit includes a second power supply input section, a differential amplifier section, and a bias control section. The power supply terminal of the second power supply input section is used to connect to an external high-voltage power supply, and the bias input terminal of the bias control section is used to connect to an external fifth bias voltage. The bias input terminal of the bias control section is used to connect to the external fifth bias voltage. The bias input terminal and control input terminal of the differential amplifier section are respectively connected to the output terminal of the bias control section and the output terminal of the second power supply input section. The output terminal of the differential amplifier section and the output terminal of the second power supply input section are respectively connected to the input terminal of the output driving unit.

[0013] In the circuit described, the second power input section includes a tenth resistor R10, an eleventh resistor R11, an eighth PMOS transistor PM8, and a ninth PMOS transistor PM9; the differential amplification section includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, an eighth NMOS transistor NM8, a tenth NMOS transistor NM10, and a thirteenth resistor R13; the bias control section includes a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, and a ninth NMOS transistor NM9; one end of the tenth resistor R10, one end of the eleventh resistor R11, and the eighth PMOS transistor PM8... The source of the tenth PMOS transistor PM10 and the source of the ninth PMOS transistor PM9 are respectively used to connect to an external high-voltage power supply; the other end of the tenth resistor R10, the drain of the eighth PMOS transistor PM8, and the gate of the ninth PMOS transistor PM9 are connected together as an internal positive feedback node of the second power supply access section; the other end of the eleventh resistor R11 and the drain of the ninth PMOS transistor PM9 are connected together as an output terminal of the three-stage level shifting unit; the source of the tenth PMOS transistor PM10 is connected to the drain of the eighth PMOS transistor PM8, and the gate of the tenth PMOS transistor PM10, the source of the ninth PMOS transistor PM9, and the drain of the ninth PMOS transistor PM8 are connected to an external high-voltage power supply; the other end of the eleventh resistor R11 and the drain of the ninth PMOS transistor PM9 are connected together as an output terminal of the three-stage level shifting unit; the source of the tenth PMOS transistor PM10 is connected to the drain of the eighth PMOS transistor PM8, and the gate of the tenth PMOS transistor PM10, the drain of the eighth PMOS transistor PM8, and the gate of the ninth PMOS transistor PM9 are connected to an external high-voltage power supply. The gate of the eleventh PMOS transistor PM11 and one end of the twelfth resistor R12 are respectively used to connect to the external fifth bias voltage; the source of the eleventh PMOS transistor PM11 is connected to the drain of the ninth PMOS transistor PM9; the drain of the tenth PMOS transistor PM10 is connected to the drain of the eighth NMOS transistor NM8, and the drain of the eleventh PMOS transistor PM11 is connected to one end of the thirteenth resistor R13; the gates of the eighth NMOS transistor NM8 and the tenth NMOS transistor NM10 are respectively connected to the output terminal of the second-level level shifting unit; the twelfth resistor R... The other end of resistor 12, one end of the fifteenth resistor R15, and the gate of the ninth NMOS transistor NM9 are connected together; the drain of the ninth NMOS transistor NM9 is connected to one end of the fourteenth resistor R14; the other end of the thirteenth resistor R13, the drain of the tenth NMOS transistor NM10, and the other end of the fourteenth resistor R14 are connected together as another output terminal of the three-stage level shifting unit; the other end of the fifteenth resistor R15, the source of the ninth NMOS transistor NM9, the source of the eighth NMOS transistor NM8, and the source of the tenth NMOS transistor NM10 are respectively grounded.

[0014] In the circuit described, the output driving unit includes a push-pull driving section; the control input terminal of the push-pull driving section is connected to the output terminal of the three-level level shifting unit, the power supply terminal of the push-pull driving section is used to connect to an external high-voltage power supply, and the output terminal of the push-pull driving section is used to output a high-voltage driving signal to control the external power transistor.

[0015] The present invention also provides a driver chip, wherein the driver chip integrates a multi-level level shifting circuit as described above.

[0016] The present invention also provides a power semiconductor device comprising a multi-level level shifting circuit as described above.

[0017] Beneficial effects: This invention provides a multi-stage level shifting circuit. Through a three-stage series integrated architecture consisting of a first-stage level shifting unit, a second-stage level shifting unit, a third-stage level shifting unit, and an output driving unit, it achieves graded distribution of voltage stress. Each stage only bears a portion of the voltage difference, significantly expanding the voltage conversion range from the low-voltage digital domain to the high-voltage power domain. Each level shifting unit sequentially completes the initial level boost, signal shaping, and final level matching, effectively avoiding noise interference during signal transmission and significantly optimizing the circuit's anti-interference performance and signal response rate. This solves the technical shortcomings of traditional cross-coupled level shifting circuits, which use a single topology and cannot simultaneously achieve high-voltage isolation, low-power operation, and high driving capability. It also overcomes the technical defects of traditional circuits, such as limited voltage conversion range, high static power consumption, weak operational reliability, and insufficient load driving capability. Attached Figure Description

[0018] Figure 1 A functional block diagram of the multi-level level shifting circuit provided by the present invention; Figure 2 The circuit schematic diagram of the first-level level shift unit provided by the present invention; Figure 3 The circuit schematic diagram of the two-level level displacement unit provided by the present invention; Figure 4 The circuit schematic of the three-level level shifting unit provided by the present invention; Figure 5 The circuit schematic of the output driving unit provided by the present invention; Figure 6 This is the circuit schematic of an existing cross-coupled level shifter circuit.

[0019] Explanation of main component symbols: 1-Level shift unit, 11-First power supply input section, 12-Differential conversion section, 13-Input bias section, 2-Level shift unit, 21-High voltage bias section, 22-Differential switch section, 23-Load network section, 3-Level shift unit, 31-Second power supply input section, 32-Differential amplification section, 33-Bias control section, 4-Output drive unit. Detailed Implementation

[0020] This invention provides a multi-level level shifting circuit, a driving chip, and a power semiconductor device. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0021] In the description of this invention, it should be understood that the terms "installation" and "connection" should be interpreted broadly, and those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] like Figures 1 to 5 As shown, this invention provides a multi-stage level shifting circuit, including a first-stage level shifting unit 1, a second-stage level shifting unit 2, a third-stage level shifting unit 3, and an output driving unit 4. The first-stage level shifting unit 1 is used to initially raise the received external low-voltage differential input signal into a first-stage high-voltage differential signal, and its output terminal is connected to the input terminal of the second-stage level shifting unit 2. The second-stage level shifting unit 2 is used to perform a second-stage raising and signal shaping processing on the received first-stage high-voltage differential signal, and its output terminal is connected to the input terminal of the third-stage level shifting unit 3. The third-stage level shifting unit 3 is used to perform a third-stage raising and signal matching processing on the received second-stage differential output signal, and its output terminal is connected to the input terminal of the output driving unit 4. The output terminal of the output driving unit 4 is used to output a high-voltage driving signal, which is used to directly control the on and off states of an external power transistor.

[0023] The multi-stage level shifting circuit disclosed in this invention achieves graded distribution of voltage stress through a three-stage series integrated architecture consisting of a first-stage level shifting unit 1, a second-stage level shifting unit 2, a third-stage level shifting unit 3, and an output driving unit 4. Each stage only bears a portion of the voltage difference, significantly expanding the voltage conversion range from the low-voltage digital domain to the high-voltage power domain. Each level shifting unit sequentially completes the initial level boost, signal shaping, and final level matching, effectively avoiding noise interference during signal transmission and significantly optimizing the circuit's anti-interference performance and signal response rate. This solves the technical shortcomings of traditional cross-coupled level shifting circuits, which use a single topology and cannot simultaneously achieve high-voltage isolation, low-power operation, and high driving capability. It also overcomes the technical defects of traditional circuits, such as limited voltage conversion range, high static power consumption, weak operational reliability, and insufficient load driving capability.

[0024] In some implementations, such as Figure 1 and Figure 2As shown, the first-level level shifting unit 1 includes a first power input section 11, a differential conversion section 12, and an input bias section 13. The power input terminal of the first power input section 11 is used to connect to an external high-voltage power supply. The bias input terminal of the differential conversion section 12 is used to connect to an external first bias voltage. The bias input terminal of the input bias section 13 is used to connect to an external second bias voltage. The signal input terminal of the input bias section 13 is used to receive an external low-voltage differential input signal. The input terminal of the differential conversion section 12 is connected to the output terminal of the input bias section 13 and the output terminal of the first power input section 11, respectively. The output terminal of the differential conversion section 12 is connected to the input terminal of the second-level level shifting unit 2.

[0025] Traditional cross-coupled level shifting circuits always have a DC path from the high-voltage power supply to ground in a stable state, generating a continuous static current and causing significant power consumption waste. Furthermore, during state switching, if there is a synchronization error between the two input signals, the upper and lower transistors will conduct simultaneously, forming a transient breakdown current with a very large amplitude, causing power network fluctuations and even device damage. The multi-stage level shifting circuit disclosed in this embodiment, by setting a first power input section 11, a differential conversion section 12, and an input bias section 13, introduces a series resistor network in the power path, combined with a constant current source bias design, cutting off the DC path from the power supply to ground and limiting the static current to the microampere or even nanoampere level, significantly reducing the circuit's static power consumption. Simultaneously, the resistor current-limiting network naturally suppresses transient breakdown current; even if there is a synchronization error in the input signal, the current is limited to a safe range, avoiding device damage and power network fluctuations, and greatly improving the circuit's reliability and fault tolerance to input signals.

[0026] In some implementations, such as Figure 2As shown, the first power input section 11 includes a first diode D1, a second diode D2, a first resistor R1, and a second resistor R2; the differential conversion section 12 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third resistor R3, a fourth resistor R4, a first NMOS transistor NM1, a second NMOS transistor NM2, a fifth resistor R5, and a sixth resistor R6; the input bias section 13 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5; the cathode of the first diode D1, one end of the first resistor R1, and the second diode D... The cathode of transistor 2, one end of the second resistor R2, the source of the first PMOS transistor PM1, and the source of the second PMOS transistor PM2 are respectively used to connect to an external high-voltage power supply; the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the anode of the first diode D1, the other end of the first resistor R1, and one end of the third resistor R3 are connected together as an output terminal of the differential conversion unit 12; the drain of the second PMOS transistor PM2, the gate of the first PMOS transistor PM1, the anode of the second diode D2, and the second resistor R2 are connected together as an output terminal of the differential conversion unit 12. The other end of the resistor and one end of the fourth resistor R4 are connected together as another output terminal of the differential conversion unit 12; the other end of the third resistor R3 is connected to the drain of the first NMOS transistor NM1, and the other end of the fourth resistor R4 is connected to the drain of the second NMOS transistor NM2; the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are used to connect to an external first bias voltage; the source of the first NMOS transistor NM1 is connected to one end of the fifth resistor R5, and the source of the second NMOS transistor NM2 is connected to one end of the sixth resistor R6; The other end of the fifth resistor R5 is connected to the drain of the third NMOS transistor NM3, and the other end of the sixth resistor R6 is connected to the drain of the fourth NMOS transistor NM4. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are used to receive external low-voltage differential input signals. The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is used to connect to an external second bias voltage. The source of the fifth NMOS transistor NM5 is grounded.

[0027] In this embodiment, the first power input section 11 includes a first diode D1, a second diode D2, a first resistor R1, and a second resistor R2. Its common power supply terminal is connected to an external high-voltage power supply, and the two outputs are respectively connected to two cross-coupled control nodes of the differential conversion section 12, providing a stable high-voltage power supply path for the circuit. At the same time, the unidirectional conductivity of the diodes is used to achieve overvoltage clamping protection to prevent voltage surges from damaging the devices. The differential conversion section 12 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third resistor R3, a fourth resistor R4, a first NMOS transistor NM1, a second NMOS transistor NM2, a fifth resistor R5, and a sixth resistor R6. NM1 and NM2 are controlled by an external first bias voltage. In the constant current region, two symmetrical constant current branches are formed; PM1 and PM2 are connected by a cross gate to form a positive feedback latch structure to realize the level conversion and state maintenance of the differential signal; the input bias section 13 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5. NM5 is controlled by an external second bias voltage as the total constant current source to provide a stable bias current for the entire input stage. Its source is grounded and its drain is connected to the source of NM3 and NM4 as a common current node; the gates of NM3 and NM4 respectively receive external low-voltage differential input signals Vin1 and Vin2, and their drains are respectively connected to the two constant current branches of the differential conversion section 12, and the on / off of the corresponding branches are controlled by the input signal.

[0028] In actual operation, when Vin1 is high and Vin2 is low, NM3 is turned on and NM4 is turned off, and no conductive path to ground is formed in the right branch. VOUT2 is pulled up to VDD, causing PM1 to turn off. The left branch forms a conductive path from VDD through the first power input section 11, the differential conversion section 12, and the input bias section 13 to ground. VOUT1 is pulled low to VDD. When Vin1 is low and Vin2 is high, PM2 is turned on; conversely, when Vin1 is low and Vin2 is high, there is no conduction path in the left branch, and VOUT1 is pulled up to VDD, turning off PM2; the right branch forms a corresponding conduction path, and VOUT2 is pulled low to VDD-. This enables PM1 to conduct, thereby achieving the initial conversion from low-voltage differential signal to high-voltage differential signal.

[0029] In some implementations, such as Figure 1 and Figure 3As shown, the secondary level shifting unit 2 includes a high-voltage bias section 21, a differential switch section 22, and a load network section 23. The power supply terminal of the high-voltage bias section 21 is used to connect to an external high-voltage power supply, and the bias input terminal of the high-voltage bias section 21 is used to connect to an external third bias voltage. The bias input terminal of the differential switch section 22 is used to connect to an external fourth bias voltage. The control input terminal of the differential switch section 22 is used to connect to the output terminal of the primary level shifting unit 1. The output terminal of the high-voltage bias section 21 is connected to the common power supply terminal of the differential switch section 22, and the output terminal of the differential switch section 22 is connected to the input terminal of the load network section 23. The output terminal of the load network section 23 is used to connect to the input terminal of the tertiary level shifting unit 3.

[0030] Traditional single-structure circuits have flat output signal edges and incomplete level swings, making them susceptible to noise interference and prone to false triggering. Furthermore, their single voltage rise is limited, making them unsuitable for high-voltage applications. The two-stage level shifting unit 2 disclosed in this embodiment, by setting up a high-voltage bias section 21, a differential switch section 22, and a load network section 23, uses a constant current source bias to provide a stable operating current, ensuring the consistency and stability of the circuit's operating state. The differential switch section 22 quickly switches the conducting branch according to the output signal from the previous stage, and in conjunction with the cross-gate connection structure of the load network section 23, achieves secondary signal shaping and level rise, resulting in steeper output signal edges and a more complete level swing, significantly improving the circuit's noise immunity. Simultaneously, the two-stage level rise further distributes voltage stress, expanding the overall circuit's voltage conversion range and providing a stable, high-quality input signal for the subsequent three-stage level conversion.

[0031] In some implementations, such as Figure 3As shown, the high-voltage bias section 21 includes a third PMOS transistor PM3; the differential switch section 22 includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7; the load network section 23 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM7; the source of the third PMOS transistor PM3 is used to connect to an external high-voltage power supply; the gate of the third PMOS transistor PM3 is used to connect to an external third bias voltage; the drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5, respectively; the gates of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are used to connect to the output terminal of the first-stage level shifting unit 1, respectively; the drain of the fourth PMOS transistor PM4 is connected to the sixth PMOS transistor PM6. The source terminals of the fifth PMOS transistor PM5 and the seventh PMOS transistor PM7 are connected. The gate terminals of the sixth PMOS transistor PM6 and the seventh PMOS transistor PM7 are respectively used to connect to an external fourth bias voltage. The drain terminals of the sixth PMOS transistor PM6, the sixth NMOS transistor NM6, the gate terminal of the seventh NMOS transistor NM7, and one end of the eighth resistor R8 are connected together as one output terminal of the load network section 23. The drain terminals of the seventh PMOS transistor PM7, the seventh NMOS transistor NM7, the gate terminal of the sixth NMOS transistor NM6, one end of the seventh resistor R7, and one end of the ninth resistor R9 are connected together as another output terminal of the load network section 23. The other end of the eighth resistor R8, the other end of the ninth resistor R9, the source terminal of the sixth NMOS transistor NM6, and the source terminal of the seventh NMOS transistor NM7 are respectively grounded.

[0032] In this embodiment, the high-voltage biasing section 21 includes a third PMOS transistor PM3. The source of the third PMOS transistor PM3 is connected to an external high-voltage power supply and is controlled by an external third bias voltage to operate in the constant current region, serving as a high-voltage constant current source to provide a stable operating current for the differential switching section 22, ensuring the consistency of the circuit's operating state. The differential switching section 22 includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7. The common source of PM4 and PM5 is connected to the output terminal of the high-voltage biasing section 21, and their gates respectively receive the two differential output signals VOUT1 and VOUT2 from the first-level level shifting unit 1. The switching transistors control the on / off state of the corresponding branches; PM6 and PM7 are controlled by an external fourth bias voltage to operate in the constant current region and are connected in series in the drain branches of PM4 and PM5 respectively to further stabilize the branch current; the load network section 23 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7. NM6 and NM7 adopt a cross-gate connection to form a cross-coupled shaping structure. The two output nodes VOUT3 and VOUT4 are respectively connected to the two output terminals of the differential switch section 22. The branch current is converted into a voltage signal through the resistive load, and the signal edge is sharpened by the cross-coupled structure.

[0033] In actual operation, the secondary level shifting unit 2 disclosed in this embodiment has the following characteristics: when VOUT1 is high and VOUT2 is low, PM4 is cut off and PM5 is turned on. The left branch does not form a conduction path to VDD, and VOUT3 is pulled down to ground, causing NM7 to be cut off. The right branch forms a conduction path from VDD through the high-voltage bias section 21, the differential switch section 22, and the load network section 23 to ground. The voltage of VOUT4 is equal to the voltage drop across R9. Conversely, when VOUT1 is low and VOUT2 is high, PM4 is turned on and PM5 is cut off. The right branch has no conduction path, and VOUT4 is pulled down to ground, causing NM6 to be cut off. The left branch forms a corresponding conduction path, and the voltage of VOUT3 is equal to the voltage drop across R8, thereby realizing the secondary level boosting and shaping of the signal.

[0034] In some implementations, such as Figure 1 and Figure 4As shown, the three-level level shifting unit 3 includes a second power input section 31, a differential amplifier section 32, and a bias control section 33. The power supply terminal of the second power input section 31 is used to connect to an external high-voltage power supply, and the bias input terminal of the bias control section 33 is used to connect to an external fifth bias voltage. The bias input terminal of the bias control section 33 is used to connect to the external fifth bias voltage. The bias input terminal and control input terminal of the differential amplifier section 32 are respectively connected to the output terminal of the bias control section 33 and the output terminal of the second power input section 31. The output terminal of the differential amplifier section 32 and the output terminal of the second power input section 31 are respectively connected to the input terminal of the output driving unit 4.

[0035] Traditional circuits often have output signal voltage amplitude and driving capability that are difficult to directly match the gate driving requirements of power transistors. Furthermore, state switching relies on a positive feedback mechanism driven by a single transistor, resulting in slow switching speeds in high-voltage differential applications and failing to meet the operating requirements of high-frequency switching power supplies. The three-stage level shifting unit 3 disclosed in this embodiment, by setting a second power input section 31, a differential amplifier section 32, and a bias control section 33, introduces an internal positive feedback node to accelerate state switching, significantly improving the circuit's switching speed and response characteristics. The bias control section 33 provides a stable bias voltage to the differential amplifier section 32, ensuring the stability of the circuit's operating point and simultaneously achieving final level matching of the output signal, enabling the output signal to directly drive the subsequent output drive unit 4. In addition, the three-stage level shifting further distributes voltage stress, allowing the circuit to withstand higher total voltage differences and meet the driving requirements of hundreds of volts high-voltage power devices.

[0036] In some implementations, such as Figure 4As shown, the second power input section 31 includes a tenth resistor R10, an eleventh resistor R11, an eighth PMOS transistor PM8, and a ninth PMOS transistor PM9; the differential amplifier section 32 includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, an eighth NMOS transistor NM8, a tenth NMOS transistor NM10, and a thirteenth resistor R13; the bias control section 33 includes a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, and a ninth NMOS transistor NM9; one end of the tenth resistor R10, one end of the eleventh resistor R11, and the eighth PMOS transistor PM8... The source of the tenth PMOS transistor PM10 and the source of the ninth PMOS transistor PM9 are respectively used to connect to an external high-voltage power supply; the other end of the tenth resistor R10, the drain of the eighth PMOS transistor PM8, and the gate of the ninth PMOS transistor PM9 are connected together as an internal positive feedback node of the second power supply access section 31; the other end of the eleventh resistor R11 and the drain of the ninth PMOS transistor PM9 are connected together as an output terminal of the three-stage level shifting unit 3; the source of the tenth PMOS transistor PM10 is connected to the drain of the eighth PMOS transistor PM8, and the gate of the tenth PMOS transistor PM10, the drain of the eighth PMOS transistor PM8, and the gate of the ninth PMOS transistor PM9 are connected to the drain of the eighth PMOS transistor PM8. The gate of the eleventh PMOS transistor PM11 and one end of the twelfth resistor R12 are respectively used to connect to the external fifth bias voltage; the source of the eleventh PMOS transistor PM11 is connected to the drain of the ninth PMOS transistor PM9; the drain of the tenth PMOS transistor PM10 is connected to the drain of the eighth NMOS transistor NM8, and the drain of the eleventh PMOS transistor PM11 is connected to one end of the thirteenth resistor R13; the gates of the eighth NMOS transistor NM8 and the tenth NMOS transistor NM10 are respectively connected to the output terminal of the second-level level shifting unit 2; the twelfth resistor R12... The other end of resistor 12, one end of the fifteenth resistor R15, and the gate of the ninth NMOS transistor NM9 are connected together; the drain of the ninth NMOS transistor NM9 is connected to one end of the fourteenth resistor R14; the other end of the thirteenth resistor R13, the drain of the tenth NMOS transistor NM10, and the other end of the fourteenth resistor R14 are connected together as another output terminal of the three-level level shifting unit 3; the other end of the fifteenth resistor R15, the source of the ninth NMOS transistor NM9, the source of the eighth NMOS transistor NM8, and the source of the tenth NMOS transistor NM10 are respectively grounded.

[0037] In this embodiment, the second power input section 31 includes a tenth resistor R10, an eleventh resistor R11, an eighth PMOS transistor PM8, and a ninth PMOS transistor PM9. Its common power supply terminal is connected to an external high-voltage power supply. PM8 and PM9 are connected in a cross-gate configuration, forming an internal positive feedback node VOUT5 and a first output node VOUT6. The internal positive feedback node VOUT5 also serves as one power supply terminal of the differential amplifier section 32, and the first output node VOUT6 serves as another power supply terminal of the differential amplifier section 32 and the first output terminal of the three-stage level shifting unit 3, accelerating circuit state switching through a positive feedback mechanism. The differential amplifier section 32 includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, an eighth NMOS transistor NM8, a tenth NMOS transistor NM10, and a thirteenth resistor R13. PM10 and PM11... The sources of NM8 and NM10 are respectively connected to the internal positive feedback node VOUT5 and the first output node VOUT6, and are controlled by the external fifth bias voltage to operate in the constant current region. The gates of NM8 and NM10 respectively receive the two differential output signals VOUT3 and VOUT4 of the second-level level shifting unit 2, which are used as switching transistors to control the on / off of the corresponding branches and realize the final level conversion of the signal. The bias control unit 33 includes the twelfth resistor R12, the fourteenth resistor R14, the fifteenth resistor R15 and the ninth NMOS transistor NM9. It provides a stable gate bias voltage for NM9 through a resistor voltage divider network, so that NM9 operates in the constant current region. The drain of NM9 is connected to the second output node VOUT7 through R14, and together with the output branch of the differential amplifier unit 32, it forms the current path of the three-level level shifting unit 3, stabilizing the voltage level of the second output node VOUT7.

[0038] In actual operation, the three-level level shifting unit 3 disclosed in this embodiment, when VOUT3 is low and VOUT4 is high, NM8 is cut off and NM10 is turned on. The left branch of the differential amplifier section 32 does not form a conductive path to ground, and the internal positive feedback node VOUT5 is pulled up to VDD, causing PM9 to be cut off. The right branch forms a conductive path from VDD through the second power input section 31 and the differential amplifier section 32 to ground. VOUT6 and VOUT7 are the voltage drops of the corresponding branches, respectively. Conversely, when VOUT3 is high and VOUT4 is high, NM8 is cut off and NM10 is turned on. When OUT4 is low, NM8 is turned on and NM10 is turned off. The left branch forms a conduction path from VDD through the second power input section 31 and the differential amplifier section 32 to ground. The right branch forms a conduction path from VDD through the second power input section 31, the differential amplifier section 32 and the bias control section 33 to ground. VOUT5, VOUT6 and VOUT7 are the voltage drops of the corresponding branches. Among them, the VOUT5 node accelerates the state switching of PM8 and PM9 through a positive feedback mechanism to ensure that the circuit responds quickly to changes in the input signal.

[0039] In some implementations, such as Figure 1 and Figure 5 As shown, the output drive unit 4 includes a push-pull drive section; the control input terminal of the push-pull drive section is connected to the output terminal of the three-level level shift unit 3, the power supply terminal of the push-pull drive section is used to connect to an external high-voltage power supply, and the output terminal of the push-pull drive section is used to output a high-voltage drive signal to control the external power transistor.

[0040] In this embodiment, the push-pull drive unit includes a twelfth PMOS transistor PM12 and an eleventh NMOS transistor NM11. The source of PM12 is connected to an external high-voltage power supply, and its gate receives the first output signal VOUT6 of the three-level level shifting unit 3. Its drain is connected to the drain of NM11 to form the final output node VOUT8. The gate of NM11 receives the second output signal VOUT7 of the three-level level shifting unit 3, and its source is grounded. When VOUT6 is low and VOUT7 is high, PM12 is turned on, NM11 is turned off, and VOUT8 outputs a high level VDD, controlling the external power transistor to turn on. When VOUT6 is high and VOUT7 is low, PM12 is turned off, NM11 is turned on, and VOUT8 outputs a low level ground, controlling the external power transistor to turn off.

[0041] To address the issues of insufficient output drive capability in traditional level-shifting circuits, requiring multiple buffer stages to drive capacitive loads such as power MOSFETs, leading to high system complexity and significant switching losses, the output drive unit 4 disclosed in this embodiment adopts an integrated push-pull output drive structure. This structure can directly drive high-power capacitive loads without the need for additional buffer stages. By providing ampere-level fast charging and discharging current, the switching time of the power transistor is significantly shortened, effectively reducing switching losses and improving the overall efficiency of the power conversion system. At the same time, the integrated design simplifies the system structure, reduces circuit cost and size, minimizes signal delay and noise interference caused by additional buffer stages, and improves system reliability and integration.

[0042] The present invention also provides a driver chip, wherein the driver chip integrates a multi-level level shifting circuit as described above.

[0043] The present invention also provides a power semiconductor device comprising a multi-level level shifting circuit as described above.

[0044] It is understood that those skilled in the art can make equivalent substitutions or changes to the technical solution and inventive concept of the present invention, and all such changes or substitutions should fall within the protection scope of the present invention.

Claims

1. A multi-level level shifting circuit, characterized in that, It includes a first-level level shift unit, a second-level level shift unit, a third-level level shift unit, and an output drive unit; The first-level level shifting unit is used to initially boost the received external low-voltage differential input signal into a first-level high-voltage differential signal, and its output terminal is connected to the input terminal of the second-level level shifting unit. The second-level level shifting unit is used to perform second-level uplift and signal shaping processing on the received first-level high-voltage differential signal, and its output terminal is connected to the input terminal of the third-level level shifting unit. The three-level level shifting unit is used to perform three-level boosting and signal matching processing on the received two-level differential output signal, and its output terminal is connected to the input terminal of the output driving unit. The output terminal of the output drive unit is used to output a high-voltage drive signal, which is used to directly control the conduction and cutoff of the external power transistor.

2. The circuit according to claim 1, characterized in that, The first-level level shifting unit includes a first power input section, a differential conversion section, and an input bias section; the power input terminal of the first power input section is used to connect to an external high-voltage power supply, the bias input terminal of the differential conversion section is used to connect to an external first bias voltage, and the bias input terminal of the input bias section is used to connect to an external second bias voltage; the signal input terminal of the input bias section is used to receive an external low-voltage differential input signal. The input terminal of the differential converter is connected to the output terminal of the input bias unit and the output terminal of the first power supply unit, respectively, and the output terminal of the differential converter is connected to the input terminal of the second-level level shifting unit.

3. The circuit according to claim 2, characterized in that, The first power input section includes a first diode D1, a second diode D2, a first resistor R1, and a second resistor R2; the differential conversion section includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third resistor R3, a fourth resistor R4, a first NMOS transistor NM1, a second NMOS transistor NM2, a fifth resistor R5, and a sixth resistor R6; the input bias section includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5; the cathode of the first diode D1, one end of the first resistor R1, the cathode of the second diode D2, ... One end of the second resistor R2, the source of the first PMOS transistor PM1, and the source of the second PMOS transistor PM2 are respectively used to connect to an external high-voltage power supply; the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the anode of the first diode D1, the other end of the first resistor R1, and one end of the third resistor R3 are connected together as an output terminal of the differential conversion section; the drain of the second PMOS transistor PM2, the gate of the first PMOS transistor PM1, the anode of the second diode D2, and the other end of the second resistor R2 are connected together as an output terminal of the differential conversion section. One end of the fourth resistor R4 is connected to serve as another output terminal of the differential converter; the other end of the third resistor R3 is connected to the drain of the first NMOS transistor NM1, and the other end of the fourth resistor R4 is connected to the drain of the second NMOS transistor NM2; the gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are used to connect to an external first bias voltage; the source of the first NMOS transistor NM1 is connected to one end of the fifth resistor R5, and the source of the second NMOS transistor NM2 is connected to one end of the sixth resistor R6; the fifth The other end of resistor R5 is connected to the drain of the third NMOS transistor NM3, and the other end of the sixth resistor R6 is connected to the drain of the fourth NMOS transistor NM4. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are used to receive external low-voltage differential input signals. The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the drain of the fifth NMOS transistor NM5. The gate of the fifth NMOS transistor NM5 is used to connect to an external second bias voltage. The source of the fifth NMOS transistor NM5 is grounded.

4. The circuit according to claim 1, characterized in that, The second-level level shifting unit includes a high-voltage bias section, a differential switch section, and a load network section. The power supply terminal of the high-voltage bias section is used to connect to an external high-voltage power supply, the bias input terminal of the high-voltage bias section is used to connect to an external third bias voltage, and the bias input terminal of the differential switch section is used to connect to an external fourth bias voltage. The control input terminal of the differential switch section is used to connect to the output terminal of the first-level level shifting unit. The output terminal of the high-voltage bias section is connected to the common power supply terminal of the differential switch section, and the output terminal of the differential switch section is connected to the input terminal of the load network section. The output terminal of the load network section is used to connect to the input terminal of the third-level level shifting unit.

5. The circuit according to claim 4, characterized in that, The high-voltage bias section includes a third PMOS transistor PM3; the differential switch section includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7; the load network section includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a sixth NMOS transistor NM6, and a seventh NMOS transistor NM7; the source of the third PMOS transistor PM3 is used to connect to an external high-voltage power supply; the gate of the third PMOS transistor PM3 is used to connect to an external third bias voltage; the drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5, respectively; the gates of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are used to connect to the output terminal of the first-level level shifting unit, respectively; the drain of the fourth PMOS transistor PM4 is connected to the source of the sixth PMOS transistor PM6. The drain of the fifth PMOS transistor PM5 is connected to the source of the seventh PMOS transistor PM7; the gate of the sixth PMOS transistor PM6 and the gate of the seventh PMOS transistor PM7 are respectively used to connect to an external fourth bias voltage; the drain of the sixth PMOS transistor PM6, the drain of the sixth NMOS transistor NM6, the gate of the seventh NMOS transistor NM7, and one end of the eighth resistor R8 are connected together as one output terminal of the load network section; the drain of the seventh PMOS transistor PM7, the drain of the seventh NMOS transistor NM7, the gate of the sixth NMOS transistor NM6, one end of the seventh resistor R7, and one end of the ninth resistor R9 are connected together as another output terminal of the load network section; the other end of the eighth resistor R8, the other end of the ninth resistor R9, the source of the sixth NMOS transistor NM6, and the source of the seventh NMOS transistor NM7 are respectively grounded.

6. The circuit according to claim 1, characterized in that, The three-level level shifting unit includes a second power input section, a differential amplifier section, and a bias control section; the power input terminal of the second power input section is used to connect to an external high-voltage power supply, and the bias input terminal of the bias control section is used to connect to an external fifth bias voltage; the bias input terminal and control input terminal of the differential amplifier section are respectively connected to the output terminal of the bias control section and the output terminal of the second power input section, and the output terminal of the differential amplifier section and the output terminal of the second power input section are respectively connected to the input terminal of the output driving unit.

7. The circuit according to claim 6, characterized in that, The second power input section includes a tenth resistor R10, an eleventh resistor R11, an eighth PMOS transistor PM8, and a ninth PMOS transistor PM9; the differential amplification section includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, an eighth NMOS transistor NM8, a tenth NMOS transistor NM10, and a thirteenth resistor R13; the bias control section includes a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, and a ninth NMOS transistor NM9; one end of the tenth resistor R10, one end of the eleventh resistor R11, the source of the eighth PMOS transistor PM8, and the... The source of the ninth PMOS transistor PM9 is connected to an external high-voltage power supply; the other end of the tenth resistor R10, the drain of the eighth PMOS transistor PM8, and the gate of the ninth PMOS transistor PM9 are connected together as an internal positive feedback node of the second power supply access section; the other end of the eleventh resistor R11 and the drain of the ninth PMOS transistor PM9 are connected together as an output terminal of the three-stage level shifting unit; the source of the tenth PMOS transistor PM10 is connected to the drain of the eighth PMOS transistor PM8, and the gate of the tenth PMOS transistor PM10 and the gate of the eleventh PMOS transistor PM9 are connected to the drain of the eighth PMOS transistor PM8. The gate of the OS transistor PM11 and one end of the twelfth resistor R12 are respectively used to connect to the external fifth bias voltage; the source of the eleventh PMOS transistor PM11 is connected to the drain of the ninth PMOS transistor PM9; the drain of the tenth PMOS transistor PM10 is connected to the drain of the eighth NMOS transistor NM8, and the drain of the eleventh PMOS transistor PM11 is connected to one end of the thirteenth resistor R13; the gates of the eighth NMOS transistor NM8 and the tenth NMOS transistor NM10 are respectively connected to the output terminal of the second-level level shifting unit; the twelfth resistor R12... The other end of the resistor, one end of the fifteenth resistor R15, and the gate of the ninth NMOS transistor NM9 are connected together; the drain of the ninth NMOS transistor NM9 is connected to one end of the fourteenth resistor R14; the other end of the thirteenth resistor R13, the drain of the tenth NMOS transistor NM10, and the other end of the fourteenth resistor R14 are connected together as another output terminal of the three-stage level shifting unit; the other end of the fifteenth resistor R15, the source of the ninth NMOS transistor NM9, the source of the eighth NMOS transistor NM8, and the source of the tenth NMOS transistor NM10 are respectively grounded.

8. The circuit according to claim 1, characterized in that, The output drive unit includes a push-pull drive section; the control input terminal of the push-pull drive section is connected to the output terminal of the three-level level shift unit, the power supply terminal of the push-pull drive section is used to connect to an external high-voltage power supply, and the output terminal of the push-pull drive section is used to output a high-voltage drive signal to control the external power transistor.

9. A driver chip, characterized in that, The driver chip integrates a multi-level level shifting circuit as described in any one of claims 1-8.

10. A power semiconductor device, characterized in that, The power semiconductor device includes a multi-level level shifting circuit as described in any one of claims 1-8.

Images