1t1m logic circuit based on threshold resistive memory

Abstract

The application discloses a 1T1M logic circuit based on a threshold resistive memory and belongs to the technical field of integrated circuit design.The logic circuit comprises a volatile resistive memory with a parasitic capacitor and a transistor connected in series with the volatile resistive memory.The gate of the transistor is coupled to an input end, and a connecting node between the two serves as an output end.Based on a level signal received by the input end, the transistor is turned on, so that the parasitic capacitor of the volatile resistive memory accumulates charges; according to the voltage accumulated by the parasitic capacitor reaching a threshold voltage, the device is switched to a low resistance state and discharged, and then falls to a holding voltage and recovers to a high resistance state. The circuit represents a logic "1" with voltage oscillation pulses generated at the output end continuously, and represents a logic "0" without oscillation. The application utilizes the intrinsic dynamic characteristics of the device, breaks through the traditional static level calculation paradigm, effectively reduces power consumption while simplifying the circuit size, and provides a new architecture for brain-like neural morphological calculation.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a 1T1M logic circuit based on a threshold memristor. Background Technology

[0002] The von Neumann architecture suffers from a data transmission rate limitation due to the separation of in-memory and computation, forming the "von Neumann bottleneck." In contrast, the human brain employs a parallel processing mechanism that integrates in-memory and computation, providing important insights for neuromorphic computing. Currently, in-memory computing architectures based on artificial neuron circuits can simulate the basic characteristics of biological neurons, becoming a highly efficient computing solution. Further research has revealed that neurons not only rely on cell bodies and synapses, but their complex dendritic structures also enable nonlinear integrated computational capabilities, which are particularly crucial in improving the information processing efficiency of neuromorphic systems.

[0003] Research has revealed that relevant computational models have confirmed that dendrites possess the ability to perform logical operations. However, most current circuits for constructing Boolean logic operations utilize non-volatile memristors. This approach not only results in large circuit sizes and high power consumption, but also because non-volatile memristors lack the intrinsic dynamic characteristics of threshold devices, such as pulse firing and negative differential resistance. This makes it difficult to simultaneously simulate the integral firing of neurons and demonstrate the computational capabilities of dendrites, limiting them to the traditional digital Boolean logic computation paradigm and hindering the development of neuromorphic computing. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a 1T1M logic circuit based on a threshold memristor, thus solving the problems in the prior art.

[0005] The objective of this invention can be achieved through the following technical solutions: A logic circuit, comprising: A volatile memristor has parasitic capacitance, threshold voltage, and holding voltage; And a transistor, connected in series with the volatile memristor; The gate of the transistor is coupled to at least one input terminal, and the connection node between the transistor and the volatile memristor serves as the output terminal. Based on the level signal received at the input terminal, the transistor is turned on, causing the parasitic capacitance to accumulate charge; when the voltage accumulated by the parasitic capacitance reaches the threshold voltage, the volatile memristor switches to a low-resistance state and discharges; when the voltage drops to the holding voltage due to discharge, the volatile memristor returns to a high-resistance state and generates a voltage pulse at the output terminal. The voltage oscillation pulse continuously generated at the output terminal represents the first logic state, and the absence of voltage oscillation pulses at the output terminal represents the second logic state.

[0006] Furthermore, the logic circuit includes multiple independent input terminals, and the transistor is an NMOS transistor; The logic circuit also includes multiple input resistors, and the multiple input terminals are connected in series with a corresponding input resistor and then connected together to the gate of the NMOS transistor. When multiple input terminals simultaneously receive high-level signals, the NMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

[0007] Furthermore, the logic circuit also includes multiple unidirectional diodes, with each diode corresponding to a specific input resistor. The anode of a corresponding diode is connected in series at the rear end of each input resistor, and the cathode of the diode is connected to the gate of the NMOS transistor; When at least one of the input terminals receives a high-level signal, the NMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

[0008] Furthermore, the transistor is a PMOS transistor; The source of the PMOS transistor is connected to the volatile memristor; The logic circuit also includes multiple input resistors, and the multiple input terminals are connected in series with a corresponding input resistor and then connected together to the gate of the PMOS transistor. When there is no input voltage or when all of the input terminals receive a low-level signal, the PMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

[0009] Furthermore, the logic circuit also includes a plurality of unidirectional diodes, each of which corresponds one-to-one with a plurality of the input resistors; The cathode of a corresponding diode is connected in series at the rear end of each input resistor, and the anodes of the diodes are all connected to the gate of the PMOS transistor. Based on the receipt of a low-level signal at at least one of the plurality of input terminals, the output terminal generates the voltage oscillation pulse to represent logic "1".

[0010] A logic circuit, comprising: A volatile memristor has parasitic capacitance, threshold voltage, and holding voltage; And, the first transistor and the second transistor; The drain of the first transistor and the drain of the second transistor are connected to one end of the volatile memristor. The common connection point between the volatile memristor and the drains of the first transistor and the second transistor serves as the output terminal. The gate of the first transistor and the source of the second transistor are shorted to each other and connected to the first input terminal. The gate of the second transistor and the source of the first transistor are shorted to each other and connected to the second input terminal. Based on the different level signals received by the first input terminal and the second input terminal, the first transistor or the second transistor is turned on, causing the parasitic capacitance to accumulate charge; when the voltage accumulated by the parasitic capacitance reaches the threshold voltage, the volatile memristor switches to a low-resistance state and discharges, and then the voltage drops to the holding voltage according to the discharge, and the volatile memristor returns to a high-resistance state; based on the repeated charging and discharging of the parasitic capacitance between the threshold voltage and the holding voltage, the output terminal generates a voltage oscillation pulse to represent the first logic state.

[0011] Furthermore, based on the absence of signal input, or the simultaneous receipt of the same level signal by the first input terminal and the second input terminal, both the first transistor and the second transistor are in the off state, and the output terminal does not generate a voltage oscillation pulse to represent the second logic state.

[0012] Furthermore, both the first transistor and the second transistor are NMOS transistors.

[0013] A half-adder circuit includes a summing module and a carry module: The summation module employs the logic circuit described above. The first and second input terminals of the summation module receive the first and second input signals, respectively. The output terminal of the summation module is used to output the summation result of the half-adder. The carry module employs the logic circuit described above. The multiple input terminals of the carry module respectively receive the first input signal and the second input signal, and the output terminal of the carry module is used to output the carry result of the half adder.

[0014] Furthermore, the volatile memristor is a niobium oxide volatile memristor; the parasitic capacitance is the intrinsic parasitic capacitance inside the niobium oxide volatile memristor.

[0015] The beneficial effects of this invention are: 1. In the basic 1T1M architecture, this invention employs a threshold voltage ( ) and holding voltage ( This invention relates to a niobium oxide volatile memristor. After the input level controls the transistor's conduction, the memristor's internal parasitic capacitance is used for charging and discharging, generating continuous voltage oscillations at the output to represent logic "1". While simulating the integral-emission characteristics of neurons, it visually represents the logical computation capability of neuronal dendrites in an oscillatory manner. This allows the circuit to break free from the traditional digital Boolean logic computation paradigm that relies solely on static high and low levels, providing a new computational approach with dynamic characteristics for brain-like neuromorphic computing.

[0016] 2. This invention constructs multi-input AND, OR, NAND, and NOR logic gates based on a single 1T1M core circuit. Specifically, it introduces passive input resistors and diodes at the front end of the transistor gate, utilizing the unidirectional conduction characteristic of the diodes to limit the input signal path. This configuration allows the circuit to achieve multi-channel signal input and logic integration without increasing the number of core memory devices (memristors and transistors). Combined with the low-power operation mechanism of the volatile threshold memristor itself, this structure effectively simplifies the physical area occupied by the circuit and reduces the overall system power consumption.

[0017] 3. This invention proposes an XOR circuit, employing a structure where two transistors share a single volatile memristor. The gate of the first transistor is cross-shorted with the source of the second transistor, and the gate of the second transistor is cross-shorted with the source of the first transistor. In traditional circuit designs, XOR logic often requires cascading multiple basic logic gates. This invention, based on the level difference of the input signal, directly controls the conduction of a single-sided transistor using the aforementioned cross-connection. It completes the originally complex logic decision with a simplified physical device arrangement, significantly improving the topology utilization efficiency of a single-transistor, single-memristor system.

[0018] 4. This invention uses the XOR circuit module as the summation unit and the AND circuit module as the carry unit, combining them in parallel to construct a half-adder circuit. This modular combination method verifies that the threshold logic unit based on oscillation characterization proposed in this invention can not only operate independently, but also serve as a standardized underlying basic unit, smoothly extending downstream and being applied to more complex logic architectures, laying a clear hardware engineering foundation for the subsequent development of large-scale in-memory computing chips. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is the 1T1M neuron circuit structure and its circuit response diagram of the present invention; Figure 2 This invention is based on the AND and OR logic circuits of 1T1M and its timing waveform diagram. Figure 3 This is a timing waveform diagram of the NOR and NAND logic circuits based on 1T1M of the present invention; Figure 4 This invention relates to the XOR logic gate circuit structure and its timing diagram. Figure 5 This is the half-adder circuit structure and its voltage timing waveform diagram of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This invention proposes a 1T1M logic circuit based on a threshold memristor. A 1T1M neuron circuit is constructed using a niobium oxide volatile memristor and a MOSFET. The circuit satisfies Boolean logic operations by controlling the input signal strength. High and low input voltage levels represent logic "1" and "0," respectively. Oscillating voltage behavior at the output node indicates logic "1," otherwise the output is "0." Furthermore, this logic circuit can achieve multiple inputs without additional components, improving efficiency and reducing power consumption.

[0023] 1T1M neuron circuit structure as follows Figure 1 As shown in 'a', it includes a volatile memristor and an NMOS transistor, where the capacitor is the internal parasitic capacitance of the niobium oxide memristor. The niobium oxide memristor is a Poole-Frenkel (PF) mechanism with a high-resistance value R. off >2.14×10 4 Ω, resistance value R in low resistance state on <900Ω, threshold voltage 0.965V, holding voltage 0.885V. Parasitic capacitance 50pF. The transistor is a Shichman-Hodges model from LTspice software, with a threshold voltage of 0V and a channel width-to-length ratio of 1. The transistor gate is used as the input terminal. V in The drain-memristor node serves as the output terminal. V out When a voltage is applied to the gate of a transistor, the transistor turns on, and the parasitic capacitance ( Cp Charge begins to accumulate. When the voltage across the memristor reaches the threshold voltage... V th When the device switches from a high-resistance state to a low-resistance state, the capacitor discharges accordingly. When the memristor voltage drops to the holding voltage... V hold When the device returns to a high-impedance state, it generates an output pulse, thus realizing the integral-emission characteristic of the neuron; for example... Figure 1 As shown in b in the diagram. (The parasitic capacitance is set to 50pF.) Figure 1 (b in the diagram illustrates the integral-fire behavior of an artificial neuron. Because the input voltage is a short-duration pulse voltage rather than a DC voltage, multiple pulse inputs are required for integration before firing occurs after reaching the threshold voltage. Therefore, the firing frequency is low.) Specifically, from Figure 1 From b in the text, we can see that: when a series of voltage pulses are input, when the input voltage ( When the memristor is in a continuously high-level (approximately 2.5V) drive state, the voltage across the memristor is ( Instead of maintaining a static voltage, the voltage gradually increases as the capacitor begins to accumulate charge. When the voltage is 0V, the voltage across the memristor decreases slightly, indicating leakage. Subsequently, after several pulse voltage inputs, the capacitor accumulates charge and raises the voltage across the memristor to the threshold voltage. V th When the memristor switches from a high-resistance state to a low-resistance state, the capacitor begins to discharge. At the same time, the voltage across the memristor ( The output current (at the moment the wave crest drops) This will be accompanied by a very narrow and high-amplitude sharp pulse. A high level turns on the transistor, and the parasitic capacitance slowly accumulates charge, directly corresponding to... During the phase of a gradual rise in waveform, when the accumulated voltage reaches the memristor's threshold voltage (approximately 0.965V peak), the device's resistance suddenly drops, and the capacitor instantaneously releases its charge, directly leading to... sudden drop and The appearance of current spikes; when the voltage drops to the holding voltage (approximately 0.885V trough), the device returns to a high-resistivity state and restarts the next charging cycle. This confirms that the 1T1M circuit effectively simulates the integral-emission characteristics of biological neurons, and that the circuit only generates current spikes at the moment of discharge, while maintaining extremely low leakage current during the longer integral charging cycle (during the high-resistivity state), demonstrating its technical advantages in terms of overall power consumption in the control system.

[0024] The circuits for related applications will be specifically described below through the following embodiments. Figures 1-5 The truth table of the simulation parameters used in the waveform diagram is shown in Table 1 below: Table 1. Truth Table of Simulation Parameters Example 1 In order to build a basic 1T1M neuron circuit ( Figure 1 In the architecture described in a), multi-input AND and OR logic operations are implemented. This embodiment, without altering the basic 1T1M neuron circuit (i.e., the core charging / discharging structure composed of a single niobium oxide volatile memristor and a single NMOS transistor connected in series), introduces a specific signal isolation and combination network on the gate input side of the NMOS transistor. Specifically, short-circuit protection input resistors with a resistance of 100Ω are configured at each input terminal, or a diode with unidirectional conduction limiting is connected in series. Here, the diode uses the common ideal diode model in LTspice software, with a forward voltage of 0V, a forward resistance of 1MΩ, and a reverse cutoff resistance of 1TΩ. To ensure continuous oscillation, the equivalent resistance of the MOSFET after the input level is turned on must match the absolute value of the negative differential resistance of the niobium oxide memristor. This causes the circuit's operating point to fall within the negative differential resistance region of the niobium oxide device, resulting in circuit instability and oscillation. According to the above settings, multiple input signals can jointly control the conduction state of the NMOS transistor in the basic 1T1M neuron circuit according to preset logic rules, thereby triggering the oscillation response of the memristor.

[0025] An AND gate logic circuit consists of a memristor, an NMOS transistor, and an input resistor. V dd The voltage is set to 3V. The input resistor is to prevent short circuits caused by multiple input voltages. The circuit structure is as follows: Figure 2 As shown in Figure a, this circuit can implement a multi-input AND gate without adding any components. The transistor only turns on when all input ports are simultaneously high-level, causing the memristor to switch its resistive state once it reaches the threshold voltage. When the voltage drops to the holding voltage, the device returns to its HRS and generates an output pulse. This process repeats continuously. V out Oscillations will only be observed at the node, i.e., when the logic "1" is output. Figure 2 b and c in the figure show the voltage timing waveforms of the two-input and three-input AND gates, respectively; Specifically, Figure 2 b in the diagram represents two input signals ( , ) and output signal ( The voltage timing of ) is shown in the waveform if and only if and When both are at a high level (i.e., both are logic "1"), the output terminal Only then will dense oscillating waveforms appear (blue blocks, representing logic "1"). This will not occur with any other combination (e.g., inputs of 00, 10, 01). All remain flat without oscillation (representing logic "0").

[0026] Figure 2 c in the diagram represents three input signals ( ) and output signal ( The voltage timing of the input is shown. The waveform clearly reflects that only during the time interval when all three inputs are simultaneously applied high (i.e., input state 111), Only then will it exhibit a continuous oscillation state (logic "1"). All other input combinations (such as 000, 100, 110, etc.) No oscillations occurred.

[0027] This demonstrates that the waveform data closely matches the truth table of a traditional AND gate, confirming that the circuit successfully implements AND logic operations based on oscillation behavior through the mechanism of "simultaneous high-level inputs to the input terminals to turn on the transistor." Furthermore, in comparison... Figure 2 As can be seen from b and c in the figure, the architecture has good horizontal scalability; it can be smoothly expanded from two-input to three-input or even multi-input AND logic operations without adding core memory devices (1T1M) by simply connecting a branch with a short-circuit protection resistor in parallel at the input.

[0028] Based on a similar design concept, and using the AND gate circuit described above, an OR logic function can be achieved by connecting a diode in series after each input resistor, such as... Figure 2 As shown in d in the diagram. The unidirectional conduction characteristic of the diode restricts the input signal path, so as long as there is an input signal, the output node will oscillate, satisfying the condition of OR logic. Figure 2 The values ​​'e' and 'f' in the diagram also illustrate the voltage timing waveforms of the two-input and three-input OR gates.

[0029] Specifically, from Figure 2 As can be seen from 'e': only when and When the input is at a low level (i.e., the input state is 00), the output terminal... Only then will no oscillation occur (logic "0"). As long as... and There is at least one high-level signal (input state is 10, 01 or 11). The node will immediately generate an oscillating waveform (representing logic "1"); from Figure 2 As can be seen from f in the figure: for the three input terminals ( The waveform tracing shows that The circuit maintains a smooth, oscillating state only when all inputs are low (000). With any input combination containing at least one "1", the circuit reliably generates a continuous oscillating output.

[0030] This confirms that the technique of connecting a diode in series after the input resistor is effective and necessary. The unidirectional conduction characteristic of the diode successfully limits the input signal path, prevents signal backflow, and ensures that any high level can independently trigger the oscillation of the core circuit. Furthermore, the data surface only requires minor adjustments to the input peripheral network (adding a diode), and the basic 1T1M circuit can smoothly switch from AND logic to OR logic, while also supporting multiple inputs (such as...). Figure 2 The three inputs of f in the model can be flexibly expanded, reflecting the unity and flexibility of the hardware architecture.

[0031] Example 2 In digital logic systems, the introduction of NOT (Not-In-Time) properties is crucial for establishing logical completeness. Based on the working principle of the basic 1T1M neuron circuit, this embodiment proposes a variant architecture. Specifically, this embodiment replaces the NMOS transistors in the basic 1T1M neuron circuit with PMOS transistors whose controlled logic is opposite, and the source of the PMOS transistor is connected to a volatile memristor. Further combined with an input resistor and unidirectional diode peripheral network similar to that described in Embodiment 1, this embodiment implements multi-input NOR and NAND logic gates, ensuring that the PMOS transistor conducts and generates a continuous oscillating output only when a specific low-level input condition is met.

[0032] Replace the NMOS transistor with a PMOS transistor to enable the circuit to implement NOR and NAND logic. Figure 3 Figure 'a' illustrates a NOR logic circuit structure, consisting of a memristor and a PMOS transistor connected in series, with the source of the PMOS transistor connected to the memristor. According to the operating principle of the PMOS transistor: when there is no input voltage in the circuit, the transistor is turned on, and the capacitor accumulates charge, causing the voltage across the memristor to reach the threshold voltage, at which point the device switches to an resistive state; when the voltage drops to the holding voltage, the device returns to its HRS state and generates an output pulse. This process repeats continuously, enabling... V out The node voltage exhibits oscillating characteristics, i.e., output logic "1". If at least one input voltage is present, the transistor will not be able to conduct, thus preventing the memristor voltage from reaching the threshold, resulting in no oscillation signal at the output node and output logic "0". Figure 3 Figures b and c show the voltage timing waveforms of the two-input and three-input NOR gates, respectively.

[0033] Specifically, Figure 3 b in the diagram represents two input signals ( ) and output signal ( The voltage timing is shown. The waveform shows that a continuous oscillating waveform (representing logic "1") will appear at the output if and only if both input terminals have no input voltage at the same time (i.e., the input state is 00). If at least one input terminal has a high level (i.e., the input state is 01, 10, or 11), the output remains flat with no oscillation signal (representing logic "0").

[0034] Figure 3 c in the three input terminals ( Waveform tracing shows that the output oscillates only during the time interval when all three inputs are low (000). Any combination of inputs containing high levels will result in no oscillation at the output.

[0035] This demonstrates that the waveform data accurately maps to the truth table of the NOR gate. This confirms that by replacing the NMOS in the core architecture with a PMOS, utilizing the PMOS's principle of conducting when there is no input voltage and cutting off when there is an input voltage, the memristor voltage is effectively prevented from reaching the threshold, successfully achieving the inversion of the basic logic. Furthermore, the data shows that this PMOS series memristor architecture also possesses lateral scalability; by simply connecting a parallel input branch with a resistor, multi-input NOR logic operations can be stably implemented without signal interference.

[0036] Based on the NOR logic circuit structure, a unidirectional diode is connected in series after the input resistor to construct a NAND logic circuit, as shown in the figure. Figure 3 As shown in d in the diagram. The diode limits the circuit current, so the output node does not oscillate only when voltage is applied to all input terminals, indicating an output logic "0"; otherwise, it exhibits oscillating behavior, indicating an output logic "1", which satisfies the NAND logic rules. Figure 3 The values ​​e and f in the diagram represent the voltage timing waveforms of the two-input and three-input NAND gates, respectively.

[0037] Specifically, Figure 3 As can be seen from 'e', ​​the output node only stops oscillating (logic "0") when both inputs are high (i.e., input state 11). In other input cases containing low levels (00, 01, 10), the output exhibits obvious continuous oscillation behavior (logic "1").

[0038] Figure 3 As can be seen from f in the figure, the output node remains in an oscillating state under most input combinations, and the oscillation behavior disappears only when all three input terminals are high at the same time (111).

[0039] This demonstrates that the waveform characteristics closely match the truth table of NAND logic. This confirms the effectiveness of connecting a unidirectional diode in series after the input resistor in the NOR logic circuit. The diode successfully limits the circuit current path, ensuring that the PMOS transistor cannot conduct only when all inputs are at high voltage, thus satisfying the triggering rules of NAND logic. Furthermore, combining the aforementioned AND / OR test results with the NOR / NAND waveform results in this set, it proves that the basic neuron circuit architecture proposed in this invention, with the addition of external resistors and diodes, or by changing the transistor polarity, can support the construction of a general and complete set of Boolean logic gates, demonstrating the system consistency of this hardware solution.

[0040] Example 3 The XOR operation, due to its non-linear separability, typically requires complex logic gate combinations in traditional designs. To simplify the circuit structure, this embodiment... Figure 1 The basic 1T1M architecture shown in Figure a has been expanded in parallel and restructured in terms of the number of devices, resulting in a novel cross-coupled architecture of a dual-transistor single memristor (2T1M). Compared to the basic 1T1M architecture, this embodiment introduces a second NMOS transistor, and connects the drains of both NMOS transistors to one end of the volatile memristor. Simultaneously, the gate of the first NMOS transistor is shorted to the source of the second NMOS transistor, and the gate of the second NMOS transistor is shorted to the source of the first NMOS transistor. This special topology, based on signal differential characteristics triggering unilateral conduction, can directly map the XOR logic truth table with a minimal structure.

[0041] In digital logic circuits, the XOR gate is also used as a basic logic circuit module. The XOR logic principle is: when the two input values ​​are different, the output is 1; when the two input values ​​are the same, the output is 0. Based on this principle, an XOR logic circuit is constructed using two NMOS transistors and a memristor. The drains of the two NMOS transistors are connected to one end of the memristor, and the sources and gates are cross-connected. The circuit structure is as follows: Figure 4 As shown in 'a', according to this circuit structure, when only one signal is input, one NMOS transistor is turned on, and the circuit output oscillates, i.e., outputs logic "1". When there is no signal input or two signals are simultaneously input at high levels, the NMOS transistor is not turned on, and the output node does not oscillate, i.e., outputs logic "0". Therefore, it conforms to the behavior of an XOR logic circuit. The voltage timing diagram of this circuit is shown in Figure 'a'. Figure 4 As shown in b in the figure.

[0042] from Figure 4 b in the diagram represents the two input signals of the XOR logic circuit. ) and output signal ( The timing waveform shows that when only one input is high (i.e., the input state is "10" or "01"), the output... This results in continuous voltage oscillation behavior (representing logic "1"). When both inputs are simultaneously without a signal (input state "00") or simultaneously high (input state "11"), the output... It remains flat, with no oscillating behavior (representing logic "0").

[0043] The timing waveform precisely conforms to the "different signals equal 1, same signals equal 0" operation rule of XOR logic. This confirms the effectiveness of the "cross-connected source and gate of two NMOS transistors" topology of this invention. It successfully achieves single-sided transistor conduction control based on signal differences, thus completing the traditionally complex XOR logic determination without adding additional logic gate stacking.

[0044] Example 4 The foregoing embodiments have demonstrated the feasibility of using single-unit logic gates based on threshold memristors in basic Boolean operations. To further verify the system-level scalability of the basic logic unit proposed in this invention and its application potential in complex computing architectures, this embodiment constructs a half-adder circuit. Specifically, this embodiment uses the dual-transistor cross-connected XOR logic gate module constructed in Embodiment 3 as the summation module of the half-adder, and the multi-input AND logic gate module constructed in Embodiment 1 as the carry module of the half-adder. The two modules receive the same input signal in parallel, thereby completing basic arithmetic operations in a memory-based computing architecture. The summation and carry functions of a half-adder essentially correspond to XOR and AND operations. Therefore, combining AND gates and XOR gates to form a half-adder circuit demonstrates the scalability of these basic Boolean logic units. The circuit structure is as follows: Figure 5 As shown in 'a'. Figure 5 The voltage timing waveform is shown in b in the figure. The truth table of the half-adder is shown in Table 2 below, which facilitates direct observation of the circuit output to determine the circuit's accuracy. The results show that the logic circuit proposed in this invention can be used as a basic unit in more complex logic architectures.

[0045] Table 2 Truth Table for Half Adder from Figure 5 Figure b shows four waveforms of a half-adder circuit composed of AND and XOR gates, including two input signals ( ), summation output signal ( S ) and carry output signal ( C When the input combination is "10" or "01", only the summation node is used.S Exhibiting oscillating behavior (logic "1"), carry node C No oscillation (logic "0"). The summation node is active when the input combination is "11". S The oscillation disappears (logic "0"), while the carry node... C It begins to exhibit oscillating behavior (logic "1"). When the input combination is "00", S Nodes and C None of the nodes have an oscillation signal (logic "0").

[0046] Waveform data demonstrates that by combining the basic XOR gate (for summation) and AND gate (for carry) in parallel, the two modules can work collaboratively based on the same set of input signals, and no unexpected crosstalk occurs in their voltage oscillation behavior. This dynamic response result confirms that the 1T1M basic unit based on oscillation behavior proposed in this invention has good system-level scalability and can be used as a low-level standardized module for further application in arithmetic operations and more complex neuromorphic logic architectures.

[0047] Table 2 clearly lists the steady-state results for the four variables: when input When it is (0,0), S =0 and C =0; when the input is (1,0) or (0,1), S =1 and C =0; when the input is (1,1), S =0 and C =1. This truth table will... Figure 5 The complex high and low levels and the simulation time dynamics of whether continuous oscillation occurs in the b-th stage of the circuit are successfully abstracted and mapped to the easily observable and judgeable Boolean algebraic expressions of "0" and "1" in standard digital circuits. The data in the truth table matches the theoretical operation results of the standard half-adder. This ultimately confirms that the technical route proposed in this invention, based on the oscillation characteristics of volatile threshold memristors, is not only physically feasible but also possesses rigorous accuracy in logical operation results, achieving the expected goal of replacing traditional static logic circuits to perform arithmetic operations.

[0048] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0049] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A logic circuit, characterized in that, include: A volatile memristor has parasitic capacitance, threshold voltage, and holding voltage; And a transistor, connected in series with the volatile memristor; The gate of the transistor is coupled to at least one input terminal, and the connection node between the transistor and the volatile memristor serves as the output terminal. Based on the level signal received at the input terminal, the transistor is turned on, causing the parasitic capacitance to accumulate charge; When the voltage accumulated by the parasitic capacitance reaches the threshold voltage, the volatile memristor switches to a low-resistance state and discharges. As the voltage drops to the holding voltage due to discharge, the volatile memristor returns to a high-resistance state and generates a voltage pulse at the output terminal. The voltage oscillation pulse continuously generated at the output terminal represents the first logic state, and the absence of voltage oscillation pulses at the output terminal represents the second logic state.

2. The 1T1M logic circuit based on a threshold memristor according to claim 1, characterized in that, The logic circuit includes multiple independent input terminals, and the transistor is an NMOS transistor; The logic circuit also includes multiple input resistors, and the multiple input terminals are connected in series with a corresponding input resistor and then connected together to the gate of the NMOS transistor. When multiple input terminals simultaneously receive high-level signals, the NMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

3. The 1T1M logic circuit based on a threshold memristor according to claim 2, characterized in that, The logic circuit also includes multiple unidirectional diodes, with each diode corresponding to a specific input resistor. The anode of a corresponding diode is connected in series at the rear end of each input resistor, and the cathode of the diode is connected to the gate of the NMOS transistor; When at least one of the input terminals receives a high-level signal, the NMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

4. The 1T1M logic circuit based on a threshold memristor according to claim 1, characterized in that, The transistor is a PMOS transistor; The source of the PMOS transistor is connected to the volatile memristor; The logic circuit also includes multiple input resistors, and the multiple input terminals are connected in series with a corresponding input resistor and then connected together to the gate of the PMOS transistor. When there is no input voltage or when all of the input terminals receive a low-level signal, the PMOS transistor is turned on, and the output terminal generates the voltage oscillation pulse to represent logic "1".

5. The 1T1M logic circuit based on a threshold memristor according to claim 4, characterized in that, The logic circuit also includes a plurality of unidirectional diodes, each of which corresponds to one of the plurality of input resistors; The cathode of a corresponding diode is connected in series at the rear end of each input resistor, and the anodes of the diodes are all connected to the gate of the PMOS transistor. Based on the receipt of a low-level signal at at least one of the plurality of input terminals, the output terminal generates the voltage oscillation pulse characterizing logic "1".

6. A logic circuit, characterized in that, include: A volatile memristor has parasitic capacitance, threshold voltage, and holding voltage; And, the first transistor and the second transistor; The drain of the first transistor and the drain of the second transistor are connected to one end of the volatile memristor. The common connection point between the volatile memristor and the drains of the first transistor and the second transistor serves as the output terminal. The gate of the first transistor and the source of the second transistor are shorted to each other and connected to the first input terminal. The gate of the second transistor and the source of the first transistor are shorted to each other and connected to the second input terminal. Based on the different level signals received by the first input terminal and the second input terminal, the first transistor or the second transistor is turned on, causing the parasitic capacitance to accumulate charge; When the voltage accumulated by the parasitic capacitance reaches the threshold voltage, the volatile memristor switches to a low-resistance state and discharges, and then the voltage drops to the holding voltage due to the discharge, and the volatile memristor returns to a high-resistance state; based on the repeated charging and discharging of the parasitic capacitance between the threshold voltage and the holding voltage, the output terminal generates a voltage oscillation pulse to represent the first logic state.

7. The logic circuit according to claim 6, characterized in that, When there is no signal input, or when the first input terminal and the second input terminal simultaneously receive the same level signal, both the first transistor and the second transistor are in the off state, and the output terminal does not generate a voltage oscillation pulse to represent the second logic state.

8. The logic circuit according to claim 6, characterized in that, Both the first transistor and the second transistor are NMOS transistors.

9. A half-adder circuit, characterized in that, Includes a summation module and a carry module: The summing module employs the logic circuit described in any one of claims 6-8. The first input terminal and the second input terminal of the summing module respectively receive the first input signal and the second input signal. The output terminal of the summing module is used to output the summation result of the half-adder. The carry module employs the logic circuit described in claim 2. The multiple input terminals of the carry module respectively receive the first input signal and the second input signal, and the output terminal of the carry module is used to output the carry result of the half adder.

10. The half-adder circuit according to claim 9, characterized in that, The volatile memristor is a niobium oxide volatile memristor; the parasitic capacitance is the intrinsic parasitic capacitance inside the niobium oxide volatile memristor.

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