Method for fast establishment of lock-in time of a phase-locked loop and phase-locked loop circuit

Abstract

The application provides a method for quickly establishing a lock-in time of a phase-locked loop and a phase-locked loop circuit. The method comprises the following steps: obtaining a target phase-locked frequency; in response to the target phase-locked frequency deviating from a preset phase-locked adjustment frequency, setting a tuning voltage of an input voltage-controlled oscillator as a boundary value of an output voltage of a charge pump; and when the tuning voltage is the boundary value of the output voltage, increasing a working current of the charge pump. The application provides a method for quickly establishing a lock-in time. In the case that the target phase-locked frequency deviates from the preset phase-locked adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is quickly pulled to a voltage value close to the target phase-locked frequency, a preset voltage function is realized, the voltage tuning span in the phase-locked process is reduced, and the lock-in time is shortened. In the phase-locked process, the working current of the charge pump is increased to widen the loop bandwidth, accelerate the charging and discharging speed of the loop capacitance, and further shorten the lock-in time.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop (PLL) control technology, and in particular to a method for rapidly establishing the PLL locking time and a PLL circuit. Background Technology

[0002] Lock time is one of the most important metrics for frequency sources, directly impacting system performance, efficiency, reliability, and communication quality. Almost all frequency hopping sources have specific requirements for lock time. A shorter lock time is always better; however, in practical engineering, optimizing lock time often requires balancing numerous factors such as phase noise, spurious emission suppression, power consumption, size, and cost. While single-phase-locked loop (PLL) frequency sources cannot match the lock time of ping-pong or direct-synthesized frequency sources, they offer significant advantages in terms of low cost, low power consumption, and small size.

[0003] To shorten lock-in time, existing solutions mainly fall into two categories: one is to add auxiliary hardware such as pre-set voltage to accelerate frequency traction; the other is to optimize loop parameters, such as increasing loop bandwidth or increasing phase detection frequency. However, the former will additionally increase chip area, power consumption, and system debugging complexity, and is prone to introducing spurious interference; the latter is limited by the rigid trade-off between speed and performance, that is, increasing bandwidth will weaken the ability to suppress near-end spurious interference, and increasing phase detection frequency will solidify the frequency step and sacrifice frequency hopping resolution. It can be seen that existing technologies cannot avoid hardware overhead or performance degradation, and there is an urgent need for a new solution to further shorten the lock-in time of the phase-locked loop without deteriorating spectral purity or increasing hardware costs. Summary of the Invention

[0004] This invention provides a method for rapidly establishing the lock time of a phase-locked loop (PLL) and a PLL circuit, to solve the technical problem in the prior art that it is difficult to balance hardware cost, spectral purity and frequency hopping flexibility when shortening the lock time.

[0005] In a first aspect, the present invention provides a method for rapidly establishing the lock time of a phase-locked loop, comprising: Obtain the target phase-locked frequency; In response to the target phase-locked frequency deviating from the preset phase-locked adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is set to the output voltage boundary value of the charge pump; When the tuning voltage is the output voltage boundary value, the operating current of the charge pump is increased to shorten the lock-in time.

[0006] In one embodiment of the present invention, the output voltage boundary value includes zero and the power supply voltage. In response to the target phase-locked frequency deviating from a preset phase-locked frequency adjustment, setting the tuning voltage of the input voltage-controlled oscillator to the output voltage boundary value of the charge pump includes: when the target phase-locked frequency is less than the preset phase-locked frequency adjustment, controlling the charge pump to enter a discharge mode to adjust the tuning voltage to zero; when the target phase-locked frequency is greater than the preset phase-locked frequency adjustment, controlling the charge pump to enter a charging mode to adjust the tuning voltage to the power supply voltage of the charge pump.

[0007] In one embodiment of the present invention, when the tuning voltage is the boundary value of the output voltage, increasing the operating current of the charge pump includes: if the tuning voltage is zero or the power supply voltage, turning off the charging mode or discharging mode of the charge pump, and setting the operating current to the upper limit of the configurable current range.

[0008] In one embodiment of the present invention, the establishment method further includes: after the phase-locked loop is locked, restoring the operating current to the initial set value.

[0009] Secondly, the present invention also provides a phase-locked loop circuit, comprising: A phase detector is used to compare the phase of an input signal, including the target phase-locked frequency, with a feedback signal and generate a pulse control signal based on the phase difference. A charge pump is used to output a charging current or a discharging current according to the pulse control signal, and the operating current includes the charging current and the discharging current. A loop filter is used to filter, smooth, and integrally convert the operating current to obtain the tuning voltage; A voltage-controlled oscillator for generating an oscillation signal based on the amplitude of the tuning voltage; The power divider is used to distribute the oscillation signal into at least two signal outputs, one of which is the output signal of the phase-locked loop and the other is the feedback signal, which is fed back to the feedback input terminal of the phase detector to form a closed-loop phase-locked loop. The control module is configured to, in response to the target phase-locked frequency deviating from the preset phase-locked adjustment frequency, set the tuning voltage to the output voltage boundary value of the charge pump, and increase the operating current when the tuning voltage is the output voltage boundary value.

[0010] In one embodiment of the present invention, the charge pump includes a first PMOS transistor, a first NMOS transistor, and a current adjustment unit. The current adjustment unit increases the operating current when the tuning voltage is the output voltage boundary value. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the gates of the first PMOS transistor and the first NMOS transistor are connected to the pulse control signal, and the drain of the first PMOS transistor is the output terminal of the charge pump.

[0011] In one embodiment of the present invention, the current regulation unit includes N second PMOS transistors, N third PMOS transistors, a fourth PMOS transistor, a fifth PMOS transistor, N second NMOS transistors, N third NMOS transistors, a fourth NMOS transistor, a fifth NMOS transistor, and an operational amplifier. The sources of the N second PMOS transistors are connected to the power supply voltage. The drain of the i-th second PMOS transistor is connected to the source of the i-th third PMOS transistor. The drains of the N third PMOS transistors are all connected to the sources of the fifth PMOS transistors. The source of the fifth PMOS transistor is also connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the fourth PMOS transistor is also connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to the output of the operational amplifier. The output of the operational amplifier is connected to the drain of the fifth NMOS transistor. The drain of the first NMOS transistor is connected to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor, the drains of the N second NMOS transistors are all connected to the source of the fifth NMOS transistor, the source of the i-th second NMOS transistor is connected to the drain of the i-th third PMOS transistor, the sources of the N third NMOS transistors are grounded, the non-inverting input of the operational amplifier is also connected to the output of the charge pump, wherein the gates of the N second PMOS transistors are all connected to a first reference current, the gates of the N third NMOS transistors are all connected to a second reference current, the gates of the N third PMOS transistors are connected to a first control signal, the gates of the N second NMOS transistors are connected to a second control signal, the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected to a third control signal, and the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to a fourth control signal, where i and N are both positive integers, and 1 ≤ i < N.

[0012] In one embodiment of the present invention, the width-to-length ratio of the (i+1)th second PMOS transistor is twice the width-to-length ratio of the ith second PMOS transistor, and the width-to-length ratio of the (i+1)th third PMOS transistor is twice the width-to-length ratio of the ith third PMOS transistor; the width-to-length ratio of the (i+1)th second NMOS transistor is twice the width-to-length ratio of the ith second NMOS transistor, and the width-to-length ratio of the (i+1)th third NMOS transistor is twice the width-to-length ratio of the ith third NMOS transistor.

[0013] The beneficial effects of this invention are as follows: This invention proposes a method for rapidly establishing the lock-up time of a phase-locked loop (PLL) and a PLL circuit. The method includes: acquiring a target PLL frequency; in response to a deviation of the target PLL frequency from a preset PLL adjustment frequency, setting the tuning voltage of the input voltage-controlled oscillator (VCO) to the output voltage boundary value of the charge pump; when the tuning voltage is at the output voltage boundary value, increasing the operating current of the charge pump to shorten the lock-up time. This application provides a rapid lock-up time establishment scheme. Based on the situation where the target PLL frequency deviates from the preset PLL adjustment frequency, the tuning voltage of the input VCO is rapidly pulled to a voltage value close to the target PLL frequency to realize the preset voltage function, thereby reducing the voltage tuning span during the phase-locking process and shortening the lock-up time; during the phase-locking process, by increasing the operating current of the charge pump to widen the loop bandwidth and accelerate the charging and discharging speed of the loop capacitor, the lock-up time is further shortened. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] In the attached diagram: Figure 1 This is a flowchart illustrating the method for rapidly establishing the phase-locked loop locking time provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the phase-locked loop circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the charge pump provided in an embodiment of the present invention.

[0016] Figure reference numerals: 210 – Phase detector; 220 – Charge pump; 221 – Current regulating unit; 230 – Loop filter; 240 – Voltage-controlled oscillator; 250 – Power divider; 260 – Control module; Uin – Input signal; U FB - Feedback signal; Icp - Operating current; V T - Tuning voltage; V VCO- Oscillation signal; U OUT - Output signal. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0018] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0019] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0020] Lock-in time is a core metric for frequency sources, directly impacting system performance, efficiency, and communication quality. Almost all frequency hopping sources have stringent requirements for it. While shortening lock-in time in engineering often involves a trade-off with phase noise, spurious emission suppression, power consumption, and size, for single-phase-locked loop (SLL) architectures, efforts are focused on overcoming the inherent bottleneck of lock-in speed while maintaining advantages in low cost, low power consumption, and small size. To accelerate lock-in, existing technologies mainly follow two paths: one is to add auxiliary hardware such as pre-set voltages to achieve rapid frequency pulling, but this increases chip area, power consumption, and debugging complexity, and can easily worsen spurious emissions; the other is to optimize loop parameters, such as widening the bandwidth or increasing the phase detection frequency. However, increased bandwidth weakens near-end spurious emission suppression, and increasing the phase detection frequency fixes the frequency step, sacrificing frequency hopping flexibility.

[0021] To solve the above problems, such as Figure 1 As shown, the present invention provides a method for rapidly establishing the phase-locked loop (PLL) locking time, the method comprising at least steps S110 to S130: S110, Obtain the target phase-locked frequency.

[0022] Specifically, the input signal is obtained from the input terminal of the phase detector, and the input signal includes the target phase-locked frequency fd.

[0023] S120. In response to the target phase-locked frequency deviating from the preset phase-locked adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is set to the output voltage boundary value of the charge pump.

[0024] Before the phase-locked loop (PLL) begins normal locking, a pre-locking operation is performed to determine the voltage-controlled oscillator (VCO) at the tuning voltage V. T The frequency output when it is equal to half of the charge pump power supply voltage Vcp is used as the preset phase-locked loop adjustment frequency fmid.

[0025] Specifically, the output voltage boundary value includes zero and the power supply voltage. In response to a deviation of the target phase-locked frequency from the preset phase-locked frequency, the tuning voltage of the input voltage-controlled oscillator is set to the output voltage boundary value of the charge pump. This includes: when the target phase-locked frequency is less than the preset phase-locked frequency, controlling the charge pump to enter discharge mode so that the tuning voltage is adjusted to zero; and when the target phase-locked frequency is greater than the preset phase-locked frequency, controlling the charge pump to enter charging mode so that the tuning voltage is adjusted to the power supply voltage of the charge pump.

[0026] Specifically, in practical applications, the output voltage boundary values ​​of the charge pump include zero and the power supply voltage Vcp. The target phase-locked frequency fd is compared with the preset phase-locked adjustment frequency fmid. When the target phase-locked frequency is not equal to the preset phase-locked adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is set as the output voltage boundary value of the charge pump. This includes: when the target phase-locked frequency fd is less than the preset phase-locked adjustment frequency fmid, controlling the charge pump to enter discharge mode, and after a fixed delay (e.g., 1 second), pulling the tuning voltage of the input voltage-controlled oscillator down to zero; when the target phase-locked frequency fd is greater than the preset phase-locked adjustment frequency fmid, controlling the charge pump to enter charging mode, and after a fixed delay, pulling the tuning voltage of the input voltage-controlled oscillator up to the charge pump's power supply voltage Vcp, making the charge pump's output closer to the tuning voltage corresponding to the target phase-locked frequency fd. The fixed delay time can be adjusted according to the actual situation.

[0027] S130. When the tuning voltage is the output voltage boundary value, increase the operating current of the charge pump to shorten the lock-in time.

[0028] In detail, when the tuning voltage is at the output voltage boundary value, the operating current of the charge pump is increased, including: if the tuning voltage is zero or the power supply voltage, the charging mode or discharging mode of the charge pump is turned off, and the operating current is set to the upper limit of the configurable current range. Specifically, when the tuning voltage is 0V or the power supply voltage Vcp, if the current mode of the charge pump is charging mode, the charging mode is turned off; if the current mode of the charge pump is discharging mode, the discharging mode is turned off; and the operating current Icp of the charge pump is set to the upper limit of the configurable current range. For example, if the configurable current range is [0, 2.54], and the current unit is milliamperes, then the operating current is set to 2.54mA. After a delay, the charge pump completes the phase-locked loop locking at the maximum operating current Icp.

[0029] More specifically, the establishment method also includes restoring the operating current to its initial set value after the phase-locked loop (PLL) locks. Specifically, after PLL locking is completed, the charge pump's operating current Icp is restored to its initial set value, typically half of the configurable current range, i.e., 1.28mA. This achieves rapid PLL locking without requiring additional circuitry or degrading frequency source parameters such as spurious emissions, phase noise, and frequency hopping steps.

[0030] like Figure 2 As shown, this application also provides a phase-locked loop circuit, including: Phase detector 210 is used to compare the input signal Uin, which includes the target phase-locked frequency Fd, with the feedback signal U. FB Perform a phase comparison and generate a pulse control signal PD_out based on the phase difference; The charge pump 220 is used to output charging current or discharging current according to the pulse control signal PD_out. The operating current Icp includes both charging current and discharging current. Loop filter 230 is used to filter, smooth, and integrally convert the operating current Icp to obtain the tuning voltage V. T ; Voltage-controlled oscillator 240, used to adjust the voltage according to the tuning voltage V T The amplitude generates an oscillation signal V. VCO ; Power divider 250 is used to divide the oscillation signal V VCO The signal is allocated to at least two output channels, one of which serves as the output signal U of the phase-locked loop. OUT The other path is the feedback signal U. FB The feedback is sent to the feedback input of the phase detector to form a closed-loop phase lock; Control module 260 is used to adjust the tuning voltage V in response to the target phase-locked frequency fd deviating from the preset phase-locked adjustment frequency fmid. T The output voltage boundary value of charge pump 220 is set, and the tuning voltage V is...T When the output voltage reaches the boundary value, increase the operating current Icp.

[0031] Specifically, such as Figure 2 As shown, the phase-locked loop circuit includes a phase detector 210, a charge pump 220, a loop filter 230, a voltage-controlled oscillator 240, a power divider 250, and a control module 260. The phase detector 210 converts the input signal Uin and the feedback signal U... FB A phase comparison is performed, and a pulse control signal PD_out is generated based on the phase difference. The input terminal of charge pump 220 is connected to the output terminal of phase detector 210, and charge pump 220 generates operating current Icp under the control of pulse control signal PD_out. The input terminal of loop filter 230 is connected to the output terminal of charge pump 220. Loop filter 230 filters and smooths operating current Icp, and converts operating current Icp into a continuous voltage signal, i.e., tuning voltage V, through integration. T The input terminal of the voltage-controlled oscillator 240 is connected to the output terminal of the loop filter 230. The voltage-controlled oscillator 240 adjusts according to the tuning voltage V. T The amplitude generates an oscillation signal V. VCO The input terminal of the power divider 250 is connected to the output terminal of the voltage-controlled oscillator 240. The power divider 250 divides the oscillation signal V... VCO The signal is divided into two paths, with the first path serving as the output signal U of the phase-locked loop. OUT The second signal serves as the feedback signal U. FB The feedback signal U FB Feedback is sent to the feedback input terminal of the phase detector 210, thus forming a closed-loop phase-locked loop structure. The power divider 250 can generate multiple external output signals, and the specific output signals are determined according to the actual situation.

[0032] The control module 260 receives an input signal Uin, which includes the target phase-locked frequency fd. The control module 260 compares the target phase-locked frequency fd with the preset phase-locked adjustment frequency fmid. When the target phase-locked frequency fd and the preset phase-locked adjustment frequency fmid are not equal, the control module 260 adjusts the tuning voltage V input to the voltage-controlled oscillator 240. T The tuning voltage V T Pull-up to the supply voltage Vcp or pull-down to ground, and at the tuning voltage V T When the power supply voltage Vcp is zero, adjust the operating current Icp of the charge pump 220 to the upper limit of the configurable current range.

[0033] In detail, such as Figure 3 As shown, the charge pump 220 includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a current regulation unit 221. The current regulation unit 221 adjusts the voltage V at the tuning voltage V. TWhen the output voltage boundary value is reached, the operating current Icp is increased; the source of the first PMOS transistor PM1 is connected to the power supply voltage Vcp, the drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1, the source of the first NMOS transistor NM1 is grounded, the pulse control signal PD_out is connected to the gate of the first PMOS transistor PM1, the gate of the first NMOS transistor NM1 is connected to the pulse control signal PD_out, and the drain of the first PMOS transistor PM1 is the output terminal of the charge pump 220.

[0034] More in detail, such as Figure 3As shown, the current regulation unit 221 includes N second PMOS transistors (PM21~PM2N), N third PMOS transistors (PM31~PM3N), a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, N second NMOS transistors (NM21~NM2N), N third NMOS transistors (NM31~NM3N), a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and an operational amplifier COMP. The sources of the N second PMOS transistors (PM21~PM2N) are connected to the power supply voltage Vcp, and the drain of the i-th second PMOS transistor PM2i is connected to the i-th third PMOS transistor PM2i. The source of S-MOSFET PM3i and the drains of N third PMOS transistors (PM31~PM3N) are all connected to the source of the fifth PMOS transistor PM5. The source of the fifth PMOS transistor PM5 is also connected to the source of the fourth PMOS transistor PM4. The drain of the fourth PMOS transistor PM4 is connected to the drain of the fourth NMOS transistor NM4. The drain of the fourth PMOS transistor PM4 is also connected to the non-inverting input of the operational amplifier COMP. The inverting input of the operational amplifier COMP is connected to the output of the operational amplifier COMP. The output of the operational amplifier COMP is connected to the drain of the fifth NMOS transistor NM5. The drain of the fifth PMOS transistor PM5 is connected to the source of the fifth PMOS transistor PM5. The drain of the fifth NMOS transistor NM5 is connected to the source of the fourth NMOS transistor NM4. The drains of N second NMOS transistors (NM21~NM2N) are all connected to the source of the fifth NMOS transistor NM5. The source of the i-th second NMOS transistor NM2i is connected to the drain of the i-th third NMOS transistor NM3i. The sources of N third NMOS transistors (NM31~NM3N) are grounded. The non-inverting input of the operational amplifier COMP is also connected to the output of the charge pump 220. The gates of the N second PMOS transistors (PM21~PM2N) are all connected to the first reference current Ibias. 1. The gates of N third NMOS transistors (NM31~NM3N) are all connected to the second reference current Ibias2. The gates of N third PMOS transistors (PM31~PM3N) are connected to the first control signal UP[0:N-1]. The gates of N second NMOS transistors (NM21~NM2N) are connected to the second control signal DN[0:N-1]. The gates of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are connected to the third control signal K1. The gates of the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are connected to the fourth control signal K2. i and N are both positive integers, 1≤i<N.

[0035] It should be noted that, as Figure 3As shown, the current regulation unit 221 includes seven second PMOS transistors (PM21~PM27), seven third PMOS transistors (PM31~PM37), seven second NMOS transistors (NM21~NM27), and seven third NMOS transistors (NM31~NM37). The drain of the first second PMOS transistor PM21 is connected to the source of the first third PMOS transistor PM31, the drain of the second second PMOS transistor PM22 is connected to the source of the second third PMOS transistor PM32, and so on, with the drain of the seventh second PMOS transistor PM27 connected to the source of the seventh third PMOS transistor PM37. Similarly, the source of the first second NMOS transistor NM21 is connected to the drain of the first third NMOS transistor NM31, the source of the second second NMOS transistor NM22 is connected to the drain of the second third NMOS transistor NM32, and so on, with the source of the seventh second NMOS transistor NM27 connected to the drain of the seventh third NMOS transistor NM37. The gates of the seven third PMOS transistors (PM31~PM37) are connected to the first control signal UP[0:6], which is a 7-bit parallel digital control code. The gates of the seven second NMOS transistors (NM21~NM27) are connected to the second control signal DN[0:6], which is a 7-bit parallel digital control code.

[0036] More specifically, the width-to-length ratio of the (i+1)th second PMOS transistor is twice that of the ith second PMOS transistor, and the width-to-length ratio of the (i+1)th third PMOS transistor is twice that of the ith third PMOS transistor; the width-to-length ratio of the (i+1)th second NMOS transistor is twice that of the ith second NMOS transistor, and the width-to-length ratio of the (i+1)th third NMOS transistor is twice that of the ith third NMOS transistor.

[0037] Specifically, such as Figure 3As shown, the aspect ratio of the second PMOS transistor PM22 is twice that of the first PMOS transistor PM21, the aspect ratio of the third PMOS transistor PM23 is twice that of the second PMOS transistor PM22, and so on. The aspect ratio of the seventh PMOS transistor PM27 is twice that of the sixth PMOS transistor PM26. Similarly, the aspect ratio of the second PMOS transistor PM32 is twice that of the first PMOS transistor PM31, the aspect ratio of the third PMOS transistor PM33 is twice that of the second PMOS transistor PM32, and so on. The aspect ratio of the seventh PMOS transistor PM37 is twice that of the sixth PMOS transistor PM36. The aspect ratio of the second NMOS transistor NM22 is twice that of the first NMOS transistor NM21, the aspect ratio of the third NMOS transistor NM23 is twice that of the second NMOS transistor NM22, and so on. The aspect ratio of the seventh NMOS transistor NM27 is twice that of the sixth NMOS transistor NM26. Similarly, the aspect ratio of the second NMOS transistor NM32 is twice that of the first NMOS transistor NM31, the aspect ratio of the third NMOS transistor NM33 is twice that of the second NMOS transistor NM32, and so on. The aspect ratio of the seventh NMOS transistor NM37 is twice that of the sixth NMOS transistor NM36.

[0038] It is important to emphasize that the operating current Icp is 1.28mA after the seventh PMOS transistor PM37 and the seventh NMOS transistor NM27 are turned on; the operating current Icp is 0.64mA after the sixth PMOS transistor PM36 and the sixth NMOS transistor NM26 are turned on; and so on, halving to 0.02mA after the first PMOS transistor PM31 and the first NMOS transistor NM21 are turned on. When all seven PMOS transistors (PM31~PM37) and the seven NMOS transistors (NM21~NM27) are turned on, the operating current Icp of the charge pump 220 is 1.28mA + 0.64mA + ... + 0.02mA = 2.54mA. Therefore, when the seventh third PMOS transistor PM37 is turned on, the seventh second NMOS transistor NM27 is turned on, and the first third PMOS transistor PM31 to the sixth third PMOS transistor PM36 are turned off, and the first second NMOS transistor NM21 to the sixth second NMOS transistor NM26 are turned off, the operating current Icp of the charge pump 220 can be half of the configurable current range, i.e., 1.28mA.

[0039] refer to Figures 1 to 3 As shown, the working principle of the phase-locked loop circuit provided in this application is as follows: The control module 260 compares the target phase-locked frequency fd with the preset phase-locked adjustment frequency fmid. When the target phase-locked frequency fd is less than the preset phase-locked adjustment frequency fmid, the control module 220 controls the charge pump 220 to start the discharge mode. After a delay, the control module discharges the tuning voltage V input to the voltage-controlled oscillator 240. T Pulling down to zero, when the target phase-locked frequency fd is greater than the preset phase-locked adjustment frequency fmid, the charge pump 220 is controlled to start charging mode. After a delay, the tuning voltage V output by the voltage-controlled oscillator 240 is increased. T Pulling up the power supply voltage Vcp to charge pump 220 makes the output of charge pump 220 closer to the tuning voltage V corresponding to the target phase-locked frequency fd. T .

[0040] When the tuning voltage V T When the voltage is 0V or the power supply voltage Vcp, if the current mode of charge pump 220 is charging mode, the charging mode is turned off; if the current mode of charge pump 220 is discharging mode, the discharging mode is turned off; and the operating current Icp in charge pump 220 is set to the upper limit of the configurable current range, that is, all seven third PMOS transistors (PM31~PM37) are turned on, and all seven second NMOS transistors (NM21~NM27) are turned on. Among them, the third control signal K1 and the fourth control signal K2 are opposite in level, and the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are not turned on at the same time as the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5. To avoid affecting other characteristics of the phase-locked loop (PLL), after phase locking is completed, the operating current Icp of the charge pump 220 is set to the initial value. This means the seventh PMOS transistor PM37 and the seventh NMOS transistor NM27 are turned on, while the first through sixth PMOS transistors PM31 are turned off, and the first through sixth NMOS transistors NM21 are turned off, thus completing frequency hopping. In this way, the lockout time of the PLL circuit can be reduced from 200 microseconds to 40 microseconds.

[0041] Specifically, when the tuning voltage is 0V, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are turned on, and the seven third PMOS transistors (PM31~PM37) are turned on, adjusting the charging current to the maximum. At this time, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are turned off, and the seven second NMOS transistors (NM21~NM27) are turned on. When the tuning voltage is the power supply voltage Vcp, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are turned on, and the seven second NMOS transistors (NM21~NM27) are turned on, adjusting the discharge current to the maximum. At this time, the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are turned off, and the seven third PMOS transistors (PM31~PM37) are turned on.

[0042] This invention proposes a method for rapidly establishing the lock-up time of a phase-locked loop (PLL) and a PLL circuit. The method includes: acquiring a target PLL frequency; in response to a deviation of the target PLL frequency from a preset PLL adjustment frequency, setting the tuning voltage of the input voltage-controlled oscillator (VCO) to the output voltage boundary value of the charge pump; when the tuning voltage is at the output voltage boundary value, increasing the operating current of the charge pump to shorten the lock-up time; and restoring the operating current of the charge pump to its initial set value after phase-locking is completed. This application provides a rapid lock-up time establishment scheme. Based on the deviation of the target PLL frequency from the preset PLL adjustment frequency, the tuning voltage of the input VCO is rapidly pulled to a voltage value close to the target PLL frequency to achieve the preset voltage function, thereby reducing the voltage tuning span during the phase-locking process and shortening the lock-up time. During the phase-locking process, the operating current of the charge pump is increased to widen the loop bandwidth and accelerate the charging and discharging speed of the loop capacitor, further shortening the lock-up time. After the PLL is locked, the operating current of the charge pump is restored to its normal value to maintain the frequency source's spurious emissions, phase noise, and frequency hopping step unaffected.

[0043] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for rapidly establishing the locking time of a phase-locked loop, characterized in that, include: Obtain the target phase-locked frequency; In response to the target phase-locked frequency deviating from the preset phase-locked adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is set to the output voltage boundary value of the charge pump; When the tuning voltage is the output voltage boundary value, the operating current of the charge pump is increased to shorten the lock-in time.

2. The method for rapidly establishing the phase-locked loop locking time according to claim 1, characterized in that, The output voltage boundary value includes zero and the supply voltage. In response to the target phase-locked frequency deviating from the preset phase-locked frequency adjustment frequency, the tuning voltage of the input voltage-controlled oscillator is set as the output voltage boundary value of the charge pump, including: When the target phase-locked frequency is less than the preset phase-locked adjustment frequency, the charge pump is controlled to start the discharge mode so that the tuning voltage is adjusted to zero. When the target phase-locked frequency is greater than the preset phase-locked adjustment frequency, the charge pump is controlled to start the charging mode so that the tuning voltage is adjusted to the power supply voltage.

3. The method for rapidly establishing the phase-locked loop locking time according to claim 2, characterized in that, When the tuning voltage is at the output voltage boundary value, the operating current of the charge pump is increased, including: If the tuning voltage is zero or the power supply voltage is zero, the charging or discharging mode of the charge pump is turned off, and the operating current is set to the upper limit of the configurable current range.

4. The method for rapidly establishing the phase-locked loop locking time according to claim 3, characterized in that, The establishment method further includes: After the phase-locked loop is locked, the operating current is restored to the initial set value.

5. A phase-locked loop circuit, characterized in that, include: A phase detector is used to compare the phase of an input signal, including the target phase-locked frequency, with a feedback signal and generate a pulse control signal based on the phase difference. A charge pump is used to output a charging current or a discharging current according to the pulse control signal, and the operating current includes the charging current and the discharging current. A loop filter is used to filter, smooth, and integrate the operating current to obtain the tuning voltage; A voltage-controlled oscillator for generating an oscillation signal based on the amplitude of the tuning voltage; The power divider is used to distribute the oscillation signal into at least two signal outputs, one of which is the output signal of the phase-locked loop and the other is the feedback signal, which is fed back to the feedback input terminal of the phase detector to form a closed-loop phase-locked loop. The control module is configured to, in response to the target phase-locked frequency deviating from the preset phase-locked adjustment frequency, set the tuning voltage to the output voltage boundary value of the charge pump, and increase the operating current when the tuning voltage is the output voltage boundary value.

6. The phase-locked loop circuit according to claim 5, characterized in that, The charge pump includes a first PMOS transistor, a first NMOS transistor, and a current regulation unit. The current regulation unit increases the operating current when the tuning voltage is the output voltage boundary value. The source of the first PMOS transistor is connected to the power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is grounded, the gates of the first PMOS transistor and the first NMOS transistor are connected to the pulse control signal, and the drain of the first PMOS transistor is the output terminal of the charge pump.

7. The phase-locked loop circuit according to claim 6, characterized in that, The current regulation unit includes N second PMOS transistors, N third PMOS transistors, a fourth PMOS transistor, a fifth PMOS transistor, N second NMOS transistors, N third NMOS transistors, a fourth NMOS transistor, a fifth NMOS transistor, and an operational amplifier. The sources of the N second PMOS transistors are connected to the power supply voltage. The drain of the i-th second PMOS transistor is connected to the source of the i-th third PMOS transistor. The drains of the N third PMOS transistors are all connected to the sources of the fifth PMOS transistors. The source of the fifth PMOS transistor is also connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the fourth PMOS transistor is also connected to the non-inverting input of the operational amplifier. The inverting input of the operational amplifier is connected to the output of the operational amplifier. The output of the operational amplifier is connected to the drain of the fifth NMOS transistor. The drain of the fifth PMOS transistor is connected to the... The drain of the fifth NMOS transistor is connected to the source of the fourth NMOS transistor. The drains of N second NMOS transistors are all connected to the sources of the fifth NMOS transistor. The source of the i-th second NMOS transistor is connected to the drain of the i-th third PMOS transistor. The sources of N third NMOS transistors are grounded. The non-inverting input of the operational amplifier is also connected to the output of the charge pump. The gates of N second PMOS transistors are all connected to a first reference current. The gates of N third NMOS transistors are all connected to a second reference current. The gates of N third PMOS transistors are connected to a first control signal. The gates of N second NMOS transistors are connected to a second control signal. The gates of the fourth PMOS transistor and the fifth PMOS transistor are connected to a third control signal. The gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to a fourth control signal. i and N are both positive integers, and 1 ≤ i < N.

8. The phase-locked loop circuit according to claim 7, characterized in that, The width-to-length ratio of the (i+1)th second PMOS transistor is twice that of the ith second PMOS transistor, and the width-to-length ratio of the (i+1)th third PMOS transistor is twice that of the ith third PMOS transistor; the width-to-length ratio of the (i+1)th second NMOS transistor is twice that of the ith second NMOS transistor, and the width-to-length ratio of the (i+1)th third NMOS transistor is twice that of the ith third NMOS transistor.

Images