A pulse synchronization control method of a multi-modal acquisition circuit

Abstract

The present application relates to the automatic control technical field of electronic oscillator and pulse generator, disclose a kind of pulse synchronous control method of multimode acquisition circuit, comprising: as the pulse generator, multiplex phase-locked frequency division circuit receives global synchronization reference clock and frequency division generates hardware sampling trigger pulse, realizes phase automatic control and synchronization;When receiving configuration instruction, issue state latch signal, freeze the pulse output state of phase-locked frequency division circuit, write parameter and reconfigure hardware unit, release state latch signal and relock phase after reconfiguration completion, keep the phase stability of pulse generation process;Issue control level drive switch array, control each excitation path break.

Description

Technical Field

[0001] This invention relates to the field of automatic control technology for electronic oscillators and pulse generators, and more specifically, to a pulse synchronization control method for a multi-mode acquisition circuit. Background Technology

[0002] Multi-channel sensor acquisition systems typically utilize pulse generation and phase synchronization circuits to generate sampling clocks. Common methods include using discrete circuits or fixed signal chain chips to complete clock distribution and pulse generation. When the system simultaneously acquires different types of sensor signals such as pressure, temperature, vibration, and speed, each channel usually needs to be set with a different sampling frequency. The pulse generation circuit needs to divide the global reference clock source to generate multiple hardware sampling trigger pulses according to the sampling frequency set for each channel. Whether the trigger pulses can maintain accurate phase alignment and stable timing directly affects the synchronous acquisition quality of multi-channel sensor data.

[0003] In industrial equipment operation and complex working conditions, sensor types may need to be changed and acquisition parameters may need to be adjusted. Therefore, acquisition circuits usually need to have online reconfiguration capabilities. In addition to the physical limitations of the hardware topology being constrained by the fixed signal chain, there are also shortcomings in pulse synchronization and logic control methods. For example, Chinese invention patent CN103592881B discloses a multi-channel signal synchronous sampling control circuit based on FPGA. It uses latching signals generated inside the FPGA to perform unified back-end latching of multiple data to achieve synchronous reading of multiple data. However, this method only performs static latching of data at the data acquisition and processing back-end, and does not establish a dynamic phase-locking and alignment mechanism for heterogeneous sampling rates at the pulse generation source. When the channel parameters are dynamically reconfigured online, its control logic cannot block the high-frequency glitches and phase loss caused by asynchronous register writing. At the same time, the transient electromagnetic shock caused by the switching of the front-end excitation mode is very likely to crosstalk the clock circuit, resulting in pulse timing drift and phase loss.

[0004] Therefore, when multiple pulses operate in parallel at different sampling frequencies, how to improve the phase alignment accuracy and automatic synchronization control performance of multiple pulses, avoid generating high-frequency glitch pulses during dynamic reconstruction and maintain stable pulse generation, and reduce electromagnetic crosstalk of excitation switching on the phase-locked loop are still problems that existing pulse synchronization control technologies need to solve. Summary of the Invention

[0005] To address the problems in the background art, this invention provides a pulse synchronization control method for a multi-mode acquisition circuit, comprising the following steps: Step S1: The isolated bus communication unit receives the global synchronization reference clock sent by the master station; the multi-channel phase-locked frequency divider circuit inside the SDA acquisition chip receives the global synchronization reference clock, performs phase-locked frequency division according to the preset sampling rate parameters of each channel, and generates the hardware sampling trigger pulse of the corresponding channel. The hardware sampling trigger pulse of each channel takes the global synchronization reference clock as the phase alignment reference. Step S2: When the channel configuration instruction is received, the MCU global configuration unit of the SDA acquisition chip sends a status latch signal to freeze the current hardware working state of each channel and the pulse output state of the multi-channel phase-locked frequency divider circuit. Step S3: The MCU global configuration unit writes channel parameters to the hardware configuration register, reconfigures the programmable interface unit, FPGA modulation unit and dual DSP filtering unit according to the preset pipeline timing, and sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel. Step S4: When the reconfiguration is completed, the state latch signal is released, the multi-channel phase-locked frequency divider circuit resumes operation and relocks the phase, and outputs an aligned hardware sampling trigger pulse to block the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse.

[0006] Preferably, step S3, which involves reconfiguring the programmable interface unit, FPGA modulation unit, and dual DSP filtering unit according to a preset pipeline timing sequence, includes: step S31, issuing register latch timing, freezing the hardware operating state of the current multi-channel independent acquisition channel unit, and synchronously releasing the port configuration resources of the programmable interface unit, the modulation logic resources of the FPGA modulation unit, and the filtering operation resources of the dual DSP filtering unit; step S32, after completing the writing of channel parameters into the hardware configuration register, configuring the signal access mode of the programmable interface unit, the modulation gain of the FPGA modulation unit, and the filtering order of the dual DSP filtering unit according to a preset pipeline timing sequence, and recalibrating the division coefficients of the multi-channel phase-locked frequency divider circuit.

[0007] Preferably, step S3, which sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel, includes: step S33, where the excitation generator inside the isolated power supply module receives the excitation configuration signal from the MCU global configuration unit and generates an excitation signal with a set waveform; step S34, where the MCU global configuration unit sends channel switch control levels to the switch array composed of multiple D flip-flops and transistors via the SDA bus, whereby the multiple D flip-flops latch the channel switch control levels and drive the corresponding transistors to turn on or off, controlling the on / off state of the excitation output path of each acquisition channel, and blocking the phase interference of the excitation switching pulse on the hardware sampling trigger pulse.

[0008] Preferably, the excitation signal for generating the set waveform in step S33 includes: the excitation source inside the isolated power supply module switching between a sine wave excitation mode with a frequency of 0.1Hz to 10kHz and an amplitude of 0V to 10V, a constant voltage excitation mode of 0V to 10V, and a constant current excitation mode of 4mA to 20mA to generate the corresponding excitation signal.

[0009] Preferably, after outputting the aligned hardware sampling trigger pulse in step S4, a hardware preprocessing pipeline synchronization step is also included. The hardware preprocessing pipeline synchronization step includes: step S41, under the edge triggering of the hardware sampling trigger pulse, multiple independent acquisition channel units synchronously perform analog-to-digital conversion on the input analog sensing signal to generate digital data; step S42, the digital data sequentially enters the hardware preprocessing unit, and under the control of a unified hardware synchronization clock, temperature and pressure coupled temperature drift correction and noise reduction calculations are performed in parallel according to the pipeline timing.

[0010] Preferably, the temperature and pressure coupled temperature drift correction in step S42 includes: the digital data flows into the hardware error compensation module in the hardware preprocessing unit, and within the operating temperature range of -40℃ to 85℃, the digital data is used to perform real-time hardware correction of temperature and pressure coupled temperature drift based on a two-dimensional plane compensation algorithm or a two-dimensional curved surface compensation algorithm, and the corrected data is stored in the on-chip data cache register.

[0011] Preferably, the method further includes a timestamp embedding and packet transmission step, which includes: step S43, when the analog-to-digital conversion is completed, the hardware pipeline obtains the count value of the current global synchronization reference clock and embeds a unified high-precision timestamp in the data frame header of the preprocessed data; step S44, the data with the embedded high-precision timestamp enters the independent data buffer of the corresponding channel, and according to the transmission bandwidth of the isolated bus communication unit, it is packaged into digital data packets according to the time-division reuse logic and uploaded to the master station via the isolated Ethernet bus.

[0012] Preferably, the isolation power supply module has three independently isolated power supplies that are electrically isolated from each other, which independently supply power to the sensing excitation circuit, the SDA acquisition chip core circuit and the Ethernet bus circuit, respectively. The isolation withstand voltage is not less than 2000V, blocking the pulse interference generated by the motor and hydraulic system.

[0013] Preferably, the multi-channel independent acquisition unit synchronously acquires sensor signals of different signal types; the signal types include ±50mV small signals, 0V to 10V voltage signals, 4mA to 20mA current signals, ICP piezoelectric signals, thermocouple signals, and SPI or IIC digital signals; under software reconfiguration and pulse synchronization control, the multi-channel independent acquisition unit can complete the pulse synchronous acquisition of multimodal sensor signals in parallel without changing the hardware circuit.

[0014] The embodiments of the present invention have at least the following beneficial effects: 1. In the pulse synchronization control of the multi-modal acquisition circuit, a global synchronization reference clock is used as a unified phase reference, and hardware sampling trigger pulses for each channel are generated through a multi-channel phase-locked frequency divider circuit. This enables the trigger pulses of channels with different sampling rates to maintain stable phase alignment, reduce the cumulative phase drift and high-frequency timing jitter under heterogeneous sampling frequencies, avoid pulse generation out-of-synchronization, thereby improving the pulse synchronization and timing stability during multi-channel parallel sampling, and providing a stable clock reference for the synchronous acquisition of multi-modal sensing signals.

[0015] 2. During the dynamic reconstruction of channel parameters, the working state of each channel and the pulse output state of the multi-channel phase-locked frequency divider circuit are temporarily maintained by state latching, and the phase is relocked after the reconfiguration is completed. This can avoid high-frequency glitches and phase loss caused by asynchronous register updates, reduce the impact of parameter switching on the pulse generation process, maintain good phase continuity of the trigger pulses before and after reconstruction, and maintain the stability of the control state of each channel.

[0016] 3. By controlling the channel switch level through multiple D flip-flops and controlling the excitation output path of each channel separately, the excitation mode switching and sampling pulse control can be separated, reducing the impact of transient electromagnetic interference generated by excitation switching on the multi-channel phase-locked frequency divider circuit. As a result, the excitation output and sampling pulse of each channel can work relatively independently, reducing the pulse interference caused by the excitation switching of active sensors, which is beneficial to maintaining the stability of sampling pulses and sensing signals under complex working conditions. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the invention are illustrated by way of example and not limitation, wherein: Figure 1 This is a flowchart of the sampling trigger pulse phase locking and dynamic reconstruction process of the present invention; Figure 2 This is a diagram showing the architecture of the multi-channel sampling control circuit and the key signal correlation of the present invention. Detailed Implementation

[0018] The principles and spirit of the present invention will now be described with reference to several exemplary embodiments in conjunction with the accompanying drawings. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0019] A pulse synchronization control method for a multi-mode acquisition circuit includes the following steps: Step S1: The isolated bus communication unit receives the global synchronization reference clock sent by the master station; the multi-channel phase-locked frequency divider circuit inside the SDA acquisition chip receives the global synchronization reference clock, performs phase-locked frequency division according to the preset sampling rate parameters of each channel, and generates the hardware sampling trigger pulse of the corresponding channel. The hardware sampling trigger pulse of each channel takes the global synchronization reference clock as the phase alignment reference. Step S2: When the channel configuration instruction is received, the MCU global configuration unit of the SDA acquisition chip sends a status latch signal to freeze the current hardware working state of each channel and the pulse output state of the multi-channel phase-locked frequency divider circuit. Step S3: The MCU global configuration unit writes channel parameters to the hardware configuration register, reconfigures the programmable interface unit, FPGA modulation unit and dual DSP filtering unit according to the preset pipeline timing, and sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel. Step S4: When the reconfiguration is completed, the state latch signal is released, the multi-channel phase-locked frequency divider circuit resumes operation and relocks the phase, and outputs an aligned hardware sampling trigger pulse to block the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse.

[0020] Preferably, step S3, which involves reconfiguring the programmable interface unit, FPGA modulation unit, and dual DSP filtering unit according to a preset pipeline timing sequence, includes: step S31, issuing register latch timing, freezing the hardware operating state of the current multi-channel independent acquisition channel unit, and synchronously releasing the port configuration resources of the programmable interface unit, the modulation logic resources of the FPGA modulation unit, and the filtering operation resources of the dual DSP filtering unit; step S32, after completing the writing of channel parameters into the hardware configuration register, configuring the signal access mode of the programmable interface unit, the modulation gain of the FPGA modulation unit, and the filtering order of the dual DSP filtering unit according to a preset pipeline timing sequence, and recalibrating the division coefficients of the multi-channel phase-locked frequency divider circuit.

[0021] Preferably, step S3, which sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel, includes: step S33, where the excitation generator inside the isolated power supply module receives the excitation configuration signal from the MCU global configuration unit and generates an excitation signal with a set waveform; step S34, where the MCU global configuration unit sends channel switch control levels to the switch array composed of multiple D flip-flops and transistors via the SDA bus, whereby the multiple D flip-flops latch the channel switch control levels and drive the corresponding transistors to turn on or off, controlling the on / off state of the excitation output path of each acquisition channel, and blocking the phase interference of the excitation switching pulse on the hardware sampling trigger pulse.

[0022] Preferably, the excitation signal for generating the set waveform in step S33 includes: the excitation source inside the isolated power supply module switching between a sine wave excitation mode with a frequency of 0.1Hz to 10kHz and an amplitude of 0V to 10V, a constant voltage excitation mode of 0V to 10V, and a constant current excitation mode of 4mA to 20mA to generate the corresponding excitation signal.

[0023] Preferably, after outputting the aligned hardware sampling trigger pulse in step S4, a hardware preprocessing pipeline synchronization step is also included. The hardware preprocessing pipeline synchronization step includes: step S41, under the edge triggering of the hardware sampling trigger pulse, multiple independent acquisition channel units synchronously perform analog-to-digital conversion on the input analog sensing signal to generate digital data; step S42, the digital data sequentially enters the hardware preprocessing unit, and under the control of a unified hardware synchronization clock, temperature and pressure coupled temperature drift correction and noise reduction calculations are performed in parallel according to the pipeline timing.

[0024] Preferably, the temperature and pressure coupled temperature drift correction in step S42 includes: the digital data flows into the hardware error compensation module in the hardware preprocessing unit, and within the operating temperature range of -40℃ to 85℃, the digital data is used to perform real-time hardware correction of temperature and pressure coupled temperature drift based on a two-dimensional plane compensation algorithm or a two-dimensional curved surface compensation algorithm, and the corrected data is stored in the on-chip data cache register.

[0025] Preferably, the method further includes a timestamp embedding and packet transmission step, which includes: step S43, when the analog-to-digital conversion is completed, the hardware pipeline obtains the count value of the current global synchronization reference clock and embeds a unified high-precision timestamp in the data frame header of the preprocessed data; step S44, the data with the embedded high-precision timestamp enters the independent data buffer of the corresponding channel, and according to the transmission bandwidth of the isolated bus communication unit, it is packaged into digital data packets according to the time-division reuse logic and uploaded to the master station via the isolated Ethernet bus.

[0026] Preferably, the isolation power supply module has three independently isolated power supplies that are electrically isolated from each other, which independently supply power to the sensing excitation circuit, the SDA acquisition chip core circuit and the Ethernet bus circuit, respectively. The isolation withstand voltage is not less than 2000V, blocking the pulse interference generated by the motor and hydraulic system.

[0027] Preferably, the multi-channel independent acquisition unit synchronously acquires sensor signals of different signal types; the signal types include ±50mV small signals, 0V to 10V voltage signals, 4mA to 20mA current signals, ICP piezoelectric signals, thermocouple signals, and SPI or IIC digital signals; under software reconfiguration and pulse synchronization control, the multi-channel independent acquisition unit can complete the pulse synchronous acquisition of multimodal sensor signals in parallel without changing the hardware circuit.

[0028] Example 1: This example uses the overall sensor acquisition of a 20-ton hydraulic excavator as an example. It requires distributed synchronous acquisition of six heterogeneous sensor signals: high-frequency vibration, oil temperature, hydraulic pressure, speed, oil level, and machine posture. The isolated bus communication unit receives the global synchronization reference clock from the master station via an isolated Ethernet bus. The SDA acquisition chip's internal multi-channel phase-locked frequency divider circuit receives the global synchronization reference clock and performs phase-locked frequency division calculations based on the preset sampling rate parameters of each channel to generate the corresponding channel's hardware sampling trigger pulse. The first channel corresponds to the ICP vibration sensor, with a sampling rate configured at 100kHz. A 100kHz hardware sampling trigger pulse is generated; the second channel corresponds to the oil temperature thermocouple, with a sampling rate configured at 10Hz; the third channel corresponds to the hydraulic pressure sensor, with a sampling rate configured at 1kHz; the fourth channel corresponds to the speed Hall sensor, configured in digital pulse input mode; the fifth channel corresponds to the oil level sensor, with a sampling rate configured at 100Hz; and the sixth channel corresponds to the tilt sensor, with a sampling rate configured at 500Hz. The hardware sampling trigger pulses of each channel are phase-aligned with the global synchronization reference clock, and the phase deviation between the hardware sampling trigger pulses of each channel and the global synchronization reference clock satisfies the following relationship: ,in, For the first The actual phase of the channel hardware sampling trigger pulse. For the phase of the global synchronization reference clock, To achieve the maximum allowable pulse phase jitter limit, the measured phase deviation is less than 10ns, enabling automatic phase control and synchronization alignment of multi-channel heterogeneous sampling pulses from the underlying oscillation source.

[0029] When driving the various heterogeneous sensors of the excavator, the MCU global configuration unit of the SDA acquisition chip receives the excitation configuration command issued by the master station. The excitation generator inside the isolated power supply module receives the excitation configuration signal from the MCU global configuration unit and generates an excitation signal with a set waveform. Among them, the first channel outputs a sine wave excitation signal with an amplitude of 10V and a frequency of 1kHz to drive the piezoelectric vibration sensor; the second and fourth channels turn off the excitation output; the third channel outputs a constant pressure excitation signal from 0V to 10V to drive the strain gauge hydraulic pressure sensor; and the fifth channel outputs a 4mA to 20V constant pressure excitation signal. A constant current excitation signal of mA drives the oil level sensor, and a constant voltage excitation signal of 5V is output from the sixth channel to drive the tilt sensor. The MCU global configuration unit sends channel switch control levels to the switch array composed of multiple D flip-flops and transistors via the SDA bus. The multiple D flip-flops latch the channel switch control levels and drive the corresponding transistors to turn on or off, controlling the on / off of the excitation output path of each acquisition channel. The multiple D flip-flops latch and drive the control levels, blocking the phase interference of the excitation switching pulse on the hardware sampling trigger pulse, and realizing the decoupled operation of multi-mode excitation output and sampling pulse control.

[0030] When the pressure sensor is replaced on-site at the hydraulic excavator, and the input range is switched from 0V to 25MPa to 0V to 40MPa, the MCU global configuration unit of the SDA acquisition chip receives the channel configuration command and issues a status latch signal to freeze the current hardware operating status of each channel and the pulse output status of the multi-channel phase-locked frequency divider circuit. The MCU global configuration unit writes the channel parameters of the third channel to the hardware configuration register, reconfigures the programmable interface unit, FPGA modulation unit, and dual DSP filtering unit according to the preset pipeline timing, and issues the register latch timing to freeze the current hardware operating status of the multi-channel independent acquisition channel unit. Simultaneously, it releases the port configuration resources of the programmable interface unit, the modulation logic resources of the FPGA modulation unit, and the filtering operation resources of the dual DSP filtering unit. After completing the parameter writing to the hardware configuration register, it sequentially configures the signal access mode of the programmable interface unit, the modulation gain of the FPGA modulation unit, and the filtering order of the dual DSP filtering unit according to the preset pipeline timing, and recalibrates the multi-channel... The division coefficient of the phase-locked frequency divider circuit releases the state latch signal when the reconfiguration is completed. The multi-channel phase-locked frequency divider circuit resumes operation and relocks the phase, outputting an aligned hardware sampling trigger pulse. The configuration reconstruction process is completed within 5 seconds without high-frequency glitch pulse output. The phase interference of the blocking parameter reconfiguration with the hardware sampling trigger pulse is prevented. During the reconfiguration process, the MCU global configuration unit sends the local reconstruction bit stream data packet to the field programmable gate array in the FPGA modulation unit through the internal serial peripheral interface, updating the modulation gain register address of its logic module to the newly written gain coefficient. When reconfiguring the filter order of the dual digital signal processors in the dual DSP filtering unit, a smooth loading mechanism of historical state cache is adopted to keep the filter state variables and historical sampling data in the on-chip high-speed static memory at the previous moment. When the filter order is reconfigured from 8th to 16th, the new filter coefficients directly inherit the old state variables as the recursion starting point after being written, thereby avoiding output data discontinuity and numerical jump caused by algorithm reconstruction transients.

[0031] Triggered by the edge of the hardware sampling trigger pulse, multiple independent acquisition channel units synchronously perform analog-to-digital conversion on the input analog sensing signals to generate digital data. The pressure sensing signal is transmitted via a 15-meter long line and then connected to the input terminal IN. Overvoltage protection is provided by a circuit consisting of resistors R3 and R4 and Zener diode D1. The signal is then sent to an impedance matching conditioning circuit consisting of operational amplifiers U1 and U2, where analog-to-digital conversion is completed at the front end. The digital data sequentially enters the hardware preprocessing unit, with a unified hardware synchronization clock using a global synchronization reference clock as the time base. Under the control of the unified hardware synchronization clock, the hardware preprocessing unit performs temperature and pressure coupling temperature drift correction and noise reduction calculations in parallel according to the pipeline timing. The digital data from the third channel flows into the hardware error compensation module in the hardware preprocessing unit, operating within a temperature range of -40℃ to 85℃. Based on a two-dimensional surface compensation algorithm, the hardware performs real-time hardware correction of temperature and pressure coupling temperature drift of digital data. When using a two-dimensional plane compensation algorithm, the hardware error compensation module establishes a plane compensation relationship based on pre-calibrated temperature and pressure node data, using temperature and pressure as two compensation dimensions. It then corrects the digital data according to the compensation amount corresponding to the current temperature and pressure. The corrected data is stored in the on-chip data buffer register, and wavelet denoising and complementary filtering operations are performed by the hardware parallel noise reduction module. When the analog-to-digital conversion is completed, the hardware pipeline obtains the count value of the current global synchronization reference clock and embeds a unified high-precision timestamp into the data frame header of the pre-processed data. The data with the high-precision timestamp is entered into the independent data buffer area of ​​the corresponding channel and packaged into digital data packets according to the time-division reuse logic based on the transmission bandwidth of the isolated bus communication unit.

[0032] During the specific packaging process, the amount of data that can be sent within a transmission cycle is determined based on the available transmission bandwidth of the isolated bus communication unit. Non-overlapping transmission time slots are allocated to each independent data buffer according to the channel sequence. Each channel reads the buffered data in the corresponding time slot and forms a digital data packet, which is then uploaded to the main station via the isolated Ethernet bus. Under the strong electromagnetic pulse interference caused by the start and stop of the hydraulic pump and the main motor, the acquired data remains stable. The three independent isolated power supplies of the isolated power supply module provide independent isolated power supply to the sensing excitation circuit, the core circuit of the SDA acquisition chip, and the Ethernet bus circuit, respectively. The isolation withstand voltage of the whole machine reaches 2000V, and the measurement error under high and low temperature conditions is maintained within 0.05%.

[0033] Each channel in the multi-channel independent acquisition unit adopts a pre-stage physical conditioning topology that can be configured and reconfigured online. The input terminals are connected in parallel to multiple attenuation and matching branches controlled by MOSFETs: when a 4mA to 20mA current signal is input, the MCU global configuration unit controls the corresponding MOSFET to conduct, bridging a 250-ohm high-precision sampling resistor between the input terminal and ground, converting the current signal into a 1V to 5V voltage signal; when a ±50mV small signal is input, the attenuation resistor network is disconnected, and the gain of the programmable gain amplifier is configured to 100. The signal is amplified by a factor of 1; when a 0V to 10V voltage signal is input, a voltage divider attenuation network is used to attenuate the signal by a ratio of 10 to 1 before sending it to a buffer amplifier with a gain of 1; when a piezoelectric signal is input, a constant current source circuit is controlled to inject a constant bias current of 4mA into the input cable and the DC blocking capacitor is turned on; when a digital bus signal is input, the front-end switches to a high-impedance digital port and maps the pin functions to a general serial bus. Through the combined level switching of the above-mentioned switch array and gain control line, each acquisition channel can achieve soft reconstruction compatible acquisition of multimodal sensing signals while keeping the physical circuit of the hardware interface completely unchanged.

[0034] The system receives a global synchronization reference clock through a multi-channel phase-locked frequency divider circuit and divides it to generate a hardware sampling trigger pulse. During the channel reconstruction phase, it performs state latching and phase-locked frequency division relocking. Combined with a switching array composed of multiple D flip-flops and transistors, it latches and drives the excitation output path, blocking the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse, eliminating phase drift under heterogeneous sampling rates, and ensuring the timing stability of the hardware sampling trigger pulse and the phase synchronization stability of the pulse generation.

[0035] Example 2: This example verifies the pulse synchronization control effect of the multi-modal acquisition circuit under electromagnetic pulse interference and cross-temperature range conditions in engineering machinery. A hardware test platform based on a multi-modal sensor signal generator and a strong electromagnetic interference simulator was built. The test platform uses an on-board 24V isolated power supply unit, connected to the slave station via a 15-meter long cable. Gaussian white noise with a signal-to-noise ratio of 20dB and 50Hz power frequency harmonic interference are injected into the input signal source. The temperature cycling range covers -40℃ to 85℃. Five sample groups are set up for testing. The sample groups of this invention use a global synchronization reference clock and a multi-channel phase-locked loop frequency divider circuit to align the hardware sampling trigger pulse. During channel reconstruction, the MCU global configuration unit issues a state latch signal and coordinates with a switch array composed of multiple D flip-flops and transistors to control the excitation output path; Control group 1 removes the phase alignment mechanism of the multi-channel phase-locked frequency divider circuit and uses an independent software timer to generate the frequency division pulse; Control group 2 does not execute the state latch control of the MCU global configuration unit and directly updates the hardware configuration register when reconstructing the channel parameters; Control group 3 removes the switch array composed of multiple D flip-flops and transistors and uses an electronic switch without latching function to switch the excitation; Control group 4 sets the maximum allowable pulse phase jitter limit to 50ns.

[0036] During the test, under the pulse impact generated by the start and stop of the hydraulic pump of a 20-ton excavator, the sampling pulse phase deviation, the number of glitches in the parameter reconstruction process, the multi-channel sampling timing deviation, the full-temperature range measurement error, and the data jump rate under strong interference were collected for each sample group. In the sample group of the present invention, which uses a global synchronous reference clock, a multi-channel phase-locked frequency division circuit, a status latch signal, and a switch array working together, the sampling pulse phase deviation was 8.2ns, the number of glitches in the parameter reconstruction process was 0, the multi-channel sampling timing deviation was 0.08μs, the full-temperature range measurement error was 0.048%, and the data jump rate under strong interference was 0.01%.

[0037] When comparing the phase alignment process, control group 1 used an independent software timer to generate frequency division pulses. Its sampling pulse phase deviation was 142.6 ns, and the multi-channel sampling timing deviation was 12.40 μs. The number of glitches in the parameter reconstruction process was 0, the full temperature range measurement error was 0.850%, and the data jump rate under strong interference was 3.20%. This group did not use a multi-channel phase-locked loop frequency divider circuit to align the hardware sampling trigger pulse with the global synchronization reference clock, resulting in phase cumulative drift during heterogeneous sampling rate operation.

[0038] When comparing the parameter reconstruction process, control group 2 retained the phase-locked frequency division function, but directly updated the hardware configuration register during the channel parameter reconstruction without executing state latch control. The sampling pulse phase deviation of this group was 9.1ns, the parameter reconstruction process generated 38 high-frequency glitch pulses, the multi-channel sampling timing deviation was 0.12μs, the full temperature range measurement error was 0.120%, and the data jump rate under strong interference was 0.45%. When the hardware configuration register was updated online, the asynchronous nature of the configuration write acted on the multi-channel phase-locked frequency division circuit and the dual DSP filtering unit, resulting in high-frequency glitch pulses, clock synchronization loss, and data jumps.

[0039] When comparing the excitation switching process, control group 3 used an electronic switch without latching function to switch the excitation. Its sampling pulse phase deviation was 45.3ns, the number of glitches in the parameter reconstruction process was 12, the multi-channel sampling timing deviation was 3.10μs, the full temperature range measurement error was 0.380%, and the data jump rate under strong interference was 1.80%. During the excitation mode switching process, since there was no switch array composed of multiple D flip-flops and transistors to latch the channel switch control level, the transient current generated by the excitation source switching crosstalked to the main phase-locked loop, and the sampling pulse phase shifted accordingly.

[0040] When comparing the maximum allowable pulse phase jitter limit, control group 4 set the limit to 50 ns, with a sampling pulse phase deviation of 52.1 ns, 0 glitches in the parameter reconstruction process, a multi-channel sampling timing deviation of 4.80 μs, a full-temperature range measurement error of 0.410%, and a data jump rate of 0.95% under strong interference. The above data, together with the other sample groups, were used to compare the effects of phase alignment, parameter reconstruction state latching, and excitation output path latching control on the pulse synchronization state.

[0041] In the prototype of this invention, the multi-channel phase-locked frequency divider circuit receives the global synchronization reference clock and locks the rising edge of the hardware sampling trigger pulse to the global synchronization reference clock. During the parameter reconfiguration process, the MCU global configuration unit sends a status latch signal. During the excitation switching process, the switch array composed of multiple D flip-flops and transistors latches the channel switch control level and controls the excitation output path. The above control processes jointly block the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse, so that the hardware sampling trigger pulse under heterogeneous sampling rate maintains phase alignment and the phase synchronization of pulse generation is stable.

[0042] Example 3: During the operation of the hydraulic system of construction machinery, electromagnetic pulse interference and bus transmission delay fluctuations can cause phase jitter of multi-channel sampling pulses. The isolated bus communication unit receives the global synchronization reference clock sent by the master station. The multi-channel phase-locked frequency division circuit inside the SDA acquisition chip completes the phase-locked frequency division control. During the system initialization phase, the isolated bus communication unit continuously receives... The global synchronization reference clock of each cycle is used to extract the discrete sequence of phase delay, where The value is set to 1024; the variance and peak-to-peak envelope difference are calculated for the discrete phase delay sequence, and then weighted and summed according to a weight ratio of 0.6 to 0.4 to obtain the basic jitter. This is then combined with the pulse period corresponding to the highest sampling rate of the channel to determine the jitter. When the global synchronization reference clock frequency is 10MHz and the maximum sampling rate is 100kHz, the basic jitter is 3.2ns. Considering the cable delay drift caused by the full temperature range of -40℃ to 85℃ at the excavator operation site and the electromagnetic interference margin, the basic jitter is multiplied by an engineering safety factor of 2.5 to obtain... The pulse length is 8.0 ns. Based on this value, the multi-channel phase-locked loop frequency divider circuit adjusts the phase detector gain and loop filter time constant of the internal phase-locked loop to ensure that the rising edge deviation between the hardware sampling trigger pulse of each channel and the global synchronization reference clock remains within a certain range. Within the allowable range, if the value is below the upper limit, the system will misadjust normal transient noise; if the value is above the upper limit, the synchronous alignment accuracy requirements of multi-channel high-frequency sampling cannot be met.

[0043] When the hydraulic excavator's operating condition changes and triggers dynamic reconfiguration of specific channel parameters, the MCU global configuration unit responds to the channel configuration command and reconfigures hardware resources according to a preset discrete five-stage timing sequence. In the first stage, the MCU global configuration unit sends a status latch signal to the multi-channel phase-locked frequency divider circuit and the hardware preprocessing unit, freezing the current hardware operating state of the six channels and the pulse output state of the multi-channel phase-locked frequency divider circuit at the current level. In the second stage, it releases the port configuration bus of the programmable interface unit, the logic reconfiguration interface of the FPGA modulation unit, and the coefficient register of the dual DSP filtering unit. In the third stage, it writes the input range, sampling bit depth, sampling rate, and filter order parameters from the channel configuration command into the corresponding hardware configuration registers, maintaining the latched state during the write operation. In the fourth stage, it rewrites the PLA access logic of the programmable interface unit, the gain coefficient of the FPGA modulation unit, and the filter order of the dual DSP filtering unit. In the fifth stage, the state latch signal is canceled, the multi-channel phase-locked frequency divider circuit resumes operation, and relocks the phase within 3 global synchronization reference clock cycles, outputting an aligned hardware sampling trigger pulse. The entire reconstruction process takes 4.2μs, during which no high-frequency glitches or clock synchronization errors occur. For low-frequency sampling channels such as 10Hz, phase locking and alignment do not directly perform edge phase detection on the 100ms period low-frequency output pulse, but rather perform phase binding based on the 10MHz global synchronization reference clock for frequency division counting. At the end of the 4.2μs reconfiguration process, the MCU global configuration unit forces the frequency divider counter of the low-frequency channel to be loaded and aligned to the global phase reference value of the high-frequency main counter, so that the 10Hz sampling pulse is aligned with the main clock reference with zero phase deviation when the reconfiguration is released, without waiting for the signal edge of the complete low-frequency pulse cycle to arrive.

[0044] To address electromagnetic interference caused by sudden excitation signal changes during the switching between piezoelectric and strain sensors, the MCU global configuration unit, the excitation source within the isolated power supply module, and the switching array composed of multiple D flip-flops U3 to U8 and NPN transistors Q2 to Q7 work together. Upon receiving the excitation mode switching command, the MCU global configuration unit sends a shutdown control level to the switching array. The multiple D flip-flops U3 to U8 latch this level on the rising edge of the SDA bus clock line and drive the NPN transistors Q2 to Q7 to shut down the corresponding channel's excitation output path. Subsequently, a 50μs time-domain wait protection window is set. Within this protection window, the MCU global configuration unit sends mode and amplitude configuration information to the excitation source. The excitation source completes waveform mode switching and amplitude stabilization within 15μs. After the excitation source output stabilizes, the MCU global configuration unit sends an enable control level to the corresponding channel's D flip-flop via the SDA bus data and clock lines. The D flip-flop latches the enable level and drives the transistor to conduct the excitation output path, isolating the transient voltage and current surges generated by the excitation switching from the sampling pulse generation circuit. The 15-meter sensing transmission cable has an equivalent parasitic capacitance and inductive component of approximately 10 nanofarads. At the moment the excitation source is cut off, the time constant of the residual charge discharge circuit is measured to be 8μs. The 50μs time-domain wait protection window is greater than 5 times the time constant discharge period, and the residual transient voltage can decay to less than 1% of the initial value.

[0045] During the front-end acquisition process, multiple independent acquisition channel units synchronously perform analog-to-digital conversion on the input analog sensor signals to generate digital data. The digital data enters the hardware preprocessing unit for processing. At the instant of analog-to-digital conversion, the hardware pipeline obtains the 32-bit counter value of the global synchronization reference clock as a high-precision timestamp and writes the timestamp into the data frame header of the preprocessed data. Subsequently, it is uploaded to the master station via the isolated Ethernet bus. In response to network topology jitter caused by long-distance transmission, the master station receives digital data packets with high-precision timestamps and performs time axis realignment and phase interpolation correction on the multi-channel data according to the timestamps to compensate for the transmission delay deviation caused by asynchronous packet upload, so that the multimodal sensor signals remain synchronized during the front-end physical acquisition and back-end data parsing process.

[0046] Example 4: This example combines Figures 1 to 2 This paper describes a pulse synchronization control method for a multi-mode acquisition circuit, such as... Figure 1As shown, in step S1, the isolated bus communication unit receives the global synchronization reference clock sent by the master station. The multi-channel phase-locked frequency divider circuit inside the SDA acquisition chip receives the global synchronization reference clock, performs phase-locked frequency division according to the preset sampling rate parameters of each channel, and generates the hardware sampling trigger pulse of the corresponding channel. The hardware sampling trigger pulse of each channel is phase aligned with the global synchronization reference clock. In step S2, when the channel configuration command is received, the MCU global configuration unit of the SDA acquisition chip sends a status latch signal to freeze the current hardware working state of each channel and the pulse output state of the multi-channel phase-locked frequency divider circuit. In step S3, the MCU global configuration unit writes the channel parameters to the hardware configuration register, reconfigures the programmable interface unit, FPGA modulation unit and dual DSP filtering unit according to the preset pipeline timing, and sends the control level to the switch array composed of multiple D flip-flops through the SDA bus to drive the excitation output path of the corresponding channel. In step S4, when the reconfiguration is completed, the status latch signal is released, the multi-channel phase-locked frequency divider circuit resumes operation and relocks the phase, outputs the aligned hardware sampling trigger pulse, and blocks the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse.

[0047] like Figure 2 As shown, the multi-channel phase-locked frequency divider circuit receives the global synchronization reference clock to synchronously generate and output hardware sampling trigger pulses. The MCU global configuration unit sends status latch signals and writes parameters to the hardware configuration register. The multi-channel D flip-flops in the switch array receive control levels to drive the excitation output path. The multi-channel independent acquisition channel unit receives analog sensing signals through the programmable interface unit. The hardware preprocessing unit generates digital data packets containing high-precision timestamps under the action of the hardware error compensation module. The isolated power supply module drives the excitation source to output excitation signals through an independent isolated power supply.

[0048] Example 5: After the vehicle data acquisition slave station is powered on and initialized, the MCU global configuration unit retrieves the pre-calibrated two-dimensional surface compensation coefficient matrix from the hardware configuration register. The calibration of this coefficient matrix covers a temperature range of -40℃ to 85℃, with a temperature step of 15℃. The pressure calibration covers the full range from 0V to 40MPa, with a pressure step of 5MPa. During the calibration process, constant pressure and temperature excitation are applied to the pressure sensor, and the original 16-bit digital values ​​after analog-to-digital conversion at each calibration node are collected. The zero-point temperature drift compensation coefficient is obtained through binary polynomial fitting. With sensitivity temperature drift compensation coefficient The two compensation coefficients are written to the hardware configuration register. After the analog-to-digital conversion of the current sampling frame is completed, the hardware error compensation module reads the data. and The original digital quantity is weighted and subtracted in real time, and the gain is corrected. The corrected data is written to the on-chip data buffer register, so that the residual nonlinear error of the output correction data is kept within 0.03% in the full temperature range and full range window.

[0049] During the real-time correction process of two-dimensional surface compensation, the original 16-bit pressure digital value is subtracted sequentially from the product of the zero-point temperature drift compensation coefficient and the real-time temperature sampling value, and then divided by 1 and the sum of the product of the sensitivity temperature drift compensation coefficient and the real-time temperature sampling value to obtain the corrected true pressure value. For the pure pressure channel without temperature sensing capability, the second channel oil temperature thermocouple completes temperature sampling at the same synchronous clock edge, and routes the real-time temperature sampling value across channels to the on-chip input register of the third channel hardware error compensation module through the internal high-speed time-division reusable bus for real-time hardware correction of temperature and pressure coupling temperature drift.

[0050] Before the multi-channel phase-locked frequency divider circuit starts phase-locked control, the isolation bus communication unit captures 64 consecutive rising edges of the global synchronization reference clock. The MCU global configuration unit calculates the average duty cycle and phase jitter variance of the input reference clock and presets the jitter threshold value. Based on the statistical results of phase jitter variance obtained from 64 consecutive rising edges of the clock during the initialization phase, and combined with the high-frequency phase noise caused by motor start-stop, calibration was performed. When the phase jitter variance exceeds... At that time, the MCU global configuration unit adjusts the capacitor array switching switch of the internal loop filter of the multi-channel phase-locked frequency divider circuit, smoothly switching the loop filter time constant from 15μs to 45μs to suppress high-frequency phase noise caused by motor start-up and shutdown at the work site; subsequently, the six-channel phase-locked frequency divider circuit generates hardware sampling trigger pulses according to their respective preset sampling rate division coefficients, and when the rising edge of the first global synchronization reference clock arrives, the hardware pipeline clears the internal phase-locked counters of the six hardware sampling trigger pulses to zero and latches the phase, eliminating the fixed phase deviation between channels caused by hardware circuit wiring delay, so that the six channels enter the edge-aligned synchronous sampling state after initialization.

[0051] Example 6: Currently, multiple SDA acquisition slave stations are cascaded along the hydraulic excavator boom, stick, and undercarriage. The isolated bus communication unit receives the global synchronization reference clock from the master station. To compensate for the propagation delay introduced by the cascaded transmission cables, the first-end SDA acquisition chip sends round-trip delay measurement pulse frames to adjacent slave stations, capturing the transmission time. With the time of receiving response The propagation delay of a single-hop cable is calculated using the following formula: ,in, For single-hop cable propagation delay, For the time of transmission, To receive the response time, when the transmission cable length is 15 meters, the measurement was... 12.0ns When the ns value is 312.0 ns, substituting it into the formula yields: MCU Global Configuration Unit The phase compensation angle corresponding to the ratio of the global synchronization reference clock period is calculated, and the phase compensation angle used to compensate for propagation delay is written into the initial phase offset register of the corresponding channel's phase-locked loop divider circuit. Based on this, each slave station compensates for the propagation delay of the cascaded cable during the hardware sampling trigger pulse generation stage, so that the analog-to-digital conversion trigger pulses of each slave station are aligned to the same time reference.

[0052] When the isolated Ethernet bus experiences a global synchronization reference clock loss due to external electromagnetic pulse interference, the out-of-synchronization detection circuit inside the SDA acquisition chip captures the missing state for three consecutive clock cycles and triggers the frequency maintenance mode. The multi-channel phase-locked divider circuit maintains the digitally controlled oscillator control voltage at the moment before the out-of-synchronization, maintaining the hardware sampling trigger pulse self-excited oscillation output. After the global synchronization reference clock is restored, the phase detector completes phase relocking within two clock cycles and restores synchronization alignment with the master station clock. During the phase relocking process, the digital phase detector detects... Once the global synchronization reference clock is restored, the current initial count value of the phase accumulator is directly reset to the edge phase value of the restored reference clock, and the hardware fast lock preset for phase alignment is completed within 200 to 300 nanoseconds. The 15 to 45 microsecond time constant of the loop filter is used for low-pass smoothing filtering and fine frequency tracking after the preset is completed. The digital phase preset fast lock and smoothing loop filter work in sequence to enable the multi-channel phase-locked frequency divider circuit to complete phase alignment within 3 clock cycles and maintain low phase noise within the time scale of 15 to 45 microseconds.

[0053] During the parallel acquisition of sensor signals through six independent multimodal acquisition channels, a voltage-current window comparison circuit is connected to the input terminal of each channel. For the fifth channel, a 4mA to 20mA current-type oil level sensor, when the sensor cable is broken, causing the input current to... Below 2mA, or short circuit causing input current When it exceeds 22mA, among which To sample the real-time input current, the window comparator circuit outputs overcurrent and open-circuit abnormal levels. The MCU global configuration unit responds to this abnormal level and sends a shutdown control level to the D flip-flop U7 corresponding to the fifth channel within 5μs, driving the transistor Q6 to shut down the fifth channel excitation output path EXC5, blocking the impact of abnormal large current on the isolation power supply module. During this period, the MCU global configuration unit marks the fifth channel status register as faulty, while the multi-channel phase-locked frequency divider circuits of the first, second, third, fourth, and sixth channels continue to output hardware sampling trigger pulses and maintain phase locking. Each normal channel continues to perform analog-to-digital conversion and high-precision timestamp embedding.

[0054] The above description is only a few preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, technical solutions formed by replacing the above-mentioned features with, but not limited to, the technical features disclosed in the embodiments of the present invention that have similar functions.

Claims

1. A pulse synchronization control method for a multi-mode acquisition circuit, characterized in that, Includes the following steps: Step S1: The isolated bus communication unit receives the global synchronization reference clock sent by the master station; the multi-channel phase-locked frequency divider circuit inside the SDA acquisition chip receives the global synchronization reference clock, performs phase-locked frequency division according to the preset sampling rate parameters of each channel, and generates the hardware sampling trigger pulse of the corresponding channel. The hardware sampling trigger pulse of each channel takes the global synchronization reference clock as the phase alignment reference. Step S2: When the channel configuration instruction is received, the MCU global configuration unit of the SDA acquisition chip sends a status latch signal to freeze the current hardware working state of each channel and the pulse output state of the multi-channel phase-locked frequency divider circuit. Step S3: The MCU global configuration unit writes channel parameters to the hardware configuration register, reconfigures the programmable interface unit, FPGA modulation unit and dual DSP filtering unit according to the preset pipeline timing, and sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel. Step S4: When the reconfiguration is completed, the state latch signal is released, the multi-channel phase-locked frequency divider circuit resumes operation and relocks the phase, and outputs an aligned hardware sampling trigger pulse to block the phase interference of parameter reconfiguration and excitation switching on the hardware sampling trigger pulse.

2. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 1, characterized in that, Step S3, which involves reconfiguring the programmable interface unit, FPGA modulation unit, and dual DSP filtering unit according to a preset pipeline timing sequence, includes: Step S31, issuing register latch timing, freezing the hardware operating state of the current multi-channel independent acquisition unit, and synchronously releasing the port configuration resources of the programmable interface unit, the modulation logic resources of the FPGA modulation unit, and the filtering operation resources of the dual DSP filtering unit; Step S32, after completing the writing of channel parameters into the hardware configuration register, configuring the signal access mode of the programmable interface unit, the modulation gain of the FPGA modulation unit, and the filtering order of the dual DSP filtering unit according to a preset pipeline timing sequence, and recalibrating the division coefficients of the multi-channel phase-locked frequency divider circuit.

3. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 1, characterized in that, Step S3, which sends control levels to the switch array composed of multiple D flip-flops via the SDA bus to drive the excitation output path of the corresponding channel, includes: Step S33, the excitation generator inside the isolated power supply module receives the excitation configuration signal from the MCU global configuration unit and generates an excitation signal with a set waveform; Step S34, the MCU global configuration unit sends channel switch control levels to the switch array composed of multiple D flip-flops and transistors via the SDA bus, the multiple D flip-flops latch the channel switch control levels and drive the corresponding transistors to turn on or off, control the on / off of the excitation output path of each acquisition channel, and block the phase interference of the excitation switching pulse on the hardware sampling trigger pulse.

4. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 3, characterized in that, The excitation signal for generating the set waveform in step S33 includes: the excitation source inside the isolated power supply module switches between a sine wave excitation mode with a frequency of 0.1Hz to 10kHz and an amplitude of 0V to 10V, a constant voltage excitation mode of 0V to 10V, and a constant current excitation mode of 4mA to 20mA to generate the corresponding excitation signal.

5. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 1, characterized in that, After the hardware sampling trigger pulse is output in step S4, a hardware preprocessing pipeline synchronization step is also included. The hardware preprocessing pipeline synchronization step includes: step S41, under the edge triggering of the hardware sampling trigger pulse, the multi-channel independent acquisition channel unit synchronously performs analog-to-digital conversion on the input analog sensing signal to generate digital data; step S42, the digital data enters the hardware preprocessing unit in sequence, and under the control of a unified hardware synchronization clock, temperature and pressure coupled temperature drift correction and noise reduction calculations are performed in parallel according to the pipeline timing.

6. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 5, characterized in that, Step S42 includes temperature and pressure coupled temperature drift correction: digital data flows into the hardware error compensation module in the hardware preprocessing unit, and within the operating temperature range of -40℃ to 85℃, the digital data is corrected in real time by hardware based on a two-dimensional plane compensation algorithm or a two-dimensional curved surface compensation algorithm. The corrected data is then stored in the on-chip data cache register.

7. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 5, characterized in that, It also includes timestamp embedding and packet transmission steps, which include: Step S43, when the analog-to-digital conversion is completed, the hardware pipeline obtains the count value of the current global synchronization reference clock and embeds a unified high-precision timestamp in the data frame header of the preprocessed data; Step S44, the data with the embedded high-precision timestamp enters the independent data buffer of the corresponding channel, and according to the transmission bandwidth of the isolated bus communication unit, it is packaged into digital data packets according to the time-division reuse logic and uploaded to the master station via the isolated Ethernet bus.

8. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 1, characterized in that, The isolated power supply module has three built-in independent isolated power supplies that are electrically isolated from each other, providing independent isolated power supply to the sensing excitation circuit, the SDA acquisition chip core circuit, and the Ethernet bus circuit, respectively. Its isolation withstand voltage is not less than 2000V, blocking pulse interference generated by the motor and hydraulic system.

9. The pulse synchronization control method for a multi-mode acquisition circuit according to claim 1, characterized in that, The multi-channel independent acquisition unit synchronously acquires sensor signals of different signal types, including ±50mV small signals, 0V to 10V voltage signals, 4mA to 20mA current signals, ICP piezoelectric signals, thermocouple signals, and SPI or IIC digital signals. Under software reconfiguration and pulse synchronization control, the multi-channel independent acquisition unit can complete the pulse synchronous acquisition of multimodal sensor signals in parallel without changing the hardware circuit.

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