Charge pump module, phase locked loop circuit and control method

Abstract

The application discloses a charge pump module, a phase-locked loop circuit and a control method, wherein the charge pump module comprises a plurality of output nodes and a charge pump body, the charge pump body is provided with a pull-up current source and a pull-down current source, the pull-up current source and the pull-down current source are connected with the corresponding output nodes in communication according to the control of a control signal to output a current. In the charge pump module, the phase-locked loop circuit and the control method, the charge pump module can realize time-division multiplexing current output through different output nodes, on the premise of reserving the independent frequency modulation capability of the multi-path output clock and not deteriorating the output phase noise index, the multi-path phase-locked loop shares the same charge pump module and the matching current correction unit, the working efficiency of the charge pump is greatly improved, the chip integration is improved, and the overall power consumption is reduced.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a charge pump module, a phase-locked loop circuit, and a control method. Background Technology

[0002] As semiconductor manufacturing processes continue to evolve, various traditional discrete functional modules are being highly integrated onto a single chip, forming a System on Chip (SoC). The operating speeds of the various functional modules within the chip differ significantly, requiring different clock signal frequencies, and each module's clock source needs to be independently adjustable.

[0003] Taking an integrated radio frequency transceiver system-on-a-chip as an example: the chip integrates three types of radio frequency paths: transmit path (TX), receive path (RX), and local oscillator path (LO). All of these paths require a gigahertz (GHz) level high-frequency clock to drive them; the analog-to-digital converter (ADC) requires a megahertz (MHz) level clock; and the baseband processor operates in the hundred megahertz range.

[0004] A phase-locked loop (PLL) is a clock generation circuit that precisely multiplies a low-frequency reference clock to generate a high-frequency clock signal that meets the needs of each module. However, each PLL can only generate a single output frequency clock. Therefore, the mainstream design of SoC clock management systems in the industry is a one-to-one independent PLL architecture. That is, for each required high-frequency clock, a complete and independent PLL system is configured separately. Each independent PLL is equipped with a dedicated phase detector (PFD), charge pump (CP) and its pull-up and pull-down current correction circuits, loop filter, voltage-controlled oscillator, frequency divider, and other units. By having multiple PLLs work in parallel and independently, they output the clock signals required by each module.

[0005] The existing clock management architecture, which uses multiple independent PLLs, can achieve independent frequency modulation output of multiple clocks, but there is still significant room for optimization in terms of chip integration and system power consumption.

[0006] When each functional module is operating in steady state, the charge pump (CP) built into each PLL is in standby mode most of the time, only making minor adjustments to the back-end low-pass filter (LPF) near the rising edge of the reference clock. To suppress the parasitic charge injection effect caused by charge pump switching, the current consumption of the charge pump during standby is the same as that during normal operation, resulting in a large amount of ineffective static power consumption. In addition, to reduce the deterministic jitter of the PLL output clock, each PLL needs to be equipped with an independent real-time correction circuit for the charge pump pull-up and pull-down currents. This correction circuit runs continuously, further increasing the system power consumption.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide a charge pump module, a phase-locked loop circuit, and a control method that can achieve independent frequency modulation output of multiple clock channels.

[0009] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0010] A charge pump module includes: multiple output nodes; a charge pump body having a pull-up current source and a pull-down current source connected to the multiple output nodes, wherein the pull-up current source and the pull-down current source are connected to the corresponding output nodes according to the control of a control signal to output current.

[0011] In one or more embodiments of the present invention, the charge pump body further includes a current control unit for adjusting the magnitude of the pull-up current and / or pull-down current.

[0012] In one or more embodiments of the present invention, the charge pump module further includes a current correction unit connected to the charge pump body, which is used to generate a correction current and perform current correction on the charge pump body based on the correction current.

[0013] In one or more embodiments of the present invention, the current correction unit includes: a current generating unit connected to a pull-up current source for generating a correction current; and a conduction control unit connected to the current generating unit and the pull-down current source for controlling the on / off state between the current generating unit and the pull-down current source.

[0014] In one or more embodiments of the present invention, the conduction control unit includes a first switch and a second switch, the first end of the first switch is connected to a current generating unit and a pull-up current source, the second end of the first switch and the first end of the second switch are connected to the current generating unit, and the second end of the second switch is connected to a pull-down current source.

[0015] In one or more embodiments of the present invention, the current correction unit further includes a third switch, which is connected to the current generating unit and the pull-up current source to control the on / off state between the current generating unit and the pull-up current source based on its own on / off state.

[0016] A specific embodiment of the present invention also provides a phase-locked loop (PLL) system, including a PLL circuit and the aforementioned charge pump module. The PLL circuit includes: a first phase-frequency detector, which generates a first control signal based on the phase difference and / or frequency difference between the output signal of the PLL circuit and a reference signal; the charge pump module outputs current through a corresponding output node according to the control of the first control signal; a first loop filter, connected to the corresponding output node of the charge pump module to generate a first voltage signal based on the current output by the charge pump module; and a voltage-controlled oscillator (VCO), connected to the first loop filter to generate an output signal based on the first voltage signal.

[0017] In one or more embodiments of the present invention, the phase-locked loop circuit system further includes a delay phase-locked loop circuit, which is used to delay the reference signal to generate a reference signal for the phase-locked loop circuit.

[0018] In one or more embodiments of the present invention, the delay phase-locked loop circuit includes a second frequency-phase detector, a second loop filter, and a delay unit. The second frequency-phase detector generates a second control signal. The charge pump module also outputs current through a corresponding output node according to the control of the second control signal. The second loop filter is connected to the corresponding output node of the charge pump module to generate a second voltage signal VCTRL based on the current output by the charge pump module. The delay unit is connected to the second loop filter to delay the reference signal based on the control of the second voltage signal VCTRL to generate a reference signal and a delayed output signal. The second frequency-phase detector also adjusts the second control signal based on the phase difference and / or frequency difference between the delayed output signal and the reference signal.

[0019] A specific embodiment of the present invention also provides a control method for a phase-locked loop (PLL) system. Based on the above-described PLL system, the control method includes: before phase locking of all PLL circuits, turning off the current correction unit for current correction of the charge pump body; after phase locking of all PLL circuits, turning on the current correction unit for current correction of the charge pump body; and / or, the control method includes: adjusting the magnitude of the pull-up current and / or the magnitude of the pull-down current based on the phase difference between the output signal and the reference signal of the PLL circuit.

[0020] Compared with existing technologies, the charge pump module, phase-locked loop circuit, and control method of this invention enable the charge pump module to achieve time-division multiplexed current output through different output nodes. While retaining the independent frequency modulation capability of multiple output clocks and without deteriorating the output phase noise performance, multiple phase-locked loops share the same charge pump module and its associated current correction unit, significantly improving the efficiency of the charge pump. Compared with existing independent frequency modulation technology for multiple clocks, redundant charge pumps and corresponding correction circuits are eliminated, effectively improving chip integration and reducing overall power consumption. Simultaneously, this invention proposes a frequency locking stage control strategy suitable for this shared architecture, addressing the technical defect that time-division multiplexing architectures easily lead to longer locking times. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit diagram of a charge pump module in the prior art.

[0023] Figure 2 This is a structural diagram of a phase-locked loop system in the prior art.

[0024] Figure 3 This is a partial circuit diagram of a phase-locked loop system in one embodiment of the present invention.

[0025] Figure 4 This is a partial circuit diagram of a phase-locked loop system in one embodiment of the present invention.

[0026] Figure 5 This is a signal waveform diagram of a phase-locked loop system in one embodiment of the present invention.

[0027] Figure 6 This is another signal waveform diagram of a phase-locked loop system in one embodiment of the present invention.

[0028] Figure 7 This is another signal waveform diagram of a phase-locked loop system in one embodiment of the present invention.

[0029] Figure 8 This is another signal waveform diagram of a phase-locked loop system in one embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0031] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0032] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0033] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0034] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0035] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0036] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0037] Example 1

[0038] like Figure 1 As shown, a charge pump module in one embodiment of the present invention includes multiple output nodes (P1, P2...Pn), a charge pump body 11, and a current correction unit 12.

[0039] The charge pump body 11 has pull-up current sources and pull-down current sources connected to multiple output nodes (P1, P2...Pn). The pull-up current sources and pull-down current sources are connected to the corresponding output nodes according to the control signal to output current (ICP1, ICP2...ICPn). The current correction unit 12 is connected to the charge pump body 11 and is used to generate a correction current I_cp_up_calibrate and perform current correction on the charge pump body 11 based on the correction current I_cp_up_calibrate.

[0040] The charge pump module can achieve time-division multiplexing of current output through different output nodes. Thus, in the application of phase-locked loops, while retaining the independent frequency modulation capability of multiple output clocks and without deteriorating the output phase noise index, multiple phase-locked loops can share the same charge pump body 11 and its matching current correction unit 12, which greatly improves the working efficiency of the charge pump.

[0041] For example, the charge pump body 11 also includes a switching unit, which is connected to multiple output nodes, pull-up current sources and pull-down current sources. The switching unit controls the connection and disconnection between the pull-up current source and the corresponding output node according to the control signal, and controls the connection and disconnection between the pull-down current source and the corresponding output node according to the control signal.

[0042] Specifically, the switching unit includes multiple switching sub-units, namely switching sub-units 1111 to 111n, which are correspondingly set with output nodes (P1, P2…Pn). Taking switching sub-unit 1111 as an example, it includes a fourth switch S41 and a fifth switch S51. The first terminal of the fourth switch S41 is connected to the pull-up current source, and the second terminal is connected to the corresponding output node P1. The fourth switch S41 controls the connection and disconnection between the pull-up current source and the corresponding output node P1 according to the control signal UP1. The first terminal of the fifth switch S51 is connected to the pull-down current source, and the second terminal is connected to the corresponding output node P1. The fifth switch S51 controls the connection and disconnection between the pull-down current source and the corresponding output node P1 according to the control signal DN1.

[0043] In one embodiment, both the fourth switch S41 and the fifth switch S51 are controlled by a high level to turn on and a low level to turn off.

[0044] The structure and control method of the remaining switch subunits are the same as those of switch subunit 1111, with only the connected output nodes and the received control signals being adaptively adjusted.

[0045] For example, the pull-up current source includes a first transistor PM2, and the pull-down current source includes a second transistor NM3. The charge pump body 11 also includes a first bias unit connected to the first transistor PM2 and the second transistor NM3. The first bias unit is used to provide bias voltage for the pull-up current source and the pull-down current source. The first bias unit includes a first bias current source IB1, a third transistor NM1, a fourth transistor NM2, and a fifth transistor PM1.

[0046] In this configuration, the first terminal of the first bias current source IB1 is connected to the power supply voltage, the second terminal of the first bias current source IB1 is connected to the second terminal of the third transistor NM1, the control terminal of the third transistor NM1, and the control terminal of the fourth transistor NM2, the first terminal of the fifth transistor PM1 is connected to the power supply voltage, the control terminal of the fifth transistor PM1 and the second terminal of the fifth transistor PM1 are connected to the second terminal of the fourth transistor NM2, and the first terminal of the fourth transistor NM2 is connected to the ground voltage.

[0047] The first terminal of the first transistor PM2 is connected to the power supply voltage, the second terminal of the first transistor PM2 is connected to the first terminal of the fourth switch, and the control terminal of the first transistor PM2 is connected to the control terminal of the fifth transistor PM1.

[0048] The first terminal of the second transistor NM3 is connected to ground voltage, the second terminal of the second transistor NM3 is connected to the first terminal of the fifth switch, and the control terminal of the second transistor NM3 is connected to the control terminal of the fourth transistor NM2.

[0049] In one embodiment, the charge pump body 11 may further include a current control unit 112, which is used to adjust the magnitude of the pull-up current and the pull-down current.

[0050] Specifically, the current control unit 112 includes multiple sixth transistors (NM1a, NM1b, NM1c…) and sixth switches (S6a, S6b, S6c…) corresponding to each sixth transistor. The first terminal of each sixth transistor is connected to ground, the second terminal of each sixth transistor is connected to the first terminal of the corresponding sixth switch, the control terminal of each sixth transistor is connected to the control terminal of the fourth transistor NM2, and the second terminal of each sixth switch is connected to the second terminal of the first bias current source IB1. By selecting the sixth transistor to connect to the bias branch through the sixth switch, the current on the fourth transistor NM2 can be adjusted, thereby simultaneously adjusting the pull-up current and pull-down current.

[0051] In one embodiment, the charge pump body 11 further includes a current control unit 113, which is used to adjust the magnitude of the pull-up current.

[0052] Specifically, the current control unit 113 includes a seventh transistor PM3 and a seventh switch S7 corresponding to the seventh transistor PM3. The first terminal of the seventh transistor PM3 is connected to the power supply voltage, the second terminal of the seventh transistor PM3 is connected to the first terminal of the seventh switch S7, the control terminal of the seventh transistor PM3 is connected to the control terminal of the first transistor PM2, and the second terminal of the seventh switch S7 is connected to the second terminal of the first transistor PM2. When the seventh switch S7 is closed, the seventh transistor PM3 is connected to the pull-up current branch, which increases the magnitude of the pull-up current. Of course, multiple sets of seventh transistors PM3 can also be correspondingly provided.

[0053] In other embodiments, the charge pump body 11 may also include a current control unit for adjusting the magnitude of the pull-down current. In this case, a circuit structure similar to the current control unit 113 is adopted, and one or more transistors are set in parallel with the two ends of the second transistor NM3 and connected to the control terminal. The on and off of these transistors can be controlled by a switch.

[0054] like Figure 1 As shown, the current correction unit 12 includes a current generation unit, a conduction control unit 121, and a third switch S3.

[0055] The first terminal of the third switch S3 is connected to the current generating unit, and the second terminal of the third switch S3 is connected to the second terminal of the first transistor PM2. The third switch controls the on / off state between the current generating unit and the second terminal of the first transistor PM2 based on its own on / off state. The current generating unit is used to generate a calibration current I_cp_up_calibrate. The conduction control unit 121 is connected to the current generating unit and the second terminal of the second transistor NM3, and is used to control the on / off state between the current generating unit and the second terminal of the second transistor NM3.

[0056] Furthermore, the current generating unit includes a first amplifier and a first capacitor C3. The first input terminal of the first amplifier is connected to the conduction control unit 121, the second input terminal of the first amplifier is connected to the reference voltage VCM, and the output terminal of the first amplifier is connected to the first terminal of the third switch S3 to generate a correction current I_cp_up_calibrate. The first terminal of the first capacitor C3 is connected to the first input terminal of the first amplifier, and the second terminal of the first capacitor C3 is connected to the output terminal of the first amplifier.

[0057] Furthermore, the first amplifier has a bias stage, a first amplification stage, and a second amplification stage, with the bias stage providing a bias voltage to the first and second amplification stages.

[0058] For example, the bias stage of the first amplifier includes an eighth transistor PM4 and a ninth transistor NM4. The first terminal of the eighth transistor PM4 is connected to the power supply voltage, the second terminals of the eighth transistor PM4 and the ninth transistor NM4 are connected to the control terminal of the ninth transistor NM4, the first terminal of the ninth transistor NM4 is connected to ground, and the control terminal of the eighth transistor PM4 receives the bias voltage. For example, the control terminal of the eighth transistor PM4 is connected to the control terminal of the first transistor PM2.

[0059] The first amplification stage of the first amplifier includes the tenth transistor PM5, the eleventh transistor PM6, the twelfth transistor NM7, the thirteenth transistor NM8, and the fourteenth transistor NM5.

[0060] The first terminal of the tenth transistor PM5 and the first terminal of the eleventh transistor PM6 are connected to the power supply voltage. The control terminals of the tenth transistor PM5 and the eleventh transistor PM6 are connected to the second terminal of the twelfth transistor NM7. The second terminal of the eleventh transistor PM6 is connected to the second terminal of the thirteenth transistor NM8 and serves as the output terminal of the first amplification stage of the first amplifier. The control terminal of the twelfth transistor NM7 is used as the first input terminal of the first amplifier, and the control terminal of the thirteenth transistor NM8 is used as the second input terminal of the first amplifier. The first terminals of the twelfth transistor NM7 and the thirteenth transistor NM8 are connected to the second terminal of the fourteenth transistor NM5. The first terminal of the fourteenth transistor NM5 is connected to ground, and the control terminal of the fourteenth transistor NM5 receives the bias voltage. For example, the control terminal of the fourteenth transistor NM5 is connected to the control terminal of the ninth transistor NM4.

[0061] The second amplification stage of the first amplifier includes a fifteenth transistor PM7, a sixteenth transistor NM6, and a second capacitor Ccmp1. The first terminal of the fifteenth transistor PM7 is connected to the power supply voltage. The second terminal of the fifteenth transistor PM7, the first terminal of the second capacitor Ccmp1, and the second terminal of the sixteenth transistor NM6 are connected to the first terminal of a third switch to generate a correction current I_cp_up_calibrate, which serves as the output terminal of the first amplifier. The control terminal of the fifteenth transistor PM7 and the second terminal of the second capacitor Ccmp1 are connected to the second terminal of the eleventh transistor PM6. The first terminal of the sixteenth transistor NM6 is connected to ground. The control terminal of the sixteenth transistor NM6 is used to receive a bias voltage; exemplarily, the control terminal of the sixteenth transistor NM6 is connected to the control terminal of the fourteenth transistor NM5.

[0062] In other embodiments, the first amplifier may also be other amplifier circuit structures.

[0063] like Figure 1 As shown, the conduction control unit 121 includes a first switch S1 and a second switch S2. The first end of the first switch S1 is connected to the second end of the third switch S3. The second ends of the first switch S1 and the first ends of the second switch S2 are connected to the control terminal of the twelfth transistor NM7. The second end of the second switch S2 is connected to the second end of the second transistor NM3.

[0064] In one embodiment, the first switch S1 is turned on or off according to the control signal UP_B, and the second switch S2 is turned on or off according to the control signal DN_B. Both the first switch S1 and the second switch S2 are controlled by a high level to turn on and a low level to turn off.

[0065] In this embodiment, all transistors are MOS transistors. The transistor numbered PM is a P-channel MOS transistor, and the transistor numbered NM is an N-channel MOS transistor. The first terminal of each transistor refers to its source, the second terminal refers to its drain, and the control terminal refers to its gate.

[0066] In other embodiments, the P / N type of each transistor can be changed, and each transistor can be replaced with other devices, with the connection method adjusted accordingly.

[0067] The charge pump module of this embodiment can be applied to a multi-output phase-locked loop system. Its working principle is briefly introduced below.

[0068] The charge pump body 11 is similar in working principle to existing charge pumps. The frequency and phase detector in the front stage of the charge pump module generates a control signal based on the frequency and phase difference between the phase-locked loop output signal and the reference signal. This control signal is generally a pulse near the rising edge of the reference signal. At this time, the switch in the switching subunit is closed under control, and the charge pump outputs current. Since it is a multi-output circuit, the front-stage frequency and phase detector generates multiple control signals, each controlling a switching subunit. Generally, these control signal pulses do not overlap, so that the charge pump module outputs current through only one output node at any given time.

[0069] When the charge pump body 11 charges and discharges the subsequent circuit, the first switch S1 and the second switch S2 are open, and the correction current I_cp_up_calibrate generated by the current correction unit 12 can supplement the pull-up current. When the charge pump body 11 stops charging and discharging the subsequent circuit, the first switch S1 and the second switch S2 are closed, short-circuiting the pull-up and pull-down currents of the charge pump body 11, automatically switching into the current self-calibration mode, and using the idle window of the charge pump module to complete the pull-up and pull-down current matching calibration in real time.

[0070] If there is a mismatch between the pull-up current source and the pull-down current source, the output node potential will deviate from the common-mode reference voltage VCM. In correction mode, the first amplifier, relying on its virtual short characteristic, forces the potential of its first input terminal to equal the reference voltage VCM. Through a negative feedback loop, it dynamically adjusts the correction current I_cp_up_calibrate to replenish the current difference in the entire pull-up branch in real time. When the total pull-up and pull-down currents reach a perfect match, the potential of the first input terminal of the op-amp is stably clamped to the reference voltage VCM, thereby eliminating the deterministic jitter caused by the current mismatch of the charge pump 10. Simultaneously, this correction loop is a continuously conducting negative feedback closed loop, which can track the minute current drift induced by 1 / f low-frequency noise in real time and dynamically adjust the correction current I_cp_up_calibrate, synchronously suppressing the periodic clock jitter caused by low-frequency noise.

[0071] Finally, the current control unit also provides the function of adjusting the pull-up current and pull-down current, which can customize different output currents for different output nodes.

[0072] Example 2

[0073] like Figure 2 As shown, this embodiment provides a phase-locked loop system, including a phase-locked loop circuit, a delay phase-locked loop circuit, and a charge pump module 10 as described in Embodiment 1.

[0074] Multiple phase-locked loop (PLL) circuits can be configured to meet multi-frequency output requirements. For example, five PLL circuits are configured, namely PLL circuits 21 to 25.

[0075] The delay phase-locked loop circuit is used to delay the reference signal to generate reference signals CKFB_PLL1~CKFB_PLL5 for phase-locked loop circuits 21~25.

[0076] Specifically, the delay phase-locked loop circuit includes a second frequency and phase detector 31, a second loop filter 32, and a delay unit 33. The second frequency and phase detector 31 generates a second control signal UP6 and a second control signal DN6. The charge pump module 10 also outputs a current ICP_DLL through the corresponding output node P6 according to the control of the second control signal UP6 and the second control signal DN6. Figure 1 As shown, the fourth switch S46 in the switch subunit 1116 is controlled by the second control signal UP6, and the fifth switch S56 is controlled by the second control signal DN6.

[0077] The second loop filter 32 is connected to the corresponding output node P6 of the charge pump module 10 to generate a second voltage signal VCTRL based on the current ICP_DLL output by the charge pump module 10. The delay unit 33 is connected to the second loop filter 32 to delay the reference signal CKREF based on the control of the second voltage signal VCTRL to generate reference signals CKREF_PLL1 to CKREF_PLL5 and a delayed output signal CKREF_OUT. The second frequency and phase detector 31 also adjusts the second control signal UP6 and the second control signal DN6 based on the phase difference and frequency difference between the delayed output signal CKREF_OUT and the reference signal CKREF.

[0078] like Figure 2 As shown, taking the phase-locked loop circuit 21 as an example, the phase-locked loop circuit 21 includes a first frequency and phase detector 211, a first loop filter 212, and a voltage-controlled oscillator 213.

[0079] Specifically, the first phase-frequency discriminator 211 generates a first control signal UP1 and a first control signal DN1 based on the phase difference and frequency difference between the output signal of the phase-locked loop circuit 21 and the reference signal CKREF_PLL1. The charge pump module 10 outputs current ICP1_PPL1 through the corresponding output node P1 according to the control of the first control signal UP1 and the first control signal DN1.

[0080] The first loop filter 212 is connected to the corresponding output node P1 of the charge pump module 10 to generate a first voltage signal based on the current ICP1_PPL1 output by the charge pump module 10. The voltage-controlled oscillator 213 is connected to the first loop filter 212 to generate an output signal CKFB_PLL1 based on the first voltage signal.

[0081] In one embodiment, the phase-locked loop circuit 21 may further include a frequency divider 214, which is used to divide the voltage-controlled oscillator 213 to generate a frequency-divided signal. The first frequency and phase detector 211 can generate a first control signal UP1 and a first control signal DN1 based on the frequency-divided signal.

[0082] Combination Figure 1 As shown, the fourth switch S41 in the switch subunit 1111 is controlled by the first control signal UP1, and the fifth switch S51 is controlled by the first control signal DN1.

[0083] like Figure 3 As shown, the first loop filter 212 includes a second amplifier and a filter unit 2121. The first input terminal of the second amplifier is connected to the output node P1 of the charge pump module 10, and the second input terminal of the second amplifier is connected to the reference voltage VCM. The filter unit 2121 is connected to the first input terminal and the output terminal of the second amplifier.

[0084] The filter unit 2121 includes a first resistor R1, a third capacitor C1 and a fourth capacitor C2. The first end of the third capacitor C1 and the first end of the fourth capacitor C2 are connected to the first input terminal of the second amplifier. The second end of the third capacitor C1 is connected to the first end of the first resistor R1. The second end of the fourth capacitor C2 and the second end of the first resistor R1 are connected to the output terminal of the second amplifier.

[0085] like Figure 3 As shown, the second amplifier has a bias stage, a first amplification stage, and a second amplification stage.

[0086] For example, the bias stage of the second amplifier includes a second bias current source IB2 and a seventeenth transistor NM9. The first terminal of the second bias current source IB2 is connected to the power supply voltage, the second terminal of the second bias current source IB2 is connected to the second terminal of the seventeenth transistor NM9 and the control terminal of the seventeenth transistor NM9, and the first terminal of the seventeenth transistor NM9 is connected to ground.

[0087] The first amplification stage of the second amplifier includes the eighteenth transistor PM8, the nineteenth transistor PM9, the twentieth transistor NM12, the twenty-first transistor NM13, and the twenty-second transistor NM10.

[0088] The first terminal of the eighteenth transistor PM8 and the first terminal of the nineteenth transistor PM9 are connected to the power supply voltage. The control terminals of the eighteenth transistor PM8 and the nineteenth transistor PM9 are connected to the second terminal of the eighteenth transistor PM8. The second terminal of the nineteenth transistor PM9 is connected to the second terminal of the twenty-first transistor NM13 and serves as the output terminal of the first amplification stage of the second amplifier. The second terminal of the twentieth transistor NM12 is connected to the second terminal of the eighteenth transistor PM8. The first terminals of the twentieth transistor NM12 and the twenty-second transistor NM10 are connected to the second terminal of the twenty-second transistor NM10. The first terminal of the twenty-second transistor NM10 is connected to the ground voltage.

[0089] The control terminal of the twentieth transistor NM12 is used as the first input terminal of the second amplifier, the control terminal of the twenty-first transistor NM13 is used as the second input terminal of the second amplifier, and the control terminal of the twenty-second transistor NM10 is connected to the control terminal of the seventeenth transistor NM9 to receive the bias voltage.

[0090] The second amplification stage of the second amplifier includes a fifth capacitor Ccmp2, ​​a twenty-third transistor PM10, and a twenty-fourth transistor NM11. The first terminal of the twenty-third transistor PM10 is connected to the power supply voltage. The control terminal of the twenty-third transistor PM10, the first terminal of the fifth capacitor Ccmp2, ​​and the second terminal of the nineteenth transistor PM9 are connected. The second terminals of the twenty-third transistor PM10 and the second terminal of the fifth capacitor Ccmp2 are connected to the second terminal of the twenty-fourth transistor NM11 and serve as the output terminal of the second amplifier. The first terminal of the twenty-fourth transistor NM11 is connected to ground. The control terminal of the twenty-fourth transistor NM11 is connected to the control terminal of the seventeenth transistor NM9 to receive the bias voltage.

[0091] The fifth capacitor, Ccmp2, ​​serves as a phase correction device for the local feedback loop of the second amplification stage, ensuring the closed-loop stability of the second operational amplifier.

[0092] When the first loop filter 212 is working, relying on the virtual short characteristic of the operational amplifier, the output node P1 potential will be forcibly clamped to the reference voltage VCM. The first resistor R1, the third capacitor C1, and the fourth capacitor C2 in the filter unit 2121 together form a second-order filter correction network for the PLL loop.

[0093] like Figure 3 As shown, the voltage-controlled oscillator 213 includes a twenty-fifth transistor PM11, a twenty-sixth transistor PM12, a twenty-seventh transistor NM15, a twenty-eighth transistor NM16, a twenty-ninth transistor NM14, an inductor L, a sixth capacitor Cvar1, and a seventh capacitor Cvar2.

[0094] Specifically, the first terminal of the 25th transistor PM11 and the first terminal of the 26th transistor PM12 are connected to the power supply voltage. The second terminal of the 25th transistor PM11 and the second terminal of the 27th transistor NM15 are connected to the first terminal of the inductor and serve as the first output terminal of the voltage-controlled oscillator 213. The second terminal of the 26th transistor PM12 and the second terminal of the 28th transistor NM16 are connected to the second terminal of the inductor and serve as the second output terminal of the voltage-controlled oscillator 213. The control terminal of the 25th transistor PM11 and the control terminal of the 27th transistor NM15 are connected to the second terminal of the inductor, and the control terminal of the 26th transistor PM12 and the control terminal of the 28th transistor NM16 are connected to the first terminal of the inductor.

[0095] The first terminal of the twenty-seventh transistor NM15 and the first terminal of the twenty-eighth transistor NM16 are connected to the second terminal of the twenty-ninth transistor NM14. The first terminal of the twenty-ninth transistor NM14 is connected to ground voltage. The control terminal of the twenty-ninth transistor NM14 is connected to the control terminal of the seventeenth transistor NM9 to receive bias voltage.

[0096] The first terminal of the sixth capacitor Cvar1 is connected to the first terminal of the inductor, the first terminal of the seventh capacitor Cvar2 is connected to the second terminal of the inductor, and the second terminals of the sixth capacitor Cvar1 and the seventh capacitor Cvar2 are connected to the second terminal of the twenty-fourth transistor NM11.

[0097] Among them, the sixth capacitor Cvar1 and the seventh capacitor Cvar2 are variable capacitors. By adjusting the voltage of the lower plate of the variable capacitor, the equivalent capacitance of the LC resonant circuit is changed, and the oscillation frequency can be continuously adjusted.

[0098] The first frequency and phase detector 211, the second frequency and phase detector 31, and the frequency divider 214 can all be products of the existing technology.

[0099] The structure of phase-locked loop circuits 22 to 25 is the same as that of phase-locked loop circuit 21. The only difference is that the output nodes connected to the charge pump module 10 are adjusted to output nodes P2 to P5 respectively, and the required reference signals are reference signals CKREF_PLL2 to CKREF_PLL5 respectively.

[0100] For ease of description, the corresponding labels for each component and signal in phase-locked loop circuits 22 to 25 are as follows: first frequency and phase detectors 21 to 51, first loop filters 22 to 52, voltage-controlled oscillators 23 to 53, output signals and reference signals CKREF_PLL2 to CKREF_PLL5, first control signals UP2 to UP5, first control signals DN2 to DN5, output currents ICP1_PPL2 to ICP1_PPL5, and output signals CKFB_PLL2 to CKFB_PLL5.

[0101] It is understood that in other embodiments, other numbers of phase-locked loop circuits can also be set, and the number of devices such as output nodes, switching sub-units, and voltage-controlled inverters can be adjusted accordingly.

[0102] like Figure 4 As shown, the second loop filter 32 includes a third amplifier and a second filter unit 321. The first input terminal of the third amplifier is connected to the output node P6 of the charge pump module 10, and the second input terminal of the third amplifier is connected to the reference voltage VCM. The second filter unit 321 is connected to the first input terminal and the output terminal of the third amplifier.

[0103] The second filter unit 321 includes an eighth capacitor C4. The first end of the eighth capacitor C4 is connected to the first input terminal of the third amplifier, and the second end of the eighth capacitor C4 is connected to the output terminal of the third amplifier.

[0104] like Figure 4 As shown, the third amplifier has a bias stage, a first amplification stage, and a second amplification stage.

[0105] For example, the bias stage of the third amplifier includes a third bias current source IB3 and a thirtieth transistor NM17. The first terminal of the third bias current source IB3 is connected to the power supply voltage, the second terminal of the third bias current source IB3 is connected to the second terminal of the thirtieth transistor NM17 and the control terminal of the thirtieth transistor NM17, and the first terminal of the thirtieth transistor NM17 is connected to the ground voltage.

[0106] The first amplification stage of the third amplifier includes transistors PM13 (31st), PM14 (32nd), NM20 (33rd), NM21 (34th), and NM18 (35th).

[0107] The first terminal of transistor PM13 (31st) and the first terminal of transistor PM14 (32nd) are connected to the power supply voltage. The control terminals of transistors PM13 and PM14 are connected to the second terminal of transistor PM13. The second terminal of transistor PM14 is connected to the second terminal of transistor NM21 (34th) and serves as the output terminal of the first amplification stage of the third amplifier. The second terminal of transistor NM20 (33rd) is connected to the second terminal of transistor PM13 (31st). The first terminal of transistor NM20 (33rd) and the first terminal of transistor NM18 (35th) are connected to the second terminal of transistor NM18. The first terminal of transistor NM18 (35th) is connected to ground.

[0108] The control terminal of the thirty-third transistor NM20 is used as the first input terminal of the third amplifier, the control terminal of the thirty-fourth transistor NM21 is used as the second input terminal of the third amplifier, and the control terminal of the thirty-fifth transistor NM18 is connected to the control terminal of the thirtieth transistor NM17 to receive the bias voltage.

[0109] The second amplification stage of the third amplifier includes a ninth capacitor Ccmp3, a thirty-sixth transistor PM15, and a thirty-seventh transistor NM19. The first terminal of the thirty-sixth transistor PM15 is connected to the power supply voltage. The control terminal of the thirty-sixth transistor PM15, the first terminal of the ninth capacitor Ccmp3, and the second terminal of the thirty-second transistor PM14 are connected. The second terminals of the thirty-sixth transistor PM15 and the second terminal of the ninth capacitor Ccmp3 are connected to the second terminal of the thirty-seventh transistor NM19 and serve as the output terminal of the third amplifier. The first terminal of the thirty-seventh transistor NM19 is connected to ground. The control terminal of the thirty-seventh transistor NM19 is connected to the control terminal of the thirtieth transistor NM17 to receive the bias voltage.

[0110] The ninth capacitor, Ccmp3, serves as a phase correction device for the local feedback loop of the second amplification stage, ensuring the closed-loop stability of the second operational amplifier.

[0111] In a delay-locked loop (PLL) circuit, loop correction can be achieved using only a single, small eighth capacitor, C4 (3pF). Because the stability constraints of the delay loop are more relaxed, there is no need to configure a complex second-order correction network, further reducing the chip area occupied by the circuit.

[0112] In this embodiment, all transistors are MOS transistors. The transistor numbered PM is a P-channel MOS transistor, and the transistor numbered NM is an N-channel MOS transistor. The first terminal of each transistor refers to its source, the second terminal refers to its drain, and the control terminal refers to its gate.

[0113] In other embodiments, the P / N type of each transistor can be changed, and each transistor can be replaced with other devices, with the connection method adjusted accordingly.

[0114] like Figure 4 As shown, the delay unit 33 includes multiple voltage-controlled inverters connected in series. The input terminal of the first voltage-controlled inverter is used to receive the reference signal CKREF. The control terminal of the voltage-controlled inverter is connected to the second terminal of the thirty-sixth transistor PM15 to receive the second voltage signal VCTRL. Based on the control of the second voltage signal VCTRL, the voltage-controlled inverter inverts and delays the reference signal CKREF to generate reference signals CKREF_PLL1 to CKREF_PLL5 and a delayed output signal CKREF_OUT.

[0115] Specifically, there are 12 voltage-controlled inverters. The second inverter outputs the reference signal CKREF_PLL1, the fourth inverter outputs the reference signal CKREF_PLL2, the sixth inverter outputs the reference signal CKREF_PLL3, the eighth inverter outputs the reference signal CKREF_PLL4, the tenth inverter outputs the reference signal CKREF_PLL5, and the tenth inverter outputs the delayed output signal CKREF_OUT. Each voltage-controlled inverter has the same delay time under the same second voltage signal VCTRL.

[0116] In other embodiments, the delay phase-locked loop circuit may not be provided. Instead, other circuit modules can generate various reference signals and ensure that the reference signals required by each phase-locked loop circuit have a phase difference, so as to ensure that the charge pump module 10 does not output multiple currents at the same time.

[0117] This embodiment also provides a control method for a phase-locked loop (PLL) system. Based on the PLL system described in any of the above embodiments, the control method includes: generating a first control signal using a first phase-frequency detector based on the phase difference and frequency difference between the output signal of the PLL circuit and a reference signal; outputting current through a corresponding output node using a charge pump module 10 according to the control of the first control signal; generating a first voltage signal using a first loop filter and the charge pump module 10 based on the current output by the charge pump module 10 at the corresponding output node; and generating an output signal using a voltage-controlled oscillator (VCO) based on the first voltage signal.

[0118] Furthermore, the control method also includes: using a delay phase-locked loop circuit to delay the reference signal to generate a reference signal for the phase-locked loop circuit.

[0119] Specifically, this includes: generating a second control signal via the second frequency and phase detector 31; outputting current through the corresponding output node P6 via the charge pump module 10 according to the control of the second control signal; generating a second voltage signal VCTRL via the second loop filter 32 based on the current output by the charge pump module 10 at the corresponding output node P6; delaying the reference signal CKREF via the delay unit 33 based on the control of the second voltage signal VCTRL to generate a reference signal and a delayed output signal CKREF_OUT; and adjusting the second control signal via the second frequency and phase detector 31 based on the phase difference and frequency difference between the delayed output signal CKREF_OUT and the reference signal CKREF.

[0120] Combination Figure 5 As shown, the delay phase-locked loop circuit delays the reference signal CKREF to generate 5 reference signals: CKREF_PLL1 to CKREF_PLL5, which are used as reference signals for phase-locked loop circuits 21 to 25, respectively.

[0121] Preferably, the delay time between each adjacent reference signal is the same. Further, the reference signal CKREF and the reference signals CKREF_PLL1 to CKREF_PLL5 form an equally spaced delay chain with a delay time of T / (N+1), where T is the period of the reference signal CKREF and N is the number of phase-locked loop circuits.

[0122] Combination Figure 1 , Figure 6 As shown, for example, both the first and second frequency-phase detectors 31 are triggered by rising edges, meaning that the pulses of each first and second control signal are near the rising edge of the corresponding reference signal / reference signal. Simultaneously, there is a phase difference between the reference signal CKREF and the reference signals CKREF_PLL1 to CKREF_PLL5. Therefore, we can divide the timing of the charge pump module 10 based on the phase sequence of each signal:

[0123] From the rising edge of the reference signal CKREF to the rising edge of the reference signal CKREF_PLL1, only the switch subunit 1116 corresponding to the output node P6 is enabled, and the charge pump module 10 charges and discharges the second loop filter 32; from the rising edge of the reference signal CKREF_PLL1 to the rising edge of the reference signal CKREF_PLL2, only the switch subunit 1111 corresponding to the output node P1 is enabled, and the charge pump module 10 charges and discharges the first loop filter 11 of the phase-locked loop circuit 21; from the rising edge of the reference signal CKREF_PLL2 to the rising edge of the reference signal CKREF_PLL3, only the switch subunit 1112 corresponding to the output node P2 is enabled, and the charge pump module 10 charges and discharges the first loop filter of the phase-locked loop circuit 22; reference From the rising edge of signal CKREF_PLL3 to the rising edge of reference signal CKREF_PLL4, only the switch subunit 1113 corresponding to output node P3 is enabled, and the charge pump module 10 charges and discharges the first loop filter of phase-locked loop circuit 23; from the rising edge of reference signal CKREF_PLL4 to the rising edge of reference signal CKREF_PLL5, only the switch subunit 1114 corresponding to output node P4 is enabled, and the charge pump module 10 charges and discharges the first loop filter of phase-locked loop circuit 24; from the rising edge of reference signal CKREF_PLL5 to the rising edge of reference signal CKREF, only the switch subunit 1115 corresponding to output node P5 is enabled, and the charge pump module 10 charges and discharges the first loop filter of phase-locked loop circuit 25.

[0124] Within each period of the reference signal CKREF, the charge pump module sequentially drives the delay circuit and the five phase-locked loops in a 10-minute time division, enabling a single charge pump module to serve all clock generation loops in a 10-minute time division. In steady state, the six charge pump current pulses ICP1_PPL1 to ICP_DLL are completely separated in the time domain, with no overlapping conduction intervals. The pull-up and pull-down current sources are connected to the output node in a time division via a switching subunit. At any given time, only a single loop filter is connected to the charge pump. The control voltages of each loop are isolated from each other, there is no signal crosstalk between the multiple phase-locked loops, and the frequency and phase of each output clock remain completely independent.

[0125] This solution generates a multi-phase reference signal by adding a delay circuit. However, the delay circuit only implements a fixed delay, eliminating the need for wideband locking logic of the phase-locked loop (PLL). The control logic is simple, the loop correction requirements are lenient, and the accompanying capacitor size is much smaller than the loop filter of the PLL, resulting in extremely low hardware area overhead. In contrast, the traditional five-channel independent PLL solution requires each PLL to be configured with an independent charge pump and correction circuit. This solution retains only one charge pump module, eliminating four sets of redundant hardware, significantly reducing chip area, and simultaneously eliminating the static and dynamic power consumption generated by the continuous operation of the four charge pumps, significantly reducing the total system power consumption.

[0126] The maximum operating speed of the charge pump module 10 is constrained by the minimum output pulse width of each frequency and phase detector; for example, the minimum pulse width limit is approximately 200 ps. The maximum operating frequency of the charge pump module 10 is increased to six times that of the reference signal CKREF. Taking the 48 MHz reference signal CKREF as an example, after time-division multiplexing, the maximum operating frequency of the charge pump module 10 is 288 MHz, and the duration of each drive pulse is still much greater than the 200 ps limit pulse width. The circuit timing margin is sufficient, and the performance of the charge pump is not affected by the multiplexing mechanism.

[0127] This embodiment also provides a control method for a phase-locked loop system. Based on the phase-locked loop system described in any of the above embodiments, the control method includes: before the phase of all phase-locked loop circuits is locked, turning off the current correction unit 12 for the current correction of the charge pump body 11; and after the phase of all phase-locked loop circuits is locked, turning on the current correction unit 12 for the current correction of the charge pump body 11.

[0128] Specifically, turning off the third switch S3 disables the current correction unit 12 for the charge pump body 11, while turning on the third switch S3 enables the current correction unit 12 for the charge pump body 11.

[0129] It should be noted that after current correction is enabled, the on / off state of the first switch S1 is opposite to that of the enabled fourth switch, and the on / off state of the second switch S2 is opposite to that of the enabled fifth switch. For example, from the rising edge of the reference signal CKREF to the rising edge of the reference signal CKREF_PLL1, only the fourth switch S46 and the fifth switch S56 are enabled. In this case, the on / off state of the first switch S1 is opposite to that of the fourth switch S46, and the on / off state of the second switch S2 is opposite to that of the fifth switch S56. That is, during the non-idle time slot of the charge pump, the current correction unit 12 corrects the pull-up current, and during the idle time slot of the charge pump, the current correction unit 12 corrects the pull-down current.

[0130] The current correction loop is only enabled after the delay unit and all phase-locked loop circuits have completed locking. This fully utilizes the idle time slots of the charge pump during each reference clock cycle to continuously calibrate the pull-up and pull-down currents, reducing the deterministic periodic jitter of the output clock caused by current mismatch and low-frequency current noise from the charge pump. During the frequency acquisition phase when the loop is not locked, the current correction loop remains off, using the uncalibrated raw charging and discharging current to charge and discharge each loop filter. This is because during the output frequency acquisition phase, the output clock frequency is continuously and dynamically adjusted, and small current mismatches will not significantly degrade circuit performance. However, during the output frequency acquisition process, the charge pump needs to continuously alternate charging and discharging, and the effective sampling time slots that can be allocated to the correction path are extremely narrow. Enabling self-calibration prematurely can easily cause abnormal adjustment and instability of the correction loop.

[0131] Combination Figure 1 As shown, in one embodiment, the switching state of the seventh switch S7 is the opposite of that of the third switch S3. When the loop is unlocked, the entire pull-up current is provided by the first transistor PM2 and the seventh transistor PM3. For example, the reference current ICP of the charge pump is designed to be 20uA, of which the first transistor PM2 provides 15uA and the seventh transistor PM3 provides 5uA. After the loop is locked, the 5uA current originally provided by the seventh transistor PM3 is supplemented by the current correction unit 12.

[0132] This embodiment also provides a control method for a phase-locked loop system. Based on the phase-locked loop system described in any of the above embodiments, the control method includes: adjusting the magnitude of the pull-up current and the magnitude of the pull-down current based on the phase difference between the output signal and the reference signal of the phase-locked loop circuit.

[0133] For a traditional independent phase-locked loop (PLL) architecture, the loop filter can perform charging and discharging operations within the complete reference signal cycle. The total charge injected into the loop filter by the charge pump within a single reference clock cycle (Tref) is: In the formula, Icp is the charge pump current, and the phase error is continuously variable, ranging from 0 to 360°.

[0134] This invention employs a time-division multiplexing architecture, requiring the time-division driving of six loop filters within the same reference signal period Tref. The maximum charge / discharge time of a single loop filter is only Tref / 6, corresponding to a charge injection amount within a single period of [missing information]. .

[0135] Without adding a current multiplication mechanism, the charge injected in a single cycle under the same phase error is only 1 / 6 of that of the traditional scheme, and the loop lock-in time will be extended to six times the original, which cannot meet the system timing requirements.

[0136] Specifically, when the phase difference between the output signal and the reference signal of the phase-locked loop (PLL) increases, the pull-up and pull-down currents for the next output to the PLL are increased; conversely, when the phase difference between the output signal and the reference signal decreases, the pull-up and pull-down currents for the next output to the PLL are decreased. This can specifically improve the locking speed of the PLL.

[0137] Combination Figure 7 As shown, in one embodiment, the phase difference interval is divided by the edge of the reference signal CKREF and the edges of the reference signals CKREF_PLL1~CKREF_PLL5, and the phase difference interval is matched with the adjustment coefficient. The pull-up current and pull-down current are adjusted according to the adjustment coefficient corresponding to the phase difference interval in which the output signal of the phase-locked loop circuit is located.

[0138] For example, the phase difference intervals are divided here with the rising edge as the boundary. It can be seen that each phase difference interval is 60° wide, and there are 6 intervals in one cycle. The adjusted current is the reference current multiplied by the adjustment coefficient. The matching relationship between the phase difference and the adjustment coefficient is as follows:

[0139] When the phase difference is between 0° and 60°, the adjustment coefficient is 1, and the pull-up and pull-down currents at the next output are equal to the single reference current of 20uA.

[0140] When the phase difference is between 60° and 120°, the adjustment coefficient is 2, and the pull-up current and pull-down current at the next output are double the reference current of 40uA.

[0141] When the phase difference is between 120° and 180°, the adjustment coefficient is 3, and the pull-up and pull-down currents at the next output are three times the reference current of 60uA.

[0142] When the phase difference is between 180° and 240°, the adjustment coefficient is 4, and the pull-up and pull-down currents at the next output are four times the reference current of 80uA.

[0143] When the phase difference is between 240° and 300°, the adjustment coefficient is 5, and the pull-up and pull-down currents at the next output are five times the reference current of 100uA.

[0144] When the phase difference is between 300° and 360°, the adjustment coefficient is 6, and the pull-up current and pull-down current at the next output are six times the reference current of 120uA.

[0145] Combination Figure 1 As shown, in one embodiment, the width-to-length ratios of the various sixth transistors are different. By selecting the sixth transistor connected to the circuit through the sixth switch, the pull-up current and pull-down current can be adjusted.

[0146] Specifically, there are five groups of sixth transistors and sixth switches. The width-to-length ratio of the fourth transistor NM2 to the third transistor NM1, the sixth transistors NM1a, NM1b, NM1c, NM1d, and NM1e is 1:1:1:2:3:4:5. The magnitude of the first bias current source IB1 is six times the reference current.

[0147] When the phase difference is between 0° and 60°, the sixth switch S6e is turned on; when the phase difference is between 120° and 180°, the sixth switch S6d is turned on; when the phase difference is between 120° and 180°, the sixth switch S6c is turned on; when the phase difference is between 180° and 240°, the sixth switch S6b is turned on; when the phase difference is between 240° and 300°, the sixth switch S6a is turned on; when the phase difference is between 300° and 360°, all the sixth switches are turned off, thus achieving the aforementioned current multiplication effect.

[0148] Combination Figure 8 As shown, for example, during the frequency tracking of the five phase-locked loop circuits, phase-locked loop circuit 25 has completed locking, so ICP1_PPL5 = 20uA (single); the phase difference of phase-locked loop circuit 24 is less than 60°, so it is considered to be close to completing locking, so ICP1_PPL4 = 20uA; phase-locked loop circuits 21~3, according to their respective phase error ranges, correspondingly double the pull-up / pull-down current for the next reference clock cycle.

[0149] In summary, this solution uses only one set of charge pump body 11 and a single set of current correction circuits for all phase-locked loop (PLL) and delay PLL circuits, eliminating the need for four sets of redundant charge pumps and correction hardware. Furthermore, the delay circuit used for time-sharing scheduling requires only a small-area capacitor for correction, resulting in minimal additional circuit area overhead. When expanding the system to include new PLL channels, only one set of selection switches needs to be added, without requiring an additional current source, thus meeting the high integration requirements of SoC development.

[0150] In the existing architecture, the charge pumps of each phase-locked loop (PLL) are in a standby state for extended periods during steady-state operation, with the standby current matching the operating current. This, coupled with the continuous operation of multiple independent correction circuits, consumes significant static power. This invention uses time-division multiplexing to increase the effective operating time slot of a single charge pump several times, eliminating redundant static power consumption caused by multiple charge pumps operating synchronously in standby mode. Furthermore, multiple channels share a single real-time current correction circuit, saving the continuous energy consumption generated by the long-term operation of multiple correction circuits. This significantly optimizes the power consumption of the overall clock management module, making it more suitable for low-power terminal design requirements.

[0151] All phase-locked loop circuits, delay phase-locked loop circuits, and current correction circuits share the same reference voltage VCM. When the charge pump switches between the six channels, there is no significant voltage jump at the output node, which greatly reduces the clock deterministic period jitter introduced by the channel switching action. The entire architecture can achieve multi-channel sharing without sacrificing phase noise performance.

[0152] This invention enables current self-calibration after all loops are fully locked, and utilizes idle periods to match pull-up and pull-down charging and discharging currents in real time, suppressing clock deterministic jitter caused by pull-up and pull-down current mismatch and low-frequency noise.

[0153] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0154] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A charge pump module, characterized in that, include: Multiple output nodes; The charge pump body has pull-up current sources and pull-down current sources connected to multiple output nodes. The pull-up current sources and pull-down current sources are connected to the corresponding output nodes according to the control signal to output current.

2. The charge pump module according to claim 1, characterized in that, The charge pump body also includes a current control unit, which is used to adjust the magnitude of the pull-up current and / or pull-down current.

3. The charge pump module according to claim 1, characterized in that, The charge pump module also includes a current correction unit, which is connected to the charge pump body and is used to generate a correction current and perform current correction on the charge pump body based on the correction current.

4. The charge pump module according to claim 3, characterized in that, The current correction unit includes: The current generation unit is connected to the pull-up current source and is used to generate a correction current; The conduction control unit is connected to the current generating unit and the pull-down current source, and is used to control the on / off state between the current generating unit and the pull-down current source.

5. The charge pump module according to claim 4, characterized in that, The conduction control unit includes a first switch and a second switch. The first end of the first switch is connected to the current generating unit and the pull-up current source. The second end of the first switch and the first end of the second switch are connected to the current generating unit. The second end of the second switch is connected to the pull-down current source.

6. The charge pump module according to claim 4, characterized in that, The current correction unit also includes a third switch, which is connected to the current generating unit and the pull-up current source to control the on / off state between the current generating unit and the pull-up current source based on its own on / off state.

7. A phase-locked loop system, comprising a phase-locked loop circuit and a charge pump module as described in any one of claims 1 to 6, characterized in that, The phase-locked loop circuit includes: The first frequency and phase detector generates a first control signal based on the phase difference and / or frequency difference between the output signal of the phase-locked loop circuit and the reference signal; the charge pump module outputs current through the corresponding output node according to the control of the first control signal. The first loop filter is connected to the corresponding output node of the charge pump module to generate a first voltage signal based on the current output by the charge pump module. A voltage-controlled oscillator is connected to a first loop filter to generate an output signal based on a first voltage signal.

8. The phase-locked loop system according to claim 7, characterized in that, The phase-locked loop circuit system also includes a delay phase-locked loop circuit, which is used to delay the reference signal to generate a reference signal for the phase-locked loop circuit.

9. The phase-locked loop system according to claim 8, characterized in that, The delay phase-locked loop circuit includes a second frequency-phase detector, a second loop filter, and a delay unit. The second frequency-phase detector generates a second control signal. The charge pump module also outputs current through a corresponding output node according to the control of the second control signal. The second loop filter is connected to the corresponding output node of the charge pump module to generate a second voltage signal based on the current output by the charge pump module. The delay unit is connected to the second loop filter to delay the reference signal based on the control of the second voltage signal to generate a reference signal and a delayed output signal. The second frequency-phase detector also adjusts the second control signal based on the phase difference and / or frequency difference between the delayed output signal and the reference signal.

10. A control method for a phase-locked loop system, based on the phase-locked loop system according to any one of claims 7 to 9, characterized in that, The control method includes: before phase locking of all phase-locked loop circuits, disabling current correction of the charge pump body by the current correction unit; after phase locking of all phase-locked loop circuits, enabling current correction of the charge pump body by the current correction unit; and / or, The control method includes: adjusting the magnitude of the pull-up current and / or the pull-down current based on the phase difference between the output signal and the reference signal of the phase-locked loop circuit.

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