A phase-locked loop adaptive control method and system

Abstract

The application discloses a phase-locked loop adaptive control method and system, and relates to the technical field of clock synchronization, which comprises the following steps: obtaining state evaluation parameters corresponding to a target phase-locked loop, wherein the state evaluation parameters comprise a phase error change rate; determining a bandwidth adjustment strategy according to the state evaluation parameters when the target phase-locked loop is in a tracking mode; and performing tracking control on the target phase-locked loop through the bandwidth adjustment strategy. It can be seen that the application can more accurately identify the dynamic change of the tracking bandwidth required by the phase error change rate to realize accurate dynamic adjustment of the bandwidth, can reduce the time required for locking, can improve the tracking performance, can reduce the phase noise, can reduce the output clock jitter, can improve the long-term stability, and thus can realize effective balance between the tracking performance and noise suppression.

Description

Technical Field

[0001] This application relates to the field of clock synchronization technology, specifically to a phase-locked loop adaptive control method and system. Background Technology

[0002] Digital phase-locked loop (DPLL) and other PLL designs are fundamental and critical technologies in the clock field, and their performance directly affects the synchronization accuracy and stability of communication networks. Among them, traditional PLL architectures such as... Figure 1 As shown, its core components include a PFD (Phase Frequency Detector), a DLF (Digital Loop Filter), a DCO (Digitally Controlled Oscillator), and a frequency divider (such as...). Figure 1 (e.g., / M, / N).

[0003] In related technologies, PLLs typically use loop filters with fixed bandwidth; however, fixed bandwidth has inherent contradictions: when the bandwidth is large, the PLL has a fast tracking speed and strong acquisition capability, but weak noise suppression capability, resulting in large output clock jitter; when the bandwidth is small, the noise suppression capability is strong and the output clock is stable, but the tracking speed is slow and it is difficult to adapt to rapid changes in the input source.

[0004] It is evident that achieving an effective balance between tracking performance and noise suppression is a pressing issue that needs to be addressed. Summary of the Invention

[0005] This application provides a phase-locked loop adaptive control method and system, which can solve the technical problem of imbalance between tracking performance and noise suppression caused by using fixed bandwidth to implement phase-locked loop control in the prior art.

[0006] In a first aspect, embodiments of this application provide a phase-locked loop adaptive control method, including: Obtain the state evaluation parameters corresponding to the target phase-locked loop, wherein the state evaluation parameters include the phase error change rate; When the target phase-locked loop is in tracking mode, a bandwidth adjustment strategy is determined based on the state evaluation parameters; The target phase-locked loop is tracked and controlled using the bandwidth adjustment strategy described above.

[0007] In conjunction with the first aspect, in one implementation, determining the bandwidth adjustment strategy based on the state assessment parameters includes: The bandwidth adjustment strategy is determined based on the target difference between the rates of change of two adjacent phase errors.

[0008] In conjunction with the first aspect, in one implementation, the state evaluation parameters further include frequency stability and input source state information. After the step of obtaining the state evaluation parameters corresponding to the target phase-locked loop, the method further includes: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

[0009] In conjunction with the first aspect, in one embodiment, the method further includes: In the hold mode, historical frequency information prior to the loss of the input source is acquired; The historical frequency information is smoothed and filtered to obtain the target frequency information; The target frequency information is used as the control input for the target phase-locked loop.

[0010] In conjunction with the first aspect, in one embodiment, the method further includes: The frequency offset and phase difference between the input clock and the reference clock are determined based on first-in-first-out (FIFO) technology. Frequency stability is determined based on the frequency deviation. The phase error change rate is determined based on the phase difference.

[0011] In conjunction with the first aspect, in one embodiment, prior to the step of determining frequency stability based on the frequency deviation, the method further includes: The target temperature change is predicted based on the target environment information corresponding to the target crystal oscillator. The target environment information includes the real-time temperature of the target crystal oscillator, the duration of operation, the target location, and the historical temperature information corresponding to the target location. The temperature drift compensation value is determined based on the target temperature change and the preset crystal oscillator temperature characteristic curve. The frequency deviation is corrected by the temperature drift compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

[0012] In conjunction with the first aspect, in one embodiment, prior to the step of determining frequency stability based on the frequency deviation, the method further includes: Obtain the cumulative operating time corresponding to the target crystal oscillator; The aging compensation value is determined based on the cumulative working time. The frequency deviation is corrected by the aging compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

[0013] Secondly, embodiments of this application provide a phase-locked loop adaptive control system, comprising: A status monitoring module is used to acquire status evaluation parameters corresponding to the target phase-locked loop, the status evaluation parameters including the phase error change rate; An adaptive control module is used to determine a bandwidth adjustment strategy based on the state evaluation parameters when the target phase-locked loop is in tracking mode; and to perform tracking control on the target phase-locked loop through the bandwidth adjustment strategy.

[0014] In conjunction with the second aspect, in one implementation, the adaptive control module is specifically used for: The bandwidth adjustment strategy is determined based on the relationship between the target difference between two adjacent phase error change rates and the preset change rate difference threshold.

[0015] In conjunction with the second aspect, in one implementation, the state evaluation parameters further include frequency stability and input source state information, and the adaptive control module is specifically used for: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

[0016] In conjunction with the second aspect, in one implementation, the adaptive control module is further configured to: In the hold mode, historical frequency information prior to the loss of the input source is acquired; The historical frequency information is smoothed and filtered to obtain the target frequency information; The target frequency information is used as the control input for the target phase-locked loop.

[0017] In conjunction with the second aspect, in one implementation, the status monitoring module is further configured to: The frequency offset and phase difference between the input clock and the reference clock are determined based on first-in-first-out (FIFO) technology. Frequency stability is determined based on the frequency deviation. The phase error change rate is determined based on the phase difference.

[0018] In conjunction with the second aspect, in one embodiment, the phase-locked loop adaptive control system further includes an environmental monitoring module and a frequency calibration module. The environmental monitoring module is used to predict the target temperature change based on the target environmental information corresponding to the target crystal oscillator. The target environmental information includes the real-time temperature of the target crystal oscillator, its operating time and its target location, and historical temperature information corresponding to the target location. The frequency calibration module is used to determine the temperature drift compensation value based on the target temperature change and the preset crystal oscillator temperature characteristic curve; the frequency deviation is corrected by the temperature drift compensation value to obtain the target frequency deviation, and the status monitoring module performs the step of determining the frequency stability based on the frequency deviation based on the target frequency deviation.

[0019] In conjunction with the second aspect, in one embodiment, the environmental monitoring module is further configured to acquire the cumulative operating time corresponding to the target crystal oscillator; the frequency calibration module is further configured to determine an aging compensation value based on the cumulative operating time; the frequency deviation is corrected by the aging compensation value to obtain the target frequency deviation, and the status monitoring module is configured to perform the step of determining the frequency stability based on the frequency deviation based on the target frequency deviation.

[0020] The beneficial effects of the technical solutions provided in this application include at least the following: The system acquires state evaluation parameters corresponding to the target phase-locked loop, including the phase error change rate. The phase error change rate reflects the rate or trend of change of the phase error between the PLL input and output. A large phase error change rate indicates that the output has not yet tracked the input source, requiring the loop to track quickly. Conversely, a small phase error change rate indicates that the output has already tracked the input source, necessitating noise suppression. When the target PLL is in tracking mode, a bandwidth adjustment strategy is determined based on the state evaluation parameters, and tracking control is applied accordingly. Specifically, the bandwidth is automatically increased for rapid acquisition when the phase error change rate is large, and decreased to suppress noise when the phase error change rate is small, resolving the contradiction that a fixed bandwidth cannot simultaneously address both aspects. Therefore, this application uses the phase error change rate to evaluate the PLL tracking state, enabling more accurate identification of dynamic changes in the required tracking bandwidth. This allows for precise dynamic bandwidth adjustment, reducing the locking time, improving tracking performance, reducing phase noise, decreasing output clock jitter, and improving long-term stability, thus achieving an effective balance between tracking performance and noise suppression. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a traditional PLL architecture; Figure 2 This is a flowchart illustrating an embodiment of the phase-locked loop adaptive control method of this application; Figure 3 This is a schematic diagram of the optimized PLL architecture with adaptive loop filter function involved in the embodiments of this application; Figure 4 This is a schematic diagram of the phase-locked loop bandwidth adjustment process involved in the embodiments of this application; Figure 5 This is a schematic diagram of the input source status and phase frequency offset detection involved in the embodiment of this application. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0024] In a first aspect, embodiments of this application provide a phase-locked loop adaptive control method.

[0025] In one embodiment, reference is made to Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the phase-locked loop adaptive control method of this application. Figure 2 As shown, the phase-locked loop adaptive control method includes: Step S10: Obtain the state evaluation parameters corresponding to the target phase-locked loop, wherein the state evaluation parameters include the phase error change rate.

[0026] As an example, it should be noted that the target phase-locked loop can be a digital phase-locked loop or other types of phase-locked loops, which are not limited here; in this embodiment, the phase error change rate refers to how quickly the phase error in the target phase-locked loop changes with time, which reflects the input clock (e.g., Figure 3 (Ref_in) and output clock (i.e. Figure 3 The rate or trend of phase difference change between the feedback clock (Freq_out) and the feedback clock (Freq_out) is considered. It's understandable that a large rate of phase error change implies a need for large bandwidth for tracking, while a small rate of phase error change implies a focus on noise suppression, in which case large bandwidth is unnecessary. Based on this, see [link to relevant documentation]. Figure 3 As shown, this embodiment can use a status monitoring module to detect phase error and obtain status evaluation parameters, including the rate of change of phase error, thereby providing a data basis for subsequent precise dynamic adjustment of bandwidth.

[0027] Step S20: When the target phase-locked loop is in tracking mode, determine the bandwidth adjustment strategy based on the state evaluation parameters.

[0028] As an example, in this embodiment, when the target phase-locked loop is in tracking mode, the state evaluation engine assesses the tracking status of the phase-locked loop by the phase error change rate, so as to more accurately identify the dynamic changes in the bandwidth required for tracking, thereby achieving precise dynamic adjustment of the bandwidth through the bandwidth optimizer. If the phase error change rate is large, it means that the output has not yet tracked the input source and the loop needs to track it quickly. At this time, the bandwidth optimizer automatically increases the bandwidth to quickly capture it. If the phase error change rate is small, it means that the output has tracked the input source. At this time, it is necessary to focus on suppressing noise. Therefore, the bandwidth optimizer will reduce the bandwidth to suppress noise, which can solve the contradiction that a fixed bandwidth cannot take both into account.

[0029] Further, in one embodiment, determining the bandwidth adjustment strategy based on the state evaluation parameters includes: The bandwidth adjustment strategy is determined based on the target difference between the rates of change of two adjacent phase errors.

[0030] As an example, in this embodiment, the difference between the rates of change of two adjacent phase errors within a certain time window (i.e., the target difference) can more accurately reflect the dynamic changes in the phase-locked loop tracking state. Based on this, when the target difference is positive, it means that the rate of change of phase error is increasing further. At this time, increasing the bandwidth can be used as a bandwidth adjustment strategy to quickly capture the target. When the target difference is negative, it means that the rate of change of phase error is decreasing. At this time, decreasing the bandwidth can be used as a bandwidth adjustment strategy to suppress noise. When the target difference is 0 or close to 0, it indicates that the rate of change of phase error is stabilizing. At this time, the bandwidth can be adjusted according to the desired parameters of the target phase-locked loop to balance tracking performance and noise suppression.

[0031] It should be understood that, for a loop filter, the circuit equation of a second-order proportional-integral circuit (i.e., the transfer function of a second-order loop filter) is:

[0032] In the formula, Indicates the loop bandwidth. This is the proportional path gain coefficient of the loop filter. This represents the gain coefficient of the integrating path of the loop filter. This represents the Laplace transfer factor.

[0033] It should be noted that the most commonly used parameters for a second-order PLL are the natural frequency and the damping coefficient; the natural frequency is also called the undamped natural frequency. The unit is rad / s, and the damping coefficient is The calculation relationship between the two is as follows:

[0034]

[0035] In the formula, It is the gain coefficient of PFD. It is the gain coefficient of the voltage-controlled oscillator (VCO); where, for a second-order type-II PLL, the loop gain is... for:

[0036] It should be understood that the above formula represents the open-loop gain generated by the proportional path, and a second-order PLL loop has only one parameter. That's not enough; a second parameter is needed, such as the damping coefficient. To control stability; in this case, any two parameters in a second-order PLL loop can be expressed using the other two parameters, and the commonly used formulas are as follows:

[0037] It should be noted that the commonly used filter bandwidth is generally expressed in 3dB bandwidth. Therefore, the low-pass response 3dB bandwidth of a second-order class 2 PLL is... It can be expressed by the following formula:

[0038] The above analysis reveals three main parameters for a loop filter: loop bandwidth, damping coefficient, and gain parameter. Loop bandwidth determines the loop's response speed to the input signal and its noise suppression capability (i.e., wider bandwidth results in faster response but weaker noise suppression, and vice versa). The damping coefficient affects loop stability; a larger damping coefficient leads to a more stable output but a slower loop response, while a smaller damping coefficient results in a faster response but a tendency for output oscillation. The gain parameter (i.e., proportional gain and integral gain) directly affects the loop's dynamic characteristics and must be designed to meet performance specifications. Therefore, in scenarios where the input source changes dynamically, this embodiment can reduce... The damping coefficient is adjusted to prioritize a fast response, and can be dynamically adjusted based on the phase-locked loop response after the input source stabilizes. and The value is used to dynamically change the PLL bandwidth to achieve a balance between noise and response speed.

[0039] Therefore, when the target difference is positive, i.e., the rate of change of phase error increases, the damping coefficient can be reduced. The value is used as a bandwidth adjustment strategy to increase bandwidth, thereby enabling faster capture; among them, the damping coefficient and The amount of reduction in the value can be determined according to actual needs, such as reducing the damping coefficient to 1. Alternatively, it can be determined by combining the preset target difference with the reduction in the damping coefficient. The mapping relationship between the decrease in value is determined, and this mapping relationship can be determined through experimental calibration. When the target difference is negative, that is, when the rate of change of phase error decreases, the damping coefficient can be increased and the value decreased. As a bandwidth adjustment strategy, the goal is to reduce bandwidth, thereby reducing output noise; similarly, the increase in damping coefficient and... The amount of reduction in the value can be determined according to actual needs, such as increasing the damping coefficient to 4. Of course, it can also be determined by combining the preset target difference with the increase in the damping coefficient. The mapping relationship between the decrease in value is determined, and this mapping relationship can be determined through experimental calibration.

[0040] When the target difference is 0 or approaches 0, meaning the phase error rate of change tends to stabilize, the proportional path gain coefficient can be adjusted according to the preset upper limit of loop gain (e.g., <0.2dB), the preset expected value of damping coefficient (e.g., 5), and the upper limit of loop bandwidth (e.g., ITU-T G.813 requires the PLL bandwidth to be below 10Hz). and / or proportional path gain coefficient Adjustments are made as a bandwidth adjustment strategy, i.e., the adjusted bandwidth. and The corresponding loop gain needs to meet the upper limit requirement of the loop gain, the damping coefficient needs to meet the expected value requirement of the damping coefficient, and the loop bandwidth needs to meet the upper limit requirement of the loop bandwidth.

[0041] Step S30: Track and control the target phase-locked loop using the bandwidth adjustment strategy.

[0042] In this exemplary embodiment, after determining the bandwidth adjustment strategy, the parameter update controller directly and smoothly adjusts the bandwidth parameters of the DLF in the target PLL through the bandwidth adjustment strategy to achieve tracking control of the target PLL. It can be seen that this embodiment achieves dynamic bandwidth adjustment through the phase error change rate, which not only reduces the locking time and improves tracking performance, but also reduces phase noise, reduces output clock jitter, and improves long-term stability, thereby achieving an effective balance between tracking performance and noise suppression.

[0043] Furthermore, in one embodiment, the state evaluation parameters further include frequency stability and input source state information. After the step of obtaining the state evaluation parameters corresponding to the target phase-locked loop, the method further includes: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

[0044] As an example, it should be noted that frequency stability refers to the ability of an oscillator (such as a crystal oscillator or phase-locked loop output) to maintain a stable output frequency within a specified time. Input source status information includes whether the input source is lost or not; based on this, see [link to relevant documentation]. Figure 4 As shown, in this embodiment, when performing adaptive control of the target phase-locked loop, the input source status is first monitored (specifically, a first-in-first-out FIFO can be used to monitor the presence or absence of the input source). If no input source is detected (i.e., the input source is lost), the target phase-locked loop is controlled to enter the HOLD state (i.e., hold mode), and the stored historical frequency information (such as frequency offset) is read as the control input for the subsequent target phase-locked loop, and the hold smoothing filter module is enabled. If an input source is detected (i.e., the input source is not lost), the target phase-locked loop is controlled to enter the tracking mode. At this time, the initial loop bandwidth can be preset to f / 100 and the initial damping coefficient can be taken as 2 according to the frequency value f of the input source, and the second-order proportional-integral low-pass filter is implemented in this way. and The initial values ​​are preset, and the phase error and frequency offset error changes are continuously detected in real time.

[0045] Specifically, if the frequency stability is determined to be poor based on the frequency offset error change, the division ratio can be adjusted until the frequency stability tends to be stable. After the frequency stability tends to be stable, the phase error change rate is determined based on the phase error change, and the magnitude of the phase error change rate determines whether to continue in tracking mode or enter locked mode (i.e., the PLL remains locked, meaning the DLF maintains the current bandwidth). If the phase error change rate is less than or equal to a preset phase error change rate threshold (the specific value can be determined according to actual needs and is not limited here), it indicates that the phase error change is small and no bandwidth adjustment is needed. In this case, locked mode is entered, and the frequency offset and phase values ​​are stored in a sliding manner. If the phase error change rate is greater than the phase error change rate threshold, it indicates that the phase error change is large and bandwidth adjustment is needed. In this case, tracking mode is continued, and the bandwidth is dynamically adjusted based on the difference between two adjacent phase error change rates as described above to update the second-order proportional-integral low-pass filter. and Value. See also Figure 4 As shown, it should be noted that in order to avoid the problem of poor stability caused by frequent bandwidth adjustments, the damping coefficient and the bandwidth of the DLF are only updated and dynamically adjusted when the rate of change of the phase error differs by 2 times or more between two adjacent changes.

[0046] Furthermore, in one embodiment, the method further includes: In the hold mode, historical frequency information prior to the loss of the input source is acquired; The historical frequency information is smoothed and filtered to obtain the target frequency information; The target frequency information is used as the control input for the target phase-locked loop.

[0047] In this exemplary embodiment, for scenarios such as stable system operation, reference clock loss, and the need for low jitter output, after acquiring historical frequency information before the input source loss in hold mode, the hold smoothing filter module is activated. That is, the hold smoothing filter module smooths and filters the historical frequency information to obtain the target frequency information, which is then used as the control input for the target phase-locked loop to reduce output jitter and improve system stability. It should be noted that the working method and principle of the smoothing filter are common knowledge in the art and will not be elaborated upon here for the sake of brevity.

[0048] Furthermore, in one embodiment, the method further includes: The frequency offset and phase difference between the input clock and the reference clock are determined based on first-in-first-out (FIFO) technology. Frequency stability is determined based on the frequency deviation. The phase error change rate is determined based on the phase difference.

[0049] As an example, in this embodiment, the frequency offset and phase difference between the input clock and the reference clock can preferably be determined using FIFO technology; specifically, see [link to documentation]. Figure 5As shown, the FIFO (whose capacity can be determined according to actual needs, such as preferably 512 bits) depth is set at the center value position of the FIFO, the input clock of the DPLL is used as the write reference clock wr_clk of the FIFO, and the output clock of the DPLL is used as the read reference clock rd_clk of the FIFO. When the input data data_in enters the FIFO memory, if the write count value wr_cnt is 0 and unchanged, it is considered that the reference clock is lost; if wr_cnt increases, it indicates that the input clock is normal. At this time, the difference between the read count value rd_cnt and wr_cnt, fifo_err[n,0], is compared to reflect the frequency deviation between the input clock and the reference clock. Then, the frequency stability is determined based on the frequency deviation. At the same time, the difference between the real-time depth value of the FIFO and the preset center value, fifo_flag, is compared to reflect the phase difference between the input clock and the reference clock. The phase error change rate is determined based on the phase difference. Finally, the proportional-integral parameters of the target phase-locked loop are controlled based on the frequency stability and the phase error change rate. It should be noted that the specific working principles of FIFO, frequency stability, and phase error change rate are common knowledge in this field, and will not be elaborated here for the sake of brevity.

[0050] Furthermore, in one embodiment, prior to the step of determining frequency stability based on the frequency deviation, the method further includes: The target temperature change is predicted based on the target environment information corresponding to the target crystal oscillator. The target environment information includes the real-time temperature of the target crystal oscillator, the duration of operation, the target location, and the historical temperature information corresponding to the target location. The temperature drift compensation value is determined based on the target temperature change and the preset crystal oscillator temperature characteristic curve. The frequency deviation is corrected by the temperature drift compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

[0051] As an example, it is understandable that temperature variations cause changes in crystal oscillator characteristics, rendering traditional fixed-bandwidth parameters unsuitable, i.e., exhibiting poor environmental adaptability; to overcome this problem, see [link to relevant documentation]. Figure 3As shown, in this embodiment, the environmental monitoring module collects environmental parameters such as the real-time temperature T, the duration of operation, the target location, and the historical temperature information corresponding to the target location of the target crystal oscillator in the target phase-locked loop. The collected real-time temperature T is then subjected to Kalman filtering to form target environmental information. Next, temperature change trend prediction is performed based on the target environmental information to obtain the target temperature change. Specifically, the current operating location ID of the target crystal oscillator is read first, and the historical temperature information of that location is retrieved based on this ID. The target historical temperature information corresponding to the duration of operation is then filtered out from the historical temperature information. Finally, the target historical temperature information is fitted using the least squares method to obtain a temperature change trend. The potential line is used to calculate the temperature change slope corresponding to the real-time temperature of the target crystal oscillator. Then, the target temperature change is calculated using the temperature change slope and the real-time temperature. Based on the preset crystal oscillator temperature characteristic curve (which records the mapping relationship between the temperature change and the temperature drift compensation value, and is determined at the factory), the temperature drift compensation value corresponding to the target temperature change can be determined. Next, the frequency calibration module calibrates the frequency of the crystal oscillator using the temperature drift compensation value, that is, it corrects the frequency deviation obtained by FIFO detection to obtain the target frequency deviation. Finally, the frequency stability is determined based on the target frequency deviation to effectively improve the detection accuracy of frequency stability, thereby improving environmental adaptability, enhancing anti-interference ability, and increasing system reliability.

[0052] It is worth noting that before performing temperature drift compensation, it is necessary to first determine whether the target temperature change exceeds a certain value (such as 10℃). If so, it indicates that the current temperature change may be abnormal and may cause changes in the crystal oscillator characteristics. In this case, the temperature drift compensation value corresponding to the target temperature change is determined based on the crystal oscillator temperature characteristic curve, and subsequent compensation operations are performed. If not, it indicates that the current temperature change is a normal operating change and will not cause changes in the crystal oscillator characteristics or will have a very small impact, so there is no need to perform temperature drift compensation.

[0053] Furthermore, in one embodiment, prior to the step of determining frequency stability based on the frequency deviation, the method further includes: Obtain the cumulative operating time corresponding to the target crystal oscillator; The aging compensation value is determined based on the cumulative working time. The frequency deviation is corrected by the aging compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

[0054] As an example, it is understandable that crystal oscillator parameters drift over time, causing the fixed filter parameters to gradually become mismatched and unable to adapt to the effects of aging. To overcome this problem, this embodiment updates the aging rate compensation parameters (i.e., aging compensation values) based on the cumulative operating time of the target crystal oscillator. Specifically, the environmental monitoring module records the operating time of the external crystal oscillator of the target phase-locked loop in real time and stores it after power-down. When the cumulative operating time exceeds a preset time threshold (the specific value can be determined according to actual needs, such as one year), the aging compensation value is updated once. Based on the aging compensation value, the frequency deviation obtained by FIFO detection is compensated and updated to obtain the target frequency deviation. Finally, the frequency stability is determined by the target frequency deviation to effectively adapt to the effects of aging, thereby increasing the system reliability. It should be noted that the specific value of the aging compensation value can be determined according to the characteristics of different types of crystal oscillators. For example, the aging compensation value corresponding to a common crystal oscillator XO is ±3ppm, the aging compensation value corresponding to a temperature-compensated crystal oscillator TCXO is ±1ppm, and the aging compensation value corresponding to a temperature-controlled crystal oscillator OCXO is ±10ppb.

[0055] As can be seen, this embodiment provides an adaptive optimization method for PLL loop filters. It can automatically adjust the loop filter bandwidth based on the input source state, frequency, and phase error, overcoming the limitations of fixed bandwidth and achieving a good balance between tracking performance and noise suppression. Furthermore, based on crystal oscillator temperature and aging characteristics, it adds temperature compensation and aging compensation environmental adaptive compensation algorithms to improve PLL environmental adaptability and optimize long-term operating performance. In summary, this embodiment improves locking performance by dynamically modifying the bandwidth to reduce the locking time and dynamically controlling the loop gain to reduce overshoot; it also reduces phase noise and output clock jitter, improving long-term stability; in addition, it enhances environmental adaptability, strengthens anti-interference capabilities, and effectively increases system reliability.

[0056] Secondly, embodiments of this application also provide a phase-locked loop adaptive control system.

[0057] In one embodiment, the phase-locked loop adaptive control system includes: A status monitoring module is used to acquire status evaluation parameters corresponding to the target phase-locked loop, the status evaluation parameters including the phase error change rate; An adaptive control module is used to determine a bandwidth adjustment strategy based on the state evaluation parameters when the target phase-locked loop is in tracking mode; and to perform tracking control on the target phase-locked loop through the bandwidth adjustment strategy.

[0058] Furthermore, in one embodiment, the adaptive control module is specifically used for: The bandwidth adjustment strategy is determined based on the relationship between the target difference between two adjacent phase error change rates and the preset change rate difference threshold.

[0059] Furthermore, in one embodiment, the state evaluation parameters further include frequency stability and input source state information, and the adaptive control module is specifically used for: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

[0060] Furthermore, in one embodiment, the adaptive control module is also used for: In the hold mode, historical frequency information prior to the loss of the input source is acquired; The historical frequency information is smoothed and filtered to obtain the target frequency information; The target frequency information is used as the control input for the target phase-locked loop.

[0061] Furthermore, in one embodiment, the status monitoring module is also used for: The frequency offset and phase difference between the input clock and the reference clock are determined based on first-in-first-out (FIFO) technology. Frequency stability is determined based on the frequency deviation. The phase error change rate is determined based on the phase difference.

[0062] Furthermore, in one embodiment, the phase-locked loop adaptive control system further includes an environmental monitoring module and a frequency calibration module. The environmental monitoring module is used to predict the target temperature change based on the target environmental information corresponding to the target crystal oscillator. The target environmental information includes the real-time temperature of the target crystal oscillator, the duration of operation, the target location, and historical temperature information corresponding to the target location. The frequency calibration module is used to determine the temperature drift compensation value based on the target temperature change and the preset crystal oscillator temperature characteristic curve; the frequency deviation is corrected by the temperature drift compensation value to obtain the target frequency deviation, and the status monitoring module performs the step of determining the frequency stability based on the frequency deviation based on the target frequency deviation.

[0063] Furthermore, in one embodiment, the environmental monitoring module is also used to acquire the cumulative operating time corresponding to the target crystal oscillator; the frequency calibration module is also used to determine an aging compensation value based on the cumulative operating time; the frequency deviation is corrected by the aging compensation value to obtain the target frequency deviation, and the status monitoring module performs the step of determining the frequency stability based on the frequency deviation based on the target frequency deviation.

[0064] The functions of each module in the above-mentioned phase-locked loop adaptive control system correspond to the steps in the above-mentioned phase-locked loop adaptive control method embodiment, and their functions and implementation processes will not be described in detail here.

[0065] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0066] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0067] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0068] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0069] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0070] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0071] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A phase-locked loop adaptive control method, characterized in that, include: Obtain the state evaluation parameters corresponding to the target phase-locked loop, wherein the state evaluation parameters include the phase error change rate; When the target phase-locked loop is in tracking mode, a bandwidth adjustment strategy is determined based on the state evaluation parameters; The target phase-locked loop is tracked and controlled using the bandwidth adjustment strategy described above.

2. The phase-locked loop adaptive control method as described in claim 1, characterized in that, The step of determining the bandwidth adjustment strategy based on the state assessment parameters includes: The bandwidth adjustment strategy is determined based on the target difference between the rates of change of two adjacent phase errors.

3. The phase-locked loop adaptive control method as described in claim 1, characterized in that, The state evaluation parameters also include frequency stability and input source state information. After the step of obtaining the state evaluation parameters corresponding to the target phase-locked loop, the following steps are also included: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

4. The phase-locked loop adaptive control method as described in claim 3, characterized in that, The method further includes: In the hold mode, historical frequency information prior to the loss of the input source is acquired; The historical frequency information is smoothed and filtered to obtain the target frequency information; The target frequency information is used as the control input for the target phase-locked loop.

5. The phase-locked loop adaptive control method as described in claim 3, characterized in that, The method further includes: The frequency offset and phase difference between the input clock and the reference clock are determined based on first-in-first-out (FIFO) technology. Frequency stability is determined based on the frequency deviation. The phase error change rate is determined based on the phase difference.

6. The phase-locked loop adaptive control method as described in claim 5, characterized in that, Prior to the step of determining frequency stability based on the frequency deviation, the method further includes: The target temperature change is predicted based on the target environment information corresponding to the target crystal oscillator. The target environment information includes the real-time temperature of the target crystal oscillator, the duration of operation, the target location, and the historical temperature information corresponding to the target location. The temperature drift compensation value is determined based on the target temperature change and the preset crystal oscillator temperature characteristic curve. The frequency deviation is corrected by the temperature drift compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

7. The phase-locked loop adaptive control method as described in claim 5, characterized in that, Prior to the step of determining frequency stability based on the frequency deviation, the method further includes: Obtain the cumulative operating time corresponding to the target crystal oscillator; The aging compensation value is determined based on the cumulative working time. The frequency deviation is corrected by the aging compensation value to obtain the target frequency deviation, and the step of determining the frequency stability based on the frequency deviation is performed based on the target frequency deviation.

8. A phase-locked loop adaptive control system, characterized in that, include: A status monitoring module is used to acquire status evaluation parameters corresponding to the target phase-locked loop, the status evaluation parameters including the phase error change rate; An adaptive control module is used to determine a bandwidth adjustment strategy based on the state evaluation parameters when the target phase-locked loop is in tracking mode; and to perform tracking control on the target phase-locked loop through the bandwidth adjustment strategy.

9. The phase-locked loop adaptive control system as described in claim 8, characterized in that, The adaptive control module is specifically used for: The bandwidth adjustment strategy is determined based on the relationship between the target difference between two adjacent phase error change rates and the preset change rate difference threshold.

10. The phase-locked loop adaptive control system as described in claim 8, characterized in that, The state evaluation parameters also include frequency stability and input source state information, and the adaptive control module is specifically used for: If the input source status information indicates that the input source is lost, then the target phase-locked loop is controlled to enter hold mode; If the input source status information indicates that the input source has not been lost, then the target phase-locked loop is controlled to enter the tracking mode; In the tracking mode, if the frequency stability is greater than a preset frequency stability threshold and the phase error change rate is greater than a preset change rate threshold, then the bandwidth adjustment strategy determined based on the state evaluation parameters is executed.

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