Digital clock data recovery circuit and frequency locking method for recovering clock signal thereof

Abstract

A digital clock data recovery circuit and a frequency locking method for recovering a clock signal thereof, the digital clock data recovery circuit comprising a phase locked loop circuit and a frequency locked loop circuit. The phase locked loop circuit generates the recovered clock signal according to a pre-divisor, a feedback divisor and an input reference clock signal. The frequency locked loop circuit is coupled to the phase locked loop circuit. The frequency locked loop circuit adjusts one of the pre-divisor and the feedback divisor according to the input reference clock signal and an input data clock signal, so as to lock the frequency of the recovered clock signal to the frequency of the input data clock signal. The frequency locked loop circuit is implemented by digital circuits. After the frequency of the recovered clock signal is locked, the digital clock data recovery circuit operates in a data recovery mode. The present case proposes a digital clock data recovery circuit with a frequency locked loop circuit, so as to achieve a digital clock data recovery circuit with a wide frequency range.

Description

Technical Field

[0001] This invention relates to a digital clock data recovery circuit, and more particularly to a digital clock data recovery circuit employing a frequency-locked loop circuit and having a wide frequency range. Background Technology

[0002] For high-speed sequential transmission systems, the original data signal will attenuate and become distorted during transmission. Therefore, a clock data recovery circuit is needed to output data and synchronize the clock using a reference clock signal.

[0003] The frequency accuracy of the reference clock signal provided to the clock data recovery circuit is one of the key factors affecting the correctness of data recovery. If the frequency of the reference clock drifts, unwanted sampling errors will occur, and the data cannot be recovered correctly. The frequency drift problem is more severe when the reference clock signal is provided by an on-chip oscillator. Summary of the Invention

[0004] The purpose of this invention is to propose a digital clock data recovery circuit using a frequency-locked loop circuit to achieve a digital clock data recovery circuit with a wide frequency range.

[0005] The digital clock data recovery circuit proposed in this invention includes a phase-locked loop (PLL) circuit and a frequency-locked loop (LLL) circuit. The PLL circuit generates a recovered clock signal based on a pre-divisor, a feedback divisor, and an input reference clock signal. The LLL circuit is coupled to the PLL circuit and adjusts one of the pre-divisor and the feedback divisor based on the input reference clock signal and the input data clock signal, thereby locking the frequency of the recovered clock signal to the frequency of the input data clock signal. The LLL circuit is implemented using digital circuitry. After the frequency of the recovered clock signal is locked, the digital clock data recovery circuit operates in data recovery mode.

[0006] In some embodiments, the phase-locked loop circuit is further configured to multiply the ratio of the feedback divisor to the pre-divisor by the input reference clock signal to generate a recovery clock signal.

[0007] In some embodiments, the digital clock data recovery circuit further includes a first frequency divider and a second frequency divider. The first frequency divider is coupled to a frequency-locked loop circuit and is used to generate a first frequency divider signal. The second frequency divider is coupled to the frequency-locked loop circuit and is used to generate a second frequency divider signal. The frequency of the first frequency divider signal is 1 / M times the frequency of the input data clock signal, and the frequency of the second frequency divider signal is 1 / N times the frequency of the recovered clock signal, where M>N.

[0008] In some embodiments, M equals 2560 and N equals 5, and the digital clock data recovery circuit operates at half-rate.

[0009] In some embodiments, the frequency-locked loop circuit is further configured to count the number of rising edges of the second frequency-divided signal that occur during the high-potential period of the first frequency-divided signal to obtain the edge count, wherein when the edge count is equal to a target value, the frequency of the recovery clock signal is locked to the frequency of the input data clock signal.

[0010] In some embodiments, the target value is equal to 256.

[0011] In some embodiments, the frequency-locked loop circuit is further configured to: reset the frequency-locked loop circuit; set the initial values ​​of the pre-divisor and the feedback divisor; wait for the phase-locked loop circuit to reach a locked state; after the phase-locked loop circuit reaches a locked state, enter a read mode to determine whether the edge number is equal to the target value; when the edge number is not equal to the target value, enter a write mode to adjust one of the pre-divisor and the feedback divisor; after adjusting one of the pre-divisor and the feedback divisor and the phase-locked loop circuit reaches a locked state, enter a read mode; and when the edge number is equal to the target value, the frequency of the recovery clock signal is locked to the frequency of the input data clock signal.

[0012] In some embodiments, the frequency-locked loop circuit is further used to check the pattern of the input data clock signal to ensure that the input data clock signal is a valid data signal after determining that the number of edges equals the target value.

[0013] In some embodiments, the frequency-locked loop circuit is further used to calculate the difference between the edge number and the target value, thereby adjusting one of the pre-dividend and the feedback divisor based on the difference.

[0014] In some embodiments, when the absolute value of the difference is greater than or equal to 128, the frequency-locked loop circuit adjusts the pre-divisor.

[0015] In some embodiments, when the absolute value of the difference is greater than or equal to 192, the frequency-locked loop circuit adds 2 or subtracts 2 from the pre-divisor. When the absolute value of the difference is greater than or equal to 128 and less than 192, the frequency-locked loop circuit adds 1 or subtracts 1 from the pre-divisor.

[0016] In some embodiments, when the absolute value of the difference is less than 128, the frequency-locked loop circuit adjusts the feedback divisor.

[0017] In some embodiments, when the absolute value of the difference is greater than or equal to 32 and less than 128, the frequency-locked loop circuit adds or subtracts a first integer from the feedback divisor, where the first integer is the absolute value of the difference divided by 4 and then rounded up. When the absolute value of the difference is greater than or equal to 16 and less than 32, the frequency-locked loop circuit adds or subtracts a second integer from the feedback divisor, where the second integer is the absolute value of the difference divided by 8 and then rounded up. When the absolute value of the difference is greater than or equal to 8 and less than 16, the frequency-locked loop circuit adds or subtracts a third integer from the feedback divisor, where the third integer is the absolute value of the difference divided by 16 and then rounded up. When the absolute value of the difference is greater than or equal to 4 and less than 8, the frequency-locked loop circuit adds or subtracts a fourth integer from the feedback divisor, where the fourth integer is the absolute value of the difference divided by 32 and then rounded up. When the absolute value of the difference is less than 4, the frequency-locked loop circuit adds or subtracts 1 from the feedback divisor.

[0018] In some embodiments, the digital clock data recovery circuit further includes: an equalizer, a phase detector, a loop filter, a phase integrator, and a phase interpolator. The equalizer receives multiple input data signals to generate an input data clock signal. The phase detector is coupled to the equalizer and the phase-locked loop circuit and is used to sample the input data signal using the recovered clock signal. The loop filter is coupled to the phase detector and is used to provide filtering functionality. The phase integrator is coupled to the phase detector and the loop filter and is used to quantize the phase difference based on a control signal output by the phase detector. The phase interpolator is coupled to the phase integrator, the phase-locked loop circuit, and the phase detector and is used to phase-shift the recovered clock signal based on the phase difference. The equalizer, phase detector, loop filter, phase integrator, and phase interpolator are all implemented using digital circuitry.

[0019] This invention proposes a frequency locking method for a digital clock data recovery circuit, comprising: generating a recovery clock signal using a phase-locked loop (PLL) circuit based on a pre-divisor, a feedback divisor, and an input reference clock signal; and adjusting one of the pre-divisor and the feedback divisor based on the input reference clock signal and the input data clock signal using a frequency-locked loop (LLL) circuit, thereby locking the frequency of the recovery clock signal to the frequency of the input data clock signal. The LLL circuit is implemented using digital circuitry. After the frequency of the recovery clock signal is locked, the digital clock data recovery circuit operates in data recovery mode.

[0020] In some embodiments, the frequency locking method further includes multiplying the ratio of the feedback divisor to the pre-divisor by the input reference clock signal to generate a recovered clock signal.

[0021] In some embodiments, the frequency locking method further includes: receiving a first frequency divider signal and a second frequency divider signal using a frequency-locked loop circuit; counting the number of rising edges of the second frequency divider signal occurring during the high-level period of the first frequency divider signal using the frequency-locked loop circuit to obtain an edge count; and when the edge count equals a target value, locking the frequency of the recovered clock signal to the frequency of the input data clock signal. The frequency of the first frequency divider signal is 1 / M times the frequency of the input data clock signal, the frequency of the second frequency divider signal is 1 / N times the frequency of the recovered clock signal, and M>N.

[0022] In some embodiments, the frequency locking method further includes: resetting the frequency-locked loop circuit; setting initial values ​​for the pre-divisor and the feedback divisor; waiting for the phase-locked loop circuit to reach a locked state; after the phase-locked loop circuit reaches a locked state, entering a read mode to determine whether the edge number is equal to the target value; when the edge number is not equal to the target value, entering a write mode to adjust one of the pre-divisor and the feedback divisor; and after adjusting one of the pre-divisor and the feedback divisor and the phase-locked loop circuit reaches a locked state, entering a read mode.

[0023] In some embodiments, the frequency locking method further includes: checking the pattern of the input data clock signal to ensure that the input data clock signal is a valid data signal after determining that the number of edges equals the target value.

[0024] In some embodiments, the frequency locking method further includes: calculating the difference between the edge number and the target value, thereby adjusting one of the pre-dividend and the feedback dividend based on the difference.

[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] A better understanding of the invention can be obtained from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of discussion.

[0027] Figure 1 This is a circuit diagram of a digital clock data recovery circuit according to an embodiment of the present invention;

[0028] Figure 2 This is a flowchart illustrating the reading mode of the frequency-locked loop circuit according to an embodiment of the present invention;

[0029] Figure 3 This is a flowchart of the steps performed by the frequency-locked loop circuit according to an embodiment of the present invention;

[0030] Figure 4This is a state diagram of a frequency-locked loop circuit according to an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram illustrating an embodiment of the frequency-locked loop circuit according to the present invention, which adjusts one of the pre-divisor and the feedback divisor based on the difference.

[0032] Figure 6 This is a schematic diagram illustrating the recovery of the clock signal after the phase interpolator generates a phase shift;

[0033] Figure 7 This is a schematic diagram illustrating the recovery of the clock signal after the phase interpolator generates a phase shift;

[0034] Figure 8 This is a flowchart of a frequency locking method for recovering a clock signal using a digital clock data recovery circuit according to an embodiment of the present disclosure.

[0035] [Symbol Explanation]

[0036] 10: Digital Clock Data Recovery Circuit

[0037] 110: First frequency divider

[0038] 120: Second frequency divider

[0039] 130: Equalizer

[0040] 140: Phase detector

[0041] 150: Loop Filter

[0042] 160: Phase Integrator

[0043] 170: Phase interpolator

[0044] 1000: Frequency Locking Method

[0045] 1001, 1002, S1~S8: Steps

[0046] DLF_CLK: Second frequency divider signal

[0047] D10.2_CLK: Input data clock signal

[0048] D10.2_CLK / 2560: First frequency divider signal

[0049] FBK_DIV : Feedback divisor

[0050] FLL: Frequency Locked Loop Circuit

[0051] OSC_IN: Input reference clock signal

[0052] PD_CK: Clock signal

[0053] PD_data: Data signal

[0054] PI_CLK: The recovered clock signal after phase shift.

[0055] PLL: Phase-locked loop circuit

[0056] PLL_CLK: Restore clock signal

[0057] PRE_DIV : Predivisor

[0058] RXN, RXP: Input data signals

[0059] UP / DN: Control signals Detailed Implementation

[0060] The embodiments of the present invention will be discussed in detail below. However, it will be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The terms "first," "second," etc., as used herein, do not specifically refer to order or sequence, but are merely used to distinguish elements or operations described using the same technical terms.

[0061] Figure 1 This is a circuit diagram of a digital clock data recovery circuit 10 according to an embodiment of the present disclosure. The digital clock data recovery circuit 10 includes a phase-locked loop (PLL) circuit, a frequency-locked loop (FLL) circuit, a first frequency divider 110, a second frequency divider 120, an equalizer 130, a phase detector 140, a loop filter 150, a phase integrator 160, and a phase interpolator 170.

[0062] Phase detector 140 is coupled to equalizer 130. Phase detector 140 is coupled to phase-locked loop (PLL) circuit via phase interpolator 170. Loop filter 150 is coupled to phase detector 140 via second frequency divider 120. Phase integrator 160 is coupled to phase detector 140 and loop filter 150. Phase interpolator 170 is coupled to phase integrator 160, PLL circuit, and phase detector 140.

[0063] The first frequency divider 110 is coupled to a frequency-locked loop (FLL) circuit. The second frequency divider 120 is coupled to the FLL circuit. The FLL circuit is coupled to an equalizer 130 via the first frequency divider 110. The FLL circuit is coupled to a phase-locked loop (PLL) circuit.

[0064] In the embodiments disclosed herein, the phase-locked loop (PLL) circuit receives an input reference clock signal OSC_IN and generates a recovered clock signal PLL_CLK based on the pre-divider PRE_DIV, the feedback divider FBK_DIV, and the input reference clock signal OSC_IN. Specifically, the PLL circuit multiplies the input reference clock signal OSC_IN by the ratio of the feedback divider FBK_DIV to the pre-divider PRE_DIV to generate the recovered clock signal PLL_CLK. In other words, PLL_CLK = OSC_IN × (FBK_DIV / PRE_DIV). The feedback divider FBK_DIV and the pre-divider PRE_DIV are each integers.

[0065] Phase interpolator 170 receives the recovered clock signal PLL_CLK. Phase interpolator 170 performs phase shifting on the recovered clock signal PLL_CLK to generate the phase-shifted recovered clock signal PI_CLK.

[0066] Equalizer 130 receives input data signals RXP and RXN and generates an input data clock signal D10.2_CLK based on the frequencies of the input data signals RXP and RXN. In other words, the input data clock signal D10.2_CLK corresponds to the frequencies of the input data signals RXP and RXN.

[0067] The first frequency divider 110 receives the input data clock signal D10.2_CLK to generate a first frequency divider signal D10.2_CLK / 2560. The frequency of the first frequency divider signal D10.2_CLK / 2560 is 1 / M times the frequency of the input data clock signal D10.2_CLK. In the embodiment disclosed herein, M equals 2560.

[0068] Equalizer 130 eliminates the DC offset of the input data signals RXP and RXN and amplifies the high-frequency signals in the input data signals RXP and RXN, thereby transmitting the amplified input data signals to phase detector 140. Phase detector 140 receives the amplified input data signals and the phase-shifted recovered clock signal PI_CLK. Phase detector 140 samples the amplified input data signals using the phase-shifted recovered clock signal PI_CLK to detect whether the phase of the phase-shifted recovered clock signal PI_CLK is leading or lagging behind the amplified input data signals. The detection result of phase detector 140 corresponds to the control signal UP / DN, and the control signal UP / DN is transmitted from phase detector 140 to phase integrator 160.

[0069] The phase detector 140 further transmits the data signal PD_data and the clock signal PD_CK to the second frequency divider 120. The data signal PD_data corresponds to the input data signals RXP and RXN, and the clock signal PD_CK corresponds to the recovered clock signal PI_CLK after phase shift.

[0070] The second frequency divider 120 receives the clock signal PD_CK to generate a second frequency divider signal DLF_CLK. The frequency of the second frequency divider signal DLF_CLK is 1 / N times the frequency of the clock signal PD_CK. Since the clock signal PD_CK corresponds to the phase-shifted recovered clock signal PI_CLK, and the frequency of the phase-shifted recovered clock signal PI_CLK is equal to the frequency of the recovered clock signal PLL_CLK, the frequency of the second frequency divider signal DLF_CLK is 1 / N times the frequency of the recovered clock signal PLL_CLK. In the embodiment disclosed herein, N equals 5. Therefore, it can be understood that M > N.

[0071] The loop filter 150 receives the data signal PD_data and provides filtering to improve the stability of the digital clock data recovery circuit 10. The phase integrator 160 receives the filtered data signal and the control signal UP / DN. The phase integrator 160 quantizes the phase difference between the phase-shifted recovered clock signal PI_CLK and the data signal PD_data based on the detection result of the phase detector 140 (i.e., the control signal UP / DN). In other words, the phase integrator 160 quantizes the phase difference based on the control signal UP / DN output by the phase detector 140.

[0072] The phase interpolator 170 receives the recovery clock signal PLL_CLK and the phase difference, and performs phase shifting on the recovery clock signal PLL_CLK according to the phase difference, thereby generating the phase-shifted recovery clock signal PI_CLK.

[0073] The frequency-locked loop (FLL) circuit receives a first frequency divider signal D10.2_CLK / 2560 and a second frequency divider signal DLF_CLK. As described above, the first frequency divider signal D10.2_CLK / 2560 is related to the input data clock signal D10.2_CLK, and the second frequency divider signal DLF_CLK is related to the clock signal PD_CK. The clock signal PD_CK is related to the phase-shifted recovered clock signal PI_CLK, and the phase-shifted recovered clock signal PI_CLK is related to the recovered clock signal PLL_CLK, which is also related to the input reference clock signal OSC_IN. The FLL circuit adjusts one of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV according to the input reference clock signal OSC_IN and the input data clock signal D10.2_CLK, thereby locking the frequency of the recovered clock signal PLL_CLK to the frequency of the input data clock signal D10.2_CLK. Furthermore, after the frequency of the recovery clock signal PLL_CLK is locked, the digital clock data recovery circuit 10 operates in data recovery mode.

[0074] Specifically, the digital clock data recovery circuit 10 uses a frequency-locked loop (FLL) circuit to lock the frequency of the recovery clock signal PLL_CLK to the frequency of the input data clock signal D10.2_CLK, thereby solving the frequency drift problem of the input reference clock signal OSC_IN. In other words, the digital clock data recovery circuit 10 uses a frequency-locked loop (FLL) circuit to achieve a wide frequency range digital clock data recovery circuit.

[0075] In the embodiments disclosed herein, the frequency-locked loop circuit FLL, the first frequency divider 110, the second frequency divider 120, the equalizer 130, the phase detector 140, the loop filter 150, the phase integrator 160, and the phase interpolator 170 are all implemented by digital circuits, thereby realizing the digital clock data recovery circuit 10.

[0076] Figure 2 This is a schematic flowchart illustrating the readout mode of a frequency-locked loop (FLL) circuit according to an embodiment of this disclosure. Figure 2 As shown, for the read mode of the frequency-locked loop circuit (FLL), the FLL obtains the edge count by counting the number of rising edges of the second frequency-divided signal DLF_CLK that occur during the high-level period of the first frequency-divided signal D10.2_CLK / 2560. When the edge count equals the target value, the frequency of the recovery clock signal PLL_CLK is locked to the frequency of the input data clock signal D10.2_CLK.

[0077] In the embodiment disclosed herein, the target value is equal to 256. It should be noted that the digital clock data recovery circuit 10 operates at half-rate. Therefore, 2560 (i.e., M) = 256 (i.e., the target value) × 2 (i.e., half-rate) × 5 (i.e., N).

[0078] Figure 3 This is a flowchart of the steps performed by the frequency-locked loop circuit (FLL) according to an embodiment of the present disclosure. Figure 4 This is a state diagram of the frequency-locked loop circuit (FLL) according to an embodiment of the present disclosure. The FLL is used to execute steps S1 to S8. In step S1, the FLL is reset. In step S2, the FLL sets the initial values ​​of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV.

[0079] In step S3, the frequency-locked loop (FLL) circuit waits for the phase-locked loop (PLL) circuit to reach the locked state. If the PLL circuit has not yet reached the locked state, the frequency of the recovery clock signal PLL_CLK is unstable, causing the FLL circuit to obtain incorrect edge numbers. When the PLL circuit reaches the locked state, it uses the initial values ​​of the pre-divisor and the feedback divisor to set the preset frequency of the recovery clock signal PLL_CLK. In other words, the preset frequency of the recovery clock signal PLL_CLK = OSC_IN × (initial value of the feedback divisor FBK_DIV / initial value of the pre-divisor PRE_DIV).

[0080] In step S4, the frequency-locked loop (FLL) circuit enters read mode to obtain the edge count. In step S5, the FLL circuit determines whether the edge count is equal to the target value. If the FLL circuit determines that the edge count is not equal to the target value, step S6 is executed. If the FLL circuit determines that the edge count is equal to the target value, step S8 is executed.

[0081] In step S6, the frequency-locked loop (PLL) circuit enters write mode to execute step S7. In step S7, the PLL circuit adjusts one of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV, and then executes steps S3 and S4 sequentially. In other words, after one of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV is adjusted (i.e., step S7) and the PLL circuit reaches a locked state (i.e., step S3), the PLL circuit enters read mode (i.e., step S4).

[0082] In step S8, the frequency-locked loop circuit FLL reaches a locked state, locking the frequency of the recovery clock signal PLL_CLK to the frequency of the input data clock signal D10.2_CLK. For example, the frequency of the input data clock signal D10.2_CLK is 4050 MHz, the input reference clock signal OSC_IN is 27 MHz, and the target value is 256. Figure 5 As shown, by adjusting one of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV in step S7, when the number of edges equals the target value (i.e., the number of edges = 256, making the judgment result of step S5 "yes"), the recovered clock signal PLL_CLK = OSC_IN × (FBK_DIV / PRE_DIV) = 27 MHz × (150 / 1) = 4050 MHz. In other words, the frequency-locked loop circuit FLL reaches the locked state to lock the frequency of the recovered clock signal PLL_CLK to the frequency of the input data clock signal D10.2_CLK. Furthermore, in step S8, the frequency-locked loop circuit further checks the pattern of the input data clock signal D10.2_CLK (i.e., 0101010) to ensure that the input data clock signal D10.2_CLK is a valid data signal after determining that the number of edges equals the target value (i.e., the judgment result of step S5 is "yes").

[0083] In the embodiments disclosed herein, the frequency-locked loop circuit FLL calculates the difference between the edge number and the target value, thereby adjusting one of the pre-dividend PRE_DIV and the feedback divisor FBK_DIV based on the difference.

[0084] When the absolute value of the difference is greater than or equal to 128, the frequency-locked loop circuit FLL adjusts the pre-divisor PRE_DIV.

[0085] In detail, when the absolute value of the difference is greater than or equal to 192, the frequency-locked loop (FLL) circuit adds or subtracts 2 from the pre-divisor PRE_DIV. Specifically, when the difference is negative (i.e., less than or equal to -192), the FLL circuit subtracts 2 from the pre-divisor PRE_DIV. Specifically, when the difference is positive (i.e., greater than or equal to 192), the FLL circuit adds 2 to the pre-divisor PRE_DIV. For example, such as... Figure 5 As shown, after the frequency-locked loop circuit FLL is reset, the edge number is equal to 0, the target value is equal to 256, and the initial value of the pre-divisor PRE_DIV is equal to 3. The difference is equal to -256, so the frequency-locked loop circuit FLL decrements the pre-divisor PRE_DIV by 2, making the pre-divisor PRE_DIV become 1.

[0086] In detail, when the absolute value of the difference is greater than or equal to 128 and less than 192, the frequency-locked loop (FLL) circuit increments or decrements the pre-divisor PRE_DIV by 1. Specifically, when the difference is negative (i.e., less than or equal to -128 and greater than -192), the FLL circuit decrements the pre-divisor PRE_DIV by 1. Conversely, when the difference is positive (i.e., greater than or equal to 128 and less than 192), the FLL circuit increments the pre-divisor PRE_DIV by 1.

[0087] When the absolute value of the difference is less than 128, the frequency-locked loop circuit FLL adjusts the feedback divisor FBK_DIV.

[0088] In detail, when the absolute value of the difference is greater than or equal to 32 and less than 128, the frequency-locked loop (FLL) circuit adds or subtracts an integer from the divisor FBK_DIV. This integer is the result of dividing the absolute value of the difference by 4 and then rounding up. Specifically, when the difference is negative (i.e., less than or equal to -32 and greater than -128), the FLL circuit adds an integer to the divisor FBK_DIV. Specifically, when the difference is positive (i.e., greater than or equal to 32 and less than 128), the FLL circuit subtracts an integer from the divisor FBK_DIV. For example, such as... Figure 5 As shown, when the edge number is 224, the target value is 256, and the current feedback divisor FBK_DIV is 120, the difference is -32. Therefore, the frequency-locked loop circuit FLL adds 8 to the feedback divisor FBK_DIV (i.e., ...). This makes the feedback divisor FBK_DIV become 128.

[0089] In detail, when the absolute value of the difference is greater than or equal to 16 and less than 32, the frequency-locked loop (FLL) circuit adds or subtracts an integer from the divisor FBK_DIV. This integer is the result of dividing the absolute value of the difference by 8 and then rounding up. Specifically, when the difference is negative (i.e., less than or equal to -16 and greater than -32), the FLL circuit adds an integer to the divisor FBK_DIV. Specifically, when the difference is positive (i.e., greater than or equal to 16 and less than 32), the FLL circuit subtracts an integer from the divisor FBK_DIV. For example, such as... Figure 5 As shown, when the edge number is 233, the target value is 256, and the current feedback divisor FBK_DIV is 128, the difference is -23. Therefore, the frequency-locked loop circuit FLL adds 3 to the feedback divisor FBK_DIV (i.e., ...). This causes the feedback divisor FBK_DIV to become 131.

[0090] In detail, when the absolute value of the difference is greater than or equal to 8 and less than 16, the frequency-locked loop (FLL) circuit adds or subtracts an integer from the divisor FBK_DIV. This integer is the result of dividing the absolute value of the difference by 16 and then rounding up. Specifically, when the difference is negative (i.e., less than or equal to -8 and greater than -16), the FLL circuit adds an integer to the divisor FBK_DIV. Specifically, when the difference is positive (i.e., greater than or equal to 8 and less than 16), the FLL circuit subtracts an integer from the divisor FBK_DIV. For example, such as... Figure 5 As shown, when the edge number is 241, the target value is 256, and the current feedback divisor FBK_DIV is 131, the difference is -15. Therefore, the frequency-locked loop circuit FLL adds 1 to the feedback divisor FBK_DIV (i.e., ...). This makes the feedback divisor FBK_DIV become 132.

[0091] In detail, when the absolute value of the difference is greater than or equal to 4 and less than 8, the frequency-locked loop (FLL) circuit adds or subtracts an integer from the feedback divisor FBK_DIV. This integer is the result of dividing the absolute value of the difference by 32 and then rounding up. Specifically, when the difference is negative (i.e., the difference is less than or equal to -4 and greater than -8), the FLL circuit adds an integer to the feedback divisor FBK_DIV. Conversely, when the difference is positive (i.e., the difference is greater than or equal to 4 and less than 8), the FLL circuit subtracts an integer from the feedback divisor FBK_DIV.

[0092] In detail, when the absolute value of the difference is less than 4, the frequency-locked loop (FLL) circuit will increment or decrement the divisor FBK_DIV by 1. Specifically, when the difference is negative (i.e., greater than -4), the FLL circuit will increment the divisor FBK_DIV by 1. Specifically, when the difference is positive (i.e., less than 4), the FLL circuit will decrement the divisor FBK_DIV by 1.

[0093] The phase interpolator 170 generates the phase-shifted recovery clock signal PI_CLK by advancing or delaying the sampling clock of the recovery clock signal PLL_CLK. Figure 6 and Figure 7 This is a schematic diagram illustrating the recovery clock signal PI_CLK generated by the phase interpolator 170 after phase shift.

[0094] like Figure 6As shown, according to the control signal UP / DN, the rising edge of the phase-shifted recovered clock signal PI_CLK is determined to be phase-lagging relative to the center of the high-level period of the data signal PD_data. Therefore, the phase interpolator 170 advances the sampling clock of the recovered clock signal PLL_CLK in phase, so that the rising edge of the phase-shifted recovered clock signal PI_CLK is located at the center of the high-level period of the data signal PD_data.

[0095] like Figure 7 As shown, according to the control signal UP / DN, the rising edge of the phase-shifted recovered clock signal PI_CLK is determined to be phase-leading relative to the center of the high-level period of the data signal PD_data. Therefore, the phase interpolator 170 delays the sampling clock of the recovered clock signal PLL_CLK in phase, so that the rising edge of the phase-shifted recovered clock signal PI_CLK is located at the center of the high-level period of the data signal PD_data.

[0096] Figure 8 This is a flowchart of a frequency locking method 1000 for a recovered clock signal PLL_CLK in a digital clock data recovery circuit 10 according to an embodiment of the present disclosure. In step 1001, the phase-locked loop circuit PLL generates the recovered clock signal PLL_CLK based on the pre-divisor PRE_DIV, the feedback divisor FBK_DIV, and the input reference clock signal OSC_IN. In step 1002, the frequency-locked loop circuit FLL adjusts one of the pre-divisor PRE_DIV and the feedback divisor FBK_DIV based on the input reference clock signal OSC_IN and the input data clock signal D10.2_CLK, thereby locking the frequency of the recovered clock signal PLL_CLK to the frequency of the input data clock signal D10.2_CLK.

[0097] The foregoing has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will recognize that this invention can be readily used as a basis to design or modify other processes and structures, thereby achieving the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A digital clock data recovery circuit, characterized in that, include: A phase-locked loop circuit is used to generate a recovery clock signal based on a pre-divisor, a feedback divisor and an input reference clock signal; and A frequency-locked loop circuit is coupled to the phase-locked loop circuit and is used to adjust one of the pre-divisor and the feedback divisor according to the input reference clock signal and an input data clock signal, thereby locking the frequency of the recovered clock signal to the frequency of the input data clock signal; The frequency-locked loop circuit is implemented using digital circuitry. Once the frequency of the recovery clock signal is locked, the digital clock data recovery circuit operates in a data recovery mode.

2. The digital clock data recovery circuit according to claim 1, characterized in that, The phase-locked loop circuit is also used to multiply the ratio of the feedback divisor to the pre-divisor by the input reference clock signal to generate the recovery clock signal.

3. The digital clock data recovery circuit according to claim 1, characterized in that, Also includes: A first frequency divider is coupled to the frequency-locked loop circuit and is used to generate a first frequency divider signal; and A second frequency divider is coupled to the frequency-locked loop circuit and is used to generate a second frequency divider signal; The frequency of the first frequency divider signal is 1 / M times the frequency of the input data clock signal, and the frequency of the second frequency divider signal is 1 / N times the frequency of the recovery clock signal, where M>N.

4. The digital clock data recovery circuit according to claim 3, characterized in that, M equals 2560 and N equals 5, and the digital clock data recovery circuit operates at half rate.

5. The digital clock data recovery circuit according to claim 3, characterized in that, The frequency-locked loop circuit is also used to count the number of rising edges of the second frequency-locked signal that occur during the high-level period of the first frequency-locked signal to obtain an edge count, wherein when the edge count is equal to a target value, the frequency of the recovery clock signal is locked to the frequency of the input data clock signal.

6. The digital clock data recovery circuit according to claim 5, characterized in that, The target value is 256.

7. The digital clock data recovery circuit according to claim 5, characterized in that, This frequency-locked loop circuit is also used for: Reset the frequency lock loop circuit; Set the initial values ​​for the pre-divisor and the feedback divisor; Wait for the phase-locked loop circuit to reach the locked state; After the phase-locked loop circuit reaches the locked state, it enters a read mode to determine whether the edge number is equal to the target value; When the edge number is not equal to the target value, enter a write mode to adjust one of the pre-divisor and the feedback divisor; After adjusting either the pre-divisor or the feedback divisor and the phase-locked loop circuit reaches a locked state, the read mode is entered; and When the edge number equals the target value, the frequency of the recovery clock signal is locked to the frequency of the input data clock signal.

8. The digital clock data recovery circuit according to claim 7, characterized in that, The frequency-locked loop circuit is also used to check the pattern of the input data clock signal to ensure that the input data clock signal is a valid data signal after determining that the edge number is equal to the target value.

9. The digital clock data recovery circuit according to claim 5, characterized in that, The frequency-locked loop circuit is also used to calculate a difference between the edge number and the target value, thereby adjusting one of the pre-divisor and the feedback divisor based on the difference.

10. The digital clock data recovery circuit according to claim 9, characterized in that, When the absolute value of the difference is greater than or equal to 128, the frequency-locked loop circuit adjusts the pre-divisor.

11. The digital clock data recovery circuit according to claim 10, characterized in that, When the absolute value of the difference is greater than or equal to 192, the frequency-locked loop circuit adds or subtracts 2 from the pre-divisor; and When the absolute value of the difference is greater than or equal to 128 and less than 192, the frequency-locked loop circuit adds or subtracts 1 from the pre-divisor.

12. The digital clock data recovery circuit according to claim 9, characterized in that, When the absolute value of the difference is less than 128, the frequency-locked loop circuit adjusts the feedback divisor.

13. The digital clock data recovery circuit according to claim 12, characterized in that, When the absolute value of the difference is greater than or equal to 32 and less than 128, the frequency-locked loop circuit adds or subtracts a first integer to the feedback divisor. The first integer is the result of dividing the absolute value of the difference by 4 and then rounding up. When the absolute value of the difference is greater than or equal to 16 and less than 32, the frequency-locked loop circuit adds or subtracts a second integer to the feedback divisor. The second integer is the result of dividing the absolute value of the difference by 8 and then rounding up. When the absolute value of the difference is greater than or equal to 8 and less than 16, the frequency-locked loop circuit adds or subtracts a third integer to the feedback divisor. The third integer is the result of dividing the absolute value of the difference by 16 and then rounding up. When the absolute value of the difference is greater than or equal to 4 and less than 8, the frequency-locked loop circuit adds or subtracts a fourth integer to the feedback divisor. The fourth integer is the result of dividing the absolute value of the difference by 32 and then rounding up. and When the absolute value of the difference is less than 4, the frequency-locked loop circuit adds or subtracts 1 from the feedback divisor.

14. The digital clock data recovery circuit according to claim 1, characterized in that, Also includes: An equalizer is used to receive multiple input data signals to generate a clock signal for those input data signals; A phase detector is coupled to the equalizer and the phase-locked loop circuit, and is used to sample the input data signals using the recovered clock signal; A loop filter is coupled to the phase detector and is used to provide filtering functionality; A phase integrator, coupled to the phase detector and the loop filter, is used to quantize a phase difference based on a control signal output by the phase detector; and A phase interpolator, coupled to the phase integrator, the phase-locked loop circuit and the phase detector, is used to phase shift the recovered clock signal based on the phase difference; The equalizer, phase detector, loop filter, phase integrator, and phase interpolator are all implemented using digital circuits.

15. A frequency locking method for recovering a clock signal in a digital clock data recovery circuit, characterized in that, include: The recovery clock signal is generated using a phase-locked loop circuit based on a pre-divisor, a feedback divisor, and an input reference clock signal. and A frequency-locked loop circuit is used to adjust one of the pre-divisor and the feedback divisor according to the input reference clock signal and an input data clock signal, thereby locking the frequency of the recovered clock signal to the frequency of the input data clock signal; The frequency-locked loop circuit is implemented using digital circuitry. Once the frequency of the recovery clock signal is locked, the digital clock data recovery circuit operates in a data recovery mode.

16. The frequency locking method according to claim 15, characterized in that, Also includes: The ratio of the feedback divisor to the pre-divisor is multiplied by the input reference clock signal to generate the recovery clock signal.

17. The frequency locking method according to claim 15, characterized in that, Also includes: The frequency-locked loop circuit is used to receive a first frequency divider signal and a second frequency divider signal; The frequency-locked loop circuit is used to count the number of rising edges of the second frequency-divided signal occurring during the high-level period of the first frequency-divided signal to obtain an edge count; and When the edge number equals a target value, the frequency of the recovery clock signal is locked to the frequency of the input data clock signal; The frequency of the first frequency divider signal is 1 / M times the frequency of the input data clock signal, and the frequency of the second frequency divider signal is 1 / N times the frequency of the recovery clock signal, where M>N.

18. The frequency locking method according to claim 17, characterized in that, Also includes: Reset the frequency lock loop circuit; Set the initial values ​​for the pre-divisor and the feedback divisor; Wait for the phase-locked loop circuit to reach the locked state; After the phase-locked loop circuit reaches the locked state, it enters a read mode to determine whether the edge number is equal to the target value; When the edge number is not equal to the target value, enter a write mode to adjust one of the pre-divisor and the feedback divisor; and After adjusting one of the pre-divisor and the feedback divisor and the phase-locked loop circuit reaches the locked state, the read mode is entered.

19. The frequency locking method according to claim 18, characterized in that, Also includes: Check the pattern of the input data clock signal to ensure that the input data clock signal is a valid data signal after determining that the edge number equals the target value.

20. The frequency locking method according to claim 17, characterized in that, Also includes: Calculate a difference between the edge number and the target value, and adjust one of the pre-dividend and the feedback divisor based on the difference.

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