An audio clock synchronization method and system based on digital phase-locked loop

Abstract

The application discloses an audio clock synchronization method and system based on a digital phase-locked loop, which comprises receiving a reference clock signal and a feedback clock signal, obtaining a time difference T of corresponding effective edges of the two; sampling in continuous M synchronization periods to obtain an initial time difference sequence set; performing median filtering pretreatment on the sampling values in the initial time difference sequence set to obtain an effective time difference sequence set; performing linear fitting on data points (x, y) by using a least square method to obtain a fitting straight line equation; calculating a frequency deviation according to a slope k, and adjusting an output audio clock signal of a digital controlled oscillator according to the frequency deviation. The application performs linear fitting on a sampling sequence by using a least square method, estimates a frequency deviation according to a slope of a fitting straight line, evaluates a jitter characteristic according to a fitting residual error, can accurately estimate a clock frequency / phase deviation, can dynamically adjust loop parameters according to a working state, and has excellent suppression capacity for low-frequency jitter.

Description

Technical Field

[0001] This invention relates to the field of audio signal processing technology, and in particular to an audio clock synchronization method and system based on a digital phase-locked loop. Background Technology

[0002] In audio signal processing systems, multiple devices or chips need to maintain strict clock synchronization to ensure consistency in audio sampling, transmission, and playback. Clock jitter directly leads to sampling timing errors during analog-to-digital conversion (ADC) or digital-to-analog conversion (DAC), which in turn causes a deterioration in signal-to-noise ratio (SNR) and a decrease in total harmonic distortion plus noise (THD+N), ultimately resulting in audible sound quality loss.

[0003] Existing technologies mainly employ the following solutions to address clock synchronization issues, but all of them have inherent drawbacks: (1) Traditional analog PLL synchronization scheme like Figure 6 As shown, a closed-loop negative feedback system consisting of a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO) enables the local clock to track the input reference signal. However, this scheme has an inherent drawback—the loop filter needs to simultaneously achieve the contradictory functions of "tracking the slow changes in the center frequency" and "suppressing the rapid changes in jitter." In particular, for the inherent low-frequency jitter components in the reference clock (typically referring to frequency drift below 10Hz or periodic disturbances caused by power supply ripple coupling), the analog loop filter's suppression capability is severely insufficient due to order limitations and component parameter tolerances. These low-frequency jitters directly modulate the VCO, manifesting as symmetrical spurious tones in the audio output spectrum, leading to a degraded signal-to-noise ratio.

[0004] (2) Asynchronous Sampling Rate Conversion (ASRC) Scheme While ASRC can suppress output clock jitter to the accuracy level of the local crystal oscillator, it is essentially a digital resampling process. ASRC cannot effectively separate the jitter component from the signal component in the input signal. When the input clock jitter is large, the resampling process will produce aliasing distortion, and its final effect is not significantly improved compared with the traditional PLL solution.

[0005] (3) Dual-link synchronization scheme This solution transmits a low-jitter reference clock via an independent clock transmission link. While it effectively suppresses jitter, it requires a corresponding external independent clock source. When there are multiple audio playback sources in the system or clock switching is required, a corresponding number of physical transmission paths are needed, resulting in a limited system architecture and high costs.

[0006] (4) Large-capacity buffer scheme A large-capacity FIFO buffer is used to absorb clock frequency deviations, and sampling points are periodically inserted or discarded to maintain synchronization. However, this approach leads to a continuous accumulation of time delays. In real-time audio playback scenarios, the lip-sync deviation between the audio and video streams gradually increases, failing to meet the stringent requirements of audio-video synchronization.

[0007] (5) Traditional fixed-parameter digital PLL solution In digital PLLs, traditional first- or second-order digital loop filters typically use fixed coefficients. When the input reference clock (such as the recovered clock from the SPDIF receiver) contains periodic low-frequency jitter or deterministic jitter (DJ) coupled by power supply ripple, the feedback loop of a traditional DPLL cannot distinguish between "long-term frequency drift that needs to be tracked" and "short-term phase noise that needs to be filtered out." This confusion causes the PLL's digitally controlled oscillator (DCO) control word to produce periodic modulation, ultimately resulting in audible distortion or periodic fluctuations in the audio DAC output. In practical engineering applications, when the PLL is improperly configured or its parameters are poorly designed, the input test signal will exhibit symmetrical sideband components in the spectrum, directly leading to sound quality degradation.

[0008] Therefore, it is urgent to propose an audio clock synchronization method based on digital phase-locked loop to solve the above problems. Summary of the Invention

[0009] Therefore, it is necessary to address the shortcomings of existing technologies by providing an audio clock synchronization method and system based on a digital phase-locked loop. This method can accurately estimate the clock frequency / phase deviation while dynamically adjusting the loop parameters according to the working state, and has excellent suppression capabilities for low-frequency jitter.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: This invention provides an audio clock synchronization method based on a digital phase-locked loop, which includes the following steps: Step S1: Receive the reference clock signal and the feedback clock signal, compare the reference clock signal and the feedback clock signal, and obtain the time difference between their corresponding effective edges. T; Step S2: Within M consecutive synchronization cycles, calculate the time difference between the reference clock signal and the feedback clock signal. T is sampled to obtain an initial time difference sequence set X={ composed of M sampled values. , ,..., }; where M is a configurable parameter; Step S3: Set the initial time difference sequence X = { , ,..., The sampled values ​​in} are preprocessed using median filtering to obtain the effective time difference sequence set Y={ , ,..., };in, This represents the time difference after preprocessing for the i-th synchronization cycle. , The corresponding period number is ; Step S4: Use the least squares method to analyze the data points ( , Perform a linear fit and obtain the equation of the fitted line: Where k is the slope of the fitted line, representing the change in time difference for each synchronization cycle, and b is the intercept of the fitted line, representing the initial phase deviation. Step S5: Calculate the frequency deviation based on the slope k. And accordingly, adjust the synchronized audio clock signal output by the numerically controlled oscillator; among which, For reference clock period, This is the nominal output frequency of the numerically controlled oscillator.

[0011] Furthermore, the method in step S3 includes the following steps: S31. Construct a sliding window of length m; S32, Based on the initial time difference sequence set X={ , ,..., Sort the m sampling points within the sliding window, and take the median value after sorting the data within the sliding window as the time difference output result corresponding to the current sampling point; S33. Move the sliding window and output the corresponding time difference results for each sampling point to obtain the set of valid time difference sequences Y={ , ,..., }

[0012] Further, the method in step S5 includes the following steps: Calculate the frequency deviation based on the slope k. ; Based on the calculated frequency deviation Calculate the frequency control word adjustment amount ; where round() represents the rounding operation, and the frequency resolution is... = , denotes the operating clock frequency of the numerically controlled oscillator with a bit width of W; ΔFCW is superimposed on the current frequency control word FCW to obtain the updated frequency control word FCW_new; The numerically controlled oscillator accumulates the phase with FCW_new as the step value in each system clock cycle, and the overflow signal of the phase accumulator is shaped by the audio clock output unit and then outputs the synchronized audio clock signal; wherein, the numerically controlled oscillator adopts a phase accumulator structure, and the output frequency has a linear corresponding relationship with the frequency control word FCW.

[0013] Further, before step S5, the method further comprises step S4-1: dynamically adjusting the loop bandwidth according to the absolute value of the slope k.

[0014] Further, the method of step S4-1 specifically operates as follows: When |k|>K1, the loop bandwidth is adjusted to a wide bandwidth; When |k|<K2, the loop bandwidth is adjusted to a narrow bandwidth; When |k| is within the interval [K2, K1], the loop bandwidth has a linear relationship with |k|: ; wherein K1 corresponds to the equivalent slope with a relative frequency deviation of 50ppm, and K2 corresponds to the equivalent slope with a relative frequency deviation of 1ppm; denotes the proportional path gain coefficient of the loop filter.

[0015] Further, before step S5, the method further comprises step S4-2: calculating the root mean square value of the residual of the least squares fitting : ; when exceeds the preset threshold , the sampling window length M is automatically extended according to the preset setting.

[0016] Further, before step S5, the method further comprises step S5-1: obtaining a temperature compensation amount according to a pre-stored frequency-temperature characteristic lookup table, and directly performing feedforward correction on the frequency control word FCW of the numerically controlled oscillator.

[0017] Further, the method of step S5-1 specifically operates as follows: When the temperature change exceeds the preset temperature difference, the frequency offset introduced by the current temperature is obtained according to the pre-stored frequency-temperature characteristic lookup table, and it is converted into the corresponding frequency control word compensation amount ΔFCW_temp. This compensation amount is directly superimposed on the frequency control word FCW of the numerically controlled oscillator in a feedforward manner.

[0018] Furthermore, after step S5, the method further includes... Step S5-2: When the change in the time difference between two consecutive samples exceeds the preset jump threshold, When this occurs, it is determined to be an abnormal jump event.

[0019] Secondly, the present invention provides a system employing an audio clock synchronization method based on a digital phase-locked loop, comprising: A reference clock input unit is used to receive an external reference clock signal or extract a reference clock signal from a digital audio stream. The deviation detection and calculation unit is connected between the reference clock input unit and the digital PLL core circuit. It is used to count the time-domain deviation between the input reference clock signal and the feedback clock signal in multiple synchronization cycles and calculate the deviation detection result. The core circuit unit of the digital PLL includes a digitally controlled oscillator, a digital phase detector, a digital loop filter, and a programmable frequency divider; The parameter adaptive adjustment unit is connected between the deviation detection and calculation unit and the digital PLL core circuit. It is used to dynamically adjust the loop bandwidth and locking parameters in the digital PLL core circuit unit according to the deviation detection result. The audio clock output unit is used to output the synchronized audio master clock.

[0020] In summary, the audio clock synchronization method and system based on digital phase-locked loop provided by this invention collects time difference sampling values ​​within M consecutive synchronization cycles, uses the least squares method to linearly fit the sampling sequence, estimates the frequency deviation by the slope of the fitted line, and evaluates the jitter characteristics by the fitting residual. While accurately estimating the clock frequency / phase deviation, it can also dynamically adjust the loop parameters according to the working state, and has excellent suppression capability for low-frequency jitter, thus optimally separating "true frequency drift" and "random jitter" in a statistical sense. Attached Figure Description

[0021] Figure 1 A flowchart illustrating an audio clock synchronization method based on a digital phase-locked loop provided in an embodiment of the present invention; Figure 2 A flowchart illustrating another audio clock synchronization method based on a digital phase-locked loop provided in an embodiment of the present invention; Figure 3A schematic diagram of an audio clock synchronization system based on a digital phase-locked loop provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the internal structure of the deviation detection and calculation unit provided in an embodiment of the present invention; Figure 5 This is a curve showing the variation of loop bandwidth with the absolute value of the error slope |k| provided in an embodiment of the present invention; Figure 6 This is a block diagram illustrating the principle of a traditional analog PLL synchronization scheme. Detailed Implementation

[0022] To further understand the features, technical means, and specific objectives and functions achieved by the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0023] Figure 1 This is a flowchart illustrating an audio clock synchronization method based on a digital phase-locked loop (PLL) according to an embodiment of the present invention. This PLL-based audio clock synchronization method is applied to PLL-based audio clock synchronization systems such as high-fidelity audio playback systems, distributed audio acquisition systems, and digital audio interface clock recovery circuit systems that are sensitive to clock jitter. The aforementioned PLL-based audio clock synchronization system includes: The reference clock input unit is used to receive an external reference clock signal or extract a reference clock signal from a digital audio stream (such as SPDIF, I2S, AES / EBU). The deviation detection and calculation unit is connected between the reference clock input unit and the digital PLL core circuit. It is used to statistically analyze the time-domain deviation between the input reference clock signal and the feedback clock signal in multiple synchronization cycles and calculate the deviation detection result. Specifically, the deviation detection and calculation unit integrates a time-to-digital converter (TDC), a median filter module, and a least-squares fitting calculation module. It is responsible for multi-cycle clock deviation acquisition, abnormal data preprocessing, time-domain deviation statistical calculation, separating frequency deviation from phase jitter, and outputting accurate clock deviation characteristic parameters. The core circuit unit of the digital PLL, including the digitally controlled oscillator (DCO), digital phase detector, digital loop filter, and programmable frequency divider, is the core carrier for clock generation and frequency phase closed-loop correction. It is responsible for outputting the original audio master clock and generating the feedback clock. The parameter adaptive adjustment unit is connected between the deviation detection and calculation unit and the digital PLL core circuit. It is used to dynamically adjust the loop bandwidth and locking parameters in the digital PLL core circuit unit according to the deviation detection result. The audio clock output unit is used to output the synchronized audio master clock (MCLK).

[0024] like Figures 1 to 4 As shown, this audio clock synchronization method based on a digital phase-locked loop includes steps S1-S5, as detailed below: Step S1: Receive the reference clock signal and the feedback clock signal, compare the reference clock signal and the feedback clock signal, and obtain the time difference between their corresponding effective edges. T; where the reference clock signal is provided by an external high-precision clock or extracted from a digital audio stream (such as SPDIF, I2S, AES / EBU) and serves as the system's time base. The feedback clock is generated by dividing the audio master clock MCLK output by the digitally controlled oscillator (DCO) using a programmable frequency divider.

[0025] Specifically, the reference clock input unit acquires the base clock and outputs a stable reference clock signal as the system's time base through external high-precision clock input or digital audio stream parsing. The digitally controlled oscillator (DCO) in the digital PLL core circuit unit outputs the original audio master clock MCLK, which is then divided by an internal programmable frequency divider to generate a synchronous feedback clock signal, thus constructing a closed-loop feedback link.

[0026] like Figure 4 As shown, the time-to-digital converter (TDC) built into the deviation detection and calculation unit receives a reference clock signal and a feedback clock signal. The effective edge of the reference clock signal is used as the TDC start signal, and the in-phase effective edge of the feedback clock signal is used as the TDC stop signal. The TDC outputs the time difference ΔT between the corresponding edges of the two clock signals. This time difference directly represents the phase error of the current cycle. The TDC time resolution is preferably 10ps to 100ps.

[0027] In this embodiment, when ΔT>0, the feedback clock lags behind the reference clock; when ΔT<0, the feedback clock leads the reference clock; when ΔT is constant, the phase difference is fixed and there is no frequency deviation; however, if ΔT gradually increases / decreases, there is a frequency deviation, which requires subsequent correction operations.

[0028] Step S2: The deviation detection and calculation unit calculates the time difference between the reference clock signal and the feedback clock signal over M consecutive synchronization cycles. T is sampled to obtain an initial time difference sequence set X={ composed of M sampled values. , ,..., }; where M is the sampling window length, which can be adaptively adjusted according to jitter, and M is a configurable parameter, preferably M≥16. Step S3: The deviation detection and calculation unit sets the initial time difference sequence X={ , ,..., The sampled values ​​in} are preprocessed using median filtering to obtain the effective time difference sequence set Y={ , ,..., };in, This represents the time difference after preprocessing for the i-th synchronization cycle. , The corresponding period number is In the effective time difference sequence set Y, the time differences yi are arranged sequentially according to the sampling time. Each sampled value is labeled to obtain the time differences in the effective time difference sequence set Y. The corresponding permutation number, also known as the period number. .

[0029] Because metastability, power supply noise, and signal interference can all produce single-point jump anomalies in the initial time difference sequence of TDC output (occurring only in a single cycle, with an amplitude much larger than normal jitter), these anomalies will severely damage the slope and residual accuracy of subsequent least squares fitting, leading to incorrect bandwidth adjustment.

[0030] To this end, this invention employs a median filter with a window length of 5 to preprocess the initial time difference sequence, thereby removing single-point jump values ​​from the initial time difference sequence set, ensuring the authenticity and stability of the time difference sequence, avoiding outliers from interfering with the slope and residual calculation accuracy of subsequent least squares fitting, and improving the loop's anti-interference capability. Specifically, the process includes the following steps: S31. Construct a sliding window of length m; wherein m is preferably 5, but other lengths can be selected as needed; S32, Based on the initial time difference sequence set X={ , ,..., Sort the m sampling points within the sliding window, and take the median value after sorting the data within the sliding window as the time difference output result corresponding to the current sampling point; S33. Move the sliding window and output the corresponding time difference results for each sampling point to obtain the set of valid time difference sequences Y={ , ,..., }

[0031] Step S4: Use the least squares method to analyze the data points ( , Perform a linear fit and obtain the equation of the fitted line: ; Where k is the slope of the fitted line, representing the change in time difference for each synchronization cycle, in seconds per cycle; b is the intercept of the fitted line, representing the initial phase deviation, in seconds. The formula for calculating the slope k is: The physical meaning of slope k: When k>0, the feedback clock frequency is faster than the reference clock, and the time difference accumulates and increases with the number of cycles. When k < 0, the feedback clock frequency is slower than the reference clock, and the time difference decreases cumulatively as the number of cycles increases.

[0032] The formula for calculating the intercept b is: The intercept b reflects the initial phase deviation between the two clock signals and can be used for initial phase alignment calibration of a digitally controlled oscillator (DCO).

[0033] Step S5: Calculate the frequency deviation based on the slope k. And accordingly, adjust the synchronized audio clock signal output by the numerically controlled oscillator; among which, The reference clock period (i.e., the nominal time interval of the synchronization period) is in seconds. This is the nominal output frequency of the numerically controlled oscillator, measured in Hz.

[0034] In this invention, since the unit of slope k is "seconds / cycle", it represents the accumulated time deviation in each synchronization cycle, and its conversion relationship with relative frequency deviation (ppm) is as follows: For example: when When =20.833us, corresponding It is approximately 0.048 ppm.

[0035] Specifically, the method in step S5 includes the following steps: The parameter adaptive adjustment unit calculates the frequency deviation based on the slope k. ; Based on the calculated frequency deviation Calculate the adjustment amount of the frequency control word (FCW). ; where round() represents the rounding operation, and the frequency resolution is... = , This refers to the operating clock frequency of a digitally controlled oscillator (DCO) with a bit width of W. The ΔFCW is superimposed on the current frequency control word FCW to obtain the updated frequency control word FCW_new; The digitally controlled oscillator (DCO) accumulates the phase with FCW_new as the step value in each system clock cycle, and the overflow signal of the phase accumulator is shaped by the audio clock output unit to output a synchronized audio clock signal; wherein the digitally controlled oscillator (DCO) adopts a phase accumulator structure, and the output frequency has a linear corresponding relationship with the frequency control word FCW.

[0036] By adjusting the frequency control word in real time, the audio clock output by the digitally controlled oscillator (DCO) can quickly track the reference clock, achieve precise synchronization of frequency and phase, and maintain extremely low output jitter.

[0037] In some embodiments, before step S5, the method further comprises Step S4-1: The parameter adaptive adjustment unit dynamically adjusts the loop bandwidth according to the absolute value of the slope k, that is, dynamically adjusts the bandwidth parameter of the digital loop filter according to the absolute value of the slope k; when |k|>K1, the loop bandwidth is adjusted to a wide bandwidth; when |k|<K2, the loop bandwidth is adjusted to a narrow bandwidth; when |k| is in the interval [K2, K1], the loop bandwidth has a linear relationship with |k|: ; Wherein, K1 (first threshold): corresponds to the equivalent slope with a relative frequency deviation of 50 ppm; K2 (second threshold): corresponds to the equivalent slope with a relative frequency deviation of 1 ppm; is denoted as the proportional path gain coefficient of the loop filter, are respectively denoted as the maximum value and the minimum value of the proportional path gain coefficient in the digital loop filter.

[0038] Specifically, when |k|>K1, it is determined that the system is in the frequency acquisition stage (Acquisition Mode). At this time, the frequency deviation is large and fast tracking is required. The system adopts a wide loop bandwidth (corresponding to a larger proportional path gain coefficient and integral path gain coefficient ), so as to accelerate the locking speed; When |k|<K2, it is determined that the system is in the locked hold stage (Locked Mode). At this time, the frequencies are basically synchronized, and jitter suppression needs to be focused on. The system adopts a narrow loop bandwidth (corresponding to smaller and ), so as to maximize the suppression of jitter transfer; When K2≤|k|≤K1, it is determined that the system is in the transition stage (Transition Mode). In order to avoid the phase hit of the output clock caused by the sudden change of loop parameters, the loop bandwidth and |k| have a linear relationship for smooth transition.

[0039] In this embodiment, the larger proportional path gain coefficient in the wide loop bandwidth and integral path gain coefficient Refers to the proportional path gain coefficient in this system. and integral path gain coefficient The maximum value; a smaller proportional path gain coefficient in a wide loop bandwidth. and integral path gain coefficient Refers to the proportional path gain coefficient in this system. and integral path gain coefficient The minimum value.

[0040] In some embodiments, prior to step S5, the method further includes... Step S4-2: Calculate the root mean square value of the least squares fit residuals. : When the root mean square value of the residual Exceeding the preset threshold When the sampling window length M is automatically extended according to the preset setting, the preset setting refers to the sampling window length M being determined based on the root mean square value of the residual. With preset threshold The comparison results switch between two sampling window lengths. For example, when the sampling window length M can be 32 or 128, the system defaults to a sampling window length of M=32. When the root mean square value of the residual... Exceeding the preset threshold At this time, the system automatically extends the sampling window length M from 32 to 128 to improve the frequency resolution of low-frequency periodic interference, and at the same time enables the notch filter to achieve targeted suppression of specific interference frequencies.

[0041] Specifically, the parameter adaptive adjustment unit adjusts the residual root mean square value of the least square fit calculated by the operation unit by the deviation detection. With preset threshold Comparisons are made to achieve jitter classification and adaptive processing. When... When: The input jitter is determined to be mainly random jitter, and statistical averaging can effectively suppress it; when When the input reference clock is determined to contain strong deterministic jitter (such as periodic power supply ripple interference), the system automatically extends the sampling window length M (for example, from 32 to 128) to improve the frequency resolution of low-frequency periodic jitter, and combines it with a notch filter to specifically suppress jitter components at specific frequencies.

[0042] In a specific application of this embodiment, under an ideal, interference-free locked state, the system is allowed to operate normally, continuously collecting multiple sets (e.g., 1000 sets) of residual root mean square values ​​corresponding to M=32 sampling periods. , ... ; Statistically analyze all benchmark samples to obtain the benchmark mean μ and benchmark standard deviation σ of the inherent random jitter; where, a preset threshold is used. = μ + N * σ, where N is configurable and is typically 3 to 6.

[0043] In some embodiments, prior to step S5 of the present invention, the method further includes... Step S5-1: Obtain the temperature compensation amount according to the pre-stored frequency-temperature characteristic lookup table (LUT) and directly feed forward to correct the frequency control word FCW of the digitally controlled oscillator (DCO).

[0044] Temperature compensation and the adaptive digital phase-locked loop of the present invention form a dual closed-loop regulation architecture. Temperature compensation is used to quickly suppress large frequency deviations caused by temperature changes, and the adaptive loop is used for subsequent accurate tracking and phase locking, thereby ensuring high-precision, low-jitter synchronous output of the audio clock signal across the entire temperature range.

[0045] Specifically, when the temperature change exceeds the preset temperature difference, the frequency offset introduced by the current temperature is obtained according to the pre-stored frequency-temperature characteristic lookup table (LUT), and it is converted into the corresponding frequency control word compensation amount ΔFCW_temp. This compensation amount is directly superimposed on the frequency control word FCW of the digitally controlled oscillator (DCO) in a feedforward manner to quickly offset the frequency deviation caused by temperature drift. The preset temperature difference is set to 2℃, but it can also be set to other temperature differences as needed.

[0046] Correspondingly, the audio clock synchronization system based on a digital phase-locked loop of the present invention also includes a temperature compensation unit connected to the deviation detection and calculation unit. This temperature compensation unit includes a temperature sensor integrated with the main control chip and maintains a frequency-temperature lookup table (LUT). When the ambient temperature changes by more than 2°C, the deviation detection and calculation unit calculates the frequency deviation... Based on this, a feedforward compensation amount proportional to the rate of temperature change is superimposed and directly applied to the frequency control word of the DCO. This allows the core circuit unit of the digital PLL to maintain a locked state without waiting for the least squares statistical convergence delay in scenarios with rapid temperature changes (such as the preheating stage of outdoor broadcasting equipment).

[0047] In some embodiments, when the audio source is switched or the clock reference source changes, the input clock may experience a large instantaneous phase jump. Following step S5, the present invention further includes... Step S5-2: When the change in the time difference between two consecutive samples exceeds the preset jump threshold, When this occurs, it is determined to be an abnormal jump event; at this time, the system forcibly clears the historical accumulator (resets). , , , And reset the sampling window (M starts counting again from 1) to prevent the least squares algorithm from making incorrect overshoot adjustments due to invalid historical data.

[0048] This invention discloses an audio clock synchronization method and system based on a digital phase-locked loop. By collecting time difference sampling values ​​within M consecutive synchronization cycles, the least squares method is used to linearly fit the sampling sequence. The slope of the fitted line is used to estimate the frequency deviation, and the fitting residual is used to evaluate the jitter characteristics. While accurately estimating the clock frequency / phase deviation, the loop parameters can be dynamically adjusted according to the working state, exhibiting excellent suppression capability for low-frequency jitter. Thus, in a statistical sense, the "true frequency drift" and "random jitter" are optimally separated.

[0049] Furthermore, this invention can extract two key pieces of information from the fitting results: the fitting slope k and the fitting residual (RMS value), and apply them in a closed-loop manner. The fitting slope precisely represents the frequency offset and is used for subsequent closed-loop bandwidth control. This is the "signal" part, which is fully utilized. The fitting residual (RMS value) quantifies and characterizes phase jitter, used to distinguish between random and deterministic jitter, and to determine whether to enable notch filtering or adjust the statistical window. This is the "noise" part, which is also analyzed and utilized. This signal separation and dual utilization mechanism, which uses both principal components and residuals, fundamentally decouples frequency offset and jitter, laying the foundation for precise synchronization of frequency and phase.

[0050] like Figure 2 As shown, in order to make the technical solution of the present invention clearer, preferred embodiments will be described below.

[0051] Step S1: Receive the reference clock signal and the feedback clock signal, compare the reference clock signal and the feedback clock signal, and obtain the time difference between their corresponding effective edges. T; Step S2: Within M consecutive synchronization cycles, calculate the time difference between the reference clock signal and the feedback clock signal. T is sampled to obtain an initial time difference sequence set X={ composed of M sampled values. , ,..., }; where M is a configurable parameter; Step S3: Set the initial time difference sequence X = { , ,..., The sampled values ​​in} are preprocessed using median filtering to obtain the effective time difference sequence set Y={ , ,..., };in, This represents the time difference after preprocessing for the i-th synchronization cycle. , The corresponding period number is ; Step S4: Use the least squares method to analyze the data points ( , Perform a linear fit and obtain the equation of the fitted line: Where k is the slope of the fitted line, representing the change in time difference for each synchronization cycle, and b is the intercept of the fitted line, representing the initial phase deviation. Step S4-1: Dynamically adjust the loop bandwidth based on the absolute value of the slope k; Step S4-2: Calculate the root mean square value of the least squares fit residuals. : When the root mean square value of the residual Exceeding the preset threshold At that time, the sampling window length M is automatically extended according to the preset settings; Step S5-1: Obtain the temperature compensation amount according to the pre-stored frequency-temperature characteristic lookup table and directly feed forward to correct the frequency control word FCW of the numerically controlled oscillator; Step S5: Calculate the frequency deviation based on the slope k. And accordingly, adjust the synchronized audio clock signal output by the numerically controlled oscillator; among which, For reference clock period, This refers to the nominal output frequency of the numerically controlled oscillator. Step S5-2: When the change in the time difference between two consecutive samples exceeds the preset jump threshold, When this occurs, it is determined to be an abnormal jump event.

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] Example 1 This embodiment provides an audio clock synchronization method based on a digital phase-locked loop, applied to a high-fidelity audio playback system, to provide a clock recovery scheme for the high-fidelity audio decoder.

[0054] A high-fidelity audio playback system consists of, for example, the following components. Figure 3 As shown, the system includes a reference clock input unit, a deviation detection and calculation unit, a digital PLL core circuit unit, a parameter adaptive adjustment unit, and an audio clock output unit.

[0055] The reference clock input unit receives the digital audio stream from the SPDIF coaxial / optical interface and recovers the output clock (BCK) and left / right channel clocks (LRCK) through an SPDIF receiver chip (such as AK4118, WM8805, CS8416). This recovered clock typically contains a significant jitter component, with a typical measured value of 5-80ns (peak-to-peak). In this embodiment, LRCK (frequency 48kHz) is used as the reference clock signal.

[0056] The system operating parameters are as follows: Audio sampling rate: 48kHz Reference clock LRCK frequency: 48kHz Reference clock cycle =1 / 48000≈20.833μs, Target output audio master clock MCLK frequency: 24.576MHz (512 times the frequency, i.e. 512×48kHz). Nominal output frequency =24.576MHz, The feedback division ratio N = 512 (MCLK is divided by 512 to obtain a 48kHz feedback clock). The TDC in the deviation detection and calculation unit adopts an FPGA carry chain architecture with a resolution of 50 ps. Least square fitting is performed on the time difference sequence of M=64 synchronization cycles (approximately 1.33 ms).

[0057] In this embodiment, the frequency deviation calculation example is as follows: Assuming 64 cycles of measurement and least-squares fitting are performed, the slope is calculated. .

[0058] Frequency deviation The calculation process is as follows: This means the local DCO output frequency is approximately 1.18 Hz higher than the nominal value, with a relative frequency deviation of approximately... This deviation is within the DCO fine-tuning range and is much smaller than the K2 threshold (1ppm), so the system determines that it is in the lock-and-hold phase.

[0059] Based on the above data, the dynamic parameters are adjusted as follows: The DCO uses a 32-bit accumulator structure, and its operating clock... =100MHz.

[0060] Frequency resolution is The required adjustment amount is: Therefore, increasing the frequency control word of the DCO by 51 LSB steps reduces the output frequency by approximately 1.18 Hz, approaching the nominal value of 24.576 MHz.

[0061] The loop bandwidth is adjusted as follows: Simultaneously detect the fitting residual. =0.8ns. The current frequency deviation corresponding to |k| is approximately 0.048ppm, which is much smaller than the K2 threshold (1ppm), therefore the system determines that it is in the lock-and-hold phase. According to Figure 5 The adjustment curve sets the bandwidth of the digital loop filter to a narrowband mode, approximately 200Hz. This narrowband setting provides over 40dB of input jitter suppression.

[0062] The lock status is determined as follows: When |k| is less than 0.1×10 for 10 consecutive measurements (approximately 10×1.33ms≈13.3ms). - When the frequency reaches 3ns / cycle (corresponding to an deviation of approximately 0.12Hz), the system is determined to be in a locked state, and a lock indicator signal is output via GPIO (LOCKLED lights up).

[0063] Effect verification: After adopting the solution of this invention, the SPDIF input clock, which originally had a jitter of 50ns (peak-to-peak), is processed, and the jitter of the output 24.576MHz main clock is reduced to below 0.7ns (peak-to-peak). Actual measured output specifications of an audio DAC (such as the ESSES9038Q2M) driven by this MCLK are as follows: Signal-to-noise ratio (SNR): improved from 98dB to 103dB (A-weighted) Total harmonic distortion plus noise (THD+N): Improved from -85dB to -90dB (1kHz, 0dBFS) Dynamic range (DNR): up to 112dB Compared with the traditional fixed-parameter PLL solution, the ability to suppress low-frequency jitter (50Hz-100Hz power supply ripple coupling jitter) is improved by about 10-15dB, and the subjective listening experience is that the sound background is cleaner and the details are more clearly reproduced.

[0064] Example 2 This invention discloses an audio clock synchronization method based on a digital phase-locked loop (DLL). When applied to a distributed audio acquisition system, the system comprises a master node and several slave nodes. The master node outputs a reference clock or a synchronization message with a timestamp. Each slave node acquires the synchronization signal and recovers the reference clock via wired, network, or wireless means. Internally, the slave nodes employ the DLL-based audio clock synchronization method of this invention. The time difference sequence between the reference clock and the local feedback clock is measured using a time-locked loop (TDC). After median filtering preprocessing and least-squares linear fitting, frequency deviation and phase jitter are separated. The loop bandwidth is dynamically adjusted based on the fitting results to quickly track the master node clock and suppress jitter introduced by the transmission link. Finally, the slave node's DCO outputs an audio clock signal that is strictly in phase and frequency synchronized with the master node, supplying it to the audio acquisition chip. This enables sub-microsecond synchronization of the audio sampling clocks of all distributed nodes, ensuring timestamp alignment and phase consistency of multiple audio data streams, meeting the application requirements of multi-node array acquisition, synchronous recording, and beamforming.

[0065] Specifically, the distributed audio acquisition system includes an Ethernet PHY chip that supports IEEE 1588 hardware timestamps and an STM32F4 / H7 series MCU.

[0066] The system audio parameters include: Sampling rate: 48kHz Synchronization period: 1 second (periodically sent by the master node as IEEE 1588 Sync messages). MCLK: 24.576MHz (generated by the MCU timer PWM output). Here, 24.576MHz is the local slave node's synchronized audio master clock (MCLK), which is used as the nominal frequency f_nom in the frequency deviation calculation formula. It is used to convert the dimensionless relative frequency deviation (ppm) into a dimensional absolute frequency correction (Hz), thereby guiding the fine-tuning of the local crystal oscillator or DDS, as detailed below: In this embodiment, each slave node receives IEEE 1588 Precision Time Protocol (PTP) Sync messages periodically broadcast by the master node via Ethernet. The IEEE 1588 protocol eliminates the uncertainty of protocol stack software latency by adding hardware timestamps at the PHY layer. A local MCU's built-in high-precision timer (32-bit, 168MHz counting frequency, approximately 6ns resolution) captures the precise arrival time of the Sync message at the PHY, generating a timestamp sequence. Each slave node maintains a 64-bit local clock counter, driven by the system clock frequency. Each time a Sync message is received, it records: the master node's sending timestamp (extracted from the Sync message) and the local receiving timestamp (hardware captured). The difference between the two reflects the time deviation between the master and slave clocks.

[0067] Due to random queuing delays in network transmission, this timestamp difference contains a large random jitter component (typically Gaussian distributed with a standard deviation of approximately 100ns-500ns, depending on network load).

[0068] The deviation detection and processing unit processes the timestamp difference sequence of M=16 consecutive synchronization cycles (total observation time 16 seconds). Least squares estimation is used to perform linear fitting on the 16 sampling points to obtain the slope k. Multi-cycle statistical averaging effectively suppresses the influence of network random delays and accurately estimates the frequency deviation of the local crystal oscillator clock relative to the master node crystal oscillator.

[0069] In this embodiment, the frequency deviation calculation example is as follows: Assuming 16 synchronization cycles (16 seconds) of measurement, the fitted slope is k = 2.5 μs / cycle. The unit is 2.5 μs / cycle, meaning the cumulative time deviation for each synchronization cycle (1 second) is 2.5 microseconds.

[0070] Synchronization period =1 second.

[0071] Local clock nominal frequency =24.576MHz.

[0072] Frequency deviation The calculation process is as follows: Relative frequency deviation Based on the above data, the specific frequency modulation implementation method is as follows: The target output audio master clock MCLK is generated by the PWM output of the MCU timer. Since the hardware PWM adjustment granularity is relatively coarse, a 32-bit phase accumulator DDS method is used in actual engineering to obtain fine frequency adjustment capability (frequency resolution of about 0.039Hz), which can meet the requirement of accurate compensation for deviations at the 61.44Hz level.

[0073] Effect verification: Experimental results show that, after adopting the solution of this invention: The long-term synchronization accuracy between each slave node and the master node is better than ±400ns; The system runs continuously for 24 hours, and the cumulative time deviation does not exceed ±2μs; The audio data collected by each node can be seamlessly aligned and synthesized without significant phase distortion.

[0074] In summary, the audio clock synchronization method and system based on a digital phase-locked loop of the present invention has the following beneficial effects: 1. Time-domain statistical error estimation method: The least squares method is used to linearly fit the multi-period time difference sequence to estimate the frequency deviation, effectively distinguishing between long-term frequency drift and short-term random jitter.

[0075] 2. Dynamic bandwidth continuous adjustment based on fitting slope: The loop filter bandwidth is continuously and dynamically adjusted according to the value of |k|. Linear interpolation is used between the K1 and K2 thresholds to balance fast acquisition and low jitter retention, and to avoid phase step caused by parameter abrupt changes.

[0076] 3. Jitter classification and adaptive window based on fitting residuals: Random jitter and deterministic jitter are distinguished by RMS value. For strongly deterministic jitter, the statistical window is automatically extended and notch filtering is enabled. Jitter classification and notch filtering based on fitting residuals are specifically designed to identify and accurately filter out deterministic and narrowband jitter that is commonly coupled to the power supply or data bus in audio systems. This is something that existing technologies that generally rely on white noise model design loops cannot achieve.

[0077] 4. Abnormal transition detection and accumulator reset: After detecting a large instantaneous phase transition, the historical accumulator is forcibly cleared to prevent the algorithm from making erroneous overshoot adjustments; it can instantly identify and suppress large instantaneous phase measurement outliers caused by signal interference, preventing them from causing erroneous impacts on the loop's historical state, and greatly enhancing the system's robustness in complex electromagnetic environments.

[0078] 5. The audio clock synchronization system based on digital phase-locked loop integrates multiple functional units and adopts a feedforward compensation dual closed-loop architecture. It uses environmental factors such as temperature and voltage as feedforward paths and works in parallel with the phase feedback loop based on LLS. This ensures long-term frequency stability and optimizes transient response, thereby maintaining extremely low clock jitter in dynamic environments to ensure the ultimate fidelity of audio signals.

[0079] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0080] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of each unit is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0081] The steps in the method of the embodiments of the present invention can be adjusted, merged, and deleted according to actual needs. The units in the device of the embodiments of the present invention can be merged, divided, and deleted according to actual needs. In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present invention.

[0082] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. An audio clock synchronization method based on a digital phase-locked loop, characterized in that, comprising the following steps: Step S1: Receive the reference clock signal and the feedback clock signal, compare the reference clock signal and the feedback clock signal, and obtain the time difference between their corresponding effective edges. T; Step S2: Within M consecutive synchronization cycles, calculate the time difference between the reference clock signal and the feedback clock signal. T is sampled to obtain an initial time difference sequence set X={ composed of M sampled values. , ,..., }; where M is a configurable parameter; Step S3: Set the initial time difference sequence X = { , ,..., The sampled values ​​in} are preprocessed using median filtering to obtain the effective time difference sequence set Y={ , ,..., };in, This represents the time difference after preprocessing for the i-th synchronization cycle. , The corresponding period number is ; Step S4: Use the least squares method to analyze the data points ( , Perform a linear fit and obtain the equation of the fitted line: Where k is the slope of the fitted line, representing the change in time difference for each synchronization cycle, and b is the intercept of the fitted line, representing the initial phase deviation. Step S5: Calculate the frequency deviation based on the slope k. And accordingly, adjust the synchronized audio clock signal output by the numerically controlled oscillator; among which, For reference clock period, This is the nominal output frequency of the numerically controlled oscillator.

2. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, The method of step S3 includes the following steps: S31. Construct a sliding window with a length of m; S32, Based on the initial time difference sequence set X={ , ,..., Sort the m sampling points within the sliding window, and take the median value after sorting the data within the sliding window as the time difference output result corresponding to the current sampling point; S33. Move the sliding window and output the corresponding time difference results for each sampling point to obtain the set of valid time difference sequences Y={ , ,..., } 3. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, The method of step S5 includes the following steps: Calculate the frequency deviation based on the slope k. ; Based on the calculated frequency deviation Calculate the frequency control word adjustment amount ; where round() represents the rounding operation, and the frequency resolution is... = , This refers to the operating clock frequency of a numerically controlled oscillator with a bit width of W. Superpose ΔFCW on the current frequency control word FCW to obtain an updated frequency control word FCW_new; The numerically controlled oscillator accumulates the phase with FCW_new as the step value in each system clock cycle, and the overflow signal of the phase accumulator is shaped by the audio clock output unit and then outputs a synchronized audio clock signal; wherein, the numerically controlled oscillator adopts a phase accumulator structure, and the output frequency has a linear corresponding relationship with the frequency control word FCW.

4. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, Before the step S5, the method further comprises Step S4-1: Dynamically adjust the loop bandwidth according to the absolute value of the slope k.

5. The audio clock synchronization method based on a digital phase-locked loop according to claim 4, characterized in that, The specific operation of the method in step S4-1 is as follows: When |k|>K1, adjust the loop bandwidth to a wide bandwidth; When |k|<K2, adjust the loop bandwidth to a narrow bandwidth; When |k| is in the interval [K2, K1], the loop bandwidth is linearly related to |k|: ; Wherein, K1 corresponds to an equivalent slope with a relative frequency deviation of 50 ppm, and K2 corresponds to an equivalent slope with a relative frequency deviation of 1 ppm. This refers to the proportional path gain coefficient of the loop filter.

6. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, Before the step S5, the method further comprises Step S4-2: Calculate the root mean square value of the least squares fit residuals. : When the root mean square value of the residual Exceeding the preset threshold At that time, the sampling window length M is automatically extended according to the preset settings.

7. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, Before the step S5, the method further comprises Step S5-1: Obtain a temperature compensation amount according to a pre-stored frequency-temperature characteristic lookup table, and directly feed-forward correct the frequency control word FCW of the numerically controlled oscillator.

8. The audio clock synchronization method based on a digital phase-locked loop according to claim 7, characterized in that, The specific operation of the method in step S5-1 is as follows: When the temperature change exceeds a preset temperature difference, acquire the frequency offset introduced by the current temperature according to the pre-stored frequency-temperature characteristic lookup table, convert it into a corresponding frequency control word compensation amount ΔFCW_temp, and directly superpose this compensation amount to the frequency control word FCW of the numerically controlled oscillator in a feed-forward manner.

9. The audio clock synchronization method based on a digital phase-locked loop according to claim 1, characterized in that, After the step S5, the method further comprises Step S5-2: When the change in the time difference between two consecutive samples exceeds the preset jump threshold, When this occurs, it is determined to be an abnormal jump event.

10. A system employing an audio clock synchronization method based on a digital phase-locked loop, characterized in that, comprising: A reference clock input unit, configured to receive an external reference clock signal or extract a reference clock signal from a digital audio stream; A deviation detection and operation unit, connected between the reference clock input unit and the digital PLL core circuit, configured to count the time-domain deviation between the input reference clock signal and the feedback clock signal within a plurality of synchronization periods, and calculate a deviation detection result; A digital PLL core circuit unit, comprising a numerically controlled oscillator, a digital phase detector, a digital loop filter, and a programmable frequency divider; A parameter adaptive adjustment unit, connected between the deviation detection and operation unit and the digital PLL core circuit, configured to dynamically adjust the loop bandwidth and locking parameters in the digital PLL core circuit unit according to the deviation detection result; An audio clock output unit, configured to output a synchronized audio main clock.

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