Microcontroller unit and modulated waveform generator for microcontroller unit

Abstract

A microcontroller unit and a modulated waveform generator for a microcontroller unit are disclosed. The microcontroller unit includes a phase-locked loop circuit configured to modulate a source clock signal using a modulation curve to generate a modulated clock signal, wherein the modulation curve has a configuration including a variable value; and a controller to load the phase-locked loop circuit with a modulated waveform having the variable value to provide the configuration of the modulation curve. The microcontroller unit and the modulated waveform generator for a microcontroller unit can apply a modulated wave having any desired modulation shape and modulation depth, enabling configurability of the modulation curve.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more specifically, to a microcontroller unit and a modulation waveform generator for the microcontroller unit. Background Technology

[0002] Switching power supplies are widely used in various applications. To achieve miniaturization and high efficiency, their switching frequencies are typically high (e.g., tens of thousands of hertz). However, such high switching frequencies can cause serious electromagnetic interference (EMI) problems, leading to power quality degradation, affecting surrounding electronic equipment, and interfering with radio waves. Therefore, many countries have established strict EMI standards. Spread spectrum clock technology is of great value in reducing electromagnetic interference and meeting electromagnetic compatibility requirements.

[0003] Traditional spectrum shaping techniques typically employ triangular modulation curves, which result in the frequency characteristics of the switching power supply being fixed within the range of this curve. Summary of the Invention

[0004] According to an embodiment of the present invention, a microcontroller unit is proposed, comprising: a phase-locked loop circuit configured to modulate a source clock signal using a modulation curve to generate a modulated clock signal, wherein the modulation curve has a configuration including variable values; and a controller configured to load a modulation waveform having variable values ​​onto the phase-locked loop circuit to achieve configurability of the modulation curve.

[0005] According to an embodiment of the present invention, a modulation waveform generator for a microcontroller unit is also proposed, comprising: an address counter configured to provide (M-1) pointers from N to (N+M-2) or from (N+M-1) to (N+1) in response to (M-1) clock signals, wherein N is an integer greater than or equal to 0 and M is an integer greater than 1; a selector configured to select different values ​​from a series of registers in response to each pointer to provide (M-1) waveform values; and an arithmetic unit for performing arithmetic operations on the waveform values ​​and an initial frequency division factor to generate a modulation waveform.

[0006] The microcontroller unit and the modulation waveform generator for the microcontroller unit described above according to various aspects of the present invention can apply a modulation wave having any desired modulation shape and modulation depth. Attached Figure Description

[0007] Figure 1 A microcontroller unit system 100 in the prior art is schematically shown;

[0008] Figure 2 A circuit diagram of a microcontroller unit system 200 according to an embodiment of the present invention is shown schematically.

[0009] Figure 3A circuit diagram of a microcontroller unit system 300 according to an embodiment of the present invention is shown schematically.

[0010] Figure 4 A circuit diagram of a microcontroller unit system 400 according to an embodiment of the present invention is shown schematically.

[0011] Figure 5 A flowchart 500 illustrating a method for generating a modulation waveform to modulate a clock signal according to an embodiment of the present invention is shown schematically. Detailed Implementation

[0012] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0013] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0014] Figure 1 A microcontroller unit system 100 according to an embodiment of the present invention is schematically illustrated. Figure 1 In the example, the microcontroller unit system 200 includes a power converter 101 for converting an input voltage Vin into an output voltage V. OThe PLL (Phase-Locked Loop) circuit 102 is used to modulate the source clock signal clki with a variable modulation curve (i.e., variable modulation waveform), thereby generating a modulated clock signal clko. This modulated clock signal clko is used to control the power converter 101.

[0015] In one embodiment of the invention, controller 103 is configured to load a modulated waveform with variable values ​​onto PLL circuit 102 to provide a configuration of the modulation curve. Controller 103 may include a lookup table (LUT) for storing the values ​​of the modulated waveform. The modulated waveform is periodic. The lookup table may contain multiple registers.

[0016] Figure 2 A microcontroller unit system 200 according to an embodiment of the present invention is schematically illustrated, wherein the circuit configuration of the phase-locked loop circuit 102 is shown in detail. Figure 2 As shown, the phase-locked loop circuit 102 includes: a phase detector 21, a filter 22, a voltage-controlled oscillator 23, and a frequency divider 24. The phase detector 21 detects the phase difference between the source clock signal clki and the feedback signal clkf, thereby generating an error signal EA. The filter 22 filters the error signal EA to generate a filtered signal LF. The voltage-controlled oscillator 23 generates a modulated clock signal clko based on the filtered signal LF. The frequency divider 24 modulates the modulated clock signal clko under the control of the controller 103 to generate the feedback signal clkf.

[0017] In one embodiment of the invention, the controller 103 may provide the frequency divider 24 with a division coefficient that has a variable value along the modulation waveform, so that the frequency divider 24 modulates the modulation clock signal clko using the division coefficient. In one embodiment of the invention, the division coefficient may be derived from the modulation waveform.

[0018] Figure 3 A microcontroller unit system 300 according to an embodiment of the present invention is schematically illustrated, wherein the circuit configuration of the controller 103 is shown in detail. Figure 3 In the example, controller 103 includes a modulation waveform generator for generating a modulation waveform MW based on a clock signal sequence CLK and an initial division factor Kd. The modulation waveform generator is configured to select different values ​​from different registers in response to each clock signal.

[0019] In one embodiment of the invention, the clock signal may be the system clock (e.g., the source clock signal clki). In other embodiments of the invention, the clock signal may be derived from the system clock (e.g., via a frequency divider) and its frequency may be lower than the system clock. For example, the clock signal may be a sub-frequency of the system clock. For example, the frequency of the clock signal may be half or a quarter of the system clock.

[0020] Specifically, such as Figure 3 As shown, the modulation waveform generator includes an address counter 31, a selector 32, and an arithmetic unit 33. The address counter 31 is configured to provide (M-1) pointers from N to (N+M-2) or from (N+M-1) to (N+1) in response to a series of clock signals CLK, where N is an integer greater than or equal to 0, and M is an integer greater than 1. The selector 32 is configured to select a different value from a series of registers 34 in response to each pointer to generate a waveform value sequence WV. The arithmetic unit 33 is configured to perform arithmetic operations on the waveform value MV and the initial frequency division factor Kd to generate the modulation waveform MW. This arithmetic operation may include addition and subtraction operations.

[0021] In one embodiment of the invention, the numerical value M can be in 6-bit form; the value stored in each register can also be a 6-bit number. The divisor factor can be in a form with more than 6 bits, such as 10 bits.

[0022] In one embodiment of the invention, the modulation waveform MW has a modulation period comprising four quadrants: a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant. The time period of each quadrant is (M-1) times the clock period of the clock signal CLK. In the first quadrant, the address counter 31 is configured to provide a series of pointers from N to (N+M-2). Accordingly, the selector 32 is configured to select the corresponding register and read a specific waveform value from the register. Subsequently, the arithmetic unit 33 is configured to add the waveform value MV to the initial division factor Kd in response to each clock signal CLK. In the second cycle, the address counter 31 is configured to provide a series of pointers from (N+M-1) to (N+1), and the arithmetic unit 33 is configured to add the waveform value MV to the initial division factor Kd in response to each clock signal. In the third clock cycle, the address counter 31 is configured to provide a series of pointers from N to (N+M-2), and the arithmetic unit 33 is configured to subtract the waveform value MV from the initial division factor Kd in response to each clock signal CLK. In the fourth quadrant, address counter 31 is configured to provide a series of pointers from (N+M-1) to (N+1), and arithmetic unit 33 is configured to subtract waveform value MV from initial frequency division factor Kd in response to each clock signal CLK.

[0023] Therefore, by setting waveform values ​​in the register, a modulated wave with any desired modulation shape and modulation depth can be applied.

[0024] In one embodiment of the invention, the microcontroller unit system can be configured to provide a modulated waveform to the frequency divider when needed. The microcontroller unit system can also provide a fixed division factor to the frequency divider when needed.

[0025] Figure 4A microcontroller unit system 400 according to an embodiment of the present invention is schematically shown, wherein the circuit configuration of the controller 103 is shown in detail. Figure 4 The microcontroller unit system 400 shown is... Figure 3 The system is basically similar to the 300 system, the difference being... Figure 4 In the example, controller 103 further includes selection circuitry 35, which can select an initial division factor Kd or a value from the modulation waveform MW in response to the enable signal FMEN.

[0026] In one embodiment of the invention, when the enable signal FMEN is high, the frequency divider 24 is configured to modulate the modulation clock signal clko using a modulation waveform; when the enable signal FMEN is low, the frequency divider 24 is configured to modulate the modulation clock signal clko using a fixed division factor (e.g., an initial division factor Kd).

[0027] Figure 5 A flowchart 500 illustrating a method for generating a modulation waveform to modulate a clock signal according to an embodiment of the present invention is shown schematically. The method includes:

[0028] Step 501: In response to (M-1) clock signals, read waveform values ​​from a register sequence with an address range of N to (N+M-2), and accumulate the waveform values ​​to the initial frequency division coefficient under each clock signal. Here, N is an integer greater than or equal to 0, and M is an integer greater than 1.

[0029] Step 502: In response to (M-1) clock signals, read waveform values ​​from the register sequence (N+M-1) to (N+1) and accumulate the waveform values ​​to the initial frequency division factor under each clock signal.

[0030] Step 503: In response to (M-1) clock signals, read waveform values ​​from a series of registers with addresses N to (N+M-2), and subtract the waveform values ​​from the initial frequency division coefficient under each clock signal.

[0031] Step 504: In response to (M-1) clock signals, read waveform values ​​from a series of registers from addresses (N+M-1) to (N+1), and subtract the waveform values ​​from the initial frequency division factor under each clock signal.

[0032] In one embodiment of the present invention, the method further includes: selecting a modulation waveform or an initial frequency division factor to modulate a clock signal in response to an enable signal FMEN.

[0033] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A microcontroller unit, comprising: A phase-locked loop circuit is configured to modulate a source clock signal using a modulation curve to generate a modulated clock signal, wherein the modulation curve has a configuration that includes variable values; A controller is used to load a modulated waveform with variable values ​​onto a phase-locked loop circuit to provide a configuration of the modulation curve.

2. The microcontroller unit according to claim 1, wherein the controller comprises: A modulated waveform generator is used to generate a modulated waveform in response to a series of clock signals, wherein the modulated waveform generator is configured to select a different value from a different register in response to each clock signal.

3. The microcontroller unit according to claim 2, wherein the controller further comprises: The selection circuit is configured to select an initial division coefficient or a value from the modulation waveform in response to an enable signal.

4. The microcontroller unit according to claim 2, wherein the modulation waveform generator comprises: The address counter is configured to provide (M-1) pointers from N to (N+M-2) or from (N+M-1) to (N+1) in response to (M-1) clock signals, where N is an integer greater than or equal to 0 and M is an integer greater than 1; The selector is configured to select a different value from a series of registers in response to each pointer, in order to provide (M-1) waveform values; The arithmetic unit is used to perform arithmetic operations on the waveform value and the initial frequency division factor to generate the modulated waveform.

5. The microcontroller unit according to claim 4, wherein: The modulated waveform has a modulation period that includes four quadrants, and the time period of each quadrant is (M-1) times the clock period of the clock signal.

6. The microcontroller unit of claim 1, wherein the phase-locked loop circuit comprises: A frequency divider is configured to modulate a clock signal using a division factor.

7. A modulation waveform generator for a microcontroller unit, comprising: The address counter is configured to provide (M-1) pointers from N to (N+M-2) or from (N+M-1) to (N+1) in response to (M-1) clock signals, where N is an integer greater than or equal to 0 and M is an integer greater than 1; The selector is configured to respond to each pointer by selecting a different value from a series of registers to provide (M-1) waveform values; The arithmetic unit is used to perform arithmetic operations on the waveform value and the initial frequency division factor to generate the modulated waveform.

8. The modulation waveform generator as claimed in claim 7, further comprising: The selection circuit is used to select the initial frequency division factor or a value in the modulation waveform in response to the enable signal.

9. The modulation waveform generator according to claim 7, wherein the modulation waveform has a modulation period comprising four quadrants, and the time period of each quadrant is (M-1) times the clock period of the clock signal.

10. The modulation waveform generator of claim 7, wherein the modulation waveform has a modulation period comprising four quadrants, and: In the first quadrant, the address counter is configured to provide (M-1) pointers from N to (N+M-2), and the arithmetic unit is configured to add the waveform value to the initial division factor in response to each clock signal; In the second quadrant, the address counter is configured to provide (M-1) pointers from (N+M-1) to (N+1), and the arithmetic unit is configured to add the waveform value to the initial division factor in response to each clock signal; In the third quadrant, the address counter is configured to provide (M-1) pointers from N to (N+M-2), and the arithmetic unit is configured to subtract the waveform value from the initial divisor in response to each clock signal; In the fourth quadrant, the address counter is configured to provide (M-1) pointers from (N+M-1) to (N+1), and the arithmetic unit is configured to subtract the initial division factor from the waveform value in response to each clock signal.

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