Injection-locked clock multiplier circuit and clock multiplier

Abstract

The application relates to the field of analog integrated circuit technology and discloses an injection-locked clock frequency multiplication circuit and a clock frequency multiplier. The injection-locked clock frequency multiplication circuit comprises a reference clock multiple frequency multiplication circuit, which is connected with an initial clock signal and outputs a multiple frequency clock signal; a subharmonic injection-locked ring oscillator circuit, which is used for frequency tuning of the multiple frequency clock signal and outputs a target frequency multiplication clock signal after conversion; a frequency locking circuit, which is used for converging the oscillation frequency of the subharmonic injection-locked ring oscillator circuit to a target locking range; and a phase adjustment circuit, which is used for adjusting the oscillation frequency of the subharmonic injection-locked ring oscillator circuit to be equal to the frequency of the initial clock signal with a preset multiple when the frequency locking circuit is working, and for controlling the frequency of the output signal of the subharmonic injection-locked ring oscillator circuit to be synchronized with the phase of the output signal after the frequency locking of the frequency locking circuit is completed. The application can enhance the suppression ability of the injection locking to jitter and reduce the noise accumulation in the ring oscillator.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to an injection-locked clock multiplier circuit and a clock multiplier. Background Technology

[0002] Traditional clock multiplier circuits typically employ a phase-locked loop (PLL) structure, primarily composed of a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider. To achieve optimal jitter performance, the PLL usually requires a suitable loop bandwidth, generally determined approximately by the intersection of the noise contributions of each loop module and the VCO phase noise curve.

[0003] Different types of voltage-controlled oscillators (VCOs) have their own advantages and limitations in terms of power consumption, area, phase noise, tuning range, and multiphase clock generation capability. The poor phase noise of ring oscillators is mainly due to the cumulative effect of device noise in the loop, while the area limitation of inductor-capacitor VCOs is mainly due to the implementation overhead of on-chip inductors.

[0004] For a sub-harmonic injection-locked ring oscillator (SILRO), its noise suppression bandwidth is proportional to the injected reference clock frequency, and a noise suppression bandwidth greater than one-tenth of the reference frequency can be achieved. Therefore, increasing the injected clock frequency can effectively enhance phase noise suppression, thereby improving jitter performance. However, practical circuits often suffer from circuit mismatches or variations in voltage, process, and temperature, leading to a deviation between the SILRO's free oscillation frequency and an integer multiple of the injected signal frequency. The larger the deviation, the more drastically the clock jitter and reference spurious emissions worsen. Therefore, existing technology requires further improvement. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide an injection-locked clock multiplier circuit and a clock multiplier to enhance the ability of injection-locked clock multiplier to suppress jitter and reduce noise accumulation in the ring oscillator.

[0006] The technical solution of the present invention is as follows: An injection-locked clock multiplier circuit includes: A reference clock multiplier circuit is used to receive the initial clock signal and output a multiplier clock signal. The subharmonic injection locked ring oscillator circuit is used to frequency tune the multi-frequency clock signal and output it after converting it into the target frequency clock signal. A frequency locking circuit is used to converge the oscillation frequency of the subharmonic injected locking ring oscillation circuit to the target locking range; The phase adjustment circuit is used to adjust the oscillation frequency of the subharmonic injection-locked ring oscillator circuit to be equal to the frequency of the initial clock signal of a preset multiple when the frequency locking circuit is working. It is also used to control the frequency of the output signal of the subharmonic injection-locked ring oscillator circuit to be synchronized with the phase of the output signal after the frequency locking circuit completes frequency locking.

[0007] Optionally, the reference clock multiplication circuit includes: A delay phase-locked loop circuit is used to receive the initial clock signal and adjust the signal delay of the initial clock signal; A multi-phase injection-locked ring oscillator is connected to the output terminal of the delay phase-locked loop circuit. The multi-phase injection-locked ring oscillator is used to convert the initial clock signal output by the delay phase-locked loop circuit into a clock signal with multiple phases before output. An edge combiner is connected to the output of the multi-phase injection-locked ring oscillator. The edge combiner is used to combine clock signals of multiple phases and output a multi-frequency clock signal.

[0008] Optionally, the delay phase-locked loop circuit includes: A reference clock buffer is used to receive the initial clock signal and then buffer and amplify it before output. A voltage-controlled delay line is connected to the output of the reference clock buffer, and the voltage-controlled delay line is used to adjust the signal delay of the initial clock signal. A phase detector is used to detect the phase difference between the delayed initial clock signal and the reference clock signal output by the voltage-controlled delay line and output a phase detection signal. A charge pump is connected to the output terminal of the phase detector, and the charge pump is used to output a control signal to the voltage-controlled delay line according to the phase detection signal; The first buffer is disposed between the output terminal of the voltage-controlled delay line and the input terminal of the phase detector; The second buffer is disposed between the output of the multi-phase injection-locked ring oscillator and the input of the edge combiner.

[0009] Optionally, the subharmonic injection locked ring oscillator circuit includes: The delay unit circuit is used to perform differential conversion on the multi-frequency clock signal and output the target multi-frequency clock signal. A switching current source array is connected to the delay unit circuit, and the switching current source array is used to adjust the oscillation frequency coverage range of the delay unit circuit.

[0010] Optionally, the switching current source array includes: A normally open current source is used to control the oscillation of the delay unit circuit; A high-frequency / low-frequency switching current source is used to increase the frequency range of the delay unit circuit; A multi-channel thermometer code-controlled current source array is used to increase the current matching accuracy of the delay unit circuit.

[0011] Optionally, the frequency locking circuit includes: The first frequency divider is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The first frequency divider is used to divide the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit and then output it. A counter is connected to the output of the first frequency divider. The counter counts the rising edges of the target frequency multiplier clock signal after frequency division output by the first frequency divider and outputs a counting signal. A comparator, connected to the output of the counter, is used to compare the counting signal with a reference value and output a counting comparison signal; A switch switching module is connected to the output terminal of the comparator. The switch switching module is used to adjust the oscillation frequency of the subharmonic injection locking ring oscillation circuit to converge to the target locking range according to the counting comparison signal. The second frequency divider is used to receive the reference signal, divide the reference signal by frequency, and output an enable signal to the counter and the comparator.

[0012] Optionally, the phase adjustment circuit includes: A switching circuit is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The switching circuit is used to receive the initial clock signal, compare the initial clock signal with the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit, and output a frequency comparison signal. A low-pass filter is connected to the subharmonic injection locked ring oscillator circuit, and the low-pass filter is used to output a control voltage to the subharmonic injection locked ring oscillator circuit. A voltage-to-current converter is disposed between the output terminal of the switching circuit and the input terminal of the low-pass filter. The voltage-to-current converter is used to adjust the control voltage output by the low-pass filter according to the frequency comparison signal, so as to control the frequency of the output signal of the subharmonic injection locked ring oscillator circuit to be synchronized with the phase of the output signal.

[0013] Optionally, the voltage-to-current converter includes: A polarity detector is used to detect the polarity of the multi-frequency clock signal output to the voltage-current converter and control the polarity of the voltage-current converter to be the same as the polarity of the multi-frequency clock signal.

[0014] Optionally, the injection-locked clock multiplier circuit further includes: A pulse generator is disposed between the output terminal of the reference clock multi-frequency circuit and the input terminal of the subharmonic injection locked ring oscillator circuit. The pulse generator is used to convert the multi-frequency clock signal output by the reference clock multi-frequency circuit into a pulse signal and output it to the subharmonic injection locked ring oscillator circuit. An output buffer is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The output buffer is used to shape and buffer the target frequency multiplication clock signal output by the subharmonic injection locked ring oscillator circuit before outputting it.

[0015] The present invention also proposes a clock multiplier, including the injection-locked clock multiplier circuit described above.

[0016] This invention employs a two-stage cascaded injection-locked clock multiplier architecture, consisting of a reference clock multiplier circuit and a subharmonic injection-locked ring oscillator circuit. The first stage, the reference clock multiplier circuit, converts the initial clock signal into a multiplied clock signal, increasing the injection clock frequency of the second-stage circuit. The second-stage subharmonic injection-locked ring oscillator circuit converts the multiplied clock signal into a narrow injection pulse for subharmonic injection locking. Unlike traditional ring-based phase-locked loops, this invention achieves subharmonic injection locking through narrow pulse injection, reducing in-band phase noise. The phase adjustment circuit precisely eliminates the phase shift caused by injection, further suppressing in-band phase noise. The two-stage cascaded structure increases the injection frequency of the injection-locked clock multiplier and expands the noise suppression bandwidth. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 This is a functional module schematic diagram of an embodiment of the injection-locked clock multiplier circuit of the present invention.

[0019] Figure 2 This is a functional module schematic diagram of an embodiment of the reference clock multiplication circuit of the present invention.

[0020] Figure 3 This is a functional module schematic diagram of an embodiment of the subharmonic injection locked ring oscillator circuit of the present invention.

[0021] Figure 4 This is a schematic diagram of the circuit structure of the delay unit circuit of the present invention.

[0022] Figure 5 This is a schematic diagram of the circuit structure of an embodiment of the switching current source array of the present invention.

[0023] Figure 6 This is a functional module schematic diagram of an embodiment of the frequency locking circuit of the present invention.

[0024] Figure 7 This is a functional module schematic diagram of an embodiment of the phase adjustment circuit of the present invention.

[0025] Figure 8 This is a schematic diagram illustrating the working principle of the phase adjustment circuit of the present invention.

[0026] Figure 9 This is a schematic diagram of the circuit structure of an embodiment of the voltage-current converter of the present invention.

[0027] Figure 10 This is a schematic diagram of the output of the detectors with different occurrence positions and polarities of the initial clock signal in this invention.

[0028] Figure 11 This is a timing diagram of the frequency locking circuit and phase adjustment circuit of the present invention.

[0029] Figure 12 This is a phase noise characteristic diagram of the injection-locked clock multiplier circuit of the present invention.

[0030] Figure 13 This is a schematic diagram of the phase noise from the simulation of the injection-locked clock multiplier circuit of this invention.

[0031] Figure 14 This is a schematic diagram of the output spectrum of the simulation of the injection-locked clock multiplier circuit of the present invention.

[0032] Figure 15 This is a schematic diagram of the phase noise and jitter of the target frequency multiplication clock signal with different frequency multiplication coefficients according to the present invention.

[0033] Figure labeling: 10, Reference clock multiplication circuit; 111, Reference clock buffer; 112, Voltage-controlled delay line; 113, Phase detector; 114, Charge pump; 115, First buffer; 116, Second buffer; 12, Multi-phase injection-locked ring oscillator; 13, Edge combiner; 20, Subharmonic injection-locked ring oscillator circuit; 21, Delay unit circuit; 22, Switched current source array; 30, Frequency lock circuit; 31, Counter; 32, Comparator; 33, Switching module; 34, First frequency divider; 35, Second frequency divider; 40, Phase adjustment circuit; 41, Switching circuit; 42, Voltage-to-current converter; 43, Low-pass filter; 50, Pulse generator; 60, Output buffer. Detailed Implementation

[0034] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0035] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0036] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0037] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0038] Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0039] Traditional clock multiplier circuits typically employ a phase-locked loop (PLL) structure, primarily composed of a phase-frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider. To achieve optimal jitter performance, the PLL usually requires a suitable loop bandwidth, generally determined approximated by the intersection of the noise contributions of each loop module and the VCO's phase noise curve. Simultaneously, the in-band noise of the PLL is typically dominated by the PFD / CP noise, while the overall jitter performance remains largely limited by the VCO's own phase noise, necessitating a larger loop bandwidth to suppress the VCO's noise contribution. However, for loop stability considerations, the maximum loop bandwidth is often limited by the input reference frequency.

[0040] Different types of voltage-controlled oscillators (VCOs) have their own advantages and limitations in terms of power consumption, area, phase noise, tuning range, and multiphase clock generation capability. Ring oscillators have advantages such as simple structure, small area, wide tuning range, and ease of implementing multiphase output, but their phase noise performance is relatively poor. In contrast, inductor-capacitor VCOs have the advantages of low phase noise and high energy efficiency, but they usually occupy a large chip area due to the need for on-chip passive inductors. Therefore, in PLL design, it is difficult for both types of oscillators to simultaneously meet the multiple requirements of small area, low power consumption, low phase noise, and multiphase clock generation. The poor phase noise of ring oscillators is mainly due to the cumulative effect of device noise in the loop, while the area limitation of inductor-capacitor VCOs is mainly due to the implementation overhead of on-chip inductors. If a ring oscillator is used, a very large loop bandwidth is usually required to suppress its phase noise; however, due to the limitations of loop stability and input reference clock frequency, this bandwidth is often difficult to further expand, thus limiting further optimization of jitter performance. Therefore, there is still considerable room for improvement in the jitter performance of PLL structures.

[0041] On the other hand, for a sub-harmonic injection-locked ring-oscillator (SILRO), its noise suppression bandwidth is proportional to the injected reference clock frequency, and it can achieve a noise suppression bandwidth greater than one-tenth of the reference frequency. Therefore, increasing the injected clock frequency can effectively enhance phase noise suppression capabilities, thereby improving jitter performance. However, practical circuits often suffer from circuit mismatches or variations in voltage, manufacturing process, and temperature, leading to a deviation between the SILRO's free oscillation frequency and an integer multiple of the injected signal frequency. The larger the deviation, the more drastically the clock jitter and reference spurious signals worsen.

[0042] To address the aforementioned problems, this invention proposes an injection-locked clock multiplier circuit.

[0043] Reference Figure 1 In one embodiment, the injection-locked clock multiplier circuit includes: Reference clock multiplication circuit 10 is used to receive the initial clock signal and output a multiplication clock signal; The subharmonic injection locked ring oscillator circuit 20 is used to frequency tune the multi-frequency clock signal and output it after converting it into the target frequency clock signal. Frequency locking circuit 30 is used to converge the oscillation frequency of the subharmonic injection locking ring oscillation circuit 20 to the target locking range; The phase adjustment circuit 40 is used to adjust the oscillation frequency of the subharmonic injection locked ring oscillation circuit 20 to be equal to the frequency of the initial clock signal of a preset multiple when the frequency locking circuit 30 is working. It is also used to control the frequency of the output signal of the subharmonic injection locked ring oscillation circuit 20 to be synchronized with the phase of the output signal after the frequency locking circuit 30 completes frequency locking.

[0044] In this embodiment, the reference clock multiplier circuit 10 can receive the initial clock signal and perform preliminary frequency multiplication on the input initial clock signal, providing an injection reference signal that meets the frequency requirements for the subsequent subharmonic injection-locked ring oscillator circuit 20. This reduces the harmonic order requirement for subharmonic injection-locking, narrows the frequency tuning range of the subsequent ring oscillator, and reduces the overall circuit design complexity, phase noise, and power consumption. The specific conversion factor of the reference clock multiplier circuit 10 can be set according to actual conditions and user needs. The subharmonic injection-locked ring oscillator circuit 20 can then perform frequency tuning on the multiplied clock signal, converting it into a target multiplied clock signal before outputting it. Specifically, the subharmonic injection-locked ring oscillator circuit 20 utilizes the subharmonic injection-locking principle to automatically lock the oscillation frequency of the ring oscillator to an integer multiple of the target frequency of the injection reference signal. Compared to the traditional full phase-locked loop frequency multiplication structure, it eliminates the need for complex loop filter design and effectively suppresses... The frequency locking circuit 30 controls reference clock glitches, enabling the output of a high-speed oscillating clock with a frequency much higher than the injected reference signal frequency. It also boasts advantages such as fast locking speed and low output phase noise. The frequency locking circuit 30 converges the oscillation frequency of the subharmonic injection-locked ring oscillator circuit 20 to the target locking range, improving the circuit's adaptability to process fluctuations and temperature / humidity changes, and ensuring output frequency stability. The phase adjustment circuit 40 adjusts the oscillation frequency of the subharmonic injection-locked ring oscillator circuit 20 to be equal to the initial clock signal frequency at a preset multiple when the frequency locking circuit 30 is operating. It can also control the frequency and phase synchronization of the output signal of the subharmonic injection-locked ring oscillator circuit 20 after the frequency locking circuit 30 completes frequency locking. Specifically, it can finely adjust the phase of the injected clock signal, aligning the injected clock edge with a specific phase point of the internal oscillation waveform of the ring oscillator, thereby maximizing injection locking efficiency and reducing output clock noise and spurious signals. The phase adjustment circuit 40 can also perform closed-loop fine-tuning based on the phase error after injection locking to compensate for phase shifts introduced by the frequency multiplier, buffer, and ring oscillator at different process angles.

[0045] The technical solution of this invention specifically constructs a two-stage cascaded Injection Locked Clock Multiplier (ILCM) architecture using a reference clock multiplier circuit 10 and a subharmonic injection-locked ring oscillator circuit 20. The first-stage reference clock multiplier circuit 10 converts the initial clock signal into a multiplied clock signal, increasing the injection clock frequency of the second-stage circuit. The second stage is the subharmonic injection-locked ring oscillator circuit, which converts the multiplied clock signal into a narrow injection pulse for subharmonic injection locking of the SILRO. This solution achieves subharmonic injection locking through narrow pulse injection, reducing in-band phase noise. The phase adjustment circuit 40 can accurately eliminate the phase shift caused by injection, further suppressing in-band phase noise. Therefore, the two-stage cascaded structure of this solution increases the injection frequency of the ILCM and expands the noise suppression bandwidth.

[0046] In one embodiment, the reference clock multiplication circuit 10 includes: A delay phase-locked loop circuit is used to receive the initial clock signal and adjust the signal delay of the initial clock signal; A multi-phase injection-locked ring oscillator 12 is connected to the output terminal of the delay phase-locked loop circuit. The multi-phase injection-locked ring oscillator 12 is used to convert the initial clock signal output by the delay phase-locked loop circuit into a clock signal with multiple phases before outputting it. Edge combiner 13 is connected to the output of the multi-phase injection-locked ring oscillator 12. Edge combiner 13 is used to combine clock signals of multiple phases and output a multi-frequency clock signal.

[0047] In this embodiment, to improve the frequency multiplication factor and extend the noise suppression bandwidth of the injection-locked clock multiplier, a reference clock multiplication circuit 10 structure based on a delay-locked loop (DLL), a multi-phase injection-locked ring oscillator 12, and an edge combiner 13 is proposed, as follows: Figure 2 As shown, this structure, through the combination of a DLL and a multi-phase injection-locked ring oscillator 12, effectively overcomes the trade-off between phase accuracy and phase noise in traditional injection-locked ring oscillators. Utilizing a high-precision, low-noise multi-phase clock combined with an edge combiner 13, a high-frequency clock signal with low jitter and low spurious emissions can be generated. Compared to a scheme that uses only a DLL multi-phase clock and an edge combiner 13 to achieve frequency multiplication, this embodiment employs a multi-phase injection-locked ring oscillator 12 to further suppress phase errors, thereby obtaining a high-frequency output with more accurate duty cycle and lower noise. Furthermore, the high-quality multi-phase clock provided by this structure avoids the introduction of complex additional calibration circuitry, thus simplifying system implementation.

[0048] Furthermore, referring to Figure 2 In one embodiment, the delay-locked loop circuit includes: Reference clock buffer 111 is used to receive the initial clock signal and output it after buffering and amplification. A voltage-controlled delay line 112 is connected to the output terminal of the reference clock buffer 111, and the voltage-controlled delay line 112 is used to adjust the signal delay of the initial clock signal. Phase detector 113 is used to detect the phase difference between the delayed initial clock signal and the reference clock signal output by the voltage-controlled delay line 112 and output a phase detection signal; A charge pump 114 is connected to the output terminal of the phase detector 113. The charge pump 114 is used to output a control signal to the voltage-controlled delay line 112 according to the phase detection signal. The first buffer 115 is disposed between the output terminal of the voltage-controlled delay line 112 and the input terminal of the phase detector 113; The second buffer 116 is disposed between the output of the multi-phase injection locked ring oscillator 12 and the input of the edge combiner 13.

[0049] In this embodiment, the main function of the reference clock buffer 111 is to receive the input reference clock signal and buffer it to provide a stable clock signal to subsequent circuits. This improves the signal's driving capability and reduces signal attenuation and distortion during transmission. The voltage-controlled delay line 112 is used to generate an adjustable delay signal. By adjusting the input voltage, the voltage-controlled delay line 112 can change the signal delay, thereby achieving precise control of the clock signal phase. This is the core part of the DLL, capable of adjusting the phase of the output signal based on feedback from the phase detector 113. The phase detector 113 compares the phase difference between the reference clock signal and the initial clock signal delayed by the voltage-controlled delay line 112. It outputs an error signal proportional to the phase difference to indicate the current phase relationship. This error signal is used to adjust the delay of the voltage-controlled delay line 112 to achieve phase locking. The charge pump 114 receives the error signal from the phase detector 113 and converts it into a current signal. It adjusts the delay by increasing or decreasing the charge applied to the control voltage Vtune of the voltage-controlled delay line. The output of the charge pump 114 is typically filtered to smooth the control signal. The first buffer 115 and the second buffer 116 can serve as signal buffers.

[0050] For the reference clock multiplier circuit 10, changing the multiplication factor of the preceding stage can be achieved by changing the number of delay units and the number of delay units in the injection-locked ring oscillator, thus replacing the first-stage quadruple frequency multiplier with a double, triple, hexaple, or octave frequency multiplier; or by changing the structure of the logic edge combiner 13, but the function remains frequency multiplication.

[0051] In one embodiment, the subharmonic injection locked ring oscillator circuit 20 includes: Delay unit circuit 21 is used to differentially convert the multi-frequency clock signal and output the target multi-frequency clock signal; A switching current source array 22 is connected to the delay unit circuit 21, and the switching current source array 22 is used to adjust the oscillation frequency coverage range of the delay unit circuit 21.

[0052] Further, in one embodiment, the switching current source array 22 includes: A normally open current source is used to control the oscillation of the delay unit circuit 21. A high-low frequency switching current source is used to increase the frequency range of the delay unit circuit 21; A multi-channel thermometer code-controlled current source array is used to increase the current matching accuracy of the delay unit circuit 21.

[0053] In this embodiment, the subharmonic injection locked ring oscillator circuit 20 can be a current-tuned ring oscillator, the structure of which is as follows: Figure 3 As shown, power consumption can be reduced while widening the frequency tuning range. The delay unit circuit 21 of the ring oscillator adopts a pseudo-differential structure composed of cross-coupled inverters, and the specific circuit structure is as follows. Figure 4 As shown. The delay unit circuit 21 can control the switching current source array 22 via a 6-bit frequency control word switch, thereby extending the frequency tuning range to cover the free oscillation frequency from 1.6 GHz to 3.2 GHz. Its continuous tuning is achieved by a PMOS transistor connected to the control voltage Vtune.

[0054] Switching current source array 22, such as Figure 5 As shown, the system includes a normally open current source M2 to ensure oscillation startup and a minimum oscillation frequency; a high-to-low frequency switching current source M3 to extend the frequency range; and a multi-channel thermometer code-controlled current source array to improve current matching accuracy. Based on the control word resolution, this scheme can achieve a 63-channel thermometer code-controlled current source array within the designed frequency and power consumption. The thermometer code is generated by a binary-to-thermometer code converter, with the frequency control word FCW<5:0> as input. Compared to the binary control method, the thermometer code structure offers superior matching performance and monotonicity.

[0055] In one embodiment, the frequency locking circuit 30 includes: The first frequency divider 34 is connected to the output terminal of the subharmonic injection locked ring oscillator circuit 20. The first frequency divider 34 is used to divide the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit 20 and then output it. a counter 31, connected to the output end of the first frequency divider 34, wherein the counter 31 counts rising edges of the frequency-divided target frequency-multiplied clock signal output by the first frequency divider 34, and outputs a count signal; a comparator 32, connected to the output end of the counter 31, wherein the comparator 32 is configured to compare the count signal with a reference value, and output a count comparison signal; a switch switching module 33, connected to the output end of the comparator 32, wherein the switch switching module 33 is configured to adjust the oscillation frequency of the subharmonic injection-locked ring oscillation circuit 20 to converge within a target locking range according to the count comparison signal; a second frequency divider 35, configured to receive a reference signal, divide the frequency of the reference signal, and output an enable signal to the counter 31 and the comparator 32.

[0056] In this embodiment, since the initial free-running oscillation frequency of the ring oscillator may have a large deviation from the target frequency, to ensure that the oscillation frequency can automatically converge to the target locking range when the ILCM is in operation, the structure of the frequency locking circuit 30 proposed by the present invention is as Figure 6 shown. In terms of specific circuit implementation, a divide-by-four frequency divider is cascaded after a certain output phase of the oscillator first, so as to reduce the operating frequency of the frequency locking circuit 30 and reduce power consumption. A 100MHz reference signal, i.e., REF 100M is divided by 16 to generate a 6.25MHz enable signal, which is used to control the operation window of the subsequent module. When the enable signal is at a high level, the counter 31 counts the rising edges of the oscillator output after being divided by four. By increasing the bit width of the counter 31, the frequency adjustment resolution can be improved. The output of the counter 31 is sent to the digital comparator 32 to be compared with the reference value generated by the decoder. The target frequency multiplication coefficient N is encoded to generate reference codes F<6:0>, which respectively correspond to the maximum counting periods at operating points such as 1.6 / 2 / 2.4 / 2.8 / 3.2GHz, and the correspondence between the frequency multiplication coefficient N and the outputs of the binary encoder and the decoder is shown in Table 1.

[0057] Table 1

[0058] When the enable signal is at a low level, the comparator 32 outputs R and S for characterizing the frequency relationship: when R=1, it represents Freq<F (the oscillation frequency is too low); when R=0, it represents Freq>F (the oscillation frequency is too high); when S=1, it represents Freq=F (the target range is reached). The switch switching module 33 adjusts FCW<5:0> according to the comparison result, so as to realize that the frequency gradually approaches the target value. The logical relationship between the comparator input, the comparator output and the switch switching is shown in Table 2.

[0059] Table 2

[0060] The initial frequency control word (FCW) of the system can be set to 1000000. After frequency convergence is completed, FLL_done is set high, and the FCW is locked to the target frequency control word.

[0061] In one embodiment, the phase adjustment circuit 40 includes: The switching circuit 41 is connected to the output terminal of the subharmonic injection locked ring oscillator circuit 20. The switching circuit 41 is used to receive the initial clock signal, compare the initial clock signal with the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit 20, and output the frequency comparison signal. A low-pass filter 43 is connected to the subharmonic injection locked ring oscillator circuit 20. The low-pass filter 43 is used to output a control voltage Vtune to the subharmonic injection locked ring oscillator circuit 20. A voltage-to-current converter 42 is disposed between the output terminal of the switching circuit 41 and the input terminal of the low-pass filter 43. The voltage-to-current converter 42 is used to adjust the control voltage Vtune output by the low-pass filter 43 according to the frequency comparison signal, so as to control the frequency of the output signal of the subharmonic injection locked ring oscillator circuit 20 to be synchronized with the phase of the output signal.

[0062] Further, in one embodiment, the voltage-to-current converter 42 includes: A polarity detector is used to detect the polarity of the multi-frequency clock signal output to the voltage-current converter 42 and control the polarity of the voltage-current converter 42 to be the same as the polarity of the multi-frequency clock signal.

[0063] In this embodiment, the phase adjustment circuit 40 is used to achieve precise phase synchronization of the high-frequency clock, and its structure is as follows: Figure 7 As shown. Its working principle is as follows. Figure 8 As shown. The phase adjustment circuit 40 utilizes the subharmonic injection to lock the target frequency-multiplied clock signal output by the ring oscillator circuit 20, i.e., the injected pulse INJ_Pulse, to achieve phase correction between the phase relationship between the differential ring oscillator outputs RO0 and RO180. When the injected pulse arrives, the phases of RO0 and RO180 are realigned. The ideal locking state is when the center of the injected pulse is aligned with the intersection of RO0 and RO180, at which point the blue and red integral areas are equal, and V... S_P =V S_N This means that the frequency fvco of the ring oscillator is N times the injected clock frequency Nf INJEqual; In the first case, the center of the injected pulse leads the intersection of RO0 and RO180. At this time, the area of ​​the blue shaded region is larger than the area of ​​the red shaded region, and the output voltage V S_P Less than V S_N The frequency fvco of the ring oscillator is greater than N times the injected clock frequency Nf INJ In this case, the oscillator's control voltage Vtune needs to be adjusted to reduce the oscillator's frequency; in the second case, the center of the injected pulse lags behind the intersection of RO0 and RO180. At this time, the area of ​​the blue shaded region is smaller than the area of ​​the red shaded region, and the output voltage V... S_P Greater than V S_N The frequency fvco of the ring oscillator is less than N times the injected clock frequency Nf INJ At this point, it is necessary to adjust the oscillator's control voltage Vtune to increase the oscillator's frequency.

[0064] When V S_P With V S_N When a difference exists, the voltage-to-current converter 42 generates a charging / discharging current, which adjusts the low-pass filter 43, thereby changing the control voltage Vtune. The specific circuit structure of the voltage-to-current converter 42 can be found in [reference needed]. Figure 9 Setup. To avoid charge sharing issues, a rail-to-rail operational amplifier is used as a unity-gain buffer to synchronize V. OUT With V OUT_DUM The node voltage. Furthermore, to avoid potential positive feedback problems caused by injection location uncertainty, a polarity detector was designed to determine the injection direction, such as... Figure 10 As shown. Based on different injection edge alignment relationships, the outputs PO_P and PO_N are used to control the polarity of the subsequent current-to-voltage converter, thereby ensuring loop stability. The overall cooperative working principle of the frequency lock-in circuit 30 and the phase adjustment circuit 40 is as follows: Figure 11 As shown: During the operation of the frequency lock circuit 30, the integrator output remains stable, and only the oscillation frequency is adjusted; when the frequency lock circuit 30 completes frequency locking and sets FLL_done, the phase adjustment circuit 40 starts and continuously corrects the phase of the control voltage Vtune to achieve the final precise synchronization of frequency and phase.

[0065] In one embodiment, the injection-locked clock multiplier circuit further includes: A pulse generator 50 is disposed between the output terminal of the reference clock multi-frequency circuit 10 and the input terminal of the subharmonic injection locked ring oscillator circuit 20. The pulse generator 50 is used to convert the multi-frequency clock signal output by the reference clock multi-frequency circuit 10 into a pulse signal and output it to the subharmonic injection locked ring oscillator circuit 20. The output buffer 60 is connected to the output terminal of the subharmonic injection locked ring oscillator circuit 20. The output buffer 60 is used to shape and buffer the target frequency multiplication clock signal output by the subharmonic injection locked ring oscillator circuit 20 before outputting it.

[0066] In this embodiment, the multi-frequency clock signal output by the reference clock multiplier circuit 10, i.e., the subharmonic injection signal, can be used by the pulse generator 50 to generate a 400MHz injection signal. Its pulse width is adjusted via a binary switch, ranging from 35ps to 75ps. The injection signal is injected into the subharmonic injection-locked ring oscillator circuit 20 through an NMOS transistor connected across the first-stage differential output of the ring oscillator. For details, please refer to... Figure 3 The pulse generator 50 outputs INJ, which is connected to the subharmonic injection-locked ring oscillator circuit 20. It should be noted that the multiphase reference output by the preceding reference clock multiplier circuit 10 is a wide square wave with the same period as the input reference. Second harmonic injection locking only requires a trigger at the target injection moment and does not require a continuous level input. The pulse generator 50 extracts the effective edges of each multiphase reference, generating narrow pulses with a width much smaller than the adjacent injection interval: this achieves phase-pulse locking of the oscillator, avoids interference from continuous level inputs on the oscillation core's operating state, significantly improves injection efficiency, and widens the effective locking range. The output buffer 60 can shape and buffer the target multiplied clock signal output from the subharmonic injection-locked ring oscillator circuit 20 before outputting it.

[0067] Compared to the traditional frequency-locked circuit 30, in the injected clock multiplier of this scheme, the in-band phase noise is mainly dominated by the reference clock noise. Therefore, the injection-locked technology used in this scheme can effectively reduce the in-band noise level, thereby significantly improving the output jitter performance. The injection-locked clock multiplier circuit proposed in this invention increases the injection frequency of the ILCM while improving the overall multiplication factor, and further widens the noise suppression bandwidth, thereby achieving a lower jitter output.

[0068] Meanwhile, to reduce the deviation between the free oscillation frequency of SILRO and the integer multiple of the reference frequency (Nfref) caused by voltage, process, temperature variations, or device mismatch, this invention designs a frequency locking circuit 30 to ensure that the output frequency remains stable near the desired multiple of the injected frequency (i.e., within the locking range). The frequency locking circuit 30 not only enhances the injection locking's ability to suppress jitter but also improves system robustness by continuously correcting frequency deviations. Furthermore, the frequency locking circuit 30 can introduce additional in-band noise shaping effects, helping to further suppress the noise of the ring oscillator; combined with the injection locking's suppression of low-frequency noise, it can effectively reduce noise accumulation in the ring oscillator. The phase noise characteristics of the injection-locked clock multiplier in the theoretical state of this scheme can be referenced... Figure 12 .

[0069] To better illustrate the technical concept of this invention, the injection-locked clock multiplier circuit was simulated according to the circuit structure described above. The injection-locked clock multiplier circuit designed in this application is implemented using a 65nm CMOS process, with a low-frequency power supply voltage of 1.2V. Since the function of the frequency locking circuit 30 is to adjust the oscillator frequency to the target frequency locking range, the interval between two adjacent frequency bands in the tuning range of the high-frequency ring oscillator should not be too large and exceed the locking range when designing it. Its highest tuning frequency is 3.38 GHz, and its lowest frequency is 1.37 GHz. The high-frequency power supply voltage is 1.2V, and the power consumption of the ring oscillator is 1.2 mW to 3.2 mW. During the simulation, the phase noise of the ring oscillator in both free oscillation and injection-locked states was also simulated at an output frequency of 2.4 GHz. The simulation results are as follows: Figure 13 As shown, the injected signal is a 400 MHz clock from the low-frequency multiplier module. In the final injected-locked state, the phase noise of the ring oscillator output at a 1 MHz frequency offset is -128.6 dBc / Hz, a reduction of 34 dB compared to the free oscillation state. The jitter over the integration range from 10 kHz to 40 MHz is 170.1 fs. Its output spectrum is shown below. Figure 14 As shown, the spurious signal at 400 MHz for the 2.4 GHz output clock is -51.4 dBc. Simulations also show that the jitter range of the injection-locked clock multiplier designed in this paper is 170.1 fs to 213 fs and the spurious signal range is -51.4 dBc to -54.3 dBc under different multiplication factors. Figure 15 As shown.

[0070] The present invention also proposes a clock multiplier.

[0071] In one embodiment, the clock multiplier includes the injection-locked clock multiplier circuit described above. It is understood that since the above-described injection-locked clock multiplier circuit is used in the clock multiplier of the present invention, the embodiments of the clock multiplier of the present invention include all the technical solutions of all embodiments of the above-described injection-locked clock multiplier circuit, and the achieved technical effects are exactly the same, and will not be repeated here.

[0072] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An injection-locked clock multiplier circuit, characterized in that, include: A reference clock multiplier circuit is used to receive the initial clock signal and output a multiplier clock signal. The subharmonic injection locked ring oscillator circuit is used to frequency tune the multi-frequency clock signal and output it after converting it into the target frequency clock signal. A frequency locking circuit is used to converge the oscillation frequency of the subharmonic injected locking ring oscillation circuit to the target locking range; The phase adjustment circuit is used to adjust the oscillation frequency of the subharmonic injection-locked ring oscillator circuit to be equal to the frequency of the initial clock signal of a preset multiple when the frequency locking circuit is working, and is also used to control the frequency of the output signal of the subharmonic injection-locked ring oscillator circuit to be synchronized with the phase of the output signal after the frequency locking circuit completes frequency locking. The frequency locking circuit includes: The first frequency divider is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The first frequency divider is used to divide the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit and then output it. A counter is connected to the output of the first frequency divider. The counter counts the rising edges of the target frequency multiplier clock signal after frequency division output by the first frequency divider and outputs a counting signal. A comparator, connected to the output of the counter, is used to compare the counting signal with a reference value and output a counting comparison signal; A switch switching module is connected to the output terminal of the comparator. The switch switching module is used to adjust the oscillation frequency of the subharmonic injection locking ring oscillation circuit to converge to the target locking range according to the counting comparison signal. The second frequency divider is used to receive the reference signal, divide the reference signal by frequency, and output an enable signal to the counter and the comparator. The phase adjustment circuit includes: A switching circuit is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The switching circuit is used to receive the initial clock signal, compare the initial clock signal with the target frequency multiplier clock signal output by the subharmonic injection locked ring oscillator circuit, and output a frequency comparison signal. A low-pass filter is connected to the subharmonic injection locked ring oscillator circuit, and the low-pass filter is used to output a control voltage to the subharmonic injection locked ring oscillator circuit. A voltage-to-current converter is disposed between the output terminal of the switching circuit and the input terminal of the low-pass filter. The voltage-to-current converter is used to adjust the control voltage output by the low-pass filter according to the frequency comparison signal, so as to control the frequency of the output signal of the subharmonic injection locked ring oscillator circuit to be synchronized with the phase of the output signal.

2. The injection-locked clock multiplier circuit as described in claim 1, characterized in that, The reference clock multiplication circuit includes: A delay phase-locked loop circuit is used to receive the initial clock signal and adjust the signal delay of the initial clock signal; A multi-phase injection-locked ring oscillator is connected to the output terminal of the delay phase-locked loop circuit. The multi-phase injection-locked ring oscillator is used to convert the initial clock signal output by the delay phase-locked loop circuit into a clock signal with multiple phases before output. An edge combiner is connected to the output of the multi-phase injection-locked ring oscillator. The edge combiner is used to combine clock signals of multiple phases and output a multi-frequency clock signal.

3. The injection-locked clock multiplier circuit as described in claim 2, characterized in that, The delay phase-locked loop circuit includes: A reference clock buffer is used to receive the initial clock signal and then buffer and amplify it before output. A voltage-controlled delay line is connected to the output of the reference clock buffer, and the voltage-controlled delay line is used to adjust the signal delay of the initial clock signal. A phase detector is used to detect the phase difference between the delayed initial clock signal and the reference clock signal output by the voltage-controlled delay line and output a phase detection signal. A charge pump is connected to the output terminal of the phase detector, and the charge pump is used to output a control signal to the voltage-controlled delay line according to the phase detection signal; The first buffer is disposed between the output terminal of the voltage-controlled delay line and the input terminal of the phase detector; The second buffer is disposed between the output of the multi-phase injection-locked ring oscillator and the input of the edge combiner.

4. The injection-locked clock multiplier circuit as described in claim 1, characterized in that, The subharmonic injection locked ring oscillation circuit includes: The delay unit circuit is used to perform differential conversion on the multi-frequency clock signal and output the target multi-frequency clock signal. A switching current source array is connected to the delay unit circuit, and the switching current source array is used to adjust the oscillation frequency coverage range of the delay unit circuit.

5. The injection-locked clock multiplier circuit as described in claim 4, characterized in that, The switching current source array includes: A normally open current source is used to control the oscillation of the delay unit circuit; A high-frequency / low-frequency switching current source is used to increase the frequency range of the delay unit circuit; A multi-channel thermometer code-controlled current source array is used to increase the current matching accuracy of the delay unit circuit.

6. The injection-locked clock multiplier circuit as described in claim 1, characterized in that, The voltage-to-current converter includes: A polarity detector is used to detect the polarity of the multi-frequency clock signal output to the voltage-current converter and control the polarity of the voltage-current converter to be the same as the polarity of the multi-frequency clock signal.

7. The injection-locked clock multiplier circuit as described in any one of claims 1-6, characterized in that, Also includes: A pulse generator is disposed between the output terminal of the reference clock multi-frequency circuit and the input terminal of the subharmonic injection locked ring oscillator circuit. The pulse generator is used to convert the multi-frequency clock signal output by the reference clock multi-frequency circuit into a pulse signal and output it to the subharmonic injection locked ring oscillator circuit. An output buffer is connected to the output terminal of the subharmonic injection locked ring oscillator circuit. The output buffer is used to shape and buffer the target frequency multiplication clock signal output by the subharmonic injection locked ring oscillator circuit before outputting it.

8. A clock multiplier, characterized in that, Includes the injection-locked clock multiplier circuit as described in any one of claims 1-7.

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