An output significant bit number promotion method based on NS-SARADC

Abstract

The application discloses an output effective bit number improving method based on NS-SARADC, and belongs to the field of analog-digital converters. The application writes control words through an SPI interface to configure a digital prediction enabling state and an input channel; a first working clock and a second working clock are generated by dividing a main clock; when the digital prediction is enabled, segment discrimination and prediction offset compensation are performed on an ADC output code stream under the driving of the first working clock, and compensated data is output, otherwise, straight-through output is performed; to-be-output data is distributed to a straight-through serial link and a CIC extraction filtering serial link, the straight-through link is output under parallel-serial conversion of the main clock, and the filtering link is output under parallel-serial conversion of the second working clock after being sequentially subjected to cascade integration, extraction and cascade comb filtering; two-way output data is collected by an upper computer through the SPI. The application can effectively suppress high-frequency quantization noise, avoid internal overload, expand a dynamic range, and ensure that data output timing is accurate and reliable.

Description

Technical Field

[0001] This invention relates to a method for increasing the effective number of bits in the output of an NS-SAR ADC, belonging to the field of analog-to-digital converters. Background Technology

[0002] Analog-to-digital converters (ADCs), serving as a crucial bridge between the analog world and digital processing systems, are widely used in fields such as military reconnaissance, precision measurement, and medical diagnostics, and are one of the core functional modules in modern integrated circuit systems. With the continuous development of digital signal processing technology, leveraging its advantages of strong anti-interference capabilities, high stability, and ease of integration, the reliance of systems on analog-to-digital conversion accuracy is increasing, driving a sustained demand for high-resolution, high signal-to-noise ratio ADCs. Against this backdrop, noise-shaping successive approximation analog-to-digital converters (NS-SAR ADCs), which can effectively improve quantization accuracy through noise shaping techniques, are gradually becoming one of the preferred solutions for high-resolution and high signal-to-noise ratio applications.

[0003] NS-SAR ADCs push quantization noise to higher frequencies through noise shaping, thereby achieving better noise performance within the target signal bandwidth. However, their implementation faces several challenges: First, to suppress harmonic distortion caused by DAC capacitor mismatch, a novel error feedback (EF) mismatch error shaping method is used to reduce the impact of mismatch error; however, EF mismatch error shaping introduces the risk of ADC overload, resulting in limited dynamic range. Second, after noise shaping pushes noise to higher frequencies, without matching digital domain filtering and downsampling processing, high-frequency noise components will continuously be mixed in the output data, affecting subsequent processing and the final signal-to-noise ratio (SNDR). Furthermore, multi-channel data acquisition systems require channel selection and operating status configuration via communication interfaces. Without clearly defined control words and output timing coordination mechanisms, problems such as inconsistent configuration and output, and disordered data output timing can occur.

[0004] In summary, to address issues such as residual noise, limited dynamic range, and erratic readings in NS-SAR ADCs, a digital module is needed in the subsequent link for signal processing. This paper proposes a dynamic range compensation technique for digital prediction of NS-SAR ADCs, introducing a CIC decimation filter and an SPI communication interface. This provides a favorable method to increase the bit width of the effective data output by the ADC, thus meeting market demands. Summary of the Invention

[0005] This invention aims to provide a digital post-processing method for NS-SAR ADC output data. It introduces dynamic range compensation technology for digital prediction to increase the dynamic range; introduces a CIC decimation filter to suppress high-frequency noise and complete rate matching; and designs a control word that matches the data output through the SPI interface to realize channel selection and working state selection, ensuring that the data can be output correctly. This effectively solves the problems of noise residue, limited dynamic range, and reading errors in traditional ADCs.

[0006] The technical solution adopted in this invention is a method for increasing the effective number of bits of output based on NS-SARADC, which includes the following steps:

[0007] The host computer writes a control word to the chip via the SPI communication interface. The control word is used to configure the chip's operating mode and input channel selection.

[0008] The chip divides the main clock to generate a first working clock and a second working clock.

[0009] When the control word indicates that the digital prediction function is enabled, the chip, driven by the first operating clock, performs dynamic range compensation processing for the current digital bitstream output by the NS-SARADC. The compensation processing is based on segmentation discrimination of the current input data and the historical state information of the previous cycle, and selects the corresponding prediction offset for compensation according to the discrimination result, and outputs the compensated digital bitstream. When the control word indicates that the digital prediction function is not enabled, the chip directly uses the current digital bitstream output by the NS-SARADC as the digital bitstream to be output.

[0010] The chip distributes the digital code stream to be output, whether or not it has undergone the compensation process, to two parallel links: a direct serial output link and a CIC decimation and filtering serial output link.

[0011] In the direct-through serial output link, the digital code stream to be output is converted from parallel to serial and then output under the drive of the master clock;

[0012] In the CIC decimation and filtering serial output link, the digital code stream to be output is sequentially subjected to cascaded integration, decimation and cascaded comb filtering under the first working clock drive, and the filtered data is then converted from parallel to serial and output under the second working clock drive.

[0013] The host computer collects serial data output from the two links through the SPI communication interface.

[0014] Furthermore, the control word consists of a 4-bit register, where one bit is an enable control bit used to control whether the digital prediction function is enabled; the remaining three bits are channel selection bits used to select one of the eight ADC input channels.

[0015] Furthermore, the frequency of the master clock is 128MHz, the frequency of the first working clock is 16MHz, and the frequency of the second working clock is 2MHz.

[0016] Furthermore, the segmentation and discrimination, and the selection of the corresponding predicted offset for compensation based on the discrimination result, specifically includes:

[0017] Extract the high-order bits of the current input data, and determine the prediction range interval to which the current input data belongs based on the value of the high-order bits;

[0018] When the high-order bit is in the first state, a first numerical shift is introduced into the internal extended signal, and a first prediction offset is selected for compensation to form a new prediction reference value. The difference result between the current input data and the prediction reference value of the previous cycle is then output.

[0019] When the high-order bit is in the second state, the first numerical shift is introduced into the internal extended signal, and the second prediction offset is selected for compensation to form a new prediction reference value, and the difference result between the current input data and the prediction reference value of the previous cycle is output.

[0020] When the high-order bit is in the third state, a second numerical shift is introduced into the internal extended signal, and the shift of the internal extended signal by the second prediction offset is compensated to form a new prediction reference value, and the difference result between the current input data and the prediction reference value of the previous cycle is output.

[0021] When the high-order bit is in the fourth state, the internal extended signal is directly used as the new prediction reference value, and based on the relationship between the current input data and the prediction reference value of the previous cycle, as well as the range state of the previous cycle, positive differential values ​​or negative differential values ​​with sign indication are selectively output.

[0022] Furthermore, when the higher-order bit is in the fourth state, based on the relationship between the current input data and the prediction reference value of the previous cycle, as well as the range state of the previous cycle, a positive differential value or a negative differential value with a sign indication is selectively output, specifically including:

[0023] If the current input data is greater than the previous period's prediction benchmark value, then output the difference between the two and pad with zeros in the highest bit.

[0024] If the current input data is less than the prediction benchmark value of the previous cycle, and the range state of the previous cycle is a high range state or a relatively high range state, then the difference between the current input data and the prediction benchmark value of the previous cycle is output by utilizing the wraparound characteristic of the two's complement operation.

[0025] If the current input data is less than the prediction benchmark value of the previous cycle, and the range state of the previous cycle is zero offset, then the difference between the prediction benchmark value of the previous cycle and the current input data is output, and a 1 is added to the highest bit to indicate the negative direction.

[0026] If the two are equal, output zero.

[0027] Furthermore, in the CIC decimation filter serial output link, the decimation factor is 64 times, and both the cascaded integrator and the cascaded comb filter adopt a three-stage cascaded structure.

[0028] Furthermore, in the CIC decimation filter serial output link, the filtered 26-bit data is truncated into 24-bit data, and the 24-bit data is decomposed into three parallel bytes: high byte, middle byte, and low byte. Under the drive of the second working clock, the three parallel bytes are serially output sequentially.

[0029] Furthermore, the communication clock frequency of the SPI communication interface is 2MHz. The start and end of data transmission are controlled by the chip select signal, the opening of a transmission window is indicated by the preparation signal, and the end of an output frame is indicated by the completion signal.

[0030] Furthermore, the host computer samples and splices the output bit stream of the SPI communication interface within each transmission window to obtain a first output result corresponding to the direct serial output link and a second output result corresponding to the CIC decimation and filtering serial output link.

[0031] An analog-to-digital conversion system employs the aforementioned method for increasing the effective number of bits of output based on NS-SARADC for digital post-processing.

[0032] Specifically, the present invention is achieved through the following technical solution:

[0033] (a) SPI communication interface

[0034] The data interaction between the host computer and the chip uses the SPI communication protocol to reduce the number of IO ports, thereby minimizing the chip area. The configuration control word register WORD[3:0] consists of {DP_EN, ADD0, ADD1, ADD2}, where DP_EN is used to control whether the digital prediction module ADC_DP is enabled, and {ADD0, ADD1, ADD2} is used to select the 8 ADC input channels. The host computer uses CLK_64M as the excitation clock and serially writes WORD[3:0] into the chip through the SDI port of SPI to complete the working mode and channel selection. Finally, it outputs DOUT0, DOUT1, DOUT2, DOUT3 and their valid identifiers DOUT_VALID0 and DOUT_VALID1 through the SDO port of SPI for the host computer to collect. Other signals such as RST_N are reset signals and are active low, READY is used to indicate the start of signal transmission, and DONE is used to indicate the completion of signal transmission. The SPI communication clock SCLK is set to a working frequency of 2MHz to ensure the consistency of the output link and interface timing. CS_N is the chip select signal and data transmission is valid when it is low.

[0035] (ii) Clock frequency division

[0036] The ADC master clock CLK_128M is divided by 8 and 64 to obtain CLK_16M and CLK_2M respectively. CLK_16M is used as the input clock for the digital prediction module and CIC decimation filter in the subsequent link; CLK_2M is used as the working clock for the CIC decimation filter and the serialized output data.

[0037] (III) Digital Prediction Compensation Technology

[0038] Driven by the working clock CLK_16M, the ADC output data DIN[7:0] is synchronized and processed. The reset signal RST_N is used to initialize the internal register state and save the prediction reference register LAST_DATA and the range status register VCMP_r of the previous cycle as historical information for subsequent digital prediction and segmented compensation processing. The prediction range interval indicated by the high bits DIN[7:6] of the ADC output selects the corresponding segmented prediction offset DATA1 and DATA2, expands the signals UXTB and DIN_TEMP to 9 bits, and performs digital prediction offset compensation. The differential calculation between adjacent samples is completed through the two's complement principle, and finally the compensated differential output data DOUT and its valid identification signal DOUT_VALID are generated. Thus, without changing the ADC analog front-end structure, the segmented dynamic range compensation and differential encoding of the ADC output code stream based on digital prediction are realized, effectively avoiding the internal overload problem introduced by the EF MES structure, improving the equivalent dynamic range of the system and improving the continuity and stability of the output code stream.

[0039] (iv) Dual-link serial output

[0040] To compare the output effects before and after decimation filtering, this invention divides the digital output of the ADC chip into two parallel output links: one is a direct serial output link without CIC decimation filtering, and the other is a serial output link after CIC decimation filtering. When DP_EN is 1, the digital prediction module is enabled, and the DOUT[7:0] and DOUT_VALID output by the digital prediction module are input to DIN[7:0] and DIN_VALID in the two links, respectively.

[0041] In the direct link, the compensation data DOUT[7:0] output by the digital prediction module is shifted and output under the synchronization of CLK_128M to realize the conversion of 8-bit parallel data to 1-bit serial data, and outputs the valid identifier DOUT_VALID0. In the filtering link, the CIC decimation filter performs three-stage integrator cascade, 64-fold decimation and three-stage comb cascade operations on the input data DIN[7:0] under the synchronization of CLK_16M, and outputs the valid identifier DOUT_VALID; then the DOUT[25:0] output by CIC is truncated to DIN[23:0], and the P2S_CIC module decomposes DIN[23:0] into three parallel bytes under the synchronization of CLK_2M clock to output DOUT1, DOUT2 and DOUT3 serial data and output the valid identifier DOUT_VALID1 respectively by shifting the high bit to the left. Attached Figure Description

[0042] Figure 1 This is a system structure diagram of the present invention.

[0043] Figure 2 This is a structural diagram of the external control chip of the present invention.

[0044] Figure 3 This is the circuit timing diagram of the present invention. Detailed Implementation

[0045] The present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0046] Step 1: Configure the chip control word on the host computer

[0047] The host computer drives the SPI communication interface using CLK_64M as the excitation clock. First, it pulls RST_N low to reset and initialize the chip. After RST_N is pulled high and released, the host computer enters the register configuration stage. It initiates an SPI write by pulling CS_N low and serially writes WORD[3:0] via SDI under the drive of SCLK. After the write is completed, CS_N is pulled high to latch the control word and complete the acquisition configuration. The chip decodes WORD[3:0] internally and switches the working mode and selects the corresponding input channel according to DP_EN and {ADD0,ADD1,ADD2}. {ADD0,ADD1,ADD2} are 000 ~ 111, which correspond to the selection of channels 0 to 7 respectively. After the configuration is completed, the chip maintains this mode and channel selection and enters the subsequent data transmission and acquisition process.

[0048] Step 2: Clock division

[0049] The chip first divides the clock CLK_128M. After RST_N is released, the CLK_DIV module starts working, dividing CLK_128M by 8 and 64 times using a counter to obtain CLK_16M and CLK_2M respectively, and assigning different frequency clocks to the corresponding data paths to form a defined timing loop. DIN[7:0] and its valid identifier DIN_VALID drive digital prediction and decimation filtering operations in the CLK_16M clock domain. The parallel-to-serial conversion of the pass-through link is completed by the P2S_DP module in the CLK_128M clock domain for high-speed caching and shift output. The parallel-to-serial conversion of the filter link is completed by the P2S_CIC module in the CLK_2M clock domain for caching loading and shift output at a low rate after decimation.

[0050] Step 3: Digital Predictive Compensation Technology

[0051] The chip mode switch is updated and written to WORD[3:0] by the host computer, and the DP_EN status is updated in the transmission window after the READY bit is set next time. When DP_EN=0, the chip enters the bypass mode, the compensation path of ADC_DP does not participate in data calculation, DIN[7:0] and DIN_VALID are directly sent to the pass-through link and CIC link, and its pass-through output and filtered output reflect the original ADC code stream characteristics without prediction compensation. When DP_EN=1, the chip enters the dynamic range compensation mode of digital prediction. The ADC_DP module synchronously samples DIN[7:0] and DIN_VALID at the rising edge of CLK_16M, and performs segmented prediction and difference compensation based on the historical information saved by LAST_DATA and VCMP_r. The prediction range flag bit DIN[7:6] is segmented and the corresponding prediction path is selected: when DIN[7:6] is "11", the ADC output value DIN ≥ 192, and the current input is in the high range prediction segment. At this time, the module introduces a numerical shift of 128 to the internal extended signal UXTB, selects the corresponding prediction offset DATA1, performs digital prediction compensation on the output of this segment, forms a new prediction reference value LAST_DATA, and outputs the difference result DOUT_r between the current input and the prediction reference of the previous cycle, and updates the range status VCMP_r to "11". Through this segmented offset mapping, the ADC output in the high range range is effectively pulled back to the unified internal continuous coordinate system, providing a reference for subsequent differential calculation and cross-range continuity maintenance; when DIN[7:6] is "10", that is, 128 ≤ DIN < 192, it is in the higher range prediction segment. At this time, a numerical shift of 128 is also introduced into the internal extended signal UXTB, but the corresponding prediction offset is DATA2. Through digital prediction compensation, a new prediction reference value LAST_DATA and differential result DOUT_r are formed, and the range status VCMP_r is updated to "10". When DIN[7:6] is "01", that is, 64 ≤ DIN < 128, it is in the lower range prediction segment. First, a numerical shift of 64 is introduced into UXTB, and then the prediction offset of DATA2 is compensated by shifting UXTB to form a new prediction reference value LAST_DATA, so as to realize the continuous mapping of this segment and other segments in the internal coordinate system.Then, the differential result DOUT_r is output, and the corresponding range status VCMP_r is updated simultaneously. When DIN[7:6] is “00”, it is in the zero-offset prediction segment, UXTB is directly used as the new LAST_DATA, and VCMP_r is updated to “00”. At the same time, in order to ensure the continuity of cross-range switching and constrain the direction of the difference, the differential operation of DOUT_r is selected according to the size relationship between DIN_TEMP and LAST_DATA and the state of VCMP_r in the previous step: when DIN_TEMP > LAST_DATA, DIN_TEMP − LAST_DATA is output and 0 is padded in the highest bit; when DIN_TEMP < LAST_DATA and the previous step VCMP_r is “11” or “10”, by utilizing the wraparound characteristic of the two's complement operation, the negative difference generated when crossing the segment is equivalently represented as a larger positive difference, thereby maintaining the continuity of the differential code stream at the range switching point, and still outputting DIN_TEMP − LAST_DATA as the differential result; when DIN_TEMP < When LAST_DATA and the previous VCMP_r is “00”, it indicates that the value is decreasing. The highest bit is padded with 1 to represent the negative direction, and LAST_DATA - DIN_TEMP is used as the difference result; when the two are equal, 0 is output. Through the above segmented prediction discrimination and conditional difference constraint, the chip forms the compensated DOUT[7:0] and generates DOUT_VALID in digital prediction compensation mode, so that the prediction compensation process remains continuous at the segment switching point, reducing the risk of abnormal jump.

[0052] Step 4: Dual-link serial output

[0053] The compensation output is simultaneously distributed to two parallel links within the chip: a pass-through serial output link and a decimation-filter serial output link. In the pass-through link, the P2S_DP module buffers the input byte and shifts it to the left under CLK_128M synchronization, completing the conversion from 8-bit parallel to 1-bit serial DOUT0, and outputting the valid identifier DOUT_VALID0. In the filtering link, the CIC is composed of three cascaded sub-modules: an integrator INTE, a decimator DECI, and a comb COMB. The data stream is effectively transmitted through the step-by-step enable through en_r[1:0]. The INTE module uses a three-stage integration structure to accumulate the extended input sxtx step by step to achieve cascaded integration. The DECI module decimates once every 64 clock cycles to complete a 64x downsampling. The COMB module uses a three-stage first-order differential structure to subtract the input data after a one-stage delay, achieving comb filtering, thus forming the CIC decimation filter together with the previous integrator. Finally, the output DOUT of CIC is truncated, and DOUT[25:2] is used as the input DIN[23:0] of the subsequent P2C_CIC. P2S_CIC then decomposes it into the high byte DIN[23:16], the middle byte DIN[15:8], and the low byte DIN[7:0], and outputs the serial bits DOUT1, DOUT2, DOUT3 and the output validity flag DOUT_VALID1 of each byte in sequence by left shifting.

[0054] Step 5: The host computer collects and outputs data.

[0055] After entering the data acquisition phase, the serial outputs and valid flag bits of the two links are uniformly sent to the SPI output. The host computer opens a valid transmission window by setting READY and keeps CS_N low to maintain the validity of the SPI frame. Under SCLK synchronization, the chip outputs DOUT0, DOUT1, DOUT2, DOUT3 and their corresponding DOUT_VALID0 and DOUT_VALID1 sequentially through SDO. After setting READY, the chip maps the internal data stream to a fixed SPI output sequence according to the mode defined by the current WORD[3:0], and ends the current output frame when DONE is set. The host computer samples and splices the SDO bit stream within the window to obtain the corresponding results OUT1[7:0] and OUT2[15:0] for subsequent processing. If a mode or channel needs to be switched during operation, the host computer pulls CS_N high after DONE to end the current frame, and pulls CS_N low again to write a new WORD[3:0]. After the chip enters READY again, it updates the internal data flow path and SPI output sequence according to the new configuration, thereby realizing dynamic switching of mode and channel under continuous acquisition.

Claims

1. A method for increasing the effective number of bits in the output of an NS-SARADC, characterized in that, Includes the following steps: The host computer writes a control word to the chip via the SPI communication interface. The control word is used to configure the chip's operating mode and input channel selection. The chip divides the main clock to generate a first working clock and a second working clock. When the control word indicates that the digital prediction function is enabled, the chip performs dynamic range compensation processing for the current digital code stream output by the NS-SARADC under the drive of the first working clock. The compensation processing is based on the current input data and the historical state information of the previous cycle to segment and distinguish, and selects the corresponding prediction offset for compensation according to the discrimination result, and outputs the compensated digital code stream. When the control word indicates that the digital prediction function is not enabled, the chip directly uses the current digital code stream output by the NS-SARADC as the digital code stream to be output. The chip distributes the digital code stream to be output, whether or not it has undergone the compensation process, to two parallel links: a direct serial output link and a CIC decimation and filtering serial output link. In the direct-through serial output link, the digital code stream to be output is converted from parallel to serial and then output under the drive of the master clock; In the CIC decimation and filtering serial output link, the digital code stream to be output is sequentially subjected to cascaded integration, decimation and cascaded comb filtering under the first working clock drive, and the filtered data is then converted from parallel to serial and output under the second working clock drive. The host computer collects serial data output from the two links through the SPI communication interface.

2. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: The control word consists of a 4-bit register, one of which is an enable control bit used to control whether the digital prediction function is enabled; the remaining three bits are channel selection bits used to select one of the eight ADC input channels.

3. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: The master clock has a frequency of 128MHz, the first operating clock has a frequency of 16MHz, and the second operating clock has a frequency of 2MHz.

4. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that, The segmented discrimination and selection of corresponding predicted offsets for compensation based on the discrimination results specifically include: Extract the high-order bits of the current input data, and determine the prediction range interval to which the current input data belongs based on the value of the high-order bits; When the high-order bit is in the first state, a first numerical shift is introduced into the internal extended signal, and a first prediction offset is selected for compensation to form a new prediction reference value. The difference result between the current input data and the prediction reference value of the previous cycle is then output. When the high-order bit is in the second state, the first numerical shift is introduced into the internal extended signal, and the second prediction offset is selected for compensation to form a new prediction reference value, and the difference result between the current input data and the prediction reference value of the previous cycle is output. When the high-order bit is in the third state, a second numerical shift is introduced into the internal extended signal, and the shift of the internal extended signal by the second prediction offset is compensated to form a new prediction reference value, and the difference result between the current input data and the prediction reference value of the previous cycle is output. When the high-order bit is in the fourth state, the internal extended signal is directly used as the new prediction reference value, and based on the relationship between the current input data and the prediction reference value of the previous cycle, as well as the range state of the previous cycle, positive differential values ​​or negative differential values ​​with sign indication are selectively output.

5. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 4, characterized in that, When the high-order bit is in the fourth state, based on the relationship between the current input data and the prediction reference value of the previous cycle, as well as the range state of the previous cycle, a positive differential value or a negative differential value with a sign indication is selectively output, specifically including: If the current input data is greater than the previous period's prediction benchmark value, then output the difference between the two and pad with zeros in the highest bit. If the current input data is less than the prediction benchmark value of the previous cycle, and the range state of the previous cycle is a high range state or a relatively high range state, then the difference between the current input data and the prediction benchmark value of the previous cycle is output by utilizing the wraparound characteristic of the two's complement operation. If the current input data is less than the prediction benchmark value of the previous cycle, and the range state of the previous cycle is zero offset, then the difference between the prediction benchmark value of the previous cycle and the current input data is output, and a 1 is added to the highest bit to indicate the negative direction. If the two are equal, output zero.

6. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: In the CIC decimation filter serial output link, the decimation factor is 64 times, and both the cascaded integrator and the cascaded comb filter adopt a three-stage cascaded structure.

7. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: In the CIC decimation filter serial output link, the filtered 26-bit data is truncated into 24-bit data, and the 24-bit data is decomposed into three parallel bytes: high byte, middle byte, and low byte. Under the drive of the second working clock, the three parallel bytes are serially output sequentially.

8. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: The SPI communication interface has a communication clock frequency of 2MHz. The start and end of data transmission are controlled by the chip select signal, the opening of a transmission window is indicated by the preparation signal, and the end of an output frame is indicated by the completion signal.

9. The method for increasing the effective number of bits of output based on NS-SARADC according to claim 1, characterized in that: The host computer samples and splices the output bit stream of the SPI communication interface within each transmission window to obtain a first output result corresponding to the direct serial output link and a second output result corresponding to the CIC decimation and filtering serial output link.

10. An analog-to-digital conversion system, characterized in that, Digital post-processing is performed using the output effective bit enhancement method based on NS-SARADC as described in any one of claims 1 to 9.

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