A front-back stage fusion TIADC sampling time mismatch digital calibration system and method

Abstract

The application discloses a front and back stage fused TIADC sampling time mismatch digital calibration system and method, including self-correlation error extraction path, selection module, front stage correction code generation module, back stage correction code iteration module, correction code register, correction module and control module. The application extracts sampling time mismatch related error information according to TIADC channel digital output by multiplexing self-correlation error extraction path, inputs parameter known test signal to TIADC in front stage initialization stage, and generates initial correction code corresponding to current sampling time mismatch state by using known test signal parameter, and then uses the initial correction code as back stage correction code iteration initial value. Thus, the overall calibration convergence speed is improved under the condition of only a small amount of additional digital resource overhead, and the continuous tracking ability of the back stage calibration to subsequent sampling time mismatch change is reserved.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit calibration design technology, specifically to a front-end and back-end integrated TIADC sampling time mismatch digital calibration system and method. Background Technology

[0002] Analog-to-digital converters (ADCs) are key components in communication, radar, test and measurement, and high-speed data acquisition systems. With ever-increasing demands for sampling rates and conversion accuracy, single-channel ADCs are limited by factors such as manufacturing processes, analog bandwidth, power consumption, and noise, making it difficult to simultaneously meet the requirements of high speed and high accuracy. Time-interleaved analog-to-digital converters (TIADCs), by using multiple sub-ADCs to sample alternately in parallel and synthesize the output in the digital domain, can effectively improve the system's equivalent sampling rate and are therefore widely used in high-speed, high-precision data acquisition systems.

[0003] However, in practical TIADCs, each sub-channel is prone to channel mismatch errors such as offset mismatch, gain mismatch, and sampling time mismatch due to factors such as manufacturing process deviations, device mismatch, clock allocation errors, and environmental changes. Among these, sampling time mismatch causes the actual sampling time of each channel to deviate from the ideal sampling time, generating spurious components related to the input signal in the output spectrum. This reduces the system's signal-to-noise ratio and spurious-free dynamic range, making it a critical issue in TIADC calibration. Digital calibration methods typically utilize the ADC output digital code for error information extraction and correction parameter updates, eliminating the need for direct analog signal processing. Therefore, they are easier to implement and integrate in high-speed TIADC systems.

[0004] Existing digital calibration methods for addressing sampling time mismatch mainly include front-end calibration and back-end calibration. Front-end calibration methods typically input a known test signal to the TIADC before normal operation and estimate the channel sampling time mismatch or generate corresponding correction parameters based on the sampling output of each TIADC channel of the test signal. This method offers advantages such as fast error extraction and clear estimation conditions. The known test signal serves as the calibration excitation signal for sampling time mismatch estimation, and the object of front-end calibration remains the sampling time mismatch of each TIADC channel. However, this type of method usually requires a dedicated testing phase, and it is difficult to continuously track slowly varying sampling time mismatches caused by factors such as temperature, voltage, and aging after calibration. Back-end calibration methods, under normal operating signal input conditions, continuously extract sampling time mismatch-related error information based on the digital output of each TIADC channel and update the correction parameters accordingly, thereby achieving long-term tracking of sampling time mismatch. Among these, the back-end blind calibration method based on autocorrelation error information does not require the introduction of an additional dedicated reference signal or reference channel, making it more suitable for engineering applications. However, to ensure steady-state accuracy, this type of method typically uses a small iteration step size, resulting in a longer convergence time when starting from the zero correction code or default correction code. For example, Chinese patent CN105811980B discloses an adaptive blind calibration method for TIADC time error mismatch based on a differentiator, a high-pass filter, and an LMS algorithm. This scheme estimates the deviation of the relative average time error of each channel using the actual output of the TIADC and achieves digital compensation through error reconstruction. However, this scheme is a pure background adaptive iterative calibration, and the parameters need to converge gradually from the initial state.

[0005] To improve the convergence speed of background calibration, existing methods typically employ adaptive step sizes, window statistics optimization, or improvements to related detection structures to accelerate the iteration process. However, these methods still primarily rely on the background loop gradually approximating the target calibration code. Starting from zero calibration code or the default calibration code, it usually still takes a considerable amount of time to converge to a stable calibration range. Some acceleration structures also increase additional digital hardware resources and control complexity. Some engineering implementations obtain the initial calibration code during production testing or system initial configuration and write it into non-volatile memory, allowing the pre-stored code value to be directly loaded as the initial value for background iteration after system power-on. While pre-stored fixed initial calibration codes can reduce calibration waiting time after power-on, their code values ​​mainly reflect the mismatch state during factory testing or fixed configuration. If the device experiences a significant shift in initial sampling time mismatch due to aging, damage, changes in packaging stress, or long-term drift accumulation during subsequent use, the pre-stored code value may deviate from the current actual mismatch state, requiring background calibration to still start iterations from an inaccurate initial point.

[0006] To balance calibration convergence speed and subsequent tracking capability, existing technologies have proposed schemes that combine front-end calibration or pre-estimation with back-end calibration or post-estimation. However, existing schemes typically employ different mismatch estimation or correction mechanisms in the front and back stages, often requiring additional reference modules, delay adjustment structures, or complex parameter estimation algorithms in their implementation. For example, Chinese patent CN113595553A, "A Data Acquisition System and Method Based on Time-Interleaved Parallel Sampling," discloses a time-interleaved sampling correction scheme that combines pre-estimation and post-estimation. This scheme first fits and calculates the mismatch error of each sampled signal and generates a first correction signal, then uses the first correction signal as the initial correction signal to continue post-estimation optimization. However, its implementation requires an additional reference sampling module to obtain a reference signal as a mismatch error comparison benchmark, and multi-objective optimization is performed in the post-estimation stage, resulting in a large overall computational load, high hardware costs, and insufficient engineering applicability. Chinese patent CN114650056A, titled "Matrix Processor for Adjusting Input Delay to Calibrate Time Phase Mismatch of Multi-Channel Alternating ADC for SAR Search," discloses a calibration method that first sets the SAR delay value of each channel of the alternating ADC through foreground calibration (referred to as foreground calibration in this patent), and then continues to adjust the previously set SAR through background calibration (referred to as background calibration in this patent). However, the foreground calibration of this scheme requires probing the delay value bit by bit, and it also requires adding SAR delay elements and variable input delay structures in each channel, significantly increasing additional hardware overhead and implementation complexity. Chinese patent CN115733491A, titled "A Calibration System and Method for Estimating Mismatch Error of a Four-Channel TIADC System," discloses a TIADC calibration scheme that first performs offline coarse estimation using the LS algorithm, and then uses the LS estimation result as the initial value for online fine estimation using RLS recursion. However, the connection between the preceding and following steps in this scheme occurs at the Volterra model parameter estimation level, requiring the construction of the input matrix, solving the LS / RLS parameter matrix, and reconstructing the error signal, resulting in relatively high algorithm and digital implementation complexity.

[0007] Therefore, how to obtain a background iteration initial value that is closer to the current mismatch state while maintaining the continuous background tracking capability and steady-state calibration accuracy, and how to improve the overall calibration convergence speed and reduce additional hardware overhead, remains a problem to be solved in TIADC sampling time mismatch calibration. Summary of the Invention

[0008] The purpose of this invention is to provide a front-end and back-end integrated TIADC sampling time mismatch digital calibration system and method. By reusing the autocorrelation error extraction path, with only a small amount of additional digital resource overhead, the front-end initialization stage quickly generates an initial calibration code that matches the current sampling time mismatch state between the current TIADC channels based on the digital output of each channel. This initial code is then used as the initial value for the back-end calibration code iteration, thereby improving the overall calibration convergence speed and addressing the problem of inaccurate initial points when the pre-stored fixed initial calibration code undergoes a large shift in the mismatch state.

[0009] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0010] In a first aspect, the present invention discloses a front-end and back-end integrated TIADC sampling time mismatch digital calibration system, the system comprising:

[0011] The autocorrelation error extraction path is used to generate error information related to the sampling time mismatch between the TIADC channels based on the digital output of each channel of the TIADC.

[0012] The selection module is connected to the output end of the autocorrelation error extraction path. It is used to transmit the error information obtained under known test signal input conditions to the front-end calibration code generation module during the front-end initialization stage, and to transmit the error information obtained under normal working signal input conditions to the back-end calibration code iteration module during the background tracking stage.

[0013] A front-end calibration code generation module is connected to the output of the selection module and is used to generate an initial calibration code based on the parameters of the known test signal and the error information during the front-end initialization phase.

[0014] The background correction code iteration module is connected to the output of the selection module and the output of the front-end correction code generation module, respectively. It is used to receive the initial correction code and, during the background tracking phase, use the initial correction code as the initial value for correction code iteration and iteratively update the correction code according to the error information obtained during the background tracking phase.

[0015] The correction code register is connected to the output of the front-end correction code generation module and the back-end correction code iteration module, respectively, and is used to store the initial correction code in the front-end initialization stage and the current correction code output by the back-end correction code iteration module in the back-end tracking stage.

[0016] A correction module, connected to the correction code register, is used to compensate for the sampling time mismatch of the TIADC according to the correction code output by the correction code register;

[0017] The control module is used to control the multiplexing of the autocorrelation error extraction path between the front-end initialization stage and the back-end tracking stage, control the transmission path of the selection module, control the loading of the initial correction code to the back-end correction code iteration module, and control the iterative update of the back-end correction code iteration module.

[0018] Furthermore, the autocorrelation error extraction path includes a sequentially connected adjacent channel sample product module, block averaging module, and autocorrelation error generation module; the adjacent channel sample product module is used to calculate the product between adjacent channel output samples; the block averaging module is used to perform average window statistics on the product to obtain the averaged adjacent channel correlation statistics; the autocorrelation error generation module is used to generate the sampling time mismatch correlation error information based on the averaged adjacent channel correlation statistics.

[0019] Furthermore, the front-end calibration code generation module includes an error information input terminal and an initial calibration code output terminal; the error information input terminal is used to receive the error information output by the selection module during the front-end initialization phase, and the initial calibration code output terminal is used to generate and output the initial calibration code based on the error information obtained within an average window, as well as the frequency, amplitude, average window length, and calibration code time resolution of the known test signal.

[0020] ;

[0021] In the formula, Let be the initial calibration code for the i-th channel; C is the scaling factor determined by the test signal amplitude and correlation statistics. The phase difference between adjacent sampling points of a sinusoidal signal. To test the signal frequency, This is the overall sampling period of TIADC. Adjust the resolution for the time corresponding to one correction code unit; This is the error information related to the sampling time mismatch of the i-th channel.

[0022] Furthermore, the frequency, amplitude, and average window length of the known test signal are set to satisfy the whole-cycle averaging condition and the proportional conversion approximation condition, so that the front-end correction code generation module generates the initial correction code through arithmetic shift operations.

[0023] Furthermore, the background correction code iteration module includes an initial code input terminal, an error information input terminal, and a correction code output terminal; the initial code input terminal is used to receive the initial correction code generated by the front-end correction code generation module during the front-end initialization phase, so that the background correction code iteration module uses the initial correction code as the initial value for correction code iteration during the background tracking phase; the error information input terminal is used to receive the error information output by the selection module during the background tracking phase; and the correction code output terminal is used to output the current correction code after iterative updates based on the initial value for correction code iteration and the error information.

[0024] Furthermore, the control module is used to receive a foreground start signal, a foreground preparation signal, a background start signal, and a background preparation signal, and output a foreground completion signal, a foreground busy signal, and a background busy signal; wherein, the foreground start signal is used to start the foreground process, the foreground preparation signal is used to indicate that the known test signal is stable, the foreground completion signal is used to indicate that the initial calibration code has been generated and loaded, the background start signal is generated by the external system based on the foreground completion signal and used to start the background process, the background preparation signal is used to indicate that the normal working signal is stable, the foreground busy signal is used to indicate that the system is in a foreground waiting state or a foreground initialization state, and the background busy signal is used to indicate that the system is in a background waiting state or a background tracking state.

[0025] Furthermore, the test signals used in the foreground initialization phase are provided by an external signal source or generated by an on-chip or board-level test signal generation circuit, and can be switched between test signals and normal operation signals through an external system, board-level input selection unit, or on-chip input selection structure.

[0026] Furthermore, the autocorrelation error extraction path, selection module, front-end correction code generation module, back-end correction code iteration module, correction code register, and control module are all implemented by digital circuits; when the correction module adopts a digital domain compensation structure, the system completes the full digital calibration of sampling time mismatch based on the digital output of each channel of the TIADC.

[0027] Secondly, the present invention discloses a front-end and back-end integrated TIADC sampling time mismatch digital calibration method, characterized in that the method includes the following steps:

[0028] After the foreground is started, a known test signal is input to the TIADC, and after the known test signal stabilizes, the foreground initialization stage is entered. Using the digital output of each channel of the TIADC, error information related to the sampling time mismatch between the TIADC channels is generated through the autocorrelation error extraction path.

[0029] An initial correction code is generated based on the parameters of the known test signal and the error information;

[0030] The initial correction code is written into the correction code register for sampling time mismatch compensation and loaded into the background correction code iteration module as the initial value for correction code iteration in the background tracking stage.

[0031] After the foreground initialization phase is completed, the TIADC input is switched to the normal working signal, and the background tracking phase begins after the normal working signal stabilizes.

[0032] During the background tracking phase, the autocorrelation error extraction path is reused to generate the sampling time mismatch related error information based on the digital output of each channel under the normal operating signal of the TIADC. The background correction code iteration module continuously updates the correction code starting from the initial correction code. The updated correction code is written into the correction code register for sampling time mismatch compensation.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] First, the front-end and back-end integrated TIADC sampling time mismatch digital calibration system and method of the present invention share the same autocorrelation error extraction path in the front-end initialization stage and the back-end tracking stage. The front-end initialization stage is used to directly generate the initial calibration code, and the back-end tracking stage is used to continuously iteratively update the calibration code. Therefore, the present invention does not require additional reference signals or reference sampling channels. By only adding a front-end calibration code generation module, a selection module, and a small amount of control logic, it can improve the overall calibration convergence speed with relatively small additional digital resource overhead and maintain long-term back-end tracking capability for subsequent sampling time mismatch changes.

[0035] Second, the front-end and back-end integrated TIADC sampling time mismatch digital calibration system and method of the present invention sets the frequency, amplitude and average window length of the test signal according to the system sampling rate and the correction code time resolution, so that it simultaneously satisfies the whole cycle averaging condition and the proportional conversion approximation condition. The initial correction code conversion can be achieved by arithmetic shift, avoiding the need to set up a dedicated divider, further reducing the additional digital hardware resource overhead and implementation complexity.

[0036] Third, the front-end and back-end integrated TIADC sampling time mismatch digital calibration system and method of the present invention, for a back-end calibration system that already has adjacent channel sample product, block averaging and autocorrelation error generation modules, only needs to add a selection module, a front-end correction code generation module and initial correction code loading control logic to realize the integration of front-end initialization and back-end tracking. This can improve the overall calibration convergence speed of TIADC sampling time mismatch with a small additional digital resource overhead and maintain long-term back-end tracking capability. The system implementation has strong reusability. Attached Figure Description

[0037] Figure 1This is a block diagram of the front-end and back-end integrated TIADC sampling time mismatch digital calibration system of the present invention;

[0038] Figure 2 This is a schematic diagram of the front-end and back-end integrated calibration process;

[0039] Figure 3 This is the state transition diagram for the control module;

[0040] Figure 4 This is a timing diagram for front-end and back-end integrated calibration control.

[0041] Figure 5 A comparison chart of maximum residual sampling time-bias convergence between front-end / back-end fusion calibration and traditional back-end calibration;

[0042] Figure 6 Output spectrum before calibration;

[0043] Figure 7 This is the output spectrum after calibration. Detailed Implementation

[0044] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0045] This invention discloses a front-end and back-end integrated TIADC sampling time mismatch digital calibration system, the system comprising:

[0046] The autocorrelation error extraction path is used to generate error information related to the sampling time mismatch between the TIADC channels based on the digital output of each channel of the TIADC.

[0047] The selection module, connected to the output of the autocorrelation error extraction path, is used to transmit the error information generated under known test signal input conditions to the front-end calibration code generation module during the front-end initialization phase, and to transmit the error information generated under normal working signal input conditions to the back-end calibration code iteration module during the back-end tracking phase.

[0048] A front-end calibration code generation module is connected to the output of the selection module and is used to generate an initial calibration code based on the parameters of the known test signal and the error information during the front-end initialization phase.

[0049] The background correction code iteration module is connected to the output of the selection module and the output of the front-end correction code generation module, respectively. It is used to receive the initial correction code and, during the background tracking phase, use the initial correction code as the initial value for correction code iteration and iteratively update the correction code according to the error information obtained during the background tracking phase.

[0050] The correction code register is connected to the output of the front-end correction code generation module and the back-end correction code iteration module, respectively, and is used to store the initial correction code in the front-end initialization stage and the current correction code output by the back-end correction code iteration module in the back-end tracking stage.

[0051] A correction module, connected to the correction code register, is used to compensate for the sampling time mismatch of the TIADC according to the correction code output by the correction code register.

[0052] The control module is used to control the multiplexing of the autocorrelation error extraction path between the front-end initialization stage and the back-end tracking stage, control the transmission path of the selection module, control the loading of the initial correction code to the back-end correction code iteration module, and control the iterative update of the back-end correction code iteration module.

[0053] like Figure 1 As shown in this embodiment, a front-end and back-end integrated TIADC sampling time mismatch digital calibration system is provided, including an autocorrelation error extraction path, a selection module, a front-end calibration code generation module, a back-end calibration code iteration module, a calibration code register, a calibration module, and a control module. The digital outputs of each channel of the TIADC are input to the autocorrelation error extraction path, which generates error information related to the sampling time mismatch between TIADC channels. The selection module transmits this error information to the front-end calibration code generation module or the back-end calibration code iteration module according to the current working stage. In this invention, the working stage of generating an initial calibration code based on a known test signal is called the front-end initialization stage, and the working stage of continuously iterating and updating the calibration code after switching to a normal working signal is called the back-end tracking stage. The back-end tracking stage includes both the process of the calibration code gradually converging from its initial value to a stable calibration range and the process of continuously tracking changes in sampling time mismatch after entering the stable calibration range.

[0054] During the foreground initialization phase, the TIADC input is a known test signal, which serves as the calibration excitation with pre-determined parameters. Since the test signal parameters are pre-determined, the foreground calibration code generation module can directly generate an initial calibration code within an average window based on the error information extracted from the path output using the autocorrelation error. This initial calibration code is written to the calibration code register for sampling time mismatch compensation and loaded into the background calibration code iteration module as the initial value for calibration code iteration during the background tracking phase.

[0055] During the background tracking phase, the TIADC input is a normal operating signal. The system continues to reuse the same autocorrelation error extraction path to generate sampling time mismatch related error information. The background correction code iteration module continuously updates the correction code based on this error information and the background iteration step size. The updated correction code is written to the correction code register and used by the correction module for sampling time mismatch compensation. After entering the background tracking phase, the system no longer needs to input a known test signal, nor does it need to interrupt the normal sampling process again. The generated correction code can be used for digital domain fractional delay filtering, digital derivative compensation, or interpolation correction structures, as well as for analog variable delay lines or sampling clock phase adjustment circuits.

[0056] Regarding the number of channels, the front-end and back-end fusion calibration structure of this invention has the capability to expand the number of channels. It can flexibly expand the autocorrelation error extraction path, the front-end correction code generation module, the back-end correction code iteration module, and the correction code register according to the number of TIADC channels, making it suitable for time-interleaved sampling systems with more channels. For ease of explanation, this embodiment only uses a four-channel TIADC as an example. The four interleaved sampling channels output digital sequences y1[k], y2[k], y3[k], and y4[k], respectively. Channel 1 can be used as the reference channel, and channels 2, 3, and 4 correspond to correction codes c2, c3, and c4, respectively. The reference channel is one of the TIADC's own interleaved sampling channels, not an additional reference ADC or reference sampling channel.

[0057] For a four-channel TIADC, without applying a correction code, the actual sampling time of the m-th channel in the k-th interleaving period can be expressed as:

[0058] ;

[0059] Among them, T s This is the overall sampling period of TIADC. This represents the sampling time mismatch of the m-th channel. When using channel 1 as the reference channel, we can let... After applying the correction code, the actual sampling time of the m-th channel can be expressed as:

[0060] ;

[0061] Among them, c m [p] represents the correction code after the p-th update, t step Adjust the resolution for the time corresponding to one correction code unit.

[0062] like Figure 1As shown, the autocorrelation error extraction path includes an adjacent channel sample product module, a block averaging module, and an autocorrelation error generation module. The adjacent channel sample product module is used to calculate the product between adjacent channel output samples; the block averaging module is used to perform a finite-length average on the adjacent channel sample product results; and the autocorrelation error generation module is used to construct error information related to sampling time mismatch based on the correlation statistics of adjacent channels.

[0063] For a four-channel TIADC, the correlation statistics between adjacent channels can be expressed as:

[0064] ;

[0065] in, This represents the mathematical expectation, used to define the theoretical correlation statistic between adjacent channels; in the actual digital implementation, this correlation statistic is approximated by a finite-length average of the product of adjacent channel samples within an average window using the block averaging module. and Let m represent the digital sequence output by the m-th channel and the (m+1)-th channel in the k-th interleaving cycle. In this embodiment, m = 1, 2, 3, 4, corresponding to the aforementioned channels 1, 2, 3, and 4, respectively. Adjacent channels in equation (3) are consecutively numbered according to the actual interleaving sampling order of the TIADC. When m = 4, the next adjacent sampling channel is channel 1 in the next interleaving cycle. To unify the formula representation, channel 1 in the next interleaving cycle is equivalently denoted as channel 5, i.e. Therefore, an average correlation can be constructed based on the correlation statistics of four adjacent channels:

[0066] ;

[0067] In the formula This represents the correlation statistics between channel n and channel n+1.

[0068] Furthermore, with If we denote a non-reference channel, then the error information corresponding to the i-th non-reference channel can be expressed as:

[0069] ;

[0070] Error information ΔR iThis reflects the direction and relative magnitude of the sampling time mismatch between the i-th non-reference channel and the reference channel. It should be noted that the calibration object in both the foreground initialization phase and the background tracking phase is the sampling time mismatch between TIADC channels; the known test signal and normal operating signal are only used as input signals for their respective calibration phases. Although the two phases reuse the same autocorrelation error extraction path, the error information output by this path is not itself a correction code. In the original background calibration, this error information serves as the error driving quantity for the background correction code iteration, updating the correction code through successive iterations. Therefore, simply introducing this error information to the foreground through the selection module cannot directly obtain the initial correction code corresponding to the current sampling time mismatch. To address this, this embodiment utilizes pre-determined conditions for the foreground test signal parameters to establish a proportional conversion relationship between the error information, the sampling time mismatch, and the corresponding correction code, enabling the foreground correction code generation module to directly generate the initial correction code based on reusing the original error extraction path.

[0071] During the foreground initialization phase, the TIADC inputs a known test signal. This known test signal can be provided by an external signal source or generated by an on-chip or board-level test signal generation circuit. It can be switched between the known test signal and the normal operating signal via an external system, a board-level input selection unit, or an on-chip input selection structure. In this embodiment, the test signal is set to a sinusoidal signal with a predetermined frequency and amplitude, which can be expressed as:

[0072] ;

[0073] Where A is the amplitude of the test signal, f cal Let φ be the frequency of the test signal, φ be the initial phase, and t be the time. Since the test signal parameters are known, the front-end calibration code generation module can directly generate the initial calibration code based on the error information extracted from the autocorrelation error extraction path. In one specific implementation, the initial calibration code for the i-th channel can be expressed as:

[0074] ;

[0075] Where C is the proportionality coefficient determined by the amplitude of the test signal and related statistics, Ω = 2πf cal T s .

[0076] The frequency, amplitude, and average window length of the test signal are not arbitrarily set, but can be selected based on the system sampling rate and the time resolution of the correction code, so that they simultaneously satisfy the whole-cycle averaging condition and the proportional conversion approximation condition:

[0077] ;

[0078] Where q is a non-negative integer. At this point, the initial front-end correction code can be approximated as:

[0079] ;

[0080] That is, by adjusting -ΔR i The corresponding initial correction code can be obtained by performing a q-bit arithmetic right shift, thus avoiding the need to set up a dedicated divider in the front-end correction code generation path and reducing hardware complexity.

[0081] The initial calibration codes output by the front-end calibration code generation module can be represented as fg_code2, fg_code3, and fg_code4. These initial calibration codes are written to the calibration code register for current sampling time mismatch compensation; they are also loaded into the background calibration code iteration module as initial values ​​for calibration code iteration during the background tracking phase.

[0082] During the background tracking phase, the TIADC input switches to the normal operating signal. Since the amplitude, frequency components, and statistical characteristics of the normal operating signal are typically unknown, the error information output from the autocorrelation error extraction path is no longer directly converted into a correction code. Instead, it serves as the error driving quantity for the background correction code iteration module. The background correction code iteration module can update the correction code as follows:

[0083] ;

[0084] Among them, c i [p] represents the correction code of the i-th channel at the p-th update, μ is the background correction step size, and ΔR i [p] represents the error information obtained from the p-th average window. Since the initial value of the background correction code iteration module comes from the front-end correction code generation module, the background tracking phase does not start iterating from the zero correction code or the default correction code, but rather starts updating from a position close to the target correction code.

[0085] In this embodiment, the same autocorrelation error extraction path is reused in the front-end initialization stage and the back-end tracking stage. No separate error extraction path is set up in the front-end stage; only a front-end correction code generation module, a selection module, and corresponding control logic are added to the existing back-end calibration structure. On the one hand, sharing the hardware computing link avoids setting up a separate error extraction computing unit for the front-end, thereby reducing additional digital hardware resource overhead. This allows the present invention to improve the overall calibration convergence speed with relatively small additional digital resource overhead and maintain long-term back-end tracking capability. On the other hand, it also allows the calibration system of the present invention to be embedded in existing autocorrelation back-end blind calibration structures. For back-end calibration systems that already have adjacent channel sample product, block averaging, and autocorrelation error generation modules, only the selection module, the front-end correction code generation module, and the initial correction code loading control logic need to be added to achieve the fusion of front-end initialization and back-end tracking.

[0086] The correction code register stores the correction code currently used for sampling time mismatch compensation. During the foreground initialization phase, the correction code register is written with the initial correction code output by the foreground correction code generation module; during the background tracking phase, it is written with the current correction code output by the background correction code iteration module. The correction module compensates for the TIADC sampling time mismatch based on the correction code output from the correction code register. The correction module can be implemented using correction structures such as analog variable delay lines, sampling clock phase adjustment circuits, digital domain fractional delay filtering, and digital differential compensation. When the correction module is implemented in the digital domain, the impact of additional analog delay adjustment structures on the sampling front-end and clock path can be reduced, thereby reducing analog hardware overhead and improving system integration.

[0087] like Figure 2 As shown, in this embodiment, after the foreground starts, a known test signal is first input to the TIADC. Once the known test signal stabilizes, foreground initialization is initiated. The autocorrelation error extraction path is reused to perform correlation statistics on the digital outputs of each TIADC channel and generate error information. Then, the foreground calibration code generation module generates an initial calibration code. The initial calibration code is written to the calibration code register and loaded into the background calibration code iteration module as the initial value for subsequent background tracking. Subsequently, the TIADC input is switched to a normal operating signal. Once the normal operating signal stabilizes, background tracking is initiated. The same autocorrelation error extraction path is reused to perform correlation statistics on the digital outputs of each TIADC channel and generate the error information. The background calibration code iteration module continuously updates the calibration code. The updated current calibration code is written to the calibration code register and used for sampling time mismatch compensation. When background tracking is no longer continued, the calibration process ends.

[0088] like Figure 3As shown, the control module can be implemented using a finite state machine (FSM). The finite state machine includes an idle state, a foreground waiting state, a foreground initialization state, a background waiting state, and a background tracking state. The idle state is used to wait for the foreground start signal; the foreground waiting state is used to wait for the input known test signal to stabilize; the foreground initialization state is used to complete error information extraction and initial calibration code generation; the background waiting state is used to wait for the input normal operation signal to stabilize; and the background tracking state is used to continuously execute iterative updates of the background calibration code.

[0089] like Figure 4 As shown, all state transitions and signal updates are synchronously driven by the clock signal clk. In the idle state, after the foreground start signal fg_start becomes valid, the system enters the foreground wait state, and the control module outputs the foreground busy signal fg_busy. Simultaneously, external systems, on-chip test signal generation circuits, or input selection units input known test signals to the TIADC, and the system waits for the test signals to stabilize. When the test signals stabilize, the external system returns the foreground ready signal fg_ready to the control module, and the system enters the foreground initialization state, with fg_busy remaining valid. In the foreground initialization state, the control module generates the averaging enable signal avg_en, enabling the block averaging module; the system multiplexes the autocorrelation error extraction path to complete the correlation statistics for an average window, and when the error information valid signal update_valid becomes valid, the foreground correction code generation module directly generates the initial correction code. Subsequently, the control module generates the foreground load signal fg_load, loading the initial correction code into the background correction code iteration module. Simultaneously, the correction code register completes the writing of the initial correction code and outputs the foreground completion signal fg_done.

[0090] Upon receiving `fg_done`, the external system switches the TIADC input from the known test signal to the normal operating signal and generates a background start signal `bg_start`, putting the system into a background waiting state and outputting a background busy signal `bg_busy`. After the normal operating signal stabilizes, the external system returns a background ready signal `bg_ready` to the control module, and the system enters the background tracking state, with `bg_busy` remaining active. In the background tracking state, the control module continues to generate an averaging enable signal `avg_en`, enabling the averaging module to perform relevant statistics according to the averaging window. Whenever an averaging window completes and generates `update_valid`, the selection module, under the condition that `bg_ready` is active, transmits the error information to the background calibration code iteration module, causing it to perform a calibration code iteration update and write the current calibration code to the calibration code register. When the system resets or background tracking stops (the background ready signal `bg_ready` becomes inactive), the control module returns to the idle state.

[0091] In this embodiment, the average window length can be set to an integer multiple of the number of sampling points corresponding to one cycle of the front-end test signal, so that each average window contains an integer number of complete test signal cycles. This allows the front-end initialization stage to obtain accurate and stable correlation statistics of adjacent channels through whole-cycle averaging. The background iteration step size μ can be controlled by the control signal cal_step. A smaller background iteration step size helps reduce steady-state residual error and correction code fluctuations, while the initial correction code generated in the front-end initialization stage allows the background iteration to start from a position close to the target value, thereby reducing the number of average windows required for background iteration convergence and shortening the overall calibration convergence time.

[0092] In this embodiment, an uncalibrated output data is generated using a four-channel, 12-bit, 16-GS / s TIADC behavioral-level model, and this uncalibrated output data is used for software convergence verification and digital hardware implementation verification. The normal operating input signal is a coherent single-tone sine wave signal with a frequency set to f. in =(7313 / 65536)f s ,in, The overall sampling rate of the TIADC is given. The initial sampling time mismatch for each channel is set to 0, -2.493 ps, 2.058 ps, and -2.009 ps, respectively. To verify the tracking capability of the background tracking phase for slowly varying sampling time mismatches, a channel-related slowly varying drift term is further superimposed on the behavioral model. This slowly varying drift term changes slowly with the simulation time, and its cumulative drift amplitude is on the order of 0.30 ps. The correction code time resolution is t. step Set to 10 fs, the front-end and back-end fusion calibration and the traditional back-end calibration use the same back-end iteration step size and average window length.

[0093] like Figure 5 As shown, in the behavioral-level model, the maximum residual sampling time offset after compensation for each non-reference channel is used as the convergence criterion; when the maximum residual sampling time offset decreases to no more than two correction code time resolutions, i.e., no more than 2t... stepWhen the calibration result is considered to have entered the stable calibration range, this embodiment takes the moment when each scheme begins calibration processing after the initial input signal stabilizes as the timing start point, and the time elapsed from that moment until the calibration result enters the stable calibration range as the overall calibration convergence time. For front-end and back-end fusion calibration, this time includes front-end initialization, stabilization waiting after input signal switching, and subsequent back-end iterative convergence process. In this embodiment, one average window corresponds to 8192 four-channel interleaving cycles; since each interleaving cycle contains 4 full-speed sampling points, one average window corresponds to 32768 full-speed sampling points. To simulate the aforementioned stabilization waiting process after input signal switching, the input stabilization interval is set to one average window in the behavioral simulation. Therefore, in the overall calibration convergence time statistics of this embodiment, the front-end and back-end fusion calibration experiences one front-end initialization window and one input stabilization interval, i.e., 65536 full-speed sampling points, before the back-end tracking begins. The front-end / back-end fusion calibration enters the stable calibration range after the 14th averaging window following back-end tracking, corresponding to the 524,288th sampling point on the full sampling time axis, or the 16th equivalent averaging window based on the full sampling time axis. Traditional back-end calibration, which does not require the front-end initialization window and the aforementioned input stabilization interval introduced by switching from the known test signal to the normal operating signal, enters the stable calibration range after the 4,358,144th sampling point, or the 133rd averaging window. This result shows that, under the same back-end iteration conditions, even considering the front-end initialization window and the stabilization waiting interval after input signal switching, the overall time required for the front-end / back-end fusion calibration to enter the stable calibration range is still significantly shorter than that of traditional back-end calibration. This indicates that the initial correction code provided during the front-end initialization phase can effectively reduce the convergence process required for subsequent back-end iterations, thereby improving the overall calibration convergence speed.

[0094] like Figure 6 and Figure 7 As shown, in the digital hardware implementation verification based on model output data, there were obvious spurious components in the output spectrum before calibration caused by sampling time mismatch. After the front-end and back-end fusion calibration described in this embodiment, the relevant spurious components were effectively suppressed, and the output spectrum quality was improved. In this embodiment, the SFDR of the output spectrum before calibration was 34.9 dB and the SNDR was 34.1 dB; the SFDR of the output spectrum after calibration was 86.5 dB and the SNDR was 73.4 dB. This result shows that this embodiment can improve the overall calibration convergence speed while maintaining a good sampling time mismatch compensation effect.

[0095] Figures 1 to 4 The system structure, calibration process, control state, and control timing of the present invention are illustrated. Figure 5 This demonstrates the improved overall convergence speed of front-end / back-end fusion calibration compared to traditional back-end calibration. Figure 6 and Figure 7 The improved output spectrum before and after calibration is demonstrated. Through the above embodiments, the present invention can improve the overall calibration convergence speed of TIADC sampling time mismatch with relatively small additional digital hardware overhead, while maintaining long-term background tracking capability.

[0096] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0097] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A front-end and back-end integrated TIADC sampling time mismatch digital calibration system, characterized in that, The system includes: The autocorrelation error extraction path is used to generate error information related to the sampling time mismatch between the TIADC channels based on the digital output of each channel of the TIADC. The selection module is connected to the output end of the autocorrelation error extraction path. It is used to transmit the error information obtained under the known test signal input condition to the front-end calibration code generation module during the front-end initialization stage, and to transmit the error information obtained under the normal working signal input condition to the back-end calibration code iteration module during the background tracking stage. A front-end calibration code generation module is connected to the output of the selection module and is used to generate an initial calibration code based on the parameters of the known test signal and the error information during the front-end initialization phase. The background correction code iteration module is connected to the output of the selection module and the output of the front-end correction code generation module, respectively. It is used to receive the initial correction code and, during the background tracking phase, use the initial correction code as the initial value for correction code iteration and iteratively update the correction code according to the error information obtained during the background tracking phase. The correction code register is connected to the output of the front-end correction code generation module and the back-end correction code iteration module, respectively, and is used to store the initial correction code in the front-end initialization stage and the current correction code output by the back-end correction code iteration module in the back-end tracking stage. A correction module, connected to the correction code register, is used to compensate for the sampling time mismatch of the TIADC according to the correction code output by the correction code register. The control module is used to control the multiplexing of the autocorrelation error extraction path between the front-end initialization stage and the back-end tracking stage, control the transmission path of the selection module, control the loading of the initial correction code to the back-end correction code iteration module, and control the iterative update of the back-end correction code iteration module.

2. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The autocorrelation error extraction path includes a sequentially connected adjacent channel sample product module, block averaging module, and autocorrelation error generation module; the adjacent channel sample product module is used to calculate the product between adjacent channel output samples; the block averaging module is used to perform average window statistics on the product to obtain the averaged adjacent channel correlation statistics; the autocorrelation error generation module is used to generate the sampling time mismatch correlation error information based on the averaged adjacent channel correlation statistics.

3. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The front-end calibration code generation module includes an error information input terminal and an initial calibration code output terminal. The error information input terminal is used to receive the error information output by the selection module during the front-end initialization phase. The initial calibration code output terminal is used to generate and output the initial calibration code based on the error information obtained within an average window, as well as the frequency, amplitude, average window length, and calibration code time resolution of the known test signal. ； In the formula, Let be the initial calibration code for the i-th channel; C is the scaling factor determined by the test signal amplitude and correlation statistics. The phase difference between adjacent sampling points of a sinusoidal signal. To test the signal frequency, This is the overall sampling period of TIADC. Adjust the resolution for the time corresponding to one correction code unit; This is the error information related to the sampling time mismatch of the i-th channel.

4. The front-end and back-end integrated TIADC sampling time mismatch digital calibration system according to claim 1 or 3, characterized in that, The frequency, amplitude, and average window length of the known test signal are set to satisfy the whole-cycle averaging condition and the proportional conversion approximation condition, so that the front-end correction code generation module generates the initial correction code through arithmetic shift operations.

5. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The background calibration code iteration module includes an initial code input terminal, an error information input terminal, and a calibration code output terminal. The initial code input terminal is used to receive the initial calibration code generated by the front-end calibration code generation module during the front-end initialization phase, so that the background calibration code iteration module uses the initial calibration code as the initial value for calibration code iteration during the background tracking phase. The error information input terminal is used to receive the error information output by the selection module during the background tracking phase. The calibration code output terminal is used to output the current calibration code after iterative updates based on the initial calibration code iteration value and the error information.

6. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The control module is used to receive a foreground start signal, a foreground preparation signal, a background start signal, and a background preparation signal, and output a foreground completion signal, a foreground busy signal, and a background busy signal. The foreground start signal is used to initiate the foreground process; the foreground preparation signal indicates that the known test signal is stable; the foreground completion signal indicates that the initial calibration code has been generated and loaded; the background start signal is generated by an external system based on the foreground completion signal and used to initiate the background process; the background preparation signal indicates that the normal operating signal is stable; the foreground busy signal indicates that the system is in a foreground waiting state or a foreground initialization state; and the background busy signal indicates that the system is in a background waiting state or a background tracking state.

7. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The test signals used in the front-end initialization phase are provided by an external signal source or generated by an on-chip or board-level test signal generation circuit, and can be switched between test signals and normal operation signals through an external system, board-level input selection unit, or on-chip input selection structure.

8. The TIADC sampling time mismatch digital calibration system with front-end and back-end integration as described in claim 1, characterized in that, The autocorrelation error extraction path, selection module, front-end correction code generation module, back-end correction code iteration module, correction code register, and control module are all implemented by digital circuits; when the correction module adopts a digital domain compensation structure, the system completes the full digital calibration of sampling time mismatch based on the digital output of each channel of the TIADC.

9. A front-end and back-end integrated TIADC sampling time mismatch digital calibration method, characterized in that, The method includes the following steps: After the foreground is started, a known test signal is input to the TIADC, and after the known test signal stabilizes, the foreground initialization stage is entered. The digital output of each channel of the TIADC is used to generate error information related to the sampling time mismatch between the TIADC channels through the autocorrelation error extraction path. An initial correction code is generated based on the parameters of the known test signal and the error information; The initial correction code is written into the correction code register for sampling time mismatch compensation and loaded into the background correction code iteration module as the initial value for correction code iteration in the background tracking stage. After the foreground initialization phase is completed, the TIADC input is switched to the normal working signal, and the background tracking phase begins after the normal working signal stabilizes. During the background tracking phase, the autocorrelation error extraction path is reused to generate the sampling time mismatch related error information based on the digital output of each channel under the normal operating signal of the TIADC. The background correction code iteration module continuously updates the correction code starting from the initial correction code. The updated correction code is written into the correction code register for sampling time mismatch compensation.

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