A synchronous clock circuit

Abstract

The application provides a synchronous clock circuit, and relates to the technical field of integrated circuits.The synchronous clock circuit comprises a clock generation circuit, a shift register, delay control logic and a phase generation circuit.The clock generation circuit is used for generating a synchronous clock signal based on an externally input global sampling clock signal.The shift register is used for generating a flag signal and a feedback signal under the control of the synchronous clock signal input by the clock generation circuit.The delay control logic is used for adjusting the frequency of the synchronous clock signal input by the clock generation circuit to the shift register based on the feedback signal input by the shift register until the feedback signal generated by the shift register meets a preset condition.The phase generation circuit is used for generating a plurality of phase clock signals based on the flag signal input by the shift register and the adjusted synchronous clock signal input by the clock generation circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a synchronous clock circuit. Background Technology

[0002] With the increasing demands for sampling rate and accuracy in applications such as high-speed data acquisition, communication interfaces, and signal processing, analog-to-digital converters (ADCs) are increasingly widely used in various integrated circuit systems. In high-speed ADCs, several clock signals with sequentially staggered phases typically drive each sampling branch to complete multiple ordered samples within a single global sampling cycle, thereby improving the overall equivalent sampling rate and throughput. Therefore, generating a set of multi-phase clocks with accurate phase relationships and stable timing, starting from a single global sampling clock, is a fundamental task in high-speed ADC circuit design.

[0003] However, in related technologies, due to the influence of factors such as the chip's process batch, power supply voltage, and operating temperature, the overall clock speed of the multi-phase clock generated inside the chip is prone to shift relative to the global sampling period, which in turn affects the timing and sampling accuracy of each sampling branch of the ADC within a global sampling period. Summary of the Invention

[0004] In view of the above problems, this application provides a synchronous clock circuit.

[0005] This application provides a synchronous clock circuit, comprising: a clock generation circuit for generating a synchronous clock signal based on an externally input global sampling clock signal; a shift register for generating a flag signal and a feedback signal under the control of the synchronous clock signal input to the clock generation circuit; delay control logic for adjusting the frequency of the synchronous clock signal input from the clock generation circuit to the shift register based on the feedback signal input to the shift register, until the feedback signal generated by the shift register meets a preset condition; and a phase generation circuit for generating multiple phase clock signals based on the flag signal input to the shift register and the adjusted synchronous clock signal input to the clock generation circuit.

[0006] Further, the clock generation circuit comprises: an AND gate, configured to output a gating signal based on an externally input global sampling clock signal and a synchronous clock signal input via a feedback branch; multi-stage cascaded inverters, configured to generate the synchronous clock signal based on the gating signal input by the AND gate; a coarse adjustment delay module, configured to adjust the coarse adjustment delay amount of the signal path formed by the multi-stage cascaded inverters based on a coarse adjustment control signal input by a delay control logic; and a fine adjustment delay module, configured to adjust the fine adjustment delay amount of the signal path formed by the multi-stage cascaded inverters based on a fine adjustment control signal input by the delay control logic.

[0007] Further, the coarse adjustment delay module comprises: a plurality of first switches, which are respectively disposed between different inter-stage nodes of the multi-stage cascaded inverters and the output end of the coarse adjustment delay module, and configured to control the turn-on and turn-off of each first switch based on the bits of the coarse adjustment control signal input by the delay control logic, so as to select the number of stages of inverters participating in loop oscillation from the multi-stage cascaded inverters, thereby adjusting the coarse adjustment delay amount of the synchronous clock signal.

[0008] Further, the fine adjustment delay module comprises: a plurality of second switches, which are respectively connected in series between a plurality of capacitors and the output node of one inverter in the multi-stage cascaded inverters, and configured to control the turn-on and turn-off of each second switch based on each bit of the fine adjustment control signal input by the delay control logic, so as to adjust the number of capacitors connected to the output node of the inverter, thereby adjusting the fine adjustment delay amount of the synchronous clock signal.

[0009] Further, the shift register comprises: N stages of D flip-flops connected in series, configured to access a power supply level from the first-stage D flip-flop and input data stage by stage from the previous-stage D flip-flop to the next-stage D flip-flop under the control of the synchronous clock signal input by the clock generation circuit; the M-th stage D flip-flop among the N stages of D flip-flops connected in series, configured to output a flag signal via a first output end; the K-th stage D flip-flop and the L-th stage D flip-flop among the N stages of D flip-flops connected in series, configured such that the K-th stage D flip-flop outputs a high bit of a feedback signal, and the L-th stage D flip-flop outputs a low bit of the feedback signal, where the high bit of the feedback signal and the low bit of the feedback signal form the feedback signal; wherein N is an integer greater than a preset number, M<K<L, and M, K, and L are respectively used to indicate different period nodes of the synchronous clock signal.

[0010] Furthermore, the feedback signal input from the shift register to the delay control logic includes the current feedback signal and the historical feedback signal; the delay control logic includes: an adjustment mode selection unit, used to select an adjustment mode for adjusting the frequency of the synchronous clock signal based on the feedback signal and the current adjustment mode in response to the rising edge of the global sampling clock signal, when the current feedback signal does not meet the preset conditions; a control signal output unit, used to output a control signal for adjusting the delay amount of the synchronous clock signal to the clock generation circuit based on the adjustment mode and the frequency deviation direction indicated by the current feedback signal; and a feedback update unit, used to update the current feedback signal to the historical feedback signal after the adjustment is completed, and apply it to the selection of the next adjustment mode, until the feedback signal meets the preset conditions.

[0011] Further, the adjustment modes include a coarse adjustment mode and a corresponding coarse adjustment control signal, and a fine adjustment mode and a corresponding fine adjustment control signal; the adjustment mode selection unit includes: a mode switching subunit, used to switch the adjustment mode from the current coarse adjustment mode to the fine adjustment mode when the feedback signal or the current adjustment mode meets any of the following switching conditions: the frequency of the historical feedback signal indicating the synchronization clock signal has not reached the preset frequency, and the frequency of the current feedback signal indicating the synchronization clock signal exceeds the preset frequency; the frequency of the historical feedback signal indicating the synchronization clock signal exceeds the preset frequency, and the frequency of the current feedback signal indicating the synchronization clock signal has not reached the preset frequency; the coarse adjustment control signal corresponding to the coarse adjustment mode has reached the preset coarse adjustment lower boundary value; the coarse adjustment control signal corresponding to the coarse adjustment mode has reached the preset coarse adjustment upper boundary value; and a mode holding subunit, used to keep the coarse adjustment mode unchanged when the current feedback signal and the historical feedback signal do not meet any of the above switching conditions.

[0012] Further, the control signal output unit includes: a fine-tuning output subunit, used to output a fine-tuning control signal that steps in the direction of reducing the delay amount to the clock generation circuit when the current feedback signal indicates that the frequency of the synchronous clock signal has not reached the preset frequency and the fine-tuning control signal has not reached the preset fine-tuning lower boundary value, and when the adjustment mode is fine-tuning mode; and to output a fine-tuning control signal that steps in the direction of increasing the delay amount to the clock generation circuit when the current feedback signal indicates that the frequency of the synchronous clock signal has exceeded the preset frequency and the fine-tuning control signal has not reached the preset fine-tuning upper boundary value; and a coarse-tuning output subunit, used to output a coarse-tuning control signal that steps in the direction of reducing the delay amount according to a preset adjustment sequence to the clock generation circuit when the adjustment mode is coarse-tuning mode, and to output a coarse-tuning control signal that steps in the direction of increasing the delay amount according to a preset adjustment sequence to the clock generation circuit when the current feedback signal indicates that the frequency of the synchronous clock signal has not reached the preset frequency; and to output a coarse-tuning control signal that steps in the direction of increasing the delay amount according to a preset adjustment sequence to the clock generation circuit when the current feedback signal indicates that the frequency of the synchronous clock signal has exceeded the preset frequency.

[0013] Further, the phase generation circuit includes: a first multiplexer, used to select and output a synchronous clock signal input to the clock generation circuit and a ground level under a flag signal input to the shift register; a second multiplexer, used to select and output a first phase clock signal under a global sampling clock signal, based on the signal input to the first multiplexer and the ground level; an XOR gate, used to output a second phase clock signal based on one bit of the flag signal and feedback signal input to the shift register; and a delay unit, used to output a third phase clock signal based on the second phase clock signal input to the XOR gate; wherein the first phase clock signal, the second phase clock signal, and the third phase clock signal constitute multiple phase clock signals.

[0014] Furthermore, the circuit also includes an analog-to-digital converter (ADC) architecture; the ADC architecture includes: a first-stage ADC for sampling based on an externally input global sampling clock signal and performing analog-to-digital conversion based on a first-phase clock signal input from a phase generation circuit, outputting a first-stage conversion result; a residual amplifier for amplifying the first-stage conversion result input from the first-stage ADC based on a third-phase clock signal input from the phase generation circuit, outputting a residual signal; a second-stage ADC for sampling and performing analog-to-digital conversion on the residual signal input from the residual amplifier based on a second-phase clock signal input from the phase generation circuit, outputting a second-stage conversion result; and a digital calibration engine for performing digital calibration based on the first-stage conversion result input from the first-stage ADC and the second-stage conversion result input from the second-stage ADC.

[0015] Compared with the prior art, the synchronous clock circuit provided in this application has at least the following advantages:

[0016] (1) By introducing coarse adjustment delay module and fine adjustment delay module in clock generation circuit at the same time, and adopting coarse adjustment mechanism based on inverter stage selection and fine adjustment mechanism based on inverter output node load capacitor number switching respectively, the fine adjustment step size can be taken into account in a large delay adjustment range, so that the frequency of synchronous clock signal can quickly approach the preset frequency and achieve high-resolution stable locking, effectively overcoming the problem that traditional single delay adjustment method is difficult to balance between adjustment range and adjustment accuracy.

[0017] (2) By setting up a shift register consisting of N-stage series D flip-flops, and extracting the flag signal and feedback signal from the M-th, K-th and L-th stages respectively, the frequency deviation of the synchronous clock signal can be implicitly encoded by the level state of different period nodes during the shift process without introducing an additional counting circuit. This provides a low-overhead, high-real-time frequency deviation judgment basis for the delay control logic.

[0018] (3) By setting an adjustment mode selection unit, a control signal output unit and a feedback update unit in the delay control logic, and comprehensively judging the switching timing between coarse adjustment mode and fine adjustment mode based on the current feedback signal, historical feedback signal and the current adjustment mode, the synchronous clock circuit can quickly perform coarse adjustment convergence when the frequency deviation is large, and automatically switch to fine adjustment precise locking when approaching the target frequency. Furthermore, by limiting the upper and lower boundary values ​​of coarse adjustment and fine adjustment, the control signal overflow is avoided, thereby improving the convergence speed and stability of synchronous clock signal frequency adjustment.

[0019] (4) By setting up a phase generation circuit consisting of a first multiplexer, a second multiplexer, an XOR gate and a delay unit, and generating a first phase clock signal, a second phase clock signal and a third phase clock signal based on a synchronous clock signal and a flag signal, multiple clock signals with definite phase relationships can be output under the same phase generation architecture, providing multi-phase clock drive with strict timing alignment for downstream multi-stage pipeline modules.

[0020] (5) By combining the synchronous clock circuit with the first-stage analog-to-digital converter, the residual amplifier, the second-stage analog-to-digital converter and the digital calibration engine to form an analog-to-digital converter architecture, and using multi-phase clock signals to control the sampling, analog-to-digital conversion, residual amplification and inter-stage data transfer of each stage of the analog-to-digital converter, the analog-to-digital conversion operations of each stage can be strictly aligned to the global sampling clock signal. Combined with the digital calibration engine to calibrate the inter-stage conversion error, the conversion accuracy and anti-timing mismatch capability of the analog-to-digital converter architecture can be further improved. Attached Figure Description

[0021] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0022] Figure 1 This schematically illustrates the overall architecture of a synchronous clock circuit according to an embodiment of this application;

[0023] Figure 2 A schematic diagram of the structure of a clock generation circuit according to an embodiment of this application is shown.

[0024] Figure 3 A schematic diagram of the structure of a shift register according to an embodiment of this application is shown.

[0025] Figure 4 The schematic diagram illustrates a flow chart of the delay control logic according to an embodiment of this application;

[0026] Figure 5 The schematic diagram illustrates the adjustment timing of the clock generation circuit according to an embodiment of this application in a frequency-to-fast state;

[0027] Figure 6 A schematic diagram of the phase generation circuit according to an embodiment of this application is shown.

[0028] Figure 7 The overall timing diagram of the synchronous clock circuit according to an embodiment of this application under the Pipelined-SAR ADC architecture is illustrated schematically.

[0029] Figure 8 A schematic diagram of a Pipelined-SAR ADC architecture for a synchronous clock circuit according to an embodiment of this application is shown. Detailed Implementation

[0030] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] In the process of implementing this application, it was found that the multi-external clock input + external timing calibration architecture has some problems in the multi-module timing coordination problem of pipelined-SAR ADC.

[0034] (1) High risk of timing mismatch and limited conversion accuracy. Each operational amplifier module in the pipeline, such as reset / amplification, SAR comparison, DAC update, and sample-and-hold, relies on an independent external clock. Multiple clock signals are prone to clock skew during board-level routing, and this deviation will fluctuate with the routing length and ambient temperature. This causes the sampling window of the sample-and-hold circuit to not overlap with the effective phase of the SAR comparison clock, directly causing quantization error and reducing the linearity and conversion accuracy of the ADC.

[0035] (2) The system integration is complex and the R&D cost increases. The multi-clock interface requires the external configuration of a dedicated clock generation circuit and calibration module, which not only increases the difficulty of system hardware design and occupies additional board space, but also requires the external calibration circuit to manually adjust the timing parameters for different application scenarios, which prolongs the product development cycle and deployment cost.

[0036] (3) Poor power consumption and anti-interference ability, and insufficient stability. The transmission and driving of multiple clock signals require additional power consumption, and the superposition of multiple clocks is prone to electromagnetic coupling interference; the external clock signal is easily affected by power supply noise and electromagnetic radiation during transmission, resulting in timing jitter, which further reduces the stability of ADC operation.

[0037] (4) Poor adaptability and inability to dynamically respond to changes in operating conditions. The clock phase, duty cycle, delay and other parameters are fixed, making it difficult to adapt to the switching of the ADC's working mode in different application scenarios (such as resolution adjustment and conversion rate change), and it is also unable to compensate for timing drift caused by changes in PVT (process, voltage and temperature), which limits the application range of the ADC.

[0038] In view of this, embodiments of this application provide a synchronous clock circuit, which is designed from a single global sampling clock input, synchronous clock adaptive generation, closed-loop delay calibration, multi-phase clock derivation to analog-to-digital converter architecture integration, to obtain a PVT robust, timing accurate and flexibly portable Pipelined-SAR ADC clock driving scheme.

[0039] Figure 1 The schematic diagram illustrates the overall architecture of a synchronous clock circuit according to an embodiment of this application.

[0040] like Figure 1 As shown, the synchronous clock circuit of this embodiment includes a clock generation circuit, a shift register, delay control logic, and a phase generation circuit.

[0041] The connections between the components are as follows: The clock generation circuit has a first input terminal, a second input terminal, and an output terminal. Its first input terminal is used to receive the externally input global sampling clock signal. Its second input is connected to the output of the delay control logic to receive a control signal for adjusting the frequency of the synchronization clock signal, and its output is used to output the synchronization clock signal. The clock input of the shift register is connected to the output of the clock generation circuit to receive the synchronous clock signal. Its first output terminal is used to output the flag signal FLAG, and its second output terminal is used to output the feedback signal. The input terminal of the delay control logic is connected to the second output terminal of the shift register to provide feedback control signals. The phase generation circuit has two input terminals and multiple output terminals. Its two input terminals are respectively connected to the output terminal of the clock generation circuit and the first output terminal of the shift register to receive synchronous clock signals. It also includes a flag signal (FLAG) and outputs multiple phase clock signals through its multiple output terminals.

[0042] Based on the above architecture, the working principle of the synchronous clock circuit in this application embodiment is as follows:

[0043] The clock generation circuit generates a synchronous clock signal based on an externally input global sampled clock signal. Specifically, the global sampled clock signal, serving as the clock reference for the entire synchronous clock circuit, is input to the clock generation circuit. The clock generation circuit processes this global sampled clock signal and outputs a synchronous clock signal, which is then provided to the shift register and the phase generation circuit. Furthermore, the clock generation circuit receives a control signal from the delay control logic feedback and adjusts the frequency of its output synchronous clock signal according to this control signal, thereby achieving dynamic adjustment of the synchronous clock signal.

[0044] The shift register is used to generate a flag signal (FLAG) and a feedback signal under the control of the synchronous clock signal input to the clock generation circuit. The flag signal (FLAG) is output to the phase generation circuit, which generates multiple phase clock signals accordingly. The feedback signal is output to the delay control logic, which adjusts the frequency of the synchronous clock signal output by the clock generation circuit, thus forming a closed-loop control of the clock generation circuit.

[0045] The delay control logic adjusts the frequency of the synchronous clock signal input from the clock generation circuit to the shift register based on the feedback signal input from the shift register, until the feedback signal generated by the shift register meets a preset condition. Specifically, after receiving the feedback signal output from the shift register, the delay control logic judges the feedback signal: if the feedback signal does not meet the preset condition, the delay control logic outputs a corresponding control signal to the clock generation circuit to adjust the frequency of the synchronous clock signal output by the clock generation circuit; the adjusted synchronous clock signal is then input to the shift register again, and the shift register generates a new feedback signal and feeds it back to the delay control logic; this process is repeated until the feedback signal output by the shift register meets the preset condition, at which point the delay control logic stops adjusting, and the synchronous clock signal output by the clock generation circuit is the adjusted synchronous clock signal required. Through the closed-loop feedback adjustment mechanism consisting of the shift register, delay control logic, and clock generation circuit, the frequency of the synchronous clock signal can adaptively converge to the target state corresponding to the preset condition, thereby providing a stable and reliable clock reference for the subsequent phase generation circuit to generate multiple phase clock signals.

[0046] The phase generation circuit generates multiple phase clock signals based on the flag signal (FLAG) input from the shift register and the adjusted synchronous clock signal input from the clock generation circuit. Specifically, after the delay control logic adjusts the frequency of the synchronous clock signal, the phase generation circuit uses the adjusted synchronous clock signal as the clock reference and, in conjunction with the flag signal (FLAG) output from the shift register, generates multiple phase clock signals and outputs them externally for use by subsequent circuits.

[0047] Through the above architecture, the synchronous clock circuit of this application embodiment can adaptively adjust the frequency of the synchronous clock signal based on the externally input global sampling clock signal, using a closed-loop feedback mechanism composed of a shift register and delay control logic. After the adjustment is completed, the phase generation circuit combines the flag signal FLAG to output multiple phase clock signals, thereby realizing the accurate generation of the synchronous clock signal and the stable output of multiple phase clock signals.

[0048] Figure 2 The schematic diagram illustrates the structure of a clock generation circuit according to an embodiment of this application. In some embodiments, the clock generation circuit is essentially an inverter ring oscillator with a delay adjustment module, including: an AND gate, multiple cascaded inverters, a coarse delay adjustment module, and a fine delay adjustment module.

[0049] The connections between the components are as follows: The first input of the AND gate is used to receive the externally input global sampling clock signal. Its second input terminal is connected to the output node of the clock generation circuit via a feedback branch to receive the feedback synchronous clock signal. Its output is connected to the input of the first-stage inverter in a multi-stage cascaded inverter. The inverters in the multi-stage cascaded inverter are connected end-to-end in sequence, forming a chain structure that transmits signals from the output of the preceding inverter to the input of the following inverter. The output of the last-stage inverter in the multi-stage cascaded inverter is fed back to the second input of the AND gate via a coarse-adjustment delay module, forming a closed-loop oscillation circuit. The control terminal of the coarse-adjustment delay module is connected to the first output of the delay control logic to receive the coarse-adjustment control signal SELC[4:0]. One end of the fine-adjustment delay module is connected to the output node of one inverter in the multi-stage cascaded inverter (i.e., an internal node in the loop, preferably the output of an inverter close to the feedback node), and its control terminal is connected to the second output of the delay control logic to receive the fine-adjustment control signal SELF[4:0]. Synchronous clock signal The signal is buffered by a first-stage output inverter after passing through the feedback node and then output to the output terminal of the clock generation circuit.

[0050] Specifically, the AND gate is used for global sampling of the clock signal based on the external input. and the synchronous clock signal input via the feedback branch Output gate signal. When When the level is high, the AND gate opens the loop oscillation path, and the feedback branch... and These factors collectively determine the input levels of the multi-stage cascaded inverters, thus forming a self-oscillating circuit; when When the level is low, the AND gate closes the loop. Stop the oscillation to avoid the extra power consumption caused by invalid flips.

[0051] Cascaded inverters are used to generate synchronous clock signals based on gated signals from AND gate inputs. In one embodiment of this application, the number of stages in the cascaded inverters is preferably nine, which can be adjusted appropriately according to the target oscillation frequency. The signal path formed by the multi-stage inverters constitutes a ring oscillation loop, and its total propagation delay directly determines the frequency. The period and frequency.

[0052] The coarse adjustment delay module is used to adjust the coarse adjustment delay amount of the signal path formed by the multi-stage cascaded inverters based on the coarse adjustment control signal SELC[4:0] input to the delay control logic. In some embodiments, the coarse adjustment delay module includes a plurality of first switches, which are respectively connected in series between different inter-stage nodes of the multi-stage cascaded inverters (i.e., output nodes between different inverters) and the output terminal of the coarse adjustment delay module (i.e., loop feedback node), and the control terminal of each first switch is respectively connected to a different bit of the coarse adjustment control signal SELC[4:0].

[0053] It should be noted that the coarse adjustment delay is directly related to the coarse adjustment control signal SELC[4:0]. Essentially, it adjusts the total propagation delay of the loop by changing the number of inverter stages actually involved in the oscillation. Specifically, the delay control logic controls the on / off state of each first switch through different bits of the coarse adjustment control signal SELC[4:0]. When a certain bit in SELC[4:0] is high, the first switch corresponding to that bit is turned on, allowing the inverted output signal of the corresponding inter-stage node to be selected and fed back to the second input of the AND gate, thus determining the number of inverter stages the loop oscillates through. Only one first switch is turned on at any given time to ensure the loop's uniqueness. For example, when SELC[4:0] = 5'b10000, the first inter-stage node is selected, resulting in fewer inverter stages participating in the loop oscillation and a smaller total loop delay. The frequency is relatively high; when SELC[4:0]=5'b00001, the last inter-stage node is selected, and a large number of inverters are connected to the loop, resulting in a larger total loop delay. The frequency is low. Therefore, the value of SELC[4:0] determines the level of coarse adjustment delay, and thus determines... Coarse frequency adjustment settings.

[0054] The fine-tuning delay module is used to adjust the fine-tuning delay amount of the signal path formed by the multi-stage cascaded inverters based on the fine-tuning control signal SELF[4:0] input to the delay control logic. In some embodiments, the fine-tuning delay module includes multiple capacitors and multiple second switches, with the multiple second switches connected in series with one of the multiple capacitors and one of the multi-stage cascaded inverters (preferably the inverter closest to the feedback node, such as...). Figure 2 Between the output nodes of the inverter located at the front end of the feedback branch, and the control terminals of each second switch are connected one-to-one with different bits of the fine-tuning control signal SELF[4:0], and the other ends of each capacitor are grounded together.

[0055] It should be noted that the fine-tuning delay is directly related to the fine-tuning control signal SELF[4:0]. Essentially, it adjusts the propagation delay of the inverter stage by changing the equivalent load capacitance of the inverter's output node. Since this stage inverter is a link in the loop, its delay change reflects a subtle change in the total loop delay. Specifically, the delay control logic controls the on / off state of each second switch through each bit of the fine-tuning control signal SELF[4:0]. When a bit in SELF[4:0] is high, the corresponding second switch is turned on, and the corresponding capacitor is connected to the inverter's output node, increasing the node's equivalent load capacitance. When the bit is low, the corresponding second switch is turned off, and the capacitor is disconnected from the node. Therefore, the more high-level bits in SELF[4:0], the larger the total capacitance connected to the node, the longer the charging and discharging time of the inverter's output node, and the greater the propagation delay. The lower the frequency, the fewer the number of high-level bits in SELF[4:0], the fewer the connected capacitors, the smaller the node equivalent capacitance, and the smaller the propagation delay. The higher the frequency, the better. Therefore, SELF[4:0] achieves adjustment based on the coarse adjustment level. Fine-tuning of frequency.

[0056] In summary, the coarse adjustment delay in the clock generation circuit is determined by the coarse adjustment control signal SELC[4:0] through selecting the number of inverter stages participating in the loop oscillation, while the fine adjustment delay is determined by the fine adjustment control signal SELF[4:0] through adjusting the equivalent load capacitance of the inverter output node. These two adjustments are independent of each other and do not interfere with each other, together forming the clock generation circuit. A dual delay adjustment mechanism for frequency. Through a dual delay adjustment mechanism combining coarse and fine adjustments, the clock generation circuit can achieve high-resolution delay control over a wide frequency adjustment range. This allows for rapid approximation of the target frequency while also enabling high-precision fine-tuning during the locking phase. In one embodiment of this application, the clock generation circuit is configured by default upon power-on as SELC[4:0]=5'b00100 (corresponding to decimal 4) and SELF[4:0]=5'b10000 (corresponding to decimal 16), located in the middle range between coarse and fine adjustments, facilitating bidirectional adjustment.

[0057] Figure 3 The schematic diagram illustrates the structure of a shift register according to an embodiment of this application. In some embodiments, the shift register includes N cascaded D flip-flops, where N is an integer greater than a preset number, preferably not less than 8.

[0058] The connection relationship between the components is as follows: N stages of D flip-flops are connected in series in sequence, wherein the data input terminal D of the first-stage D flip-flop (i.e., the first-stage D flip-flop) is connected to the power supply level VDD, and the data output terminal Q thereof is connected to the data input terminal D of the second-stage D flip-flop; from the second stage to the Nth stage, the data output terminal Q of each stage of D flip-flop is connected to the data input terminal D of the next-stage D flip-flop, forming a register chain for unidirectional data transmission; the clock input terminals Clk of all D flip-flops are commonly connected to the output terminal of the clock generation circuit to receive the synchronous clock signal . The output terminal Q of the M-th stage D flip-flop among the N stages of series-connected D flip-flops serves as the first output terminal of the shift register to lead out the flag signal FLAG; the output terminal Q of the K-th stage D flip-flop and the output terminal Q of the L-th stage D flip-flop serve as the second output terminal of the shift register to jointly lead out the feedback signal, wherein the output terminal Q of the K-th stage D flip-flop leads out the high bit (such as EOC[1]) of the feedback signal, and the output terminal Q of the L-th stage D flip-flop leads out the low bit (such as EOC[0]) of the feedback signal.

[0059] Based on the above connection relationship, each time the edge of is triggered, the VDD level is transmitted one stage backward along the register chain, so as to realize accurate counting of the number of cycles. Wherein M<K<L, and M, K, and L are respectively used to indicate the synchronous clock signal different cycle nodes. In an embodiment of the present application, N is 8, M is 5, K is 7, and L is 8, that is: the FLAG signal is led out from the output terminal of the 5th-stage D flip-flop, at the triggered by the falling edge of the 5th cycle, identifying the end of the first 5 cycles; EOC[1] in the feedback signal EOC[1:0] is led out from the 7th-stage D flip-flop, triggered by the falling edge of the 7th cycle, identifying the end of the 7th cycle; EOC[0] is led out from the 8th-stage D flip-flop, triggered by the rising edge of the 8th cycle, identifying the start of the 8th cycle. Through the timing relationship of the three signals FLAG, EOC[1], and EOC[0] at different cycle nodes, implicit coding can be realized which is equivalent to the global sampling clock alignment situation.

[0060] Specifically, the feedback signal EOC[1:0] is used as the timing state feedback signal, and its three typical values respectively correspond to three frequency deviation states: EOC[1:0]=10 indicates that in one complete cycle of, exactly 7 cycles are completed, and the frequency accurately matches the preset design; EOC[1:0]=00 indicates that 7 cycles have not been completed within this cycle, the speed is too slow (that is, the frequency does not reach the preset frequency); EOC[1:0]=11 indicates that More than 7 cycles have been completed within this period, which is too fast (i.e., the frequency exceeds the preset frequency).

[0061] Figure 4 A schematic flowchart of the delay control logic according to an embodiment of this application is shown. In some embodiments, the feedback signals input from the shift register to the delay control logic include the current feedback signal EOC and the historical feedback signal EOC_PRE. The delay control logic includes an adjustment mode selection unit, a control signal output unit, and a feedback update unit.

[0062] The adjustment mode selection unit is used in response to the global sampling clock signal. On the rising edge, if the current feedback signal EOC does not meet the preset condition (i.e., EOC≠2'b10), the synchronous clock signal CK is selected for adjustment based on the feedback signal and the current adjustment mode. ASC Frequency adjustment mode. If RST_N=0 indicates that the system is in a reset state, the key parameters are initialized to SELC=5'b00100, SELF=5'b10000, EOC_PRE=2'b10, and C2F=1'b0 (C2F is the status bit indicating the current adjustment mode; C2F=1'b0 indicates coarse adjustment mode, and C2F=1'b1 indicates fine adjustment mode); if not reset, the normal adjustment process is entered.

[0063] Specifically, the adjustment mode selection unit first determines whether the EOC signal is 2'b10: if EOC=2'b10, it indicates... The frequency has converged to the target state and no adjustment is needed. Directly set C2F=1'b0; if EOC≠2'b10 (i.e., EOC=2'b00 or EOC=2'b11), then proceed to the mode decision process.

[0064] The control signal output unit is used to output a synchronization clock signal to the clock generation circuit based on the adjustment mode and the frequency deviation direction indicated by the current feedback signal EOC. The delay amount is controlled by the signal SELC[4:0] or SELF[4:0].

[0065] The feedback update unit is used to update the current feedback signal EOC to the historical feedback signal EOC_PRE register after the adjustment is completed, and apply it to the selection of the next adjustment mode until the feedback signal EOC stably meets the preset condition of EOC=2'b10.

[0066] In some embodiments, the adjustment mode selection unit further includes a mode switching subunit and a mode holding subunit. The mode switching subunit is used to switch the adjustment mode from the current coarse adjustment mode to the fine adjustment mode (i.e., set C2F=1'b1) when the feedback signal or the current adjustment mode meets any of the following switching conditions:

[0067] Condition 1: Historical feedback signal EOC_PRE=2'b00 (indicating the previous timeframe) (Frequency not reached the preset frequency) and the current feedback signal EOC=2'b11 (indicating the current frequency) If the frequency exceeds the preset frequency, it means that the coarse adjustment step is too large, causing the frequency to exceed the target value. It is necessary to switch to fine adjustment for fine calibration.

[0068] Condition 2: Historical feedback signal EOC_PRE=2'b11 (indicating the previous timeframe) (Frequency exceeds preset frequency) and the current feedback signal EOC=2'b00 (indicating the current frequency) (If the frequency has not reached the preset frequency), it also indicates that the coarse adjustment has exceeded the target value, and you need to switch to fine adjustment.

[0069] Condition 3: The coarse adjustment control signal SELC has reached the preset coarse adjustment lower boundary value (e.g., SELC=5'b00001), and cannot continue to be coarsely adjusted downwards. It is necessary to switch to fine adjustment to prevent overflow.

[0070] Condition 4: The coarse adjustment control signal SELC has reached the preset coarse adjustment upper boundary value (e.g., SELC=5'b11111), and cannot continue to be coarsely adjusted upwards. It is necessary to switch to fine adjustment to prevent overflow.

[0071] The mode holding subunit is used to keep the delay control logic unchanged (i.e., maintain C2F=1'b0) when the current feedback signal and the historical feedback signal do not meet any of the above switching conditions.

[0072] In some embodiments, the control signal output unit further includes a fine-tuning output subunit and a coarse-tuning output subunit.

[0073] The fine-tuning output subunit is used to perform fine-tuning operations when the adjustment mode is fine-tuning mode (C2F=1'b1): when the current feedback signal EOC=2'b00 (indicator) When the frequency does not reach the preset frequency and the fine-tuning control signal SELF does not reach the preset fine-tuning lower boundary value (e.g., SELF>0), a fine-tuning control signal is output to the clock generation circuit in a step-wise direction to reduce the delay, i.e., SELF=SELF-1. This reduces the number of capacitors connected to the inverter output node, reduces the equivalent load capacitance of the node, thereby reducing the fine-tuning delay and improving performance. Frequency; when the current feedback signal EOC=2'b11 (indicator) When the frequency exceeds the preset frequency and the fine-tuning control signal SELF has not reached the preset fine-tuning upper boundary value (e.g., SELF < 31), the clock generation circuit outputs a fine-tuning control signal that steps in the direction of increasing the delay, i.e., SELF = SELF + 1. This increases the number of capacitors connected to the inverter output node, increases the equivalent load capacitance of the node, thereby increasing the fine-tuning delay and reducing the frequency. Frequency, realization Fine-tuning of speed.

[0074] The coarse adjustment output subunit is used to perform coarse adjustment operations when the adjustment mode is coarse adjustment mode (C2F=1'b0): when the current feedback signal EOC=2'b00 (indicator) When the frequency does not reach the preset frequency, a coarse adjustment control signal is output to the clock generation circuit, which steps in a preset adjustment sequence to reduce the delay. For example, the SELC steps upward according to the binary correspondence sequence "1→2→4→8→16", selecting the first switch of the node at the next earlier stage, thus reducing the number of inverter stages participating in the loop oscillation, thereby reducing the coarse adjustment delay and quickly improving the clock speed. Frequency; when the current feedback signal EOC=2'b11 (indicator) When the frequency exceeds the preset frequency, a coarse adjustment control signal is output to the clock generation circuit, which steps in the direction of increasing the delay according to a preset adjustment sequence. For example, the SELC steps downward according to the sequence "16→8→4→2→1", selecting the first switch of the next later inter-stage node, increasing the number of inverter stages participating in the loop oscillation, thereby increasing the coarse adjustment delay and rapidly reducing the delay. Frequency, realization Wide range of speed calibration.

[0075] Figure 5 The schematic diagram illustrates the adjustment timing of the clock generation circuit according to an embodiment of this application in a frequency-to-fast state.

[0076] like Figure 5 As shown, when the delay control logic detects EOC[1:0]=11 (i.e. When the speed is too fast, control SELC[4:0] to adjust towards 5'b00001 (i.e., select a later inter-stage node to connect more inverters and increase the coarse adjustment delay), and SELF[4:0] to adjust towards 5'b11111 (i.e., connect more capacitors to increase the node load capacitance and increase the fine adjustment delay). After multiple After periodic calibration, As the speed gradually slows down, the feedback signal EOC[1:0] eventually converges to the preset condition of 2'b10, and the clock circuit enters a stable locked state.

[0077] Figure 6The schematic diagram illustrates a phase generation circuit according to an embodiment of this application. In some embodiments, the phase generation circuit includes a first multiplexer, a second multiplexer, an XOR gate, and a delay unit.

[0078] The connections between the components are as follows: The first multiplexer has a first data input terminal (i.e., "0" input terminal), a second data input terminal (i.e., "1" input terminal), a selection control terminal, and an output terminal. Its first data input terminal is connected to the output terminal of the clock generation circuit to receive the synchronous clock signal. The first multiplexer has a first data input terminal connected to ground level VSS, a selection control terminal connected to the first output terminal of the shift register to receive the flag signal FLAG, and an output terminal connected to the first data input terminal of the second multiplexer. The second multiplexer also has a first data input terminal (i.e., "0" input terminal), a second data input terminal (i.e., "1" input terminal), a selection control terminal, and an output terminal. Its first data input terminal is connected to the output terminal of the first multiplexer, its second data input terminal is connected to ground level VSS, and its selection control terminal is used to receive an externally input global sampling clock signal. Its output terminal serves as the first output terminal of the phase generation circuit, outputting the first phase clock signal. The two inputs of the XOR gate are connected to the ports of the first and second outputs of the shift register, respectively, to receive the flag signal FLAG and the feedback signal EOC[1]. Its output is used as the second output of the phase generation circuit to output the second phase clock signal. Its output terminal serves as the third output terminal of the phase generation circuit, outputting the third phase clock signal. .

[0079] Based on the above connection relationship, the first multiplexer is used to control the synchronous clock signal input to the clock generation circuit under the control of the flag signal FLAG. The output is selected based on the ground level VSS. Specifically, when FLAG=0, the first multiplexer output... This causes the downstream module to enter a synchronous conversion state; when FLAG=1, the first multiplexer outputs VSS (0 level), causing the downstream module to enter a reset waiting state.

[0080] The second multiplexer is used to sample the clock signal globally. Under the control of the system, the input signal of the first multiplexer and the ground level VSS are selected, and the first phase clock signal is output. .when During the valid sampling phase (high level), the second multiplexer outputs VSS to ensure... Maintain the reset level during the sampling window to avoid conflicts with the sampling timing; when When in the non-sampling phase (low level), the second multiplexer outputs the output signal of the first multiplexer, making... During FLAG=0 Flip to capture The first M (e.g., the first 5) periods are used as It is used to drive the successive approximation conversion process inside the first-stage analog-to-digital converter.

[0081] The XOR gate is used to output a second-phase clock signal based on one bit (preferably EOC[1]) of the flag signal FLAG and the feedback signal from the shift register input. By utilizing the timing difference between FLAG and EOC[1] (FLAG is triggered at the falling edge of the 5th cycle, and EOC[1] is triggered at the falling edge of the 7th cycle), the XOR gate can output a high-level pulse within a short timing window when FLAG=1 and EOC[1] has not yet been pulled high, thereby generating an XOR gate. Non-overlapping The signal is used to drive the sample-and-hold operation of the second-stage analog-to-digital converter.

[0082] The delay unit is used for the second phase clock signal based on the XOR gate input. Output the third phase clock signal In some embodiments, the delay unit may be composed of an even number of inverters (such as two inverters connected in series), for... Output after fixed delay processing ,make for Delayed version, guarantee Compared to The circuit is turned off in advance to meet the interstage timing requirement that the residual amplifier completes amplification first and then triggers the second stage sampling, thus avoiding phase conflict between the sampling window and the amplification window.

[0083] Among them, the first phase clock signal Second phase clock signal and the third phase clock signal Together they constitute the multi-phase clock signal, which is provided to different functional units of the downstream module.

[0084] Figure 7 The schematic diagram illustrates the overall timing of the synchronous clock circuit according to an embodiment of this application within a Pipelined-SAR ADC architecture. For example... Figure 7 As shown, The global sampling clock is an external input, and its duty cycle is preferably 1 / 8; The falling edge triggered clock generation circuit outputs a preset number of stable cycles. ; The first 5 cycles were taken as ,and The sampling window has a fixed phase interval; The falling edge of the 5th cycle triggers FLAG=1, and the falling edge of the 7th cycle triggers EOC[1]=1. The two are generated by XOR operation. ; After being delayed by the delay unit, the result is obtained Each phase clock signal is strictly aligned in timing. Furthermore, the clocks satisfy the non-overlapping characteristic.

[0085] Figure 8 A schematic diagram of a Pipelined-SAR ADC architecture for a synchronous clock circuit according to an embodiment of this application is shown.

[0086] like Figure 8 As shown, the synchronous clock circuit of this application can be further combined with an analog-to-digital converter (ADC) architecture to form a complete Pipelined-SAR ADC system. Specifically, the ADC architecture includes a first-stage ADC, a residual amplifier, a second-stage ADC, and a digital calibration engine.

[0087] The connection between the analog-to-digital converter architecture and the synchronous clock circuit is as follows: the sampling clock input of the first-stage analog-to-digital converter is connected to the external global sampling clock signal. The input port is connected, and its clock input terminal is connected to the first output terminal of the phase generation circuit to receive the first phase clock signal. Its signal input terminal is used to receive the analog input signal to be converted, and its digital output terminal is used to output the result of the first-stage conversion. Its residual output terminal is connected to the signal input terminal of the residual amplifier. The clock control terminal of the residual amplifier is connected to the third output terminal of the phase generation circuit to receive the third phase clock signal. Its signal output terminal is connected to the signal input terminal of the second-stage analog-to-digital converter. The sampling clock input terminal of the second-stage analog-to-digital converter is connected to the second output terminal of the phase generation circuit to receive the second phase clock signal. Its digital output is used to output the result of the second-stage conversion. The two inputs of the digital calibration engine are connected to the digital outputs of the first-stage analog-to-digital converter and the second-stage analog-to-digital converter, respectively. Its output is used to output the final N-bit conversion result after digital calibration.

[0088] The first-stage analog-to-digital converter is used for global sampling of the external input clock signal. Sampling is performed based on the first phase clock signal input to the phase generation circuit. Perform analog-to-digital conversion and output the first-level conversion result. The first-stage analog-to-digital converter is preferably a successive approximation ADC, which in Within the effective sampling window, the input signal is sampled and held, and then... The SAR logic is driven to complete successive approximation quantization within multiple cycles.

[0089] The residual amplifier is used for the third-phase clock signal based on the input of the phase generation circuit. The residual signal is amplified and output from the first-stage analog-to-digital converter (ADC) input, corresponding to the first-stage conversion result. The high-level window controls the residual amplifier to enter the amplification phase. The low-level window controls the residual amplifier to enter the reset phase, thereby ensuring that the amplifier completes an effective reset before each inter-stage data transfer, avoiding crosstalk of the residual charge from the previous cycle.

[0090] The second-stage analog-to-digital converter is used to input the second-phase clock signal based on the phase generation circuit. The residual signal input to the residual amplifier is sampled and converted from analog to digital, and the result of the second-stage conversion is output. . and The non-overlapping characteristic ensures that the second-level sampling window is completely staggered from the first-level sampling window in terms of timing, avoiding inter-level sampling conflicts; at the same time, Compared to The early shutdown design ensures that the residual signal is already stable at the moment of shutdown in the second-stage sampling phase. The second-stage analog-to-digital converter can be internally configured with... This triggers the generation of an asynchronous conversion clock, completing the second stage of successive approximation quantization.

[0091] The digital calibration engine is used to perform digital calibration based on the first-stage conversion result from the first-stage analog-to-digital converter input and the second-stage conversion result from the second-stage analog-to-digital converter input, and outputs the final high-precision N-bit conversion result.

[0092] Through the synergy between the synchronous clock circuit of this application and the aforementioned analog-to-digital converter architecture, only an external global sampling clock is needed to complete the timing drive of each stage of the entire Pipelined-SAR ADC module, without the need for additional external clock input and external calibration circuit. At the same time, the closed-loop adaptive calibration mechanism can compensate for timing drift caused by PVT changes in real time, enabling the ADC to maintain stable high-precision conversion performance under complex operating conditions such as process deviations, power supply voltage fluctuations, and temperature changes.

[0093] As can be seen from the above description, the embodiments of this application achieve at least the following technical effects:

[0094] (1) By introducing coarse adjustment delay module and fine adjustment delay module in clock generation circuit at the same time, and adopting coarse adjustment mechanism based on inverter stage selection and fine adjustment mechanism based on inverter output node load capacitor number switching respectively, the fine adjustment step size can be taken into account in a large delay adjustment range, so that the frequency of synchronous clock signal can quickly approach the preset frequency and achieve high-resolution stable locking, effectively overcoming the problem that traditional single delay adjustment method is difficult to balance between adjustment range and adjustment accuracy.

[0095] (2) By setting up a shift register consisting of N-stage series D flip-flops, and extracting the flag signal and feedback signal from the M-th, K-th and L-th stages respectively, the frequency deviation of the synchronous clock signal can be implicitly encoded by the level state of different period nodes during the shift process without introducing an additional counting circuit. This provides a low-overhead, high-real-time frequency deviation judgment basis for the delay control logic.

[0096] (3) By setting an adjustment mode selection unit, a control signal output unit and a feedback update unit in the delay control logic, and comprehensively judging the switching timing between coarse adjustment mode and fine adjustment mode based on the current feedback signal, historical feedback signal and the current adjustment mode, the synchronous clock circuit can quickly perform coarse adjustment convergence when the frequency deviation is large, and automatically switch to fine adjustment precise locking when approaching the target frequency. Furthermore, by limiting the upper and lower boundary values ​​of coarse adjustment and fine adjustment, the control signal overflow is avoided, thereby improving the convergence speed and stability of synchronous clock signal frequency adjustment.

[0097] (4) By setting up a phase generation circuit consisting of a first multiplexer, a second multiplexer, an XOR gate and a delay unit, and generating a first phase clock signal, a second phase clock signal and a third phase clock signal based on a synchronous clock signal and a flag signal, multiple clock signals with definite phase relationships can be output under the same phase generation architecture, providing multi-phase clock drive with strict timing alignment for downstream multi-stage pipeline modules.

[0098] (5) By combining the synchronous clock circuit with the first-stage analog-to-digital converter, the residual amplifier, the second-stage analog-to-digital converter and the digital calibration engine to form an analog-to-digital converter architecture, and using multi-phase clock signals to control the sampling, analog-to-digital conversion, residual amplification and inter-stage data transfer of each stage of the analog-to-digital converter, the analog-to-digital conversion operations of each stage can be strictly aligned to the global sampling clock signal. Combined with the digital calibration engine to calibrate the inter-stage conversion error, the conversion accuracy and anti-timing mismatch capability of the analog-to-digital converter architecture can be further improved.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0100] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of multiple such elements.

[0101] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0102] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A synchronous clock circuit, characterized in that, comprising: a clock generation circuit, configured to generate a synchronous clock signal based on an externally input global sampling clock signal; a shift register, configured to generate a flag signal and a feedback signal under the control of the synchronous clock signal input by the clock generation circuit; a delay control logic, configured to adjust the frequency of the synchronous clock signal input by the clock generation circuit to the shift register based on the feedback signal input by the shift register, until the feedback signal generated by the shift register meets a preset condition; a phase generation circuit, configured to generate multiple paths of phase clock signals based on the flag signal input by the shift register and the adjusted synchronous clock signal input by the clock generation circuit.

2. The circuit according to claim 1, characterized in that, The clock generation circuit comprises: an AND gate, configured to output a gating signal based on the externally input global sampling clock signal and the synchronous clock signal input via a feedback branch; multi-stage cascaded inverters, configured to generate the synchronous clock signal based on the gating signal input by the AND gate; a coarse adjustment delay module, configured to adjust the coarse adjustment delay amount of the signal path formed by the multi-stage cascaded inverters based on a coarse adjustment control signal input by the delay control logic; a fine adjustment delay module, configured to adjust the fine adjustment delay amount of the signal path formed by the multi-stage cascaded inverters based on a fine adjustment control signal input by the delay control logic.

3. The circuit according to claim 2, characterized in that, The coarse adjustment delay module comprises: a plurality of first switches, which are respectively disposed between different inter-stage nodes of the multi-stage cascaded inverters and the output end of the coarse adjustment delay module, and configured to control the on and off of each of the first switches based on the bits of the coarse adjustment control signal input by the delay control logic, select the number of inverter stages participating in loop oscillation from the multi-stage cascaded inverters, so as to adjust the coarse adjustment delay amount of the synchronous clock signal.

4. The circuit according to claim 2, characterized in that, The fine adjustment delay module comprises: a plurality of second switches, which are respectively connected in series between a plurality of capacitors and the output node of one inverter in the multi-stage cascaded inverters, and configured to control the on and off of each of the second switches based on each bit of the fine adjustment control signal input by the delay control logic, so as to adjust the number of capacitors connected to the output node of the one inverter in the multi-stage cascaded inverters, thereby adjusting the fine adjustment delay amount of the synchronous clock signal.

5. The circuit according to claim 1, characterized in that, The shift register comprises: N stages of D flip-flops connected in series, configured to have the first-stage D flip-flop connected to a power supply level, and input data from the front-stage D flip-flop to the rear-stage D flip-flop stage by stage under the control of the synchronous clock signal input by the clock generation circuit; the M-th stage D flip-flop among the N stages of series-connected D flip-flops, configured to output the flag signal via a first output end; the K-th stage D flip-flop and the L-th stage D flip-flop among the N stages of series-connected D flip-flops, configured such that the K-th stage D flip-flop outputs a high bit of the feedback signal, and the L-th stage D flip-flop outputs a low bit of the feedback signal, where the high bit of the feedback signal and the low bit of the feedback signal form the feedback signal; wherein N is an integer greater than a preset number, M<K<L, and M, K, and L are respectively used to indicate different cycle nodes of the synchronous clock signal.

6. The circuit according to claim 1, characterized in that, The feedback signal input from the shift register to the delay control logic includes a current feedback signal and a historical feedback signal; the delay control logic includes: The adjustment mode selection unit is used to respond to the rising edge of the global sampling clock signal, and when the current feedback signal does not meet the preset conditions, the delay control logic selects an adjustment mode for adjusting the frequency of the synchronization clock signal according to the feedback signal and the current adjustment mode. A control signal output unit is configured to output a control signal to the clock generation circuit to adjust the delay amount of the synchronous clock signal based on the adjustment mode and the frequency deviation direction indicated by the current feedback signal. The feedback update unit is used to update the current feedback signal to the historical feedback signal after the adjustment is completed, and apply it to the selection of the next adjustment mode until the feedback signal meets the preset condition.

7. The circuit according to claim 6, characterized in that, The adjustment modes include a coarse adjustment mode and a corresponding coarse adjustment control signal, and a fine adjustment mode and a corresponding fine adjustment control signal. The adjustment mode selection unit includes: A mode switching subunit is configured to, when the feedback signal or the current adjustment mode meets any of the following switching conditions, switch the adjustment mode from the current adjustment mode to a fine-tuning mode, wherein the current adjustment mode is a coarse-tuning mode: The historical feedback signal indicates that the frequency of the synchronization clock signal has not reached the preset frequency, and the current feedback signal indicates that the frequency of the synchronization clock signal exceeds the preset frequency; The historical feedback signal indicates that the frequency of the synchronization clock signal exceeds the preset frequency, and the current feedback signal indicates that the frequency of the synchronization clock signal has not reached the preset frequency; The coarse adjustment control signal corresponding to the coarse adjustment mode has reached the preset coarse adjustment lower boundary value; The coarse adjustment control signal corresponding to the coarse adjustment mode has reached the preset coarse adjustment upper boundary value; The mode holding subunit is used to keep the delay control logic in a coarse adjustment mode when the current feedback signal and the historical feedback signal do not meet any of the above switching conditions.

8. The circuit according to claim 7, characterized in that, The control signal output unit includes: The fine-tuning output subunit is used to output a fine-tuning control signal that steps in the direction of reducing the delay when the current feedback signal indicates that the frequency of the synchronous clock signal has not reached the preset frequency and the fine-tuning control signal has not reached the preset fine-tuning lower boundary value, when the adjustment mode is fine-tuning mode. When the current feedback signal indicates that the frequency of the synchronization clock signal exceeds the preset frequency, and the fine-tuning control signal has not reached the preset fine-tuning upper boundary value, the clock generation circuit outputs a fine-tuning control signal that steps in the direction of increasing the delay amount. The coarse adjustment output subunit is used to output a coarse adjustment control signal to the clock generation circuit in a step-by-step manner according to a preset adjustment sequence in the direction of reducing the delay when the current feedback signal indicates that the frequency of the synchronous clock signal has not reached the preset frequency, in the case where the adjustment mode is coarse adjustment mode. When the current feedback signal indicates that the frequency of the synchronization clock signal exceeds the preset frequency, a coarse adjustment control signal is output to the clock generation circuit, which steps in the direction of increasing the delay according to the preset adjustment sequence.

9. The circuit according to claim 1, characterized in that, The phase generation circuit includes: A first multiplexer is used to select and output the synchronous clock signal input to the clock generation circuit and the ground level under the flag signal input to the shift register. The second multiplexer is used to select the signal input to the first multiplexer and the ground level under the global sampling clock signal, and output the first phase clock signal; An XOR gate is used to output a second-phase clock signal based on one bit of the flag signal and the feedback signal input from the shift register; The delay unit is used to output a third phase clock signal based on the second phase clock signal input by the XOR gate; The first phase clock signal, the second phase clock signal, and the third phase clock signal constitute the multi-channel phase clock signal.

10. The circuit according to any one of claims 1 to 9, characterized in that, The circuit also includes an analog-to-digital converter architecture; the analog-to-digital converter architecture includes: The first-stage analog-to-digital converter is used to sample the global sampling clock signal input from the external input and perform analog-to-digital conversion based on the first phase clock signal input from the phase generation circuit, and output the first-stage conversion result. A residual amplifier is used to amplify the first-stage conversion result input from the first-stage analog-to-digital converter based on the third-phase clock signal input from the phase generation circuit, and output a residual signal. The second-stage analog-to-digital converter is used to sample and perform analog-to-digital conversion on the residual signal input to the residual amplifier based on the second-phase clock signal input to the phase generation circuit, and output the second-stage conversion result. A digital calibration engine is used to perform digital calibration based on the first-level conversion result input from the first-level analog-to-digital converter and the second-level conversion result input from the second-level analog-to-digital converter.

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