A column-level dual-sampling readout circuit based on infrared focal plane

Abstract

The application discloses a kind of based on infrared focal plane column-level double sampling readout circuit, belong to optoelectronic technology and microelectronic technology field.The readout circuit includes row selection logic circuit, pixel unit array and column-level readout circuit.The row selection logic circuit controls pixel array to be row gating, and the integrated voltage or reset voltage of each pixel unit is output to corresponding column-level transmission line.Each column-level readout circuit includes correlated double sampling circuit, amplifier circuit, multiplexer, buffer and analog-digital converter, the integrated voltage and reset voltage of the same pixel unit are sampled twice and difference value is obtained by the correlated double sampling circuit;The difference value signal is amplified by the amplifier circuit.The application effectively reduces pixel area to improve resolution by moving processing circuit out of pixel unit and combining column-level double sampling technology, while significantly suppressing inter-column fixed pattern noise, improve output signal uniformity and imaging quality.

Description

Technical Field

[0001] This invention relates to a column-level dual sampling readout circuit based on an infrared focal plane, belonging to the fields of optoelectronics and microelectronics. Background Technology

[0002] Infrared focal plane arrays (IRFPAs), as core components of infrared imaging systems, are widely used in military reconnaissance, satellite remote sensing, industrial temperature measurement, security monitoring, and wildlife monitoring. As a passive detection system, infrared imaging technology achieves all-weather operation by detecting the thermal radiation of target objects, offering advantages that visible light imaging cannot match in night vision and smoke penetration. With the continuous development of infrared imaging technology, the requirements for spatial resolution, temperature sensitivity, and image quality are increasing, driving the evolution of infrared focal plane arrays towards large-scale, high-resolution, and high-imaging-quality systems.

[0003] Currently, infrared focal plane array readout integrated circuits (ROICs) mainly employ direct injection (DI), buffered direct injection (BDI), and capacitive feedback transimpedance amplifiers (CTIA) as pixel-level input stages. However, with the increase in array size (from 320×256 to 1024×1024 and above) and the decrease in pixel size (from 30μm to 15μm or even smaller), traditional readout circuits face severe challenges.

[0004] The physical characteristics of infrared detectors dictate the unique design requirements of their readout circuits. Compared to visible light detectors, infrared detectors (such as those made of HgCdTe, InSb, and quantum well materials) typically exhibit extremely weak photocurrents, with typical photocurrent densities ranging from pA to nA, far lower than those of visible light detectors. Furthermore, due to the narrow bandgap characteristics of infrared materials, the dark current noise generated by thermal excitation is significantly amplified. Even with cryogenic cooling (typically operating at 77K or even lower) to suppress dark current, the residual dark current and its fluctuations still constitute the primary source of background noise, severely limiting the system's signal-to-noise ratio performance.

[0005] Secondly, there is a fundamental contradiction between the integrating capacitor and the pixel area. To accumulate sufficient signal charge under weak photocurrent conditions, the readout circuit needs to be equipped with a large-value integrating capacitor (typically in the tens of fF to pF range) at the pixel level. However, as the spatial resolution requirements of infrared imaging systems continue to increase, the pixel pitch continues to decrease. Within a limited pixel area, accommodating both the infrared detector itself and integrating a large-value integrating capacitor becomes a bottleneck restricting the resolution improvement of infrared focal plane arrays. The excessively large area proportion of the integrating capacitor makes it difficult to further reduce the pixel area and pixel pitch, hindering the effective improvement of spatial resolution.

[0006] The increase in array size also brings spatial noise and signal transmission problems. As the array size increases, the transmission distance between pixel units and readout circuits gradually increases, making the signal highly susceptible to noise interference. Simultaneously, the spatial noise of infrared focal plane arrays (including fixed-pattern noise and inter-column inconsistencies) becomes increasingly pronounced, making ensuring the uniformity of the array output signal crucial for improving image quality. In particular, component mismatches between columns in the column-level processing circuitry (including capacitor mismatch, switch charge injection mismatch, and operational amplifier offset voltage mismatch) result in non-uniformity in the output between columns, manifesting as fixed vertical stripe patterns during imaging and severely degrading image quality. Summary of the Invention

[0007] This invention provides an infrared focal plane readout circuit with small pixel center-to-center spacing, low noise crosstalk, and high precision. It employs a column-level readout architecture, moving the amplifier, buffer, and analog-to-digital converter (ADC) processing circuits out of the pixel unit to reduce the size and area of ​​the pixel circuitry and improve resolution. Simultaneously, a related double-sampling circuit is introduced at the amplifier front end to effectively eliminate spatial noise, improve the uniformity of the array output signal, and enhance image quality.

[0008] This invention is achieved through the following technical solution:

[0009] A column-level dual-sampling readout circuit based on an infrared focal plane, wherein the infrared focal plane comprises a pixel array arranged in rows and columns, and the readout circuit includes:

[0010] A row selection logic circuit is connected to each row of the pixel unit array to generate a row selection control signal to control the pixel unit array to select rows sequentially and synchronously output the integral voltage or reset voltage generated by each pixel unit in the selected row to the corresponding column-level transmission line.

[0011] Multiple column-level readout circuits are provided, with each column of pixel units connected to one of the column-level readout circuits. Each column-level readout circuit receives a voltage signal from the selected pixel unit in the corresponding column through the column-level transmission line.

[0012] Each of the column-level readout circuits further includes:

[0013] The related dual sampling circuit, whose input is connected to the column-level transmission line, is used to sample and hold the first voltage output by the same pixel unit in the integration phase and the second voltage output in the reset phase, and use the difference between the first voltage and the second voltage as the output to eliminate fixed pattern noise on the pixel unit and the column-level transmission path.

[0014] An amplifier circuit, whose input terminal is connected to the output terminal of the correlated double sampling circuit, is used to amplify the difference and output an amplified analog voltage signal.

[0015] A multiplexer, whose input is connected to the output of a plurality of adjacent columns of the amplifier circuit, is used to select one output from multiple amplified analog voltage signals in time sequence;

[0016] A buffer, whose input is connected to the output of the multiplexer, is used to perform impedance transformation and drive enhancement on the selected analog voltage signal;

[0017] An analog-to-digital converter, whose input terminal is connected to the output terminal of the buffer, is used to convert analog voltage signals into digital signals and output them to the outside of the readout circuit;

[0018] The related dual sampling circuit eliminates fixed-mode noise introduced by pixel reset noise, column operational amplifier offset voltage, and low-frequency noise by performing differential operations on the first voltage and the second voltage, thereby ensuring consistency of the output signals of each column.

[0019] Further, the pixel unit includes:

[0020] An integrating capacitor, with its lower plate grounded and its upper plate serving as an integrating node, is used to convert the input photocurrent into an integrated voltage and store it.

[0021] An integral control switch has its first end connected to the input photocurrent and its second end connected to the upper plate of the integral capacitor, used to control the integral charging of the integral capacitor by the photocurrent.

[0022] A reset control switch, with its first terminal connected to a reset voltage and its second terminal connected to the upper plate of the integrating capacitor, is used to reset the integrating node to the reset voltage during the reset phase.

[0023] A source follower, whose input terminal is connected to the upper plate of the integrating capacitor and whose output terminal is connected to the column transmission line, is used to drive the voltage signal at the integrating node to the column transmission line after impedance transformation.

[0024] A row selection switch is connected in series between the output of the source follower and the column-level transmission line. Its control terminal is connected to the row selection control signal of the row selection logic circuit, and is used to control the on / off connection between the pixel unit and the column-level transmission line.

[0025] Furthermore, the correlated dual sampling circuit and the amplification circuit are integrated into a single structure, which includes:

[0026] An operational amplifier has a common-mode voltage connected to its non-inverting input terminal, a signal input terminal at its inverting input terminal, and an output terminal at its output terminal, which is the output terminal of the amplifier circuit.

[0027] The first capacitor has its left plate connected to the column transmission line and its right plate connected to the inverting input of the operational amplifier.

[0028] The second capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier;

[0029] The third capacitor has its left plate connected to the output of the operational amplifier via a first switch and to the level shift control voltage via a second switch, and its right plate connected to the inverting input of the operational amplifier.

[0030] The first sampling switch is connected between the output terminal of the operational amplifier and the inverting input terminal, and is used to control the operational amplifier to form a unity-gain negative feedback structure during the reset sampling phase;

[0031] The left plate of the first capacitor is connected to the column transmission line via a third switch and to the common-mode voltage via a fourth switch.

[0032] Furthermore, the integration sampling phase of the related dual sampling circuit and amplification circuit operates as follows:

[0033] The pixel unit is in the output integral voltage state, the integral control switch is open, the reset control switch is open, the row selection switch is closed, and the voltage of the upper plate of the integral capacitor is the integral voltage;

[0034] The first and second switches are closed, the first sampling switch is open, the left plate of the first capacitor is connected to the column transmission line via the third switch, and the operational amplifier, due to its unity-gain negative feedback structure, has an output voltage of V. B_CDS Both the second capacitor and the third capacitor are reset to V. B_CDS .

[0035] Furthermore, the reset sampling phase operation state of the related dual sampling circuit and amplification circuit is as follows:

[0036] When the pixel unit is in the output reset voltage state, the integral control switch is open, the reset control switch is closed, the row selection switch is closed, and the upper plate of the integral capacitor is reset to the reset voltage.

[0037] The first switch and the second switch are open, the first sampling switch is closed, and the voltage on the left plate of the first capacitor is V. IN2 =V RST +Vnoise, the left plate of the third capacitor is switched to the level shift control voltage, and the output of the operational amplifier outputs the amplified and level-shifted voltage V. CDS_OUT .

[0038] Furthermore, the output voltage V of the related dual sampling circuit CDS_OUT The expression is:

[0039] ;

[0040] Among them, the first item V B_CDS The output common-mode reference is used, the second term is the level shift component, and the third term is the effective signal amplification component. The output of the related dual sampling circuit is aligned with the input range of the subsequent analog-to-digital converter by adjusting the level shift control voltage.

[0041] Furthermore, the multiplexer is an 8-to-1 multiplexer, with its input terminals connected to the output terminals of the respective 8 adjacent columns of the amplifier circuit, and its selection control terminal connected to an external timing control signal, used to sequentially transmit the amplified analog voltage signals of the 8 columns to the buffer in a time-division manner.

[0042] Furthermore, the output of the buffer is connected to the input of the analog-to-digital converter (ADC). The ADC is a successive approximation ADC, which includes a sampling switch, a CDAC capacitor array, a comparator, and digital SAR logic, used to convert the analog voltage output by the buffer into a 14-bit digital signal.

[0043] Furthermore, the operation process of the successive approximation analog-to-digital converter is as follows:

[0044] The comparator compares the input voltage with the reference voltage and outputs the comparison result to the SAR logic;

[0045] The SAR logic controls the base plate switch of the CDAC capacitor corresponding to the most significant bit and the base plate switch of the CDAC capacitor corresponding to each of the other low bits in sequence according to the comparison result, so that the input voltage approaches the reference voltage one by one. After 14 comparisons and switching, the 14-bit digital signal is converted and output.

[0046] Furthermore, the column-level readout circuit adopts a column-level shared architecture, where eight adjacent columns share one multiplexer, one buffer, and one analog-to-digital converter to optimize the layout area and improve the flexibility of the column-level circuit layout.

[0047] This invention uses capacitors to integrate photocurrent signals within pixel units, outputting the results to column-level circuitry for digital processing via source follower and column-level transmission lines. This reduces the complexity and size of the pixel circuitry, improving pixel resolution within the same area. Double sampling technology is employed in the column-level circuitry. By processing the difference between the two sampling values ​​before and after pixel integration, fixed-mode noise caused by reset noise, operational amplifier offset voltage, and low-frequency noise is eliminated, significantly improving the output consistency of the column-level readout circuitry. Simultaneously, level shifting technology is used to adjust the output voltage, matching it to the input range of the subsequent analog-to-digital converter (ADC), improving the overall dynamic range and accuracy of the system. The column-level buffer and ADC of this invention adopt a many-to-one mode. Eight column-level signals share a single buffer and ADC for analog-to-digital conversion via a multiplexer, increasing the layout space for the ADC and other column-level circuits and enhancing layout flexibility. Attached Figure Description

[0048] Figure 1 This is a system structure diagram of the present invention.

[0049] Figure 2 This is a block diagram of the column-level processing circuit structure of the present invention. Detailed Implementation

[0050] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] A column-level dual-sampling readout circuit based on an infrared focal plane array comprises three parts: a row selection logic circuit, a pixel unit array, and a column-level readout circuit. The row selection logic circuit is connected to the pixel unit array and controls the pixel array to output signals sequentially to the column-level circuit row by row. Each column of the pixel unit array is connected to a column-level readout circuit. The pixel unit converts photocurrent into a voltage value and stores the record through an integrating capacitor. When a row is selected, the integrated voltage is transmitted to the column-level circuit. The column-level circuit performs dual sampling, amplification, and analog-to-digital conversion on the voltage signal transmitted from the pixel unit, ultimately converting the analog voltage signal into a digital signal for transmission outside the readout circuit.

[0052] The pixel unit includes an integrating capacitor, an integrating control switch, a reset control switch, and a source follower, used to convert the photocurrent signal into a voltage signal. One end of the integrating control switch S1 is connected to the integrating capacitor C. INT One end is connected to the upper electrode plate, and the other end is connected to the input photocurrent terminal. One end of the reset control switch is connected to the integrating capacitor C.INT The upper plate is connected to the other end, and the other end is connected to the reset voltage V. RST Connected. One end of the source follower is connected to the integrating capacitor C. INT The upper electrode is connected to the upper plate, and the other end is connected to the pixel array column transmission line V. IN <n>Connected.

[0053] The column-level readout circuit includes a dual-sampling circuit, an amplifier circuit, an 8-to-1 multiplexer, a buffer, and an analog-to-digital converter (ADC), used to sample, amplify, and convert the voltage signal output by the pixels. One dual-sampling circuit and one amplifier circuit are shared per column, and one multiplexer, buffer, and ADC are shared for every eight columns. The signal output V of each column... IN <n>Connected to a dual-sampling circuit and an amplifier circuit for each column, the output V of the amplifier circuit CDS_OUT The output of the multiplexer is connected to the input of the buffer, and the output of the buffer is connected to the input of the buffer. BUFFER It is connected to the input of the analog-to-digital converter.

[0054] Example

[0055] A column-level processing circuit structure, wherein when the pixel array is selected to the nth row, the phase Ф of S3 is... SAMP <n>When the switch is closed, the nth row of pixels begins to read out the integrated voltage, which is then transmitted to the column-level CDS circuit. The CDS circuit includes a correlated double sampling circuit and an amplifier. This module performs two sampling operations: integration sampling and reset sampling, and performs subtraction to eliminate fixed noise. During integration sampling, switches S1 and S2 are open, and S3 is closed, placing the pixel unit in the output integration voltage stage; switches S5 and S6 are closed, and S4 is open, placing the CDS circuit in the reset stage. The integrating capacitor C inside the pixel... INT The voltage at the top plate is the integral voltage V. INT This voltage is transmitted to the column circuit via the column transmission line. At this time, the voltage across the left plate of capacitor C1 becomes V. IN1 =V INT +V noise Due to the virtual short characteristic of the operational amplifier, the voltage at the negative input node of the amplifier is related to V. B_CDS The same applies, and due to the connection state of the unity-gain negative feedback structure, the output voltage of the operational amplifier is also V. B_CDS The left and right plates of capacitors C2 and C3 were both reset to V. B_CDS In this state, the total charge stored in C1, C2, and C3 is:

[0056]

[0057] During the second phase reset sampling, switches S1 is open, S2 is closed, and S3 is closed, and the pixel unit is in the output reset voltage state; switches S5 and S6 are open, and S4 is closed, and the CDS circuit is in the sampling amplification state. The integrating capacitor C inside the pixel... INT The top plate is now reset to V. RST The voltage is transmitted to the column circuit via the column transmission line. At this time, the voltage across the left plate of capacitor C1 becomes V. IN2 =V RST +Vnoise. The voltage across the left plate of capacitor C3 is determined by V. B_CDS Transformed into shift control voltage V OS The output is the voltage V after amplification and level shifting. OUT_CDS The total charge stored in C1, C2, and C3 is:

[0058]

[0059] Furthermore, due to:

[0060]

[0061] Therefore, we can conclude that:

[0062]

[0063] Through the above V IN1 With V IN2 The subtraction operation can remove fixed noise from the array, where V in the formula... B_CDS +C3 / C2(V B_CDS -V OS (C1 / C2)×A represents the voltage offset component. V (V IN1 -V IN2 This is the voltage amplification component. In actual circuit operation, it can be adjusted by V... OS The amplified voltage offset is controlled to align the output of the column-level voltage processing circuit with the input range of the ADC.

[0064] A column-level ADC is used to realize the digital readout of grayscale information. The successive approximation ADC used in this structure mainly consists of a sampling switch, a CDAC capacitor array, a comparator, and digital SAR logic. In the conversion stage, the comparator first compares the input voltage V... IN With reference voltage V RE F compares the values ​​and transmits the comparison result D13 to the SAR logic. Based on this result, the SAR logic controls the baseboard switch to switch the baseboard voltage of the CDAC capacitor corresponding to the most significant bit (MSB), thus making V... IN Gradually approaching V REF After completing the first comparison and baseboard switching, the above process is repeated 13 times to obtain the comparison results from D12 to D0 in sequence. The baseboard switch is then used to sequentially switch the baseboard voltage of the CDAC capacitors corresponding to the remaining 13 lower least significant bits (LSBs), thus achieving V... IN For V REF The analog voltage input to the front-end is gradually approximated. After 14 comparisons and board switching, the analog voltage input to the front-end is converted into a 14-bit digital signal.

[0065] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.< / n> < / n> < / n>

Claims

1. A column-level dual-sampling readout circuit based on an infrared focal plane, wherein the infrared focal plane comprises an array of pixel units arranged in rows and columns, characterized in that, The readout circuit includes: A row selection logic circuit is connected to each row of the pixel unit array to generate a row selection control signal to control the pixel unit array to select rows sequentially and synchronously output the integral voltage or reset voltage generated by each pixel unit in the selected row to the corresponding column-level transmission line. Multiple column-level readout circuits are provided, with each column of pixel units connected to one of the column-level readout circuits. Each column-level readout circuit receives a voltage signal from the selected pixel unit in the corresponding column through the column-level transmission line. Each of the column-level readout circuits further includes: The related dual sampling circuit, whose input is connected to the column-level transmission line, is used to sample and hold the first voltage output by the same pixel unit in the integration phase and the second voltage output in the reset phase, and use the difference between the first voltage and the second voltage as the output to eliminate fixed pattern noise on the pixel unit and the column-level transmission path. An amplifier circuit, whose input terminal is connected to the output terminal of the correlated double sampling circuit, is used to amplify the difference and output an amplified analog voltage signal. A multiplexer, whose input is connected to the output of a plurality of adjacent columns of the amplifier circuit, is used to select one output from multiple amplified analog voltage signals in time sequence; A buffer, whose input is connected to the output of the multiplexer, is used to perform impedance transformation and drive enhancement on the selected analog voltage signal; An analog-to-digital converter, whose input terminal is connected to the output terminal of the buffer, is used to convert analog voltage signals into digital signals and output them to the outside of the readout circuit; The related dual sampling circuit eliminates fixed-mode noise introduced by pixel reset noise, column operational amplifier offset voltage, and low-frequency noise by performing differential operations on the first voltage and the second voltage, thereby ensuring consistency of the output signals of each column.

2. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 1, characterized in that, The pixel unit includes: An integrating capacitor, with its lower plate grounded and its upper plate serving as an integrating node, is used to convert the input photocurrent into an integrated voltage and store it. An integral control switch has its first end connected to the input photocurrent and its second end connected to the upper plate of the integral capacitor, used to control the integral charging of the integral capacitor by the photocurrent. A reset control switch, with its first terminal connected to a reset voltage and its second terminal connected to the upper plate of the integrating capacitor, is used to reset the integrating node to the reset voltage during the reset phase. A source follower, whose input terminal is connected to the upper plate of the integrating capacitor and whose output terminal is connected to the column transmission line, is used to drive the voltage signal at the integrating node to the column transmission line after impedance transformation. A row selection switch is connected in series between the output of the source follower and the column-level transmission line. Its control terminal is connected to the row selection control signal of the row selection logic circuit, and is used to control the on / off connection between the pixel unit and the column-level transmission line.

3. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 1, characterized in that, The related dual sampling circuit and the amplification circuit are integrated into a single structure, which includes: An operational amplifier has a common-mode voltage connected to its non-inverting input terminal, a signal input terminal at its inverting input terminal, and an output terminal at its output terminal, which is the output terminal of the amplifier circuit. The first capacitor has its left plate connected to the column transmission line and its right plate connected to the inverting input of the operational amplifier. The second capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier; The third capacitor has its left plate connected to the output of the operational amplifier via a first switch and to the level shift control voltage via a second switch, and its right plate connected to the inverting input of the operational amplifier. The first sampling switch is connected between the output terminal of the operational amplifier and the inverting input terminal, and is used to control the operational amplifier to form a unity-gain negative feedback structure during the reset sampling phase; The left plate of the first capacitor is connected to the column transmission line via a third switch and to the common-mode voltage via a fourth switch.

4. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 3, characterized in that, The operating state of the integral sampling stage of the relevant dual sampling circuit and amplification circuit is as follows: The pixel unit is in the output integral voltage state, the integral control switch is open, the reset control switch is open, the row selection switch is closed, and the voltage of the upper plate of the integral capacitor is the integral voltage; The first and second switches are closed, the first sampling switch is open, the left plate of the first capacitor is connected to the column transmission line via the third switch, and the operational amplifier, due to its unity-gain negative feedback structure, has an output voltage of V. B_CDS Both the second capacitor and the third capacitor are reset to V. B_CDS .

5. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 4, characterized in that, The reset sampling phase operation state of the relevant dual sampling circuit and amplification circuit is as follows: When the pixel unit is in the output reset voltage state, the integral control switch is open, the reset control switch is closed, the row selection switch is closed, and the upper plate of the integral capacitor is reset to the reset voltage. The first switch and the second switch are open, the first sampling switch is closed, and the voltage on the left plate of the first capacitor is V. IN2 =V RST +Vnoise, the left plate of the third capacitor is switched to the level shift control voltage, and the output of the operational amplifier outputs the amplified and level-shifted voltage V. CDS_OUT .

6. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 5, characterized in that, The output voltage V of the relevant dual sampling circuit CDS_OUT The expression is: ； Among them, the first item V B_CDS The output common-mode reference is used, the second term is the level shift component, and the third term is the effective signal amplification component. The output of the related dual sampling circuit is aligned with the input range of the subsequent analog-to-digital converter by adjusting the level shift control voltage.

7. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 1, characterized in that, The multiplexer is an 8-to-1 multiplexer, with its input terminals connected to the output terminals of the respective amplifier circuits of the eight adjacent columns. Its selection control terminal is connected to an external timing control signal, which is used to sequentially transmit the amplified analog voltage signals of the eight columns to the buffer in a time-division manner.

8. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 7, characterized in that, The output of the buffer is connected to the input of the analog-to-digital converter (ADC). The ADC is a successive approximation ADC, which includes a sampling switch, a CDAC capacitor array, a comparator, and digital SAR logic, and is used to convert the analog voltage output by the buffer into a 14-bit digital signal.

9. The column-level dual-sampling readout circuit based on an infrared focal plane according to claim 8, characterized in that, The working process of the successive approximation analog-to-digital converter is as follows: The comparator compares the input voltage with the reference voltage and outputs the comparison result to the SAR logic; The SAR logic controls the base plate switch of the CDAC capacitor corresponding to the most significant bit and the base plate switch of the CDAC capacitor corresponding to each of the other low bits in sequence according to the comparison result, so that the input voltage approaches the reference voltage one by one. After 14 comparisons and switching, the 14-bit digital signal is converted and output.

10. The column-level dual-sampling readout circuit based on an infrared focal plane according to any one of claims 1 to 9, characterized in that, The column-level readout circuit adopts a column-level shared architecture, in which eight adjacent columns share one multiplexer, one buffer, and one analog-to-digital converter to optimize the layout area and improve the flexibility of the column-level circuit layout.

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