Alternating integral signal conditioning circuit and method

Abstract

The application provides a kind of wheel replacement integral signal conditioning circuit and wheel replacement integral signal conditioning method, the wheel replacement integral signal conditioning circuit includes: clock unit, sampling unit and at least two integral networks;Clock unit is used to generate sampling control signal and integral control signal;Integral control signal is used to control at least two integral networks to be alternately transformed between integral state and bleeder state;Wherein, the control of integral control signal to integral network satisfies: there is an integral network in integral state at any time, and all other integral networks are in bleeder state;When integral network is in integral state, it is used to receive and integrate photoelectric signal from photoelectric conversion unit;When integral network is in bleeder state, it is used to bleed the accumulated energy;Sampling control signal is used to control sampling unit to sample integral network that ends integral state, to obtain the sampling output signal corresponding to each integral network in turn.

Description

Technical Field

[0001] This invention relates to the field of photoelectric signal detection and signal processing technology, and in particular to an alternating integral signal conditioning circuit and an alternating integral signal conditioning method. Background Technology

[0002] In semiconductor optical measurement equipment, the photoelectric signal detected by laser reflection is usually extremely weak and accompanied by random noise introduced by background light, circuit thermal noise, and laser fluctuations. To extract this weak photoelectric signal from a strong noise background, integrating circuits are widely used. The physical essence is that the photoelectric signal is coherently accumulated in the time domain, with its amplitude increasing linearly with the integration time T; while zero-mean random noise is incoherently accumulated, and its root mean square value only increases with T. Therefore, the integration process can effectively improve the signal-to-noise ratio (SNR) of the photoelectric signal and is one of the standard methods for extracting weak photoelectric signals.

[0003] However, traditional integrating signal conditioning circuits for photoelectric signals have significant shortcomings. The most common solution uses a single integrator in conjunction with an electronic reset switch. The photocurrent output from the photodetector is converted into a voltage signal by a transimpedance amplifier (TIA) and then fed into the integrator for accumulation. When the integration time is long or the incident light power is high, the voltage on the integrating capacitor of the integrator continuously rises (or falls), easily reaching the limit of the operational amplifier's output voltage swing and entering a saturation state. Once the operational amplifier is saturated, the integrator can no longer respond to changes in the input signal, resulting in waveform distortion and severely limited dynamic range. To solve the saturation problem, existing technologies typically employ a periodic reset method. After the integrated voltage reaches a preset threshold or after a fixed time, the switch connected in parallel with the integrating capacitor is closed, instantly discharging the capacitor's charge and returning the integrator to its initial state.

[0004] However, existing periodic reset schemes suffer from a reset dead zone. During the reset period, the integrator stops responding, causing signal discontinuity and information loss. Switching noise also directly contaminates the signal. The charge injection spikes introduced by each reset are directly superimposed on the output waveform, worsening the signal-to-noise ratio of weak signals. Furthermore, a fixed reset period makes it difficult to balance saturation prevention and high signal-to-noise ratio, and it is prone to saturation and has a limited dynamic range. Resetting too early or too late both lead to performance degradation. Shortening the reset time requires high-speed discharge, but the effective integration time is inversely proportional to the reset time. Summary of the Invention

[0005] The purpose of this invention is to provide an alternating integral signal conditioning circuit and an alternating integral signal conditioning method to solve the problems of integral saturation, reset dead zone and signal-to-noise ratio degradation in existing photoelectric signal integral signal conditioning circuits.

[0006] To address the aforementioned technical problems, this invention provides an alternating integral signal conditioning circuit, comprising: a clock unit, a sampling unit, and at least two integral networks; the clock unit generates a sampling control signal and an integral control signal; the integral control signal controls at least two of the integral networks to alternate between an integral state and a discharge state; wherein the integral control signal controls the integral networks in a manner that: at any given time, one integral network is in the integral state, and all other integral networks are in the discharge state; when the integral network is in the integral state, it receives and integrates photoelectric signals from a photoelectric conversion unit; when the integral network is in the discharge state, it discharges accumulated energy; the sampling control signal controls the sampling unit to sample the integral networks that have ended the integral state, thereby sequentially obtaining the sampled output signals corresponding to each integral network.

[0007] Optionally, the clock unit is used to generate at least two integration control signals to control at least two integration networks respectively; when the integration control signal is at a first level, it controls the corresponding integration network to be in the integration state; the first levels of the at least two integration control signals have a non-overlapping continuous phase alternation relationship.

[0008] Optionally, the integral network includes a controlled discharge switch, the control terminal of which is connected to the corresponding integral control signal; when the integral control signal is at the second level, the controlled discharge switch is turned on to put the corresponding integral network into the discharge state; when the integral control signal is at the first level, the controlled discharge switch is turned off to put the corresponding integral network into the integral state.

[0009] Optionally, the alternating integral signal conditioning circuit includes at least two sampling units, each of which is connected to the output of at least two integral networks; the clock unit is used to generate at least two sampling control signals to trigger the at least two sampling units to perform sampling in turn.

[0010] Optionally, the alternating integral signal conditioning circuit further includes a multiplexer, with the outputs of at least two of the integral networks respectively connected to different inputs of the multiplexer, the control terminal of the multiplexer connected to the sampling control signal, and the output of the multiplexer connected to the sampling unit; the multiplexer is used to select the integral network that has ended the integral state under the control of the sampling control signal.

[0011] Optionally, the alternating integrating signal conditioning circuit further includes a multiplexer; the integrating network includes integrating devices.

[0012] The multiplexer includes at least two logic selection channels; each logic selection channel includes two input terminals and one output terminal, one of the two input terminals is connected to the output terminal; one input terminal and the output terminal of each logic selection channel are connected to the two ends of the integrating device of the integrating network through a bleed resistor, and the other input terminal is grounded with high impedance;

[0013] The control terminal of the multiplexer is connected to the integral control signal to control the logic state of each logic selection channel. At any given time, only one logic selection channel is in the state where the input terminal is grounded and connected to the output terminal, while all other logic selection channels are in the opposite state.

[0014] Optionally, the integrator network includes an active integrator, a fully differential integrator, or a switched capacitor integrator.

[0015] Optionally, the alternating integral signal conditioning circuit may further include a control unit;

[0016] The control unit is configured to set a saturation warning threshold below the range of the sampling unit; and acquire the sampling output signal of the sampling unit within the most recent multiple sampling periods;

[0017] If the continuous average value of the sampled output signal over multiple sampling periods reaches the saturation warning threshold, or if the recent slope of the sampled output signal over multiple sampling periods increases, then it is determined that there is a risk of saturation, and the clock unit is controlled to increase the frequency of the sampling control signal and the integral control signal, or decrease the duty cycle of the integral control signal.

[0018] Optionally, the control unit is further configured to set a weak warning threshold below the saturation warning threshold, and if the continuous average value of the sampled output signal over multiple sampling periods is lower than the weak warning threshold, control the clock unit to reduce the frequency of the sampling control signal and the integral control signal, or increase the duty cycle of the integral control signal.

[0019] To address the aforementioned technical problems, the present invention also provides an alternating integral signal conditioning method, which applies the alternating integral signal conditioning circuit described above to perform integral conditioning on photoelectric signals. The alternating integral signal conditioning method includes:

[0020] Generate sampling control signals and integral control signals;

[0021] The integral control signal controls at least two integral networks to alternate between an integral state and a discharge state, ensuring that at any given time, one integral network is in the integral state and all other integral networks are in the discharge state. The integral network in the integral state is used to receive and integrate photoelectric signals from the photoelectric conversion unit; the integral network in the discharge state is used to discharge accumulated energy.

[0022] The sampling control signal controls the sampling unit to sample the integral network that has ended the integration state, so as to obtain the sampling output signal corresponding to each integral network in sequence.

[0023] In summary, in the alternating integral signal conditioning circuit and method provided by this invention, the alternating integral signal conditioning circuit includes: a clock unit, a sampling unit, and at least two integral networks; the clock unit is used to generate a sampling control signal and an integral control signal; the integral control signal is used to control at least two of the integral networks to alternate between an integral state and a discharge state; wherein, the integral control signal controls the integral networks in a manner that: at any given time, one integral network is in the integral state, and all other integral networks are in the discharge state; when the integral network is in the integral state, it is used to receive and integrate photoelectric signals from the photoelectric conversion unit; when the integral network is in the discharge state, it is used to discharge accumulated energy; the sampling control signal is used to control the sampling unit to sample the integral networks that have ended the integral state, so as to sequentially obtain the sampled output signals corresponding to each integral network.

[0024] This configuration, through the alternating integration and dissipation of at least two integrator networks, ensures that the accumulated energy of each network is released after integration, reducing or avoiding the risk of saturation limit and guaranteeing linearity and reliability under strong signals or long-term measurements. The dynamic range of the integral output is no longer limited by the op-amp output swing, significantly expanding the effective measurement dynamic range. Furthermore, the alternating operation of at least two integrator networks ensures that one network is always integrating, overcoming the signal loss during the reset period of traditional single integrators. This achieves uninterrupted accumulation of the input signal, preventing the loss of any instantaneous information for rapidly fluctuating optical signals. The alternating integration process is equivalent to low-pass filtering, possessing a natural ability to suppress high-frequency ripple and random noise, effectively canceling background DC components and common-mode noise, and improving the signal-to-noise ratio. Attached Figure Description

[0025] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0026] Figure 1 This is a schematic diagram of the principle framework of the alternating integral signal conditioning circuit according to an embodiment of the present invention.

[0027] Figure 2 This is a functional topology diagram of the alternating integral signal conditioning circuit according to an embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the integral network according to an embodiment of the present invention.

[0029] Figure 4 This is a schematic diagram of a multiplexer according to an embodiment of the present invention.

[0030] In the attached diagram: 1-Clock unit; 2-Sampling unit; 3-Integrating network; 31-Active integrator; 32-Controlled discharge switch; 4-Photoelectric conversion unit; 5-Multiplexer. Detailed Implementation

[0031] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0032] As used in this invention, the singular forms “a,” “an,” “one,” and “the” include plural objects; the term “or” is generally used to include the meaning of “and / or”; the term “a number” is generally used to include the meaning of “at least one”; and the term “at least two” is generally used to include the meaning of “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature; “one end” and “the other end,” and “proximal end” and “distal end” generally refer to two corresponding parts, which include not only endpoints. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, directional terms such as above, below, up, down, upward, downward, left, and right are used relative to exemplary embodiments as they are shown in the figures, with upward or upper direction pointing towards the top of the corresponding figure, and downward or lower direction pointing towards the bottom of the corresponding figure.

[0033] The purpose of this invention is to provide an alternating integral signal conditioning circuit and a alternating integral signal conditioning method to solve the problems of integral saturation, reset dead time, and signal-to-noise ratio degradation in existing photoelectric signal integral signal conditioning circuits. The following description refers to the accompanying drawings.

[0034] Please refer to Figure 1 and Figure 2 This invention provides an alternating integral signal conditioning circuit, comprising: a clock unit 1, a sampling unit 2, and at least two integral networks 3; the clock unit 1 is used to generate a sampling control signal and an integral control signal; the integral control signal is used to control at least two of the integral networks 3 to alternate between an integral state and a discharge state; wherein, the integral control signal controls the integral networks 3 to satisfy the following conditions: at any given time, one integral network 3 is in the integral state, and all other integral networks 3 are in the discharge state; when the integral network 3 is in the integral state, it is used to receive and integrate photoelectric signals from a photoelectric conversion unit 4; when the integral network 3 is in the discharge state, it is used to discharge accumulated energy; the sampling control signal is used to control the sampling unit 2 to sample the integral networks 3 that have ended the integral state (i.e., at the moment of completion of integration, before discharge), so as to sequentially obtain the sampling output signals corresponding to each integral network 3.

[0035] The photoelectric conversion unit 4 is the front-end of the alternating integral signal conditioning circuit in this embodiment. In one embodiment, it includes a photoelectric conversion device (such as a photodiode PD) and a transimpedance amplifier (TIA). The photoelectric conversion device is used to convert the incident photon flux Ee into a photocurrent proportional to the light intensity, which is then conditioned by the transimpedance amplifier (TIA) into a single-ended voltage signal U. TIA The single-ended voltage signal U TIA In this embodiment, it is referred to as a photoelectric signal, which is the object to be integrated and conditioned by the alternating integrating signal conditioning circuit. The specific structure and principle of the photoelectric conversion unit 4 can be found in the prior art, and will not be described in detail in this embodiment.

[0036] The sampling unit 2 includes, for example, a passive low-pass filter (LPF) and an analog-to-digital converter (ADC). It is controlled by the sampling control signal issued by the clock unit 1. It samples the integration network 3 at the moment when each integration network 3 ends its integration state, thereby obtaining the sampling output signal of each integration network 3 in sequence, and finally obtaining a digital result that is proportional to the integral value of the incident photon flux Ee.

[0037] In some embodiments, the clock unit 1 is implemented by a microcontroller (MCU). The sampling control signal and the integral control signal it generates can be PWM waves of a certain frequency, with a typical frequency range of 1kHz to 100kHz, and the duty cycle can be adjusted between 10% and 90%.

[0038] At least two integrator networks 3 have the same or symmetrical structure, and their input terminals are all connected to the output terminal of the photoelectric conversion unit 4. At least two integrator networks 3 are controlled by the integration control signal issued by the clock unit 1, and alternate between the integration state and the discharge state. At any given time, there is always one integrator network 3 in the integration state, while all other integrator networks 3 are in the discharge state.

[0039] Taking a rotating integral signal conditioning circuit containing two integral networks 3 as an example, the rotating transformation means that when the first integral network 3 is in the integration state, the second integral network 3 is in the discharge state. After a certain period of time, the states of the two integral networks 3 alternate, that is, the first integral network 3 changes from the integration state to the discharge state, and the second integral network 3 changes from the discharge state to the integration state, and so on.

[0040] When there are three or more integrator networks 3, they take turns participating in the cycle. When the first integrator network 3 is in the integrator state, the other integrator networks 3 are in the discharge state. After a certain period of time, the second integrator network 3 switches to the integrator state, the first integrator network 3 switches to the discharge state, and the other integrator networks 3 remain in the discharge state. Then, after another certain period of time, the third integrator network 3 switches to the integrator state, the second integrator network 3 switches to the discharge state, and the other integrator networks 3 continue to remain in the discharge state, and so on, in a continuous cycle.

[0041] During the alternating integration process, only one integrating network 3 in the integration state receives and integrates the photoelectric signal from the photoelectric conversion unit 4. The other integrating networks 3 do not participate in the integration of the photoelectric signal and discharge and reset the energy (charge) accumulated in the previous cycle. In this way, the continuously changing voltage signal is converted into an integral waveform without saturation.

[0042] This configuration, through the alternating integration and dissipation of at least two integrator networks 3, ensures that the accumulated energy of each integrator network 3 is dissipated after integration, reducing or avoiding the risk of saturation limit and guaranteeing linearity and reliability under strong signals or long-term measurements. The dynamic range of the integral output is no longer limited by the operational amplifier output swing, significantly expanding the effective measurement dynamic range. Furthermore, the alternating operation of at least two integrator networks 3 ensures that one network 3 is integrating at any given time, overcoming the signal loss during the reset period of traditional single integrators. This achieves uninterrupted accumulation of the input signal, preventing the loss of any instantaneous information for rapidly fluctuating optical signals. The alternating integration process is equivalent to low-pass filtering, possessing a natural ability to suppress high-frequency ripple and random noise, effectively canceling background DC components and common-mode noise, and improving the signal-to-noise ratio.

[0043] Optionally, the clock unit 1 is used to generate at least two integration control signals to control at least two integration networks 3 respectively; when the integration control signal is at a first level, it controls the corresponding integration network 3 to be in the integration state; the first levels of the at least two integration control signals have a non-overlapping continuous phase alternation relationship.

[0044] In some embodiments, the clock unit 1 can generate at least two independent integration control signals to control at least two integration networks 3 respectively. Figure 2 As shown in the example, it contains two integration networks 3, so the clock unit 1 can generate two integration control signals S1 and S2, which are used to control the two integration networks 3 respectively.

[0045] In one example, the first level is, for example, a low level "0". When the integration control signal corresponding to a certain integration network 3 is at a low level "0", the integration network 3 is in the integration state. When the integration control signal corresponding to the integration network 3 is at a second level (such as a high level "1"), the integration network 3 is in the discharge state. In order to achieve unique gating integration of the integration network 3, the first levels of at least two integration control signals must have a non-overlapping continuous phase alternation relationship. Non-overlapping means that only one integration control signal is at the first level at any given time. Continuous phase alternation relationship means that the first levels of each integration control signal alternate sequentially, and within one alternation cycle, there is always one integration control signal at the first level.

[0046] Furthermore, the alternating integral signal conditioning circuit also includes a multiplexer 5, with at least two outputs of the integral network 3 respectively connected to different inputs of the multiplexer 5, and the control terminal of the multiplexer 5 receiving the sampling control signal. Figure 2(marked as S3), the output of the multiplexer 5 is connected to the sampling unit 2; the multiplexer 5 is used to select the integration network 3 that has ended the integration state under the control of the sampling control signal. Here, the multiplexer 5 is controlled by the sampling control signal and acts as a gate. Under the trigger of the sampling control signal, the multiplexer 5 selects the integration network 3 that has ended the integration state, so that the selected integration network 3 is connected to the sampling unit 2 and triggers the sampling unit 2 to sample.

[0047] Gating is not always necessary. In some embodiments, the alternating integral signal conditioning circuit includes at least two sampling units 2, each connected to the output of at least two integral networks 3. The clock unit 1 generates at least two sampling control signals to trigger the at least two sampling units 2 to perform sampling in turn. When the multiplexer 5, which acts as a gate, is removed, the output of each integral network 3 can be connected to an independent sampling unit 2. The clock unit 1 generates at least two independent sampling control signals to control the operation of each sampling unit 2. Furthermore, the output of each sampling unit 2 is connected to an MCU, and the correct integration result is read through the data selection logic within the MCU. This approach is particularly suitable for scenarios requiring higher channel isolation.

[0048] Please continue to refer to this. Figure 2 The integral network 3 further includes a controlled discharge switch 32, the control terminal of which is connected to the corresponding integral control signal. When the integral control signal is at the second level (e.g., high level "1"), the controlled discharge switch 32 is turned on to put the corresponding integral network into the discharge state. When the integral control signal is at the first level (e.g., low level "0"), the controlled discharge switch 32 is turned off to put the corresponding integral network into the integral state.

[0049] Please refer to Figure 3 In one embodiment, the integrating network 3 includes an active integrator 31, which includes an operational amplifier U1, an integrating resistor R1, and an integrating capacitor C1, etc. An optional bias voltage V... T The current is injected into the non-inverting input of operational amplifier U1 through another resistor R2. Resistor R2 is used to balance the DC resistance at the inverting input, reducing the offset of the op-amp's input bias current. T It is a low-impedance reference source output, therefore the resistance values ​​of R1 and R2 are equal. The input voltage signal U... TIA The integrator 31 injects virtual ground through integrating resistor R1; according to the operational amplifier virtual ground principle and Kirchhoff's current law, the output voltage U of this active integrator 31 is... Oi (t) and input voltage U TIA (t) and bias voltage VT The relationship is:

[0050]

[0051] In the formula, U O1 (t0) represents the output voltage at the start of the integration cycle, ideally the initial voltage immediately after reset (close to 0V or the reference level). Set the bias voltage V. T The purpose is to set the DC bias component in the integration process. A discharge branch is connected in parallel across the integrating capacitor C1, which consists of a controlled discharge switch 32 (SPST) and a discharge resistor R3 connected in series. Let the on-resistance of the controlled discharge switch 32 be R. on Total bleed resistance R g =R3+R on When the controlled discharge switch 32 closes under the control of the integral control signal, the charge stored in the integral capacitor C1 flows through R... g Release, the voltage U across the integrating capacitor C1 O1 The transient discharge equation can be approximated as:

[0052]

[0053] Where V0 is the voltage of the integrating capacitor C1 at the initial moment of discharge (when the controlled discharge switch 32 just closes), V ∞ The steady-state final voltage of the discharge (typically 0V under virtual ground clamping of U1) has a time constant τ = R. g ×C1. To ensure that the charge of the integrating capacitor C1 is fully discharged at the end of the discharge state, and to avoid the memory effect of residual charge causing a shift in the integration starting point of subsequent cycles, the discharge time t... b It needs to be much shorter than the duration of the discharge state. Typically, the goal is to ensure that the discharge reaches within 1% of the initial value, i.e., t... b ≥4.6τ. By appropriately selecting the resistance value of R3 (and choosing a low R value). on The analog switch can control the discharge time to the microsecond level, which is sufficient to meet the reset requirements at a maximum switching frequency of 100kHz.

[0054] In terms of device selection, in some embodiments the controlled discharge switch 32 can be a single-pole single-throw analog switch (SPST). Alternatively, the controlled discharge switch 32 can also be an N-channel MOSFET with low on-resistance and low charge injection, a transmission gate composed of two MOSFETs connected back to back, or a solid-state opto-relay.

[0055] Please refer to the reference. Figure 2 and Figure 3 Assuming it contains N integrator networks 3, the voltage signal U from the front-end photoelectric conversion unit 4... TIASimultaneously applied to the signal input terminals of N integrator networks 3. At this time, the entire rotation cycle can be divided into N integration segments, which are preferably of equal length.

[0056] Taking the first integration section as an example: the integration control signal of the first integration network 3 is at the first level (such as low level "0"). This first level is applied to its controlled discharge switch 32. When the controlled discharge switch 32 is turned off, the operational amplifier U1 and the integrating capacitor C1 form a Miller integrator, which processes the voltage signal U... TIA Perform linear integration, output voltage U O1 As the integral slope rises or falls, a charge proportional to the input signal accumulates on the integrating capacitor C1. Simultaneously, the integration control signals of the remaining integrators in network 3 are all at the second level (e.g., high level "1"), their controlled discharge switch 32 closes, and the integrating capacitor rapidly discharges through the discharge branch formed by the controlled discharge switch 32 and the discharge resistor. The output voltage is forcibly reset to the operational amplifier's reference level (typically virtual ground or bias voltage V). T In the first integration segment, multiplexer 5 selects the Nth integrating network 3, outputting the voltage of the integrating capacitor of the Nth integrating network 3 at the moment of completion of the integration in the previous cycle (this voltage is still held on its integrating capacitor and has not been destroyed by the discharge reset operation in this cycle) to the subsequent sampling unit 2. At the moment the first integration segment begins (i.e., the hold state before reset), sampling unit 2 performs a sample-hold-conversion operation on the output of multiplexer 5, thus completely capturing the integration result of the Nth integrating network 3 in the previous cycle. Subsequent integration segments alternate sequentially; refer to the description of the first integration segment for details, which will not be repeated here.

[0057] Please refer to Figure 2 To further suppress high-frequency glitches and charge injection interference that may be introduced during the switching of the controlled discharge switch 32, the output of the multiplexer 5 is preferably passed through a resistor R. c and capacitor C f The first-order passive low-pass filter (LPF) is typically set to a -3dB cutoff frequency of 5 to 10 times the clock frequency. This effectively filters out switching spikes without causing excessive delay in the integral waveform settling time.

[0058] As an alternative embodiment, the active integrator 31 can be replaced with a fully differential integrator to further suppress common-mode noise, or with a switched-capacitor integrator to achieve more precise clock control gain; this embodiment is not limited to this. Those skilled in the art can configure and replace it according to the prior art.

[0059] In another alternative embodiment, a multiplexer 5 with two or more independent single-pole double-throw (SPDT) functions or equivalent functions can be used to implement an alternative scheme for alternating discharge control. This reduces the number of integral control signals required and lowers control complexity. The multiplexer 5 includes at least two logic selection channels; each logic selection channel includes two input terminals and one output terminal, with one of the two input terminals connected to the output terminal; one input terminal and the output terminal of each logic selection channel are connected to the integrator (e.g., an integrating capacitor) of an integrating network 3 via a discharge resistor, while the other input terminal is grounded at high impedance; the control terminal of the multiplexer 5 receives the integral control signal to control the logic state of each logic selection channel, wherein at any given time, only one logic selection channel is in the state where the input terminal is grounded at high impedance and connected to the output terminal, while all other logic selection channels are in the opposite state.

[0060] Please refer to the reference. Figure 4 Taking a multiplexer 5 containing two logic selection channels and corresponding to two integrator networks 3 as an example, this will be explained. Each logic selection channel is a 2:1 logic channel with 2 inputs and 1 output, where one of the two inputs is connected to the output. The first logic selection channel has inputs A1 and B1, and output Q1. The second logic selection channel has inputs A2 and B2, and output Q2. The control terminals IN1 and IN2 of the two logic selection channels may be connected together internally or driven externally; in this embodiment, they share the same integration control signal S0.

[0061] In the first logic selection channel, input A1 is connected to one end U of the integrating capacitor C1 in the first integrating network 3. i1 The output terminal Q1 is connected to the bleed resistor R. C1 Connected to the other end of the integrating capacitor C1, U O1 Input terminal B1 is connected to a high-impedance resistor R. M1 Ground (GND). In the second logic selection channel, input B2 and output Q2 are connected through a bleed resistor R. C2 The integrating capacitor C2 is connected across the second integrating network 3, and the input terminal A2 is connected through a high-impedance resistor R. M2 Grounding.

[0062] When control terminals IN1 and IN2 are low, the first logic selection channel A1 is activated and the second logic selection channel A2 is activated. At this time, the integrating capacitor C1 of the first integrating network 3 is connected to the first logic selection channel and the bleeder resistor R. C1A discharge loop is formed, and the first integrator network 3 is in the discharge state and reset; while the second logic selection channel selects A2, that is, through R... M2 When grounded, the discharge loop of the second integrator network 3 is blocked by a high signal, and the second integrator network 3 is in the integration state. Conversely, when the control terminals IN1 and IN2 are high, the entire control logic is reversed, which will not be repeated here. Since the discharge states of the two integrator networks 3 are always logically complementary and are implemented by the same integration control signal through hardware interlocking, this scheme naturally guarantees a non-overlapping continuous phase alternation relationship. It eliminates the need to set two independent integration control signals for clock unit 1 and eliminates the need for precise dead-time programming of the timing, thus simplifying the complexity of timing design. At the same time, this scheme also reduces the number of I / O pins occupied by the MCU.

[0063] Optionally, the alternating integral signal conditioning circuit further includes a control unit; the control unit is configured to set a saturation warning threshold below the range of the sampling unit 2; acquire the sampling output signal of the sampling unit 2 within the most recent multiple sampling periods; if the continuous average value of the sampling output signal within multiple sampling periods reaches the saturation warning threshold, or the recent slope of the sampling output signal within multiple sampling periods increases, then it is determined that there is a risk of saturation, and the clock unit 1 is controlled to increase the frequency of the sampling control signal and the integral control signal, or decrease the duty cycle of the integral control signal.

[0064] In some embodiments, the sampling control signal and the integration control signal generated by clock unit 1 can be at fixed frequencies. In other embodiments, the frequencies of the sampling control signal and the integration control signal generated by clock unit 1 are preferably adaptively adjustable and controlled by the control unit. Here, the control unit can be an MCU, and clock unit 1 can be external or integrated into the MCU.

[0065] In one example, the control unit can acquire the sampled output signal of sampling unit 2. It should be noted that the sampling period here should be understood as the period of N integration segments within one cycle. That is, each integration segment yields a sampled output signal, which the control unit analyzes.

[0066] The saturation warning threshold can be preset, preferably lower than the full-scale input voltage of the analog-to-digital converter (ADC) of sampling unit 2. The control unit continuously records the sampled output signal D[k] of the most recent M sampling cycles. When the continuous average value of D[k] is detected to reach the saturation warning threshold, it indicates that the voltage output by the integrator network 3 is close to the range of the analog-to-digital converter (ADC), and the control unit determines that there is a risk of saturation.

[0067] In another scenario, when a recent increase in the slope of D[k] is detected, such as an increase in the slope of the last M sampling cycles, it indicates that although the voltage output by the current integral network 3 has not yet approached the range of the analog-to-digital converter (ADC), it is on a continuous increasing trend and will soon reach the range of the ADC at the current rate of increase. The control unit can also determine that there is a risk of saturation based on this.

[0068] Upon determining a saturation risk, the control unit can adaptively implement anti-saturation control strategies to mitigate this risk. These strategies include increasing the frequencies of the sampling control signal and the integral control signal (e.g., from 10kHz to 50kHz); or reducing the duty cycle of the integral control signal (e.g., reducing the integral time percentage of a PWM wave from 50% to 20%). Executing these anti-saturation control strategies shortens the integration time window, reduces the net voltage increment of the integrating capacitor in each cycle, and suppresses the output peak within the safe input range of the analog-to-digital converter (ADC).

[0069] The control unit is further configured to set a weak warning threshold lower than the saturation warning threshold. If the continuous average value of the sampled output signal over multiple sampling periods is lower than the weak warning threshold, the control unit 1 is controlled to reduce the frequency of the sampling control signal and the integral control signal, or increase the duty cycle of the integral control signal. Alternatively, the control unit can also set a weak warning threshold, preferably much lower than the saturation warning threshold, for example, 1 / 10 to 1 / 20 of the saturation warning threshold. When the continuous average value of D[k] is detected to be lower than the weak warning threshold, it indicates that the voltage output by the integral network 3 is weak, and the control unit can adaptively execute a signal-to-noise ratio (SNR) improvement control strategy. The SNR improvement control strategy includes, for example, reducing the frequency of the sampling control signal and the integral control signal, or increasing the duty cycle of the integral control signal. This achieves a higher SNR by extending the integration time.

[0070] The closed-loop adaptive adjustment process of the control unit can be real-time and driven by the internal control strategy of the control unit. This enables the alternating integral signal conditioning circuit of this embodiment to have adaptive anti-saturation capability in response to changes in external optical power. It can intelligently cope with a wide dynamic range of optical signals, from extremely weak to extremely strong, without any manual adjustment or hardware modification. By analyzing the output trend of the samples, the control unit can actively adjust parameters such as the frequency and phase difference of the integral clock before saturation occurs, achieving predictive anti-saturation and further improving the robustness and automation of the system.

[0071] Furthermore, the frequency, duty cycle, and phase of the integration window can all be digitally controlled by the control unit, thus enabling dynamic online adjustment based on actual light intensity changes. This allows for the coverage of various detection needs, from weak low-frequency signals to rapidly changing high-frequency signals, without requiring hardware modifications.

[0072] Based on the alternating integral signal conditioning circuit provided in this embodiment, this embodiment of the invention also provides an alternating integral signal conditioning method, which includes:

[0073] Generate sampling control signals and integral control signals;

[0074] The integral control signal controls at least two integral networks 3 to alternate between an integral state and a discharge state, ensuring that at any given time, one integral network is in the integral state and all other integral networks 3 are in the discharge state. The integral network 3 in the integral state is used to receive and integrate the photoelectric signal from the photoelectric conversion unit 4. The integral network 3 in the discharge state is used to discharge the accumulated energy.

[0075] The sampling control signal controls the sampling unit 2 to sample the integral network 3 that has ended the integration state, so as to obtain the sampling output signal corresponding to each integral network 3 in sequence.

[0076] The alternating integral signal conditioning method may also include other functional steps that can be implemented by the alternating integral signal conditioning circuit described above, which will not be repeated here.

[0077] In summary, in the alternating integral signal conditioning circuit and method provided by this invention, the alternating integral signal conditioning circuit includes: a clock unit, a sampling unit, and at least two integral networks; the clock unit is used to generate a sampling control signal and an integral control signal; the integral control signal is used to control at least two of the integral networks to alternate between an integral state and a discharge state; wherein, the integral control signal controls the integral networks in a manner that: at any given time, one integral network is in the integral state, and all other integral networks are in the discharge state; when the integral network is in the integral state, it is used to receive and integrate photoelectric signals from the photoelectric conversion unit; when the integral network is in the discharge state, it is used to discharge accumulated energy; the sampling control signal is used to control the sampling unit to sample the integral networks that have ended the integral state, so as to sequentially obtain the sampled output signals corresponding to each integral network. This configuration, through the alternating integration and dissipation of at least two integrator networks, ensures that the accumulated energy of each network is released after integration, reducing or avoiding the risk of saturation limit and guaranteeing linearity and reliability under strong signals or long-term measurements. The dynamic range of the integral output is no longer limited by the op-amp output swing, significantly expanding the effective measurement dynamic range. Furthermore, the alternating operation of at least two integrator networks ensures that one network is always integrating, overcoming the signal loss during the reset period of traditional single integrators. This achieves uninterrupted accumulation of the input signal, preventing the loss of any instantaneous information for rapidly fluctuating optical signals. The alternating integration process is equivalent to low-pass filtering, possessing a natural ability to suppress high-frequency ripple and random noise, effectively canceling background DC components and common-mode noise, and improving the signal-to-noise ratio.

[0078] It should be noted that the above embodiments can be combined with each other. The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A rotating integral signal conditioning circuit, characterized in that, include: Clock unit, sampling unit, and at least two integration networks; The clock unit is used to generate sampling control signals and integration control signals; The integral control signal is used to control at least two of the integral networks to alternate between an integral state and a discharge state; wherein, the integral control signal controls the integral networks in such a way that at any given time, there is always one integral network in the integral state and all other integral networks in the discharge state. When the integrating network is in the integrating state, it is used to receive and integrate photoelectric signals from the photoelectric conversion unit; when the integrating network is in the discharging state, it is used to dissipate the accumulated energy. The sampling control signal is used to control the sampling unit to sample the integral network that has ended the integration state, so as to obtain the sampling output signal corresponding to each integral network in sequence.

2. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The clock unit is used to generate at least two integration control signals to control at least two integration networks respectively; when the integration control signal is at a first level, it controls the corresponding integration network to be in the integration state. The first levels of at least two of the integral control signals have a non-overlapping, continuous phase alternation relationship.

3. The alternating integral signal conditioning circuit according to claim 2, characterized in that, The integral network includes a controlled discharge switch, the control terminal of which is connected to the corresponding integral control signal. When the integral control signal is at the second level, it controls the controlled discharge switch to open, so that the corresponding integral network is in the discharge state. When the integral control signal is at the first level, it controls the controlled discharge switch to close, so that the corresponding integral network is in the integral state.

4. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The alternating integral signal conditioning circuit includes at least two sampling units, which are respectively connected to the output terminals of at least two integral networks; the clock unit is used to generate at least two sampling control signals to trigger at least two sampling units to perform sampling in turn.

5. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The alternating integral signal conditioning circuit further includes a multiplexer, with the outputs of at least two of the integral networks respectively connected to different inputs of the multiplexer. The control terminal of the multiplexer is connected to the sampling control signal, and the output of the multiplexer is connected to the sampling unit. The multiplexer is used to select the integral network that has ended the integral state under the control of the sampling control signal.

6. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The alternating integral signal conditioning circuit also includes a multiplexer; the integral network includes an integral device. The multiplexer includes at least two logic selection channels; each logic selection channel includes two input terminals and one output terminal, one of the two input terminals is connected to the output terminal; one input terminal and the output terminal of each logic selection channel are connected to the two ends of the integrating device of the integrating network through a bleed resistor, and the other input terminal is grounded with high impedance; The control terminal of the multiplexer is connected to the integral control signal to control the logic state of each logic selection channel. At any given time, only one logic selection channel is in the state where the input terminal is grounded and connected to the output terminal, while all other logic selection channels are in the opposite state.

7. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The integrator network includes an active integrator, a fully differential integrator, or a switched capacitor integrator.

8. The alternating integral signal conditioning circuit according to claim 1, characterized in that, The alternating integral signal conditioning circuit also includes a control unit; The control unit is configured to set a saturation warning threshold below the range of the sampling unit; and acquire the sampling output signal of the sampling unit within the most recent multiple sampling periods; If the continuous average value of the sampled output signal over multiple sampling periods reaches the saturation warning threshold, or if the recent slope of the sampled output signal over multiple sampling periods increases, then it is determined that there is a risk of saturation, and the clock unit is controlled to increase the frequency of the sampling control signal and the integral control signal, or decrease the duty cycle of the integral control signal.

9. The alternating integral signal conditioning circuit according to claim 8, characterized in that, The control unit is further configured to set a weak warning threshold below the saturation warning threshold, and if the continuous average value of the sampled output signal over multiple sampling periods is lower than the weak warning threshold, control the clock unit to reduce the frequency of the sampling control signal and the integral control signal, or increase the duty cycle of the integral control signal.

10. A method for conditioning alternating integral signals, characterized in that, The alternating integral signal conditioning circuit according to any one of claims 1 to 9 is used to integrally condition the photoelectric signal, wherein the alternating integral signal conditioning method includes: Generate sampling control signals and integral control signals; The integral control signal controls at least two integral networks to alternate between an integral state and a discharge state, ensuring that at any given time, one integral network is in the integral state and all other integral networks are in the discharge state. The integral network in the integral state is used to receive and integrate photoelectric signals from the photoelectric conversion unit; the integral network in the discharge state is used to discharge accumulated energy. The sampling control signal controls the sampling unit to sample the integral network that has ended the integration state, so as to obtain the sampling output signal corresponding to each integral network in sequence.

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