Channel state aware based adc dynamic time-sharing acquisition system, method and chip

Abstract

The application provides an ADC dynamic time-sharing acquisition system, method and chip based on channel state sensing, the system comprises: a plurality of acquisition front ends, which are connected with corresponding acquisition electrodes respectively; a multiplexing switching unit, which is configured to time-share coupling of analog output signals of a plurality of acquisition channels to an ADC module; a pre-charging unit, which is configured to pre-charge a signal level of a target channel in a channel switching gap; a state marking unit, which is configured to mark the state of each acquisition channel; and a control logic unit, which is configured to generate a dynamic control signal according to the current state marking of each acquisition channel, to drive the multiplexing switching unit to preferentially select and enable an acquisition channel in an effective state, and to skip or delay the selection and enablement of an acquisition channel in a recovery state. The application can effectively solve the technical problems of large ADC hardware overhead, long sampling establishment time during channel switching, and low effective data output rate under electrical stimulation artifacts in the prior art.

Description

Technical Field

[0001] This application belongs to the field of neural interface integrated circuit technology, and relates to a channel state-aware ADC dynamic time-division acquisition system, method and chip. Background Technology

[0002] In multi-channel EEG signal acquisition systems, traditional architectures typically pair each analog front-end signal chain with an independent analog-to-digital converter (ADC) to achieve parallel synchronous sampling. However, this fully parallel architecture is overly burdensome in terms of power consumption and chip area. Each acquisition channel requires a high-precision ADC, consuming significant area and power, severely limiting the system's integration and portability in multi-channel applications. For example, in a 128-channel neural signal recording system, if each channel is configured with an independent ADC, not only will the chip area increase dramatically, but the total power consumption will also be difficult to meet the stringent requirements of implantable or wearable devices.

[0003] In the prior art, in order to reduce the hardware overhead of multi-channel EEG signal acquisition systems, existing solutions use a small number of ADCs in conjunction with analog multiplexers for time-division acquisition. This reduces the number of ADCs by time-division coupling the analog output signals of multiple acquisition channels to the input of the ADC module. However, this time-division multiplexing architecture has several shortcomings in practical applications: Firstly, when the multiplexer switches channels, the sampling capacitor at the ADC input needs to switch from the voltage of the previous channel to the voltage of the next channel. If the setup time is insufficient, it will seriously affect the sampling accuracy and linearity, especially in high-speed time-division acquisition scenarios. Secondly, even if a fully parallel architecture is used to configure multiple independent ADCs, the gain error, offset error, and nonlinearity error between the ADCs due to process variations are difficult to completely eliminate through digital calibration. More importantly, in implantable or closed-loop EEG signal acquisition systems, the strong stimulation artifacts generated by the electrical stimulation pulses will cause the front-end amplifier to enter a saturation state, requiring a certain recovery time to return to the linear range. Traditional time-division acquisition schemes use a fixed-time polling method to sample each channel sequentially. If a channel is polled during the amplifier's saturation recovery period, invalid or even erroneous signal data will be acquired, which not only reduces the effective utilization of the ADC but may also lead to serious deviations in subsequent data processing.

[0004] Therefore, there is an urgent need in this field for an acquisition and control architecture that can effectively reduce the hardware overhead of the ADC while ensuring sampling accuracy, and can still maintain a high effective data output rate under electrical stimulation artifacts. Summary of the Invention

[0005] This application provides a channel state-aware ADC dynamic time-division acquisition system, method, and chip to solve the technical problems of high hardware overhead, long sampling setup time during channel switching, and low effective data output rate under electrical stimulation artifacts in the prior art.

[0006] In a first aspect, this application provides a channel state-aware ADC dynamic time-division acquisition system, comprising: multiple acquisition front-ends, each connected to a corresponding acquisition electrode, configured to amplify and filter EEG signals; a multiplexing unit, disposed between the output terminals of the multiple acquisition front-ends and the input terminal of the ADC module, configured to time-division couple the analog output signals of multiple acquisition channels to the input terminal of the ADC module; a pre-charging unit, disposed between the output terminal of the multiplexing unit and the input terminal of the ADC module, configured to pre-charge the signal level of the target channel during channel switching intervals; a status marking unit, connected to the status output terminal of each acquisition front-end, configured to receive feedback status signals from each acquisition channel and mark the status of each acquisition channel accordingly, the status including at least an active state and a recovery state; and a control logic unit, connected to the output terminal of the status marking unit and the control terminal of the multiplexing unit, configured to generate dynamic control signals based on the current status marking of each acquisition channel, driving the multiplexing unit to preferentially select acquisition channels in the active state and skip or delay selecting acquisition channels in the recovery state.

[0007] In one implementation of the first aspect, the multiplexing switching unit includes a multi-channel gating switch array, comprising a primary gating switch group and a secondary gating switch group; the primary gating switch group includes multiple primary gating switches, each primary gating switch having multiple input terminals connected to a corresponding acquisition front-end output terminal, and each primary gating switch having an output terminal connected to a corresponding common node, configured to select one signal from N acquisition channels to the common node; the secondary gating switch group includes at least one secondary gating switch, each secondary gating switch having multiple input terminals connected to each of the common nodes, and the secondary gating switch having an output terminal connected to the input terminal of the pre-charging unit, configured to output one of the multiple common node signals to the pre-charging unit.

[0008] In one implementation of the first aspect, the pre-charge unit includes a high-speed buffer and a sample-and-hold capacitor connected in series; the input terminal of the high-speed buffer is connected to the output terminal of the multiplexing unit, the output terminal of the high-speed buffer, the first terminal of the sample-and-hold capacitor, and the sampling input terminal of the ADC module are interconnected at the same node, and the second terminal of the sample-and-hold capacitor is grounded; the high-speed buffer is configured to pre-charge the signal voltage of the next channel to be sampled to the first terminal of the sample-and-hold capacitor via the output terminal of the high-speed buffer during the sampling conversion of the current channel, and the ADC module acquires the voltage signal on the node through its sampling input terminal.

[0009] In one implementation of the first aspect, the state flag unit includes a comparator array, an OR gate logic circuit, and a state register; the comparator array includes multiple comparators corresponding one-to-one with each acquisition channel; the signals of each acquisition channel are respectively input to the non-inverting input of the corresponding comparator, the inverting input of each comparator is connected to a reference threshold voltage, and the output of each comparator is connected to each input of the OR gate logic circuit; the output of the OR gate logic circuit is connected to the corresponding data bit of the state register and is configured to latch the amplifier saturation trigger signal or stimulus artifact trigger signal of any channel to the corresponding bit of the state register as a recovery state flag of the channel.

[0010] In one implementation of the first aspect, the acquisition front end includes: a low-noise amplifier, a low-pass filter, a first switch group, and a second switch group for each acquisition channel; the first switch group is disposed between the low-noise amplifier and the acquisition electrode, and the second switch group is disposed between the differential input terminal of the low-noise amplifier and the common-mode reference voltage or ground; the acquisition front end signal processing circuit has an acquisition state and a stimulation protection state: in the acquisition state, the first switch group is closed and the second switch group is open, so that the nerve signal is output to the analog-to-digital converter after passing through the acquisition electrode, the first switch group, the low-noise amplifier, and the low-pass filter; in the stimulation protection state, the first switch group is open and the second switch group is closed to block the electrical stimulation signal from being transmitted to the low-noise amplifier through the acquisition electrode, and the input terminal of the low-noise amplifier is short-circuited by the second switch group to block crosstalk between the acquisition front end channels.

[0011] In one implementation of the first aspect, the status marking unit marks each of the acquisition channels based on at least one of the following: whether the saturation detection signal of the amplifier of the acquisition channel is triggered; whether the acquisition channel is under the influence of electrical stimulation artifacts; and whether the output of the amplifier of the acquisition channel has recovered to the linear operating range.

[0012] In one implementation of the first aspect, the control logic unit includes a timing reference module, a channel status reading module, and a strobe address generation module; the timing reference module is configured to generate a sampling timing clock signal; the channel status reading module is configured to read the flag bits of each acquisition channel output by the status flag unit; the strobe address generation module is configured to generate a strobe address sequence for skipping the channel in the recovery state based on the flag bits, and the output terminal of the strobe address generation module is connected to the control terminal of the multiplexing unit.

[0013] In one implementation of the first aspect, the control logic unit is configured to: sequentially poll and schedule each of the acquisition channels in a default state; and when any acquisition channel is detected to be marked as being in the recovery state, suspend the sampling scheduling of the acquisition channel, and re-include it in the polling sequence after the acquisition channel recovers to the valid state.

[0014] Secondly, this application provides a channel state-aware ADC dynamic time-division acquisition method, the method comprising: a state marking step: acquiring feedback state signals of each acquisition channel, and marking each acquisition channel as an active state or a recovery state according to the feedback state signals; a dynamic scheduling step: generating a dynamic control signal according to the current state marking of each acquisition channel, the dynamic control signal being used to instruct priority scheduling of acquisition channels in the active state to participate in sampling, and skipping or delaying scheduling of acquisition channels in the recovery state; a time-division switching step: controlling a multiplexing switching network to perform channel selection switching according to the dynamic control signal, and time-division coupling the analog signal of the acquisition channel in the active state to the input terminal of the ADC module; and a pre-charging step: during the sampling conversion of the current acquisition channel, pre-charging the signal level of the next target channel so that when the next target channel is switched to the input terminal of the ADC module, the signal level of the input terminal of the ADC module is close to the signal value of the target channel.

[0015] Thirdly, this application provides a chip comprising: a channel state-aware ADC dynamic time-division acquisition system as described in the first aspect, and at least one ADC module, wherein the input terminal of the ADC module is connected to the output terminal of a pre-charging unit and is configured to perform analog-to-digital conversion on the EEG signals of each acquisition channel accessed in a time-division manner.

[0016] As described above, the channel state-aware ADC dynamic time-division acquisition system, method, and chip described in this application have the following beneficial effects:

[0017] 1. This application utilizes a multiplexing switching unit to enable a small number of ADC modules to serve multiple acquisition front-end channels in a time-sharing manner, significantly reducing ADC hardware overhead and power consumption. Compared to a fully parallel architecture where each channel has an independently configured ADC, this application drastically reduces the number of ADCs, thereby effectively reducing chip area and system power consumption, and improving integration and portability in multi-channel applications. Simultaneously, due to the significant reduction in the number of ADC modules, gain errors, offset errors, and nonlinear mismatches caused by process variations between multiple ADCs are effectively mitigated, reducing the burden on subsequent digital signal processing. Therefore, this application effectively solves the technical problems of high ADC hardware overhead, long sampling setup time during channel switching, and low effective data output rate under electrical stimulation artifacts in existing technologies.

[0018] 2. This application incorporates a pre-charge unit between the multiplexing unit and the ADC module. During channel switching intervals, the signal level of the target channel is pre-charged to near the target value, effectively shortening the ADC sampling setup time and ensuring the accuracy and linearity of high-speed time-division multiplexing. Specifically, the pre-charge unit includes a high-speed buffer and a sample-and-hold capacitor connected in series. During the sampling conversion of the current channel, the high-speed buffer pre-charges the signal voltage of the next channel to be sampled onto the sample-and-hold capacitor. When the multiplexing unit switches to the next channel, the voltage at the ADC module's sampling input has essentially reached near the target value, significantly shortening the sampling setup time. This allows the system to maintain good sampling linearity and accuracy even in multi-channel high-speed time-division switching scenarios, avoiding sampling errors caused by insufficient setup time.

[0019] 3. This application uses a status marking unit to monitor the amplifier saturation state and stimulation artifact state of each acquisition channel in real time. Each channel is marked as valid or recovering, and the control logic unit dynamically schedules the sampling order according to the channel status, prioritizing sampling of valid channels and skipping or delaying channels in recovery, thereby improving the effective data output rate under electrical stimulation artifact conditions. In implantable or closed-loop EEG signal acquisition systems, strong stimulation artifacts generated by electrical stimulation pulses can cause the acquisition front-end amplifier to enter a saturation state. This application avoids invalid sampling during the channel recovery period through a dynamic scheduling mechanism, enabling the system to maintain a high effective data output rate even under strong electrical stimulation artifact conditions, improving data communication efficiency and the reliability of subsequent signal processing. Attached Figure Description

[0020] Figure 1 The diagram shown is a schematic diagram of the principle structure of the ADC dynamic time-division acquisition system based on channel state awareness as described in the embodiments of this application.

[0021] Figure 2 The diagram shown is a schematic diagram of the principle structure of the multiplexing unit in the channel state-aware ADC dynamic time-division acquisition system described in the embodiments of this application.

[0022] Figure 3 The diagram shown is a schematic diagram of the principle structure of the pre-charge unit in the channel state-aware ADC dynamic time-division acquisition system described in the embodiments of this application.

[0023] Figure 4 The diagram shown is a schematic representation of the principle structure of the state marking unit in the channel state-aware ADC dynamic time-division acquisition system described in this application embodiment.

[0024] Figure 5 The diagram shown is a schematic representation of the acquisition front-end in the channel state-aware ADC dynamic time-division acquisition system described in this application embodiment.

[0025] Figure 6 The diagram shown is a schematic representation of the control logic unit in the channel state-aware ADC dynamic time-division acquisition system described in this application embodiment.

[0026] Figure 7 The diagram shown is a schematic of the acquisition channel architecture in the channel state-aware ADC dynamic time-division acquisition system described in the embodiments of this application.

[0027] Figure 8 The diagram shown is a schematic of the acquisition front-end AFE and ADC architecture in the channel state-aware ADC dynamic time-division acquisition system described in this application embodiment.

[0028] Figure 9 The diagram shown is a flowchart illustrating the principle of the channel state-aware ADC dynamic time-division acquisition method described in this application embodiment.

[0029] Component designation explanation

[0030] 1 Channel State Aware ADC Dynamic Time-Division Acquisition System 11 Data collection front end 111 Low noise amplifier 112 low-pass filter 113 First switch group 114 Second switch group 12 Multiplexing unit 121 Level 1 selector switch 122 Two-stage selector switch 13 Precharge unit 131 High-speed buffer 132 Sample and hold capacitor 14 Status marker unit 141 comparator array 142 OR gate logic circuit 143 Status Register 15 Control Logic Unit 151 Timing reference module 152 Channel status reading module 153 Strobor Address Generation Module 2 ADC module S10~S40 step Detailed Implementation

[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] To address the technical problems in existing multi-channel EEG signal acquisition systems using ADC time-division multiplexing, such as excessive hardware overhead due to the fully parallel architecture, insufficient sampling setup time during channel switching affecting accuracy under the time-division multiplexing architecture, and the generation of large stimulation artifacts when high-voltage stimulation pulses are coupled to the acquisition front end via electrodes in neuromodulation systems that integrate acquisition and stimulation, resulting in invalid data acquisition during the amplifier saturation recovery period and thus low effective data output rate, this paper provides a channel state-aware ADC dynamic time-division acquisition system, method, and chip.

[0034] The following will refer to the embodiments of this application. Figures 1 to 9 The technical solutions in the embodiments of this application will be described in detail.

[0035] Example 1

[0036] This embodiment provides a channel state-aware ADC dynamic time-division acquisition system. Figure 1 The diagram shown is a schematic representation of the principle structure of the channel state-aware ADC dynamic time-division acquisition system described in an embodiment of this application. Figure 1 As shown, the channel state-aware ADC dynamic time-division acquisition system 1 provided in this embodiment includes: multiple acquisition front-ends 11, multiplexing switching unit 12, pre-charging unit 13, status marking unit 14, and control logic unit 15.

[0037] In this embodiment, multiple acquisition front-ends 11 are respectively connected to corresponding acquisition electrodes and configured to amplify and filter EEG signals; the multiplexing switching unit 12 is disposed between the output terminals of the multiple acquisition front-ends 11 and the input terminal of the ADC module 2, and is configured to couple the analog output signals of multiple acquisition channels to the input terminal of the ADC module 2 in a time-division manner; the pre-charging unit 13 is disposed between the output terminal of the multiplexing switching unit 12 and the input terminal of the ADC module 2, and is configured to pre-charge the signal level of the target channel during the channel switching interval; the status marking unit 14... Each of the above is connected to the status output terminal of the acquisition front-end 11 and is configured to receive feedback status signals from each acquisition channel and mark the status of each acquisition channel accordingly. The status includes at least an active status and a recovery status. The control logic unit 15 is connected to the output terminal of the status marking unit 14 and the control terminal of the multiplexing unit 12 and is configured to generate dynamic control signals based on the current status marking of each acquisition channel, drive the multiplexing unit 12 to prioritize the acquisition channel in the active status, and skip or delay the selection of the acquisition channel in the recovery status.

[0038] This embodiment, through the coordinated control of the multiplexing unit 12, pre-charging unit 13, status marking unit 14, and control logic unit 15, can solve the technical problems in the existing ADC time-sharing acquisition architecture, such as insufficient sampling setup time during channel switching affecting accuracy, and low effective output rate caused by fixed polling acquisition of invalid data during amplifier saturation recovery due to electrical stimulation artifacts. Thus, it can achieve low-power time-sharing acquisition of high-density channels while ensuring sampling accuracy, and maintain a high effective data throughput under electrical stimulation interference environment.

[0039] The following combination Figures 2 to 8 The multiplexing unit 12, pre-charging unit 13, status marking unit 14, multiple acquisition front-ends 11, and control logic unit 15 of this embodiment will be described in detail.

[0040] In this embodiment, the multiplexing unit 12 is located between the output terminals of multiple acquisition front-ends 11 and the input terminal of the shared ADC. Its input terminal is connected to each acquisition front-end 11 in a one-to-one correspondence, and its output terminal is connected to the input terminal of the pre-charging unit 13. It is used to time-divisionally couple the analog output signals of multiple acquisition channels to the input terminal of the shared ADC, thereby realizing the time-division multiplexing of multiple channels to a small number of ADCs, which greatly reduces the hardware overhead of the ADC.

[0041] Figure 2 The diagram shown illustrates the principle structure of the multiplexing unit 12 in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 2As shown, in one implementation of this embodiment, the multiplexing unit 12 includes a multi-channel gating switch array, which is a multi-level tree-shaped switch structure, including a first-level gating switch group 121 and a second-level gating switch group 122. By adopting a multi-level tree-shaped switch structure, the multiplexing unit 12 can achieve time-division gating of a large number of acquisition channels with a limited number of switches, which helps to reduce the parasitic capacitance and leakage current of the switch array and ensure the integrity and stability of signal transmission.

[0042] The primary selection switch group 121 includes multiple primary selection switches 121. The multiple input terminals of each primary selection switch 121 are connected to the corresponding output terminals of the acquisition front-end 11, and the output terminal of each primary selection switch 121 is connected to the corresponding common node. It is configured to select one signal from the N acquisition channels and send it to the common node. Through the initial selection by the primary selection switch group 121, the signals from each acquisition front-end 11 channel are sequentially transmitted to the corresponding common node, achieving the first-level filtering of multiple input signals. This reduces the N signals to a single signal output to the common node, effectively reducing the number of input channels for the subsequent secondary selection switches 122.

[0043] In this embodiment, the secondary gating switch group 122 includes at least one secondary gating switch 122. Multiple input terminals of the secondary gating switch 122 are respectively connected to each of the common nodes, and the output terminal of the secondary gating switch 122 is connected to the input terminal of the pre-charging unit 13. It is configured to output one of the multiple common node signals to the pre-charging unit 13. Through the secondary gating switch group 122, the signals on each common node are further selected into one output to the pre-charging unit 13, achieving time-division coupling of the acquisition channel signals. The primary gating switch group 121 and the secondary gating switch group 122 work together to form a complete signal gating path, enabling the shared ADC to sample multiple acquisition channels sequentially in different time slots. This achieves time-division service of a large number of acquisition channels by a small number of ADCs, effectively reducing the ADC hardware overhead, chip area, and system power consumption of the multi-channel EEG signal acquisition system.

[0044] In this embodiment, the pre-charging unit 13 is disposed between the output terminal of the multiplexing unit 12 and the input terminal of the ADC module 2, and is used to pre-charge the signal level of the target channel during the channel switching interval, so as to shorten the sampling setup time of the ADC module 2 after channel switching.

[0045] During multi-channel time-division acquisition, when the multiplexing unit 12 switches between different acquisition channels, the sample-and-hold capacitor 132 at the input of the ADC module 2 needs to switch from the voltage of the previous channel and stabilize to the voltage of the next channel. If the charging is directly performed by the sampling switch inside the ADC, the setup time is relatively long, which limits the time-division acquisition rate. By setting up the pre-charging unit 13, the signal level of the next channel to be sampled is driven to near the target value in advance during the sampling conversion of the current channel. This ensures that the input of the ADC module 2 is close to the signal level of the target channel after the channel switch, thereby significantly shortening the sampling setup time. This ensures that the linearity and accuracy of subsequent sampling actions are not affected by the channel switching frequency, achieving high-speed and high-precision time-division acquisition.

[0046] Figure 3 The diagram shown illustrates the principle structure of the pre-charge unit 13 in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 3 As shown, in one implementation of this embodiment, the pre-charge unit 13 includes a high-speed buffer 131 and a sample-and-hold capacitor 132 connected in series.

[0047] In this configuration, the input terminal of the high-speed buffer 131 is connected to the output terminal of the multiplexing unit 12. The output terminal of the high-speed buffer 131, the first terminal of the sample-and-hold capacitor 132, and the sampling input terminal of the ADC module 2 are interconnected at the same node, and the second terminal of the sample-and-hold capacitor 132 is grounded. The high-speed buffer 131 is configured to precharge the signal voltage of the next channel to be sampled to the first terminal of the sample-and-hold capacitor 132 via the output terminal of the high-speed buffer 131 during the sampling conversion of the current channel. The ADC module 2 acquires the voltage signal at the node through its sampling input terminal. Through the above connection method, the pre-charging unit 13 constructs an independent pre-charging signal path between the multiplexing unit 12 and the ADC module 2, so that the pre-charging action before channel switching and the sampling action of the ADC module 2 can be seamlessly connected at the same node.

[0048] In this embodiment, the high-speed buffer 131 is configured to precharge the signal voltage of the next channel to be sampled to the first terminal of the sample-and-hold capacitor 132 via the output terminal of the high-speed buffer 131 during the sampling conversion of the current channel. The high-speed buffer 131 has low output impedance and high drive capability, and can provide sufficient charging current for the sample-and-hold capacitor 132 in a short time to ensure that the precharging process is completed quickly.

[0049] The ADC module 2 acquires the voltage signal at the node through its sampling input terminal. When the multiplexing unit 12 switches to the next channel, since the first end of the sample-and-hold capacitor 132 has been pre-charged to near the signal level of that channel, the sampling input terminal of the ADC module 2 does not need to start from zero or the voltage of the previous channel. It only requires a very short adjustment time to complete accurate sampling. Through the above pre-charging mechanism, the sampling setup time of the ADC module 2 after channel switching is significantly shortened, ensuring that the linearity and accuracy of subsequent sampling actions are not affected by the switching frequency. Thus, it can still maintain good signal conversion accuracy in high-speed time-division acquisition scenarios, providing a reliable guarantee for achieving high-speed, high-precision multi-channel time-division acquisition.

[0050] In this embodiment, the status marking unit 14 is connected to the status output terminal of each acquisition front end 11, and is used to receive the amplifier saturation detection signal and stimulus artifact control signal of each acquisition channel. Based on this, each channel is marked as valid or recovering, providing an accurate basis for the channel status for sampling scheduling, thereby avoiding invalid sampling during the channel recovery period and improving the effective utilization rate of the ADC and the effective data output rate of the system.

[0051] Figure 4 The diagram shown illustrates the principle structure of the state marking unit 14 in the channel state-aware ADC dynamic time-division acquisition system 1 described in this embodiment. Figure 4 As shown, in one implementation of this embodiment, the status marking unit 14 includes a comparator array 141, an OR gate logic circuit 142, and a status register 143.

[0052] The comparator array 141 converts the analog status signals of each acquisition channel into digital level signals, the OR gate logic circuit 142 integrates the multiple trigger signals of each channel, and the status register 143 latches and outputs the status flags of each channel. Through the coordinated operation of the above three sub-modules, the status flag unit 14 can convert the real-time status information of the acquisition front-end 11 into digital flag signals that can be directly read by the control logic unit 15, providing a reliable status data foundation for subsequent dynamic sampling scheduling.

[0053] Specifically, the comparator array 141 includes multiple comparators corresponding one-to-one with each acquisition channel. The amplifier saturation detection signal of each acquisition channel is input to the non-inverting input of the corresponding comparator, the inverting input of each comparator is connected to a reference threshold voltage, and the output of each comparator is connected to the input of the OR gate logic circuit 142. When the amplifier output signal of any acquisition channel exceeds the reference threshold voltage, the corresponding comparator outputs a high level, indicating that the amplifier of that channel has entered the saturation state; when the amplifier output signal does not exceed the reference threshold voltage, the comparator outputs a low level, indicating that the amplifier is operating in the linear region. Through the above comparison mechanism, the comparator array 141 converts the analog information of the amplifier saturation state of each channel into a standard digital logic level signal, realizing real-time detection and digital representation of amplifier saturation events.

[0054] In this embodiment, the output of the OR gate logic circuit 142 is connected to the corresponding data bit of the status register 143, and is configured to latch the amplifier saturation trigger signal or stimulus artifact trigger signal of any channel to the corresponding bit of the status register 143 as a recovery status marker for the channel. The OR gate logic circuit 142 performs a logical OR operation between the amplifier saturation trigger signal output from each comparator and the externally input stimulus artifact trigger signal. When any trigger condition is met, it outputs a valid level to the corresponding data bit of the status register 143. The status register 143 latches this state under the control of the system clock, and can only be cleared or updated after being read by the control logic unit 15.

[0055] Through the above-mentioned OR gate logic synthesis and register latching mechanism, the status marking unit 14 can uniformly map two independent trigger sources (amplifier saturation and stimulus artifact) to the "recovering" state in an OR logic manner, effectively avoiding the status misjudgment or omission problem that may be caused by a single judgment criterion, and improving the accuracy and robustness of channel status marking; at the same time, the parallel output mode of the status register 143 enables the control logic unit 15 to obtain the status information of all channels within one reading cycle, providing timely and reliable channel status basis for subsequent dynamic sampling scheduling decisions.

[0056] In one implementation of this embodiment, the status marking unit 14 marks each of the acquisition channels based on at least one of the following:

[0057] 1) Whether the saturation detection signal of the amplifier in the acquisition channel is triggered.

[0058] Specifically, the saturation detection signal of the amplifier in the acquisition channel is triggered when the amplifier's output signal exceeds the reference threshold voltage. This indicates that the amplifier has entered a saturation state, and the corresponding channel should be marked as being in a recovery state. Amplifier saturation is usually caused by electrical stimulation artifacts or electrode polarization voltage. Once the saturation detection signal is triggered, it indicates that the amplifier has deviated from its linear operating range. Sampling this channel at this time will yield invalid or even erroneous signal data. By using the saturation detection signal as the marking basis, the status marking unit 14 can perceive the amplifier's operating state in the most direct way and promptly mark the saturated channel as being in recovery, thereby preventing the control logic unit 15 from selecting this channel for invalid sampling during scheduling and improving the effective utilization rate of the ADC.

[0059] 2) Whether the acquisition channel is under the influence of electrical stimulation artifacts.

[0060] Specifically, whether the acquisition channel is under the influence of electrical stimulation artifacts refers to the situation where, when the system applies an electrical stimulation pulse, the acquisition channels associated with that stimulation pulse are all marked as being in a recovery state within a certain time window. In implantable or closed-loop EEG signal acquisition systems, stimulation artifacts generated by electrical stimulation pulses can interfere with adjacent or the same acquisition channels. Even if the amplifier is not yet saturated, the artifact signals themselves can cause distortion of the acquired data.

[0061] By using the period of influence of stimulus artifacts as the basis for marking, the state marking unit 14 can actively mark the relevant channel as recovering before or when the stimulus pulse arrives, without waiting for the amplifier saturation detection signal to be triggered, thereby achieving a faster channel state response and avoiding the control logic unit 15 from scheduling the channel for sampling during the artifact period, which effectively improves the system's effective data output rate during the artifact period.

[0062] 3) Whether the output of the amplifier in the acquisition channel has been restored to the linear operating range.

[0063] Specifically, the status flag unit 14 determines whether the amplifier output of the acquisition channel has recovered to the linear operating range. That is, when the amplifier exits the saturation state and resumes operation in the linear amplification range, the corresponding channel switches from the "recovery in progress" state back to the effective state. The amplifier requires a certain settling time to recover from saturation to the linear operating range. If the channel is rescheduled during the recovery process, the sampling results may still have significant errors. By using the recovery to the linear operating range as a marker, the status flag unit 14 can accurately determine whether the amplifier has fully recovered to its normal operating state, ensuring that the control logic unit 15 only re-includes the channel in the scheduling sequence when the channel truly has effective sampling conditions, thereby guaranteeing the accuracy and reliability of the sampled data.

[0064] In this embodiment, by setting multiple optional marking criteria, the status marking unit 14 can comprehensively judge the actual working status of each acquisition channel from multiple dimensions. It can use one judgment criterion alone or use multiple judgment criteria at the same time for comprehensive judgment, thereby improving the accuracy and reliability of channel status marking.

[0065] In existing acquisition front-end 11 systems that integrate acquisition and stimulation, when the high-voltage stimulation pulse is coupled to the low-noise amplifier 111 via electrodes, the lack of effective isolation protection can easily cause input stage breakdown or deep saturation, resulting in a long recovery time and completely invalid acquisition data during this period. If the residual charge on the electrodes cannot be quickly discharged after stimulation, it will cause the DC operating point of the amplifier to shift, causing the signal to deviate from the baseline. At the same time, the high-voltage pulse can also be coupled to adjacent channels through parasitic paths, causing crosstalk between channels and further reducing the effective data output rate of the system.

[0066] In this embodiment, the acquisition front-end 11 is connected to the acquisition electrodes and the multiplexing unit 12, respectively, and is used to amplify and filter the weak EEG signals picked up by the acquisition electrodes, conditioning the physiological signals at the microvolt to millivolt level to the amplitude range that the ADC module 2 can effectively quantize, while filtering out out-of-band noise and interference; in addition, during the application of the electrical stimulation pulse, the acquisition front-end 11 is also used to block the high-voltage stimulation pulse from being transmitted to the back-end circuit through the acquisition electrodes, so as to avoid damage or saturation of the acquisition front-end 11 circuit due to high voltage impact, thereby ensuring that the acquisition front-end 11 can quickly return to normal working state after the stimulation ends, and ensuring the signal fidelity, signal-to-noise ratio and system reliability of the entire acquisition.

[0067] Figure 5 The diagram shown illustrates the principle structure of the acquisition front-end 11 in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 5 As shown, in one implementation of this embodiment, the acquisition front-end 11 includes: a low-noise amplifier 111, a low-pass filter 112, a first switch group 113, and a second switch group 114, each configured for a specific acquisition channel. The first switch group 113 is positioned between the low-noise amplifier 111 and the acquisition electrode, while the second switch group 114 is positioned between the differential input terminal of the low-noise amplifier 111 and a common-mode reference voltage or ground. This embodiment, by configuring the first switch group 113 and the second switch group 114 in the acquisition front-end 11, ensures effective transmission of EEG signals by connecting the signal path during acquisition. During stimulation protection, the first switch group 113 is disconnected to block the transmission of high-current stimulation signals to the acquisition front-end 11, and the second switch group 114 is closed to short-circuit the input terminals of adjacent channels to block inter-channel crosstalk. This dual protection further enhances the safety and signal quality of the acquisition front-end 11.

[0068] In this embodiment, through the configuration of the above-mentioned switch group, the acquisition front end 11 can flexibly switch between different working modes, which not only ensures the high-fidelity transmission of weak EEG signals under normal acquisition conditions, but also provides effective input stage protection for the low-noise amplifier 111 when stimulation pulses arrive, thereby achieving the compatibility and coexistence of acquisition and stimulation in the same system.

[0069] In this embodiment, the signal processing circuit of the acquisition front-end 11 has an acquisition state and a stimulation protection state: In the acquisition state, the first switch group 113 is closed and the second switch group 114 is open, so that the nerve signal is output to the analog-to-digital converter after passing through the acquisition electrode, the first switch group 113, the low-noise amplifier 111 and the low-pass filter 112; In the stimulation protection state, the first switch group 113 is open and the second switch group 114 is closed, so as to block the electrical stimulation signal from being transmitted to the low-noise amplifier 111 through the acquisition electrode, and to short-circuit the input terminal of the low-noise amplifier 111 through the second switch group 114, so as to block crosstalk between the channels of the acquisition front-end 11.

[0070] In the acquisition state, the first switch group 113 is closed and the second switch group 114 is open, allowing the neural signal to be output to the analog-to-digital converter after passing through the acquisition electrodes, the first switch group 113, the low-noise amplifier 111, and the low-pass filter 112. In the acquisition state, the closed first switch group 113 provides a low-impedance transmission path for the physiological signal from the electrode to the amplifier, ensuring that weak signals in the microvolt to millivolt range can be transmitted to the low-noise amplifier 111 for amplification without attenuation. The open second switch group 114 prevents the differential input of the amplifier from being shorted to the common-mode reference voltage or ground, thereby ensuring that the amplifier operates normally in a differential mode, achieving high-gain, low-noise amplification of weak physiological signals. Through the coordination of the above switching states, the acquisition front-end 11 can complete high-quality signal acquisition with a complete signal chain during periods without stimuli or interference.

[0071] In the stimulation protection state, the first switch group 113 is open and the second switch group 114 is closed to block the electrical stimulation signal from being transmitted to the low noise amplifier 111 through the acquisition electrode. The differential input terminal of the low noise amplifier 111 is shorted to the common mode reference voltage or ground through the second switch group 114 to discharge residual charge on the electrode and prevent the input terminal from being left floating.

[0072] When an electrical stimulation pulse is applied to the acquisition electrode, the first switch group 113 is preferentially disconnected, physically cutting off the path of the high-voltage stimulation pulse through the acquisition electrode to the low-noise amplifier 111, preventing the amplifier input stage from being damaged by high voltage. Simultaneously, the second switch group 114 closes, shorting the differential input terminal of the low-noise amplifier 111 to a low-impedance common-mode reference voltage or ground. This provides a discharge path for residual stimulation charge on the electrode, accelerating the fading of the electrode polarization potential, and prevents the amplifier input terminal from being left floating during switch switching, thus preventing coupling with external interference. Furthermore, shorting the input terminal of the low-noise amplifier 111 by the second switch group 114 effectively blocks crosstalk between the acquisition front-end channels 11.

[0073] This embodiment provides complete input stage protection for the low-noise amplifier 111 during the application of the stimulation pulse through the coordinated control of the first switch group 113 and the second switch group 114. This avoids circuit damage and deep saturation of the amplifier caused by high voltage surges. Furthermore, the short-circuiting effect of the second switch group 114 discharges residual charge and blocks crosstalk between channels, ensuring that the acquisition front-end 11 can quickly return to normal operation after the stimulation ends. This significantly improves the reliability and signal quality of the system.

[0074] Furthermore, in one implementation of this embodiment, the acquisition front end 11 includes a resettable switch disposed between the output terminal and the inverting input terminal of the low-noise amplifier 111. The reset switch is used to close in the stimulation protection state, short-circuiting the output terminal and the inverting input terminal of the low-noise amplifier 111, forcing the low-noise amplifier 111 to switch to unity-gain buffer mode to prevent deep saturation of the internal nodes of the low-noise amplifier 111 due to overdrive voltage; and to open in the acquisition state, allowing the low-noise amplifier 111 to operate in normal amplification mode.

[0075] In one implementation of this embodiment, the acquisition front end 11 further includes an adjustable gain amplifier connected to the output terminal of the low noise amplifier 111, used to adjust the gain of the signal output by the low noise amplifier 111.

[0076] Specifically, the output of the low-noise amplifier 111 is connected to the input of the adjustable-gain amplifier. The low-noise amplifier 111 pre-amplifies the weak physiological signal picked up at the differential input and outputs it to the adjustable-gain amplifier. The adjustable-gain amplifier further adjusts the gain of the received signal according to the system configuration to meet the requirements of the subsequent analog-to-digital converter for the amplitude range of the input signal.

[0077] In one implementation of this embodiment, the low-pass filter 112 is connected to the output of the adjustable gain amplifier and is used to filter the signal amplified by the adjustable gain amplifier.

[0078] Specifically, the output of the adjustable gain amplifier is connected to the input of the low-pass filter 112. The signal amplified by the adjustable gain amplifier enters the low-pass filter 112, which filters it to remove high-frequency noise and out-of-band interference. The filtered signal is then output to the analog-to-digital converter for sampling and quantization, completing the digital acquisition of physiological signals.

[0079] In one implementation of this embodiment, the adjustable gain amplifier is a capacitively coupled programmable gain amplifier; a pseudo-resistor is connected between the input terminal of the capacitively coupled programmable gain amplifier and the common-mode voltage, which is used to provide a stable DC bias path for the adjustable gain amplifier when the interstage isolation switch is open.

[0080] In one implementation of this embodiment, the acquisition front end 11 may further include: an interstage isolation switch, disposed between the output terminal of the low noise amplifier 111 and the input terminal of the adjustable gain amplifier, for disconnecting in the stimulation protection state to block the residual influence of the high voltage stimulation pulse from being transmitted to the adjustable gain amplifier; and closing in the acquisition state to allow the signal output by the low noise amplifier 111 to be transmitted to the adjustable gain amplifier.

[0081] The interstage isolation switch prevents residual high voltage from being transmitted to the subsequent programmable gain amplifier, solving the technical problems of amplifier saturation and DC operating point drift, thereby protecting the subsequent link and accelerating recovery.

[0082] In this embodiment, the control logic unit 15 is connected to the output terminal of the status flag unit 14 and the control terminal of the multiplexing unit 12, respectively. It is used to read the current status flag of each acquisition channel output by the status flag unit 14, generate dynamic control signals according to the effective or recovery status of each channel, drive the multiplexing unit 12 to prioritize the acquisition channel in the effective state, and skip or delay the selection of the acquisition channel in the recovery state.

[0083] Through the above dynamic scheduling mechanism, the control logic unit 15 converts the channel status flag information into control instructions for the multiplexing unit 12 in real time. It can avoid channels that are affected by amplifier saturation or stimulus artifacts in real time during each sampling period, and only schedule channels with effective sampling conditions. This achieves real-time dynamic optimization of sampling scheduling, thereby effectively avoiding invalid sampling and improving the effective utilization rate of ADC module 2 and the effective data output rate of the system.

[0084] Figure 6 The diagram shown is a schematic representation of the principle structure of the control logic unit 15 in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 6 As shown, in one implementation of this embodiment, the control logic unit 15 includes a timing reference module 151, a channel status reading module 152, and a strobe address generation module 153.

[0085] The timing reference module 151 is configured to generate a sampling timing clock signal. The timing reference module 151 provides a synchronization clock for each module inside the control logic unit 15, ensuring that operations such as channel status reading, address generation, and multiplexing switching are executed in an orderly manner at precise time nodes. At the same time, the sampling timing clock signal is also used to control the sampling conversion timing of the ADC module 2, so that the channel selection switching of the multiplexing switching unit 12 and the sampling conversion cycle of the ADC module 2 are precisely synchronized, thereby ensuring that the entire time-division acquisition system can maintain a stable timing relationship during high-speed switching.

[0086] In this embodiment, the channel status reading module 152 is configured to read the flag bits of each acquisition channel output by the status flag unit 14; the gating address generation module 153 is configured to generate a gating address sequence for skipping the channel in the recovery state based on the flag bits, and the output terminal of the gating address generation module 153 is connected to the control terminal of the multiplexing unit 12.

[0087] Specifically, the channel status reading module 152 is configured to read the flag bits of each acquisition channel output by the status flag unit 14. At the beginning of each sampling period, the channel status reading module 152 reads the flag bit information of all acquisition channels in parallel from the status register 143 of the status flag unit 14, identifies whether each channel is currently in a valid state or a recovery state, and transmits the read status information to the strobe address generation module 153. Through the above parallel reading method, the control logic unit 15 can obtain the status information of all channels within one reading period, effectively shortening the status information acquisition time, enabling dynamic scheduling decisions to respond more quickly to changes in channel status, and improving the real-time performance of scheduling.

[0088] Specifically, in this embodiment, the gating address generation module 153 is configured to generate a gating address sequence that skips channels in the recovery state based on the flag bits. The output of the gating address generation module 153 is connected to the control terminal of the multiplexing unit 12. The gating address generation module 153 dynamically generates a sequence of channel addresses to be selected within the current sampling period based on the channel flag bits provided by the channel status reading module 152. When a channel in the address sequence is marked as being in the recovery state, the gating address generation module 153 automatically skips that address and proceeds to the next channel address in a valid state. Through this dynamic address generation mechanism, the multiplexing unit 12 selects only the currently valid channels in each sampling period, fundamentally avoiding invalid sampling during the channel recovery period, thereby significantly improving the effective utilization rate of the ADC module 2.

[0089] In one implementation of this embodiment, the control logic unit 15 is further configured to: perform sequential polling scheduling on each of the acquisition channels in the default state; and when any acquisition channel is detected to be marked as being in the recovery state, suspend the sampling scheduling of the acquisition channel, and re-include it in the polling sequence after the acquisition channel recovers to the valid state.

[0090] In this embodiment, the scheduling strategy provided by the control logic unit 15, using sequential polling, ensures that each channel can be sampled fairly and periodically under normal acquisition conditions without stimulation artifact interference. When a channel enters a recovery state, the control logic unit 15 dynamically removes that channel from the polling sequence, suspends its sampling scheduling, and reinstates it into the polling sequence once it recovers to an "effective" state. Through this dynamic scheduling mechanism, the control logic unit 15 effectively avoids the invalid sampling window period of each channel while maintaining the balance of polling scheduling. This ensures the fairness of sampling for each channel and maximizes the effective utilization rate of the ADC module 2, enabling the system to maintain a high effective data output rate even under electrical stimulation artifact interference.

[0091] Figure 7 The diagram shown is a schematic of the acquisition channel architecture in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 7 As shown in the figure, this embodiment uses 128 acquisition channels as an example for illustration, but this application is not limited to this specific number. In practical applications, it can be expanded to 64, 256 or more channels as needed.

[0092] Figure 7In this configuration, the acquisition electrodes E0 to E127 are divided into eight groups of 16 channels each (E0~E15, E16~E31, E32~E47, E48~E63, E64~E79, E80~E95, E96~E111, E112~E127), with each group corresponding to a 16-channel acquisition front-end 11. Each acquisition front-end 11 is connected to its corresponding acquisition electrode and is used to amplify and filter the EEG signals picked up by the acquisition electrode. For details on its specific structure, please refer to the relevant description of the acquisition front-end 11 in the aforementioned embodiments.

[0093] The output of each 16-channel acquisition front-end 11 is connected to the input of its corresponding ADC (ADC0 to ADC7). Specifically, the output of acquisition front-end 11 is connected to the input of ADC0, the output of acquisition front-end 11 is connected to the input of ADC1, and so on, with the output of acquisition front-end 11 connected to the input of ADC7. ADC0 to ADC7 refer to the shared ADC module 2 described in the previous embodiment. Each ADC is used to perform time-division sampling and analog-to-digital conversion on the 16-channel analog signals output from its corresponding acquisition front-end 11, and outputs digital signals ADCout0 to ADCout7 respectively. Through this architecture configuration, each shared ADC only needs to serve 16 acquisition channels in a time-division manner. This achieves a reasonable allocation and efficient utilization of ADC hardware resources while ensuring that the sampling rate of each channel meets application requirements, balancing system power consumption, area, and acquisition performance. It should be noted that... Figure 7 The connection between the acquisition front-end 11 and the ADC shown is a simplified illustration. In actual implementation, as described in the aforementioned embodiments, a multiplexing switching unit 12, a pre-charging unit 13, a status marking unit 14, and a control logic unit 15 are also provided between the acquisition front-end 11 and the shared ADC to realize dynamic time-division acquisition control based on channel status.

[0094] Figure 8 The diagram shown illustrates the acquisition front-end 11AFE and ADC architecture in the channel state-aware ADC dynamic time-division acquisition system 1 described in this application embodiment. Figure 8 As shown, Figure 8 As shown, taking the 16-channel acquisition front-end 11 as an example, the acquisition electrodes E0 to E15 are respectively connected to the input terminals of the corresponding low-noise amplifiers 111. Each low-noise amplifier 111 is used to perform low-noise pre-amplification of the weak physiological signals of the corresponding channel. The output terminals of each low-noise amplifier 111 are respectively connected to the input terminals of the corresponding low-pass filters 112. Each low-pass filter 112 is used to filter out high-frequency noise outside the signal frequency band. The output terminals of each low-pass filter 112 are all connected to the input terminal of the multiplexing unit 12. The multiplexing unit 12 performs time-division selection of the signals of each channel and outputs them to the input terminal of the ADC module 2 for analog-to-digital conversion.

[0095] In this embodiment, the low-noise amplifier 111 and the low-pass filter 112 together constitute the acquisition front-end 11 described in this application. For details of its specific structure and switch configuration, please refer to the description of the signal processing circuit of the acquisition front-end 11 in the foregoing embodiments. Through the above architecture configuration, the analog signals of the 16 acquisition channels can be time-division multiplexed using the same ADC module 2 for analog-to-digital conversion, effectively reducing the ADC hardware overhead. It should be noted that... Figure 8 The control module shown is one of the specific implementations of the control logic unit 15 described in the foregoing embodiments; in actual implementation, a pre-charging unit 13 and a status flag unit 14 are also provided between the acquisition front-end 11 and the ADC module 2. Figure 8 (not shown in the figure), and its specific connection relationship and function are detailed in the relevant descriptions in the foregoing embodiments.

[0096] The overall implementation process of the channel state-aware ADC dynamic time-division acquisition system 1 in this embodiment is as follows:

[0097] First, multiple acquisition front-ends 11 respectively pick up multi-channel EEG signals through their respective acquisition electrodes, and amplify and filter the weak signals to suppress out-of-band noise. At the same time, the status marking unit 14 receives the amplifier saturation detection signal output by each acquisition front-end 11 and the stimulus artifact control signal provided by the system in real time, and performs a comprehensive judgment on each acquisition channel through the comparator array 141 and OR gate logic circuit 142, marking each channel as valid or recovering, and latching it in the status register 143 for subsequent scheduling.

[0098] Secondly, the control logic unit 15 reads the channel flag bits in the status register 143 in each sampling period, dynamically generates the strobe address sequence according to the channel status, and polls each channel in sequence in the default state. When a channel is detected to be marked as recovering, the channel is automatically skipped. Only the channels in the valid state are generated with strobe addresses, and the dynamic address sequence is output to the control terminal of the multiplexing unit 12.

[0099] Furthermore, the multiplexing unit 12 selects and outputs the analog signal of the target acquisition channel to the pre-charging unit 13 according to the received gating address sequence; at the same time, during the sampling conversion of the current channel, the pre-charging unit 13 pre-charges the signal level of the next channel to be sampled to the first end of the sample-and-hold capacitor 132 through the high-speed buffer 131, so that the sampling input of the shared ADC is close to the target signal level at the moment of channel switching.

[0100] Finally, ADC module 2 performs analog-to-digital conversion on the pre-charged analog signal to the target value, outputting a valid digital signal, completing one sampling cycle. This process is repeated cyclically to achieve continuous dynamic time-sharing acquisition of multi-channel EEG signals.

[0101] Through the above implementation process, the channel state-aware ADC dynamic time-division acquisition system 1 of this embodiment achieves the following technical effects:

[0102] First, by using the multiplexing unit 12, a small number of ADC modules can serve a large number of acquisition channels in a 2-time division manner. Compared with the fully parallel architecture where each channel is configured with an independent ADC, this significantly reduces ADC hardware overhead, chip area and system power consumption. At the same time, it reduces the gain and offset mismatch problem between multiple ADCs caused by process drift.

[0103] Second, the pre-charging unit 13 pre-charges the target signal during the channel switching interval, so that the sampling input terminal of the ADC module 2 is close to the target voltage at the moment of channel switching, which greatly shortens the sampling setup time, ensures the sampling linearity and accuracy in the multi-channel high-speed time-division switching scenario, and realizes high-speed and high-precision time-division acquisition.

[0104] Third, the real-time status of each channel is marked by the status marking unit 14. With the dynamic scheduling mechanism of the control logic unit 15, the channel in the recovery state is automatically skipped under the interference of electrical stimulation artifacts. Only the signal of the effective channel is collected, which avoids invalid sampling during the amplifier saturation recovery period and significantly improves the effective utilization rate of ADC module 2 and the effective data output rate of the system.

[0105] Example 2

[0106] Please see Figure 9 The diagram shows the principle flowchart of the channel state-aware ADC dynamic time-division acquisition method described in the embodiments of this application. Figure 9 As shown, this embodiment provides a channel state-aware ADC dynamic time-division acquisition method, which can be applied to the channel state-aware ADC dynamic time-division acquisition system 1 described in this embodiment. The channel state-aware ADC dynamic time-division acquisition method of this embodiment specifically includes the following steps S10 to S40.

[0107] Step S10, Status Marking Step: Obtain the feedback status signal of each acquisition channel, and mark each acquisition channel as valid or recovering according to the feedback status signal.

[0108] Specifically, in step S10, the status marking unit 14 receives the amplifier saturation detection signal output from each acquisition front-end 11 and the stimulus artifact control signal provided by the system in real time. It compares the output signal of each channel amplifier with the reference threshold voltage using the comparator array 141, and combines this with the OR gate logic circuit 142 to comprehensively determine the two trigger signals. When the amplifier saturation detection signal of any channel is triggered or is under the influence of a stimulus artifact, that channel is marked as "recovering"; otherwise, it is marked as "valid". Through this marking mechanism, the system can monitor the working status of each acquisition channel in real time, providing accurate channel status information for subsequent dynamic sampling scheduling.

[0109] Step S20, Dynamic scheduling step: Generate a dynamic control signal based on the current status flag of each acquisition channel. The dynamic control signal is used to indicate that the acquisition channels in the effective state should be prioritized for sampling, and the acquisition channels in the recovery state should be skipped or delayed.

[0110] Specifically, in step S20, the control logic unit 15 reads the channel flag bits output by the status flag unit 14 in each sampling period. When polling each channel sequentially in the default state, if a channel is detected to be marked as "recovering", the sampling scheduling of that channel is paused, and it is dynamically removed from the polling sequence. It is then reintroduced into the polling sequence after the channel recovers to the "valid" state. For channels in the "valid" state, gating addresses are generated sequentially. Through the above dynamic scheduling mechanism, the system can effectively avoid invalid sampling windows during the amplifier saturation recovery period or the influence of stimulus artifacts, thereby improving the effective utilization rate of the ADC module 2.

[0111] Step S30, time-division switching step: control the multiplexing switching network to perform channel selection switching according to the dynamic control signal, and couple the analog signal of the acquisition channel in the effective state to the input terminal of ADC module 2 in a time-division manner.

[0112] Specifically, in step S30, the multiplexing unit 12 selects and outputs the analog signal of the target acquisition channel to the input terminals of the pre-charging unit 13 and the ADC module 2 according to the dynamic gating address sequence output by the control logic unit 15. The multiplexing unit 12 adopts a multi-level tree switch structure. Through the coordinated operation of the first-level gating switch group 121 and the second-level gating switch group 122, the signals of each acquisition channel are transmitted to the ADC module 2 in a dynamic scheduling order. Through the above time-sharing switching mechanism, a small number of ADC modules 2 can serve a large number of acquisition channels in a time-sharing manner, significantly reducing the ADC hardware overhead and system power consumption.

[0113] Step S40, Pre-charging step: During the sampling conversion of the current acquisition channel, the signal level of the next target channel is pre-charged so that when the next target channel is switched to the input of the ADC module 2, the signal level of the input of the ADC module 2 is close to the signal value of the target channel.

[0114] Specifically, in step S40, during the sampling conversion of the current channel, the high-speed buffer 131 of the pre-charge unit 13 pre-charges the signal voltage of the next channel to be sampled to the first end of the sample-and-hold capacitor 132, so that the sampling input of the ADC module 2 is close to the signal level of the target channel at the moment of channel switching. Through the above pre-charging mechanism, the sampling setup time of the ADC module 2 after channel switching is significantly shortened, ensuring that the linearity and accuracy of subsequent sampling actions are not affected by the switching frequency, and realizing high-speed, high-precision time-division acquisition.

[0115] It should be noted that the specific implementation of each step in this method embodiment can refer to the description of the corresponding function in the aforementioned embodiment of the channel state-aware ADC dynamic time-division acquisition system 1, and will not be repeated here. However, it should be noted that the channel state-aware ADC dynamic time-division acquisition system 1 described in the above embodiment can implement the channel state-aware ADC dynamic time-division acquisition method described in this application. However, the implementation system of the channel state-aware ADC dynamic time-division acquisition method described in this application includes, but is not limited to, the structure of the channel state-aware ADC dynamic time-division acquisition system 1 listed in this embodiment 1. All structural modifications and substitutions of the prior art made according to the principles of this application are included within the protection scope of this application.

[0116] The scope of protection of the channel state-aware ADC dynamic time-division acquisition method described in this application is not limited to the execution order of the steps listed in this embodiment. Any scheme implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0117] Example 3

[0118] This embodiment provides a chip, including the aforementioned channel state-aware ADC dynamic time-division acquisition system 1 and at least one ADC module 2. The input terminal of the ADC module 2 is connected to the output terminal of the pre-charging unit 13 and is configured to perform analog-to-digital conversion on the EEG signals of each acquisition channel accessed in a time-division manner.

[0119] The chip in this embodiment is, for example, an integrated chip for neural signal acquisition and stimulation, which can be implanted in the skull of experimental animals or humans to acquire local field potential (LFP) signals in real time and simultaneously apply electrical stimulation. This chip is manufactured using standard CMOS technology and integrates 128 acquisition channels, an 8-channel multiplexing unit 12, a pre-charging unit 13, a status marking unit 14, a control logic unit 15, and 8 ADC modules 2. Its typical operating voltage is 1.8V, and the total power consumption is controlled within 50mW. It is suitable for implantable or wearable bioelectrical signal acquisition devices with stringent requirements for size and power consumption.

[0120] The specific application of the chip in this embodiment is, for example, a closed-loop deep brain stimulation (DBS) system. In this application scenario, the chip acquires local field potential signals from specific brain nuclei in real time through an electrode array implanted in the skull. The acquisition front-end 11 amplifies and filters the weak neural signals. Simultaneously, when the system determines that electrical stimulation needs to be applied based on the characteristics of the acquired signals, the control logic unit 15 controls the stimulator to output stimulation pulses through the same or adjacent electrodes. During the application of stimulation pulses and for a period of time after stimulation ends, the status marking unit 14 marks the affected acquisition channels as being in a recovery state based on the stimulation artifact control signal and the amplifier saturation detection signal. The control logic unit 15 automatically skips these channels during dynamic scheduling, prioritizing the acquisition of other unaffected effective channels, thereby ensuring that high-quality neural signals can be continuously acquired during closed-loop stimulation and avoiding data interruption or signal contamination caused by stimulation artifacts. In addition, between every two sampling cycles, the pre-charging unit 13 continuously pre-charges the signal of the next channel to ensure sampling accuracy during high-speed time-division switching of multiple channels.

[0121] Through the above application method, the chip in this embodiment can achieve uninterrupted high-quality neural signal acquisition during closed-loop electrical stimulation therapy, providing a reliable signal basis for real-time adjustment of stimulation parameters, thereby improving the accuracy and effectiveness of neuromodulation therapy. It should be noted that the number of ADC modules 2 in the chip described in this application can be flexibly configured according to actual application needs. For example, in the above 128-channel embodiment, it is configured with 8 ADC modules 2, each ADC module 2 serving 16 acquisition channels in a time-sharing manner. However, this application is not limited to this; in other embodiments, the number of ADC modules 2 can be reasonably determined based on factors such as the number of channels, sampling rate requirements, and power consumption budget.

[0122] The chip provided in this embodiment executes the following process during operation:

[0123] First, multiple acquisition front-ends 11 pick up multi-channel bioelectrical signals through their respective acquisition electrodes, and amplify and filter the weak signals to suppress out-of-band noise. Simultaneously, the status marking unit 14 acquires the amplifier saturation detection signal output by each acquisition front-end 11 and the stimulus artifact control signal provided by the system in real time. The comparator array 141 compares the output signal of each channel amplifier with the reference threshold voltage, and the OR gate logic circuit 142 performs a comprehensive judgment on the two trigger signals. When the amplifier saturation detection signal of any channel is triggered or is under the influence of a stimulus artifact, that channel is marked as "recovering" and latched in the status register 143; otherwise, it is marked as "valid".

[0124] Secondly, the control logic unit 15 reads the channel flag bits in the status register 143 during each sampling period. In the default state, the control logic unit 15 performs sequential polling scheduling of each acquisition channel; when a channel is detected as being marked as "recovering," the sampling scheduling of that channel is paused, and it is dynamically removed from the polling sequence. It is then reinstated into the polling sequence once the channel recovers to the "valid" state. The control logic unit 15 generates a strobe address sequence according to the aforementioned dynamic scheduling strategy and outputs it to the control terminal of the multiplexing unit 12.

[0125] Next, the multiplexing unit 12 selects and outputs the analog signal of the target acquisition channel to the pre-charging unit 13 according to the received gating address sequence. At the same time, during the sampling conversion of the current channel, the pre-charging unit 13 pre-charges the signal voltage of the next channel to be sampled to the first end of the sample-and-hold capacitor 132 through the high-speed buffer 131, so that the sampling input of the ADC module 2 is close to the signal level of the target channel at the moment of channel switching.

[0126] Finally, ADC module 2 performs analog-to-digital conversion on the pre-charged analog signal to the target value, outputting a valid digital signal and completing one sampling cycle.

[0127] The above process is executed cyclically to achieve continuous dynamic time-sharing acquisition of multi-channel bioelectric signals.

[0128] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0129] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0130] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A channel state-aware ADC dynamic time-division acquisition system, characterized in that, include: Multiple acquisition front-ends are connected to corresponding acquisition electrodes and are configured to amplify and filter EEG signals. A multiplexing unit is located between the output terminals of the multiple acquisition front-ends and the input terminal of the ADC module, and is configured to couple the analog output signals of the multiple acquisition channels to the input terminal of the ADC module in a time-division manner. A pre-charging unit is disposed between the output terminal of the multiplexing unit and the input terminal of the ADC module, and is configured to pre-charge the signal level of the target channel during the channel switching interval. The status marking unit is connected to the status output terminal of each of the acquisition front ends, and is configured to receive the feedback status signal of each acquisition channel and mark the status of each acquisition channel accordingly. The status includes at least a valid status and a recovery status. The control logic unit is connected to the output terminal of the status flag unit and the control terminal of the multiplexing unit, respectively. It is configured to generate dynamic control signals according to the current status flag of each acquisition channel, drive the multiplexing unit to prioritize the acquisition channel in the effective state, and skip or delay the selection of the acquisition channel in the recovery state.

2. The ADC dynamic time-division acquisition system based on channel state awareness according to claim 1, characterized in that, The multiplexing unit includes a multi-channel gating switch array, comprising a primary gating switch group and a secondary gating switch group; The primary selection switch group includes multiple primary selection switches. The multiple input terminals of each primary selection switch are respectively connected to the corresponding acquisition front-end output terminal, and the output terminal of each primary selection switch is connected to the corresponding common node. It is configured to select one signal from N acquisition channels to the common node. The secondary gating switch group includes at least one secondary gating switch, the multiple input terminals of the secondary gating switch are respectively connected to each of the common nodes, and the output terminal of the secondary gating switch is connected to the input terminal of the pre-charging unit, and is configured to output one of the multiple common node signals to the pre-charging unit.

3. The ADC dynamic time-division acquisition system based on channel state awareness according to claim 1, characterized in that, The pre-charge unit includes a high-speed buffer and a sample-and-hold capacitor connected in series; the input terminal of the high-speed buffer is connected to the output terminal of the multiplexing unit, the output terminal of the high-speed buffer, the first terminal of the sample-and-hold capacitor and the sampling input terminal of the ADC module are connected to the same node, and the second terminal of the sample-and-hold capacitor is grounded; The high-speed buffer is configured to precharge the signal voltage of the next channel to be sampled to the first end of the sample-and-hold capacitor via the output of the high-speed buffer during the sampling conversion of the current channel, and the ADC module acquires the voltage signal on the node through its sampling input.

4. The channel state-aware ADC dynamic time-division acquisition system according to claim 1, characterized in that, The status marking unit includes a comparator array, an OR gate logic circuit, and a status register; The comparator array includes multiple comparators that correspond one-to-one with each acquisition channel; the signals of each acquisition channel are respectively input to the non-inverting input terminal of the corresponding comparator, the inverting input terminal of each comparator is connected to the reference threshold voltage, and the output terminal of each comparator is connected to each input terminal of the OR gate logic circuit. The output of the OR gate logic circuit is connected to the corresponding data bit of the status register and is configured to latch the amplifier saturation trigger signal or stimulus artifact trigger signal of any channel to the corresponding bit of the status register as a recovery status marker for the channel.

5. The channel state-aware ADC dynamic time-division acquisition system according to claim 4, characterized in that, The acquisition front end includes: a low-noise amplifier, a low-pass filter, a first switch group, and a second switch group for each acquisition channel; The first switch group is disposed between the low-noise amplifier and the acquisition electrode, and the second switch group is disposed between the differential input terminal of the low-noise amplifier and the common-mode reference voltage or ground; The acquisition front-end signal processing circuit has an acquisition state and a stimulation protection state: In the acquisition state, the first switch group is closed and the second switch group is open, so that the neural signal is output to the analog-to-digital converter after passing through the acquisition electrodes, the first switch group, the low-noise amplifier and the low-pass filter; In the stimulation protection state, the first switch group is open and the second switch group is closed to block the electrical stimulation signal from being transmitted to the low noise amplifier through the acquisition electrode, and the input terminal of the low noise amplifier is short-circuited by the second switch group to block crosstalk between the acquisition front-end channels.

6. The channel state-aware ADC dynamic time-division acquisition system according to claim 1, 3, or 4, characterized in that, The status marking unit marks each of the acquisition channels based on at least one of the following criteria: Whether the saturation detection signal of the amplifier in the acquisition channel is triggered; Whether the acquisition channel is under the influence of electrical stimulation artifacts; Has the output of the amplifier in the acquisition channel been restored to the linear operating range? 7. The channel state-aware ADC dynamic time-division acquisition system according to claim 1, characterized in that, The control logic unit includes a timing reference module, a channel status reading module, and a strobe address generation module; The timing reference module is configured to generate a sampling timing clock signal; The channel status reading module is configured to read the flag bits of each acquisition channel output by the status flag unit; The strobe address generation module is configured to generate a strobe address sequence that skips the channel in the recovery state based on the flag bit, and the output of the strobe address generation module is connected to the control terminal of the multiplexing unit.

8. The channel state-aware ADC dynamic time-division acquisition system according to claim 1, characterized in that, The control logic unit is configured as follows: By default, each of the aforementioned acquisition channels is sequentially polled and scheduled. as well as When any acquisition channel is detected to be marked as being in the recovery state, the sampling scheduling of the acquisition channel is paused, and the acquisition channel is reinstated into the polling sequence after it recovers to the valid state.

9. A channel state-aware ADC dynamic time-division acquisition method, characterized in that, The method includes: Status marking steps: Obtain the feedback status signal of each acquisition channel, and mark each acquisition channel as valid or recovering based on the feedback status signal; Dynamic scheduling steps: Generate dynamic control signals based on the current status flags of each acquisition channel. The dynamic control signals are used to indicate that acquisition channels in the active state should be prioritized for sampling, and acquisition channels in the recovery state should be skipped or delayed. Time-division switching steps: Control the multiplexing switching network to perform channel selection switching according to the dynamic control signal, and couple the analog signal of the acquisition channel in the effective state to the input terminal of the ADC module in a time-division manner; Pre-charging step: During the sampling conversion of the current acquisition channel, the signal level of the next target channel is pre-charged so that when the next target channel is switched to the input of the ADC module, the signal level of the input of the ADC module is close to the signal value of the target channel.

10. A chip, characterized in that, include: The channel state-aware ADC dynamic time-division acquisition system according to any one of claims 1 to 8, and At least one ADC module, the input of which is connected to the output of the pre-charge unit, is configured to perform analog-to-digital conversion on the EEG signals from each time-division multiplexing acquisition channel.

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