A JESD204B receive circuit verification system and method

Abstract

The application discloses a JESD204B receiving circuit verification system and method, and the system comprises a virtual sequence generator, the virtual sequence generator is in communication connection with a data source agent, the data source agent is in communication connection with a data source interface, the data source interface is in communication connection with a sending model and a deterministic delay measurement module respectively, and the sending model and the deterministic delay measurement module are in communication connection with a design under test respectively; a sending agent is in communication connection with the sending model through a sending interface; a receiving agent is in communication connection with the design under test through a receiving interface; a scoreboard is in communication connection with the sending agent and the receiving agent respectively; the sending model is a JESD204B sending model, and the design under test is a JESD204B receiving circuit. The application realizes automatic verification of the JESD204B receiving circuit, improves verification efficiency, and fills the blank of JESD204B receiving circuit verification.

Description

Technical Field

[0001] This invention belongs to the field of chip verification technology, specifically relating to a JESD204B receiver circuit verification system and method. Background Technology

[0002] In high-speed analog-to-digital converters (DACs), as the sampling rate of the converter increases, the traditional LVDS (Low Voltage Differential Signaling) data interface, limited by the interface signal transmission rate, can no longer meet the requirements. JESD204B, a high-speed serial interface standard developed by JEDEC (Junior High-Speed ​​Engineering Council), is specifically designed to connect high-speed data converters and logic devices. Based on SERDES (serializer) technology, JESD204B enables high-speed data transmission. Therefore, JESD204B receiver circuits are widely used in high-speed DACs.

[0003] To ensure the correctness of the JESD204B receiver circuit, it needs to be verified, but there is currently no corresponding verification system or method. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a JESD204B receiver circuit verification system and method, which realizes automatic verification of JESD204B receiver circuits, improves verification efficiency, and fills the gap in JESD204B receiver circuit verification.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, a JESD204B receiver circuit verification system is provided, comprising: a virtual sequence generator, which is communicatively connected to a data source agent, which is communicatively connected to a data source interface, which is communicatively connected to a transmission model and a deterministic delay measurement module, and the transmission model and the deterministic delay measurement module are communicatively connected to the design under test; a transmission agent, which is communicatively connected to the transmission model through a transmission interface; a receiver agent, which is communicatively connected to the design under test through a receiver interface; and a scoring board, which is communicatively connected to the transmission agent and the receiver agent; wherein the transmission model is a JESD204B transmission model, and the design under test is a JESD204B receiver circuit.

[0007] Further, the data source proxy is used to receive the data source sequence generated by the virtual sequence generator according to the set test cases, and drive the data source interface to generate stimulus data according to the data source sequence; the sending proxy is used to receive the sending sequence generated by the virtual sequence generator according to the set test cases, and drive the sending interface to generate a mode switching signal according to the sending sequence, the mode switching signal being used to drive the sending model to enter the set working mode; the scoreboard is used to receive the stimulus data obtained by the sending proxy through the sending model, and receive the output data obtained by the proxy from the design under test, and perform a consistency comparison between the stimulus data and the output data; the deterministic delay measurement module is used to measure the time from when the stimulus data enters the sending model to when it is output by the design under test.

[0008] Furthermore, it also includes a clock proxy, which is communicatively connected to the virtual sequence generator and the clock interface, respectively. The clock interface is communicatively connected to the sending model and the design under test, respectively. The clock proxy is used to receive the clock sequence generated by the virtual sequence generator according to the set test cases, and drive the clock interface to generate a clock signal according to the clock sequence. The clock signal is used to input the sending model and the design under test.

[0009] Furthermore, it also includes a sysref generation model, which is communicatively connected to the clock interface, the transmitting model, and the design under test. The sysref generation model is used to receive the clock signal output by the clock interface and generate a sysref signal of a set period according to the set working mode. The sysref signal is used to input the transmitting model and the design under test.

[0010] Furthermore, it also includes a reset agent, which is communicatively connected to the virtual sequence generator and the reset interface, respectively. The reset interface is communicatively connected to the sending model and the design under test, respectively. The reset agent is used to receive the reset sequence generated by the virtual sequence generator according to the set test cases, and drive the reset interface to generate a reset signal according to the reset sequence. The reset signal is used to input the sending model and the design under test.

[0011] Furthermore, it also includes an SPI agent, which is communicatively connected to the virtual sequence generator and the SPI interface, respectively. The SPI interface is communicatively connected to the design under test. The SPI agent is used to receive the SPI sequence generated by the virtual sequence generator according to the set test cases, and drive the SPI interface to generate a start signal according to the SPI sequence. The start signal is used to input the design under test and cause the design under test to enter the functional mode to be tested.

[0012] Furthermore, at least one test case is prepared based on the function to be tested.

[0013] Furthermore, the sending agent includes a sequence generator, a driver, and a monitor, and the receiving agent includes a monitor.

[0014] Furthermore, the system is built on UVM.

[0015] Secondly, a JESD204B receiver circuit verification method is provided, based on the JESD204B receiver circuit verification system described in the first aspect. The method includes: selecting test cases according to verification requirements; a virtual sequence generator generating a data source sequence and a transmission sequence according to the selected test cases; a data source agent receiving the data source sequence and driving the data source interface to generate stimulus data according to the data source sequence, the stimulus data being simultaneously input into a transmission model and a deterministic delay measurement module; a transmission agent receiving the transmission sequence and driving the transmission interface to generate a mode switching signal according to the transmission sequence, used to drive the transmission model into a set working mode; simultaneously, acquiring the stimulus data through the transmission model and sending the stimulus data to a scoring board; a receiver agent acquiring the output data of the design under test through a receiver interface and sending it to the scoring board; the scoring board performing a consistency comparison between the received stimulus data and the output data of the design under test; and a deterministic delay measurement module measuring the time from when the stimulus data enters the transmission model to when it is output by the design under test.

[0016] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0017] (1) The present invention communicates with the data source agent through a virtual sequence generator, the data source agent communicates with the data source interface, the data source interface communicates with the sending model and the deterministic delay measurement module respectively, the sending model and the deterministic delay measurement module communicate with the design under test respectively; the sending agent communicates with the sending model through the sending interface; the receiving agent communicates with the design under test through the receiving interface; the scoreboard communicates with the sending agent and the receiving agent respectively; the invention realizes the automatic verification of the JESD204B receiving circuit, improves the verification efficiency, and fills the gap in the verification of the JESD204B receiving circuit.

[0018] (2) The present invention uses a UVM system, which has good structure and high reusability;

[0019] (3) The present invention improves verification efficiency by using random test cases. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a verification system structure for a JESD204B receiver circuit provided in an embodiment of the present invention;

[0021] Figure 2This is a flowchart of the verification method for the JESD204B receiving circuit in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0023] Example 1

[0024] like Figure 1 As shown, a JESD204B receiver circuit verification system comprises a virtual sequence generator communicating with a data source agent, which in turn communicates with a data source interface. The data source interface communicates with both a transmission model and a deterministic delay measurement module. The transmission model and the deterministic delay measurement module are each connected to the design under test (DUT). A transmission agent communicates with the transmission model via a transmission interface. A receiving agent communicates with the DUT via a receiving interface. A scoring board communicates with both the transmission and receiving agents. The transmission model is a JESD204B transmission model, and the DUT is a JESD204B receiver circuit. A clock agent communicates with both the virtual sequence generator and the clock interface, which in turn communicates with both the transmission model and the DUT. A sysref generation model communicates with the clock interface, the transmission model, and the DUT. A reset agent communicates with both the virtual sequence generator and the reset interface, which in turn communicates with both the transmission model and the DUT. An SPI agent communicates with both the virtual sequence generator and the SPI interface, which in turn communicates with the DUT.

[0025] The system is built on UVM and is divided into a top layer, a test layer, and an environment layer.

[0026] The top layer includes the test layer, SPI (Serial Peripheral Interface) interface, clock interface, reset interface, data source interface, transmit interface, receive interface, sysref (a reference signal specified in the JESD204B protocol for implementing deterministic delay) generation model, transmit model, deterministic delay measurement module, and the design under test. Each interface is used for interface signal control and data communication between the test layer, sysref generation model, JESD204B transmit model, deterministic delay measurement module, and the design under test.

[0027] Sysref generation model: Using the data clock generated by the clock interface, different periods of sysref signals are generated according to different JESD204B operating modes, and sent to the JESD204B to transmit the model and the design under test.

[0028] Transmission Model: The transmission model is a JESD204B transmission circuit model, including the transport layer, link layer, and physical layer. The data transmission operation mode of this model matches the operation mode of the design under test.

[0029] The deterministic delay measurement module detects specific data transmitted from the data source interface and starts counting from zero using a data clock. It stops counting when the corresponding specific data is output by the design under test. The counted time represents the elapsed time from when the data enters the transmitting model to when it is output by the JESD204B receiving circuit.

[0030] The testing layer includes an environment layer and several test cases. Based on one or more functionalities of the JESD204B transmitting or receiving circuit, corresponding test cases are written.

[0031] The environment layer includes a virtual sequence generator, clock agent, reset agent, send agent, SPI agent, data source agent, receive agent, and scoreboard.

[0032] Virtual sequence generator: The virtual sequence generator internally contains pointers to the actual sequence generator. The virtual sequence generator uses it to send the clock sequence, reset sequence, transmit sequence, SPI sequence, and data source sequence to the clock agent, reset agent, transmit agent, SPI agent, and data source agent, respectively.

[0033] Clock Agent: The clock agent drives the clock interface according to the clock sequence to generate various clock signals, which are then sent to the sysref generation model, the JESD204B transmission model, the deterministic delay measurement module, and the design under test.

[0034] Reset Agent: The reset agent drives the reset interface according to the reset sequence, generates a reset signal, and sends it to the sysref generation model, JESD204B transmission model, deterministic delay measurement module and the design under test, resetting them to their initial state.

[0035] Transmitter Agent: Based on the transmission sequence, the transmitter agent drives the transmit interface, generates a mode switching signal, and controls the JESD204B transmit model to enter the specified working mode; it receives the raw excitation data from the transmit model and sends it to the scoreboard.

[0036] SPI Proxy: The SPI proxy drives the SPI interface according to the SPI sequence, generates a start signal, and controls the design under test to enter the functional mode under test.

[0037] Data source agent: The data source agent drives the data source interface according to the data source sequence, generates stimulus data, and sends it to the JESD204B transmission model and deterministic delay measurement module.

[0038] Receive Agent: The receive agent receives the data from the design under test and sends it to the scoreboard.

[0039] Scoreboard: The scoreboard compares the raw excitation data sent by the JESD204B model with the signal output by the design under test to determine the verification result.

[0040] The sending agent contains a sequence generator, a driver, and a monitor; the receiving agent contains only a monitor; and all other agents contain a sequence generator and a driver.

[0041] The verification system of this invention can automatically verify the JESD204B receiving circuit, filling the gap in JESD204B receiving circuit verification. Furthermore, this invention improves verification efficiency through random test cases.

[0042] Example 2

[0043] Based on the JESD204B receiver circuit verification system described in Embodiment 1, this embodiment provides a JESD204B receiver circuit verification method, including:

[0044] Select test cases based on the verification requirements;

[0045] The virtual sequence generator generates a data source sequence and a transmission sequence based on the selected test cases;

[0046] The data source agent receives the data source sequence and drives the data source interface to generate stimulus data according to the data source sequence. The stimulus data is simultaneously input into the transmission model and the deterministic delay measurement module.

[0047] The sending agent receives the sending sequence and drives the sending interface to generate a mode switching signal based on the sending sequence, which is used to drive the sending model to enter the set working mode; at the same time, it obtains the stimulus data through the sending model and sends the stimulus data to the scoreboard.

[0048] The receiving agent obtains the output data of the design to be tested through the receiving interface and sends it to the scoreboard;

[0049] The scoring board performs a consistency comparison between the received stimulus data and the output data of the design under test;

[0050] The deterministic delay measurement module measures the time from when the stimulus data enters the transmission model to when it is output by the design under test.

[0051] like Figure 2 As shown, the detailed steps of the JESD204B receiver circuit verification method of the present invention are as follows.

[0052] Step 1: Select the corresponding test case based on the simulation command line option +UVM_TESTNAME.

[0053] Step 2: Start the virtual sequence for the test case.

[0054] Step 3: The virtual sequence first instantiates a send transaction and randomizes the send transaction using a randomization method. The send transaction contains various parameters related to the JESD204B working mode.

[0055] Step 4: The virtual sequence generates corresponding clock transactions based on the JESD204B working mode obtained by randomizing the transmission transactions. Then, the clock sequence is transmitted to the clock driver through the virtual sequence generator and the sequence generator in the clock proxy. The clock driver generates the sysref generation model, the JESD204B transmission model, the deterministic delay measurement module, and the clock required by the design under test through the clock interface.

[0056] Step 5: The sysref model uses the data clock generated by the clock interface to generate sysref signals of different periods according to different JESD204B operating modes, and sends them to the JESD204B to transmit the model and the design under test.

[0057] Step 6: The virtual sequence instantiates another reset transaction and randomizes it. The reset sequence is then sent. Through the virtual sequence generator and the sequence generator in the reset agent, the reset transaction is transmitted to the reset driver. The reset driver generates the sysref generation model, the JESD204B transmission model, the deterministic delay measurement module, and the reset signal required by the design under test through the reset interface.

[0058] Step 7: The virtual sequence is retransmitted. The transmission transaction is transmitted to the transmission driver through the virtual sequence generator and the sequence generator in the transmission agent. The transmission driver controls the JESD204B transmission model to enter the specified working mode through the transmission interface.

[0059] Step 8: The virtual sequence sends several SPI sequences according to different JESD204B working modes. The SPI transactions are transmitted to the SPI driver through the virtual sequence generator and the sequence generator in the SPI agent. The SPI driver configures the registers of the design under test through the SPI interface, so that the design under test enters the functional mode under test.

[0060] Step 9: The virtual sequence then sends the data source sequence. Through the virtual sequence generator and the sequence generator in the data source agent, the data source transaction is transmitted to the data source driver. The data source driver generates stimulus data according to the transaction and inputs the stimulus data to the JESD204B sending model and deterministic delay measurement module through the data source interface.

[0061] Step 10: The JESD204B transmission model, according to the JESD204B transmission protocol, transforms the raw stimulus data through the transport layer, link layer, and physical layer, and outputs it to the design under test. Simultaneously, the JESD204B transmission model sends the raw stimulus data to the scoreboard via the transmission agent's monitor. At the same time, the deterministic delay measurement module detects a specific data point from the data source interface and starts counting from zero using the data clock.

[0062] Step 11: After the test design receives the serial data sent by the JESD204B transmitting model, it recovers the original stimulus data through the physical layer, link layer and transport layer according to the JESD204B transmission protocol. The recovered original stimulus data is then sent to the scoring board through the monitor of the receiving agent and simultaneously transmitted to the deterministic delay measurement module.

[0063] Step 12: In the scoreboard, after receiving data from the sending agent and receiving agent, it is stored in different queues. Then, data from the receiving agent's queue is popped first until a specific data is detected. Next, data from the sending agent's queue is popped again until the corresponding specific data is detected. Then, data from both queues is popped sequentially and compared one by one. If they are different, the simulation fails.

[0064] Step 13: In the deterministic delay measurement module, once specific data corresponding to the output of the design under test is detected, the counting stops. The counted number is the time elapsed from when the data enters the JESD204B transmission model to when the design under test outputs the data.

[0065] Step 14: Repeat steps 6 to 13 several times, keeping the same JESD204B working mode. Each time, the time measured by the deterministic delay measurement module in step 13 is compared with the time measured in the first time. If they are different, the simulation fails.

[0066] Step 15: Generate verification results and verification report based on the results of Steps 12 and 14.

[0067] Based on the functional points of the design under test (JESD204B receiver circuit), random test cases are constructed, and coverage is collected through regression testing to achieve the required coverage, thereby completing the verification.

[0068] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A JESD204B receiver circuit verification system, characterized in that, include: A virtual sequence generator is provided, which is communicatively connected to a data source agent. The data source agent is communicatively connected to a data source interface. The data source interface is communicatively connected to a transmission model and a deterministic delay measurement module, respectively. The transmission model and the deterministic delay measurement module are communicatively connected to the design under test. A sending agent, which communicates with the sending model through a sending interface; A receiving agent, which communicates with the design under test through a receiving interface; A scoring board, which is communicatively connected to both the sending agent and the receiving agent; The transmitting model is the JESD204B transmitting model, and the design under test is the JESD204B receiving circuit.

2. The JESD204B receiver circuit verification system according to claim 1, characterized in that, The data source proxy is used to receive the data source sequence generated by the virtual sequence generator according to the set test cases, and drive the data source interface to generate stimulus data according to the data source sequence; The sending agent is used to receive the sending sequence generated by the virtual sequence generator according to the set test cases, and drive the sending interface to generate a mode switching signal according to the sending sequence. The mode switching signal is used to drive the sending model to enter the set working mode. The scoring board is used to receive the incentive data obtained by the sending agent through the sending model, and to receive the output data obtained by the agent from the design under test, and to perform a consistency comparison between the incentive data and the output data. The deterministic delay measurement module is used to measure the time from when the stimulus data enters the transmission model to when it is output by the design under test.

3. The JESD204B receiver circuit verification system according to claim 2, characterized in that, It also includes a clock agent, which is communicatively connected to the virtual sequence generator and the clock interface, and the clock interface is communicatively connected to the sending model and the design under test. The clock proxy is used to receive the clock sequence generated by the virtual sequence generator according to the set test cases, and drive the clock interface to generate a clock signal according to the clock sequence. The clock signal is used to input the sending model and the design under test.

4. The JESD204B receiver circuit verification system according to claim 3, characterized in that, It also includes a sysref generation model, which is communicatively connected to the clock interface, the transmission model, and the design under test. The sysref generation model is used to receive the clock signal output from the clock interface and generate a sysref signal with a set period according to the set working mode. The sysref signal is used to input the transmission model and the design under test.

5. The JESD204B receiver circuit verification system according to claim 2, characterized in that, It also includes a reset agent, which is communicatively connected to the virtual sequence generator and the reset interface, and the reset interface is communicatively connected to the sending model and the design under test. The reset agent is used to receive the reset sequence generated by the virtual sequence generator according to the set test cases, and drive the reset interface to generate a reset signal according to the reset sequence. The reset signal is used to input the sending model and the design to be tested.

6. The JESD204B receiver circuit verification system according to claim 2, characterized in that, It also includes an SPI agent, which is communicatively connected to the virtual sequence generator and the SPI interface, and the SPI interface is communicatively connected to the design under test. The SPI agent is used to receive the SPI sequence generated by the virtual sequence generator according to the set test cases, and drive the SPI interface to generate a start signal according to the SPI sequence. The start signal is used to input the design under test and cause the design under test to enter the functional mode to be tested.

7. The JESD204B receiver circuit verification system according to claim 2, characterized in that, At least one test case must be prepared based on the function to be tested.

8. The JESD204B receiver circuit verification system according to claim 2, characterized in that, The sending agent includes a sequence generator, a driver, and a monitor, and the receiving agent includes a monitor.

9. The JESD204B receiver circuit verification system according to claim 1, characterized in that, The system is built on UVM.

10. A verification method for a JESD204B receiver circuit, characterized in that, Based on the JESD204B receiver circuit verification system according to any one of claims 1 to 9, the method includes: Select test cases based on the verification requirements; The virtual sequence generator generates a data source sequence and a transmission sequence based on the selected test cases; The data source agent receives the data source sequence and drives the data source interface to generate stimulus data according to the data source sequence. The stimulus data is simultaneously input into the transmission model and the deterministic delay measurement module. The sending agent receives the sending sequence and drives the sending interface to generate a mode switching signal based on the sending sequence, which is used to drive the sending model to enter the set working mode; at the same time, it obtains the stimulus data through the sending model and sends the stimulus data to the scoreboard. The receiving agent obtains the output data of the design to be tested through the receiving interface and sends it to the scoreboard; The scoring board performs a consistency comparison between the received stimulus data and the output data of the design under test; The deterministic delay measurement module measures the time from when the stimulus data enters the transmission model to when it is output by the design under test.

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