A high-speed high-precision digital-to-analog converter applied to a radio frequency direct transmitting end

Abstract

The application discloses a high-speed and high-precision digital-to-analog converter applied to a radio frequency direct transmitting end and belongs to the technical field of integrated circuits.The digital-to-analog converter comprises a clock module, an SPI module, a bias module, a high-speed Serdes interface, a digital signal processor (DSP) and a DAC core.The DAC core comprises a DEM decoding circuit, a parallel-serial conversion circuit, a random switch coding circuit and a four-switch driving circuit.The DEM dynamic matching decoding, the multi-mode parallel-serial conversion and the random four-switch driving technology are used to effectively inhibit the harmonic distortion caused by the current source mismatch nonlinearity and the switch non-ideal effect, to realize the high-precision and high-signal-to-noise-and-distortion ratio (SFDR) requirement, and to design three working modes of NRZ, MixMode and 2*NRZ for flexible switching, support 16 times of digital clock sampling rate output, and meet the core requirements of the radio frequency direct transmitting system on high speed, high precision, high SFDR and wide bandwidth.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter. Background Technology

[0002] Digital-to-analog converters (DACs), with their ability to convert digital signals into analog signals, have become key components for driving various precision devices and generating radio frequency front-end signals in complex signal paths. Therefore, they are widely used in many fields such as optoelectronic detection systems, radar systems, electronic warfare applications, quantum computing technology, measuring instruments, and wireless communication.

[0003] With the continuous advancement of integrated circuit technology, the demand for high-speed, high-precision DAC chips in various systems is increasing, and the performance of analog devices is gradually becoming a key limiting factor affecting the overall system performance improvement. Therefore, in-depth research into the key technologies of high-speed, high-precision digital-to-analog converters (DACs) to improve DAC performance and bandwidth is of profound significance. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a high-speed, high-precision digital-to-analog converter for use in direct radio frequency (RF) transmitters. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a high-speed, high-precision digital-to-analog converter for use in a direct radio frequency transmitter, comprising: Clock module, SPI module, bias module, high-speed SerDes interface, digital signal processor (DSP) and DAC core; among which, The clock module is used to perform frequency division processing on the external input clock signal and output the corresponding clock signal to the high-speed SerDes interface, digital signal processor (DSP) and DAC core. The SPI module is used to control the operating mode of the digital-to-analog converter; The bias module is used to generate temperature-independent current and bias voltage to the high-speed SerDes interface and DAC core. The high-speed SerDes interface is used to receive quadrature I and Q data of digital signals under the control of the clock module, and to transmit the status information back to the digital signal processor (DSP) through the LVDS interface as the data input of the DSP. The digital signal processor (DSP) is used to perform interpolation and mixing processing on its own data input under the control of the clock module, and output transformed parallel data. The DAC core, under the control of the clock module, performs digital-to-analog conversion on the transformed parallel data through DEM dynamic matching decoding, multi-mode parallel-to-serial conversion, and randomized four-switch drive processing, and outputs the corresponding digital-to-analog conversion result.

[0005] In one embodiment of the present invention, the clock module includes: Clock receiver and clock divider; among which, The clock receiver is used to receive external input clock signals; The clock divider is used to divide the external input clock signal to generate a corresponding clock signal to the high-speed SerDes interface, digital signal processor (DSP), and DAC core.

[0006] In one embodiment of the present invention, the DAC core includes: The circuit includes a DEM decoding circuit, a parallel-to-serial conversion circuit, a random switch encoding circuit, and a four-switch drive circuit; among which... The DEM decoding circuit is used to perform format conversion and randomization processing on the parallel data output by the digital signal processor (DSP) to obtain low-speed parallel data. The parallel-to-serial conversion circuit is used to convert low-speed parallel data into high-speed serial data. The random switch encoding circuit is used to process high-speed serial data according to randomized four-switch control logic and output corresponding control signals. The four-switch drive circuit is used to output a current signal based on the control signal and the bias voltage output by the bias module, and after conversion by the load resistor, output the corresponding analog voltage as the result of digital-to-analog conversion.

[0007] In one embodiment of the present invention, during the randomization process, dynamic coding matching technology is used to randomly select the current source of the thermometer code, thereby reducing the nonlinear effects caused by current source mismatch in the thermometer code.

[0008] In one embodiment of the present invention, the parallel-to-serial conversion circuit includes: Two sets of 8-channel to 1-channel parallel-to-serial conversion modules; Each parallel-to-serial conversion module contains 31 parallel-to-serial conversion units.

[0009] In one embodiment of the present invention, the operating mode of the digital-to-analog converter includes: NRZ mode, Mix-Mode mode, and 2×NRZ mode; In NRZ mode, the two parallel-to-serial conversion modules output the same data; In Mix-Mode, the data output by the two parallel-to-serial conversion modules are the same, but with opposite signs. In 2×NRZ mode, the two parallel-to-serial conversion modules output two parallel data streams.

[0010] In one embodiment of the present invention, the process by which the random switch encoding circuit processes high-speed serial data according to randomized four-switch control logic and outputs corresponding control signals includes: High-speed serial data output from parallel-to-serial conversion circuit DoutA and DoutB Synchronization is achieved through DFF flip-flops and the signals are converted into differential signals. , , and ; For differential signals , , and The random code corresponding to the clock signal is ANDed with the corresponding control logic; DoutA The corresponding control logic passes through two stages of latches to obtain the A-channel latch signal; DoutB The corresponding control logic passes through a three-stage latch to obtain the B-channel latch signal; The A-channel latch signal and the B-channel latch signal are combined by a selector to obtain four pairs of complementary control signals.

[0011] In one embodiment of the present invention, there is a phase difference of half a sampling clock cycle between the A-channel latch signal and the B-channel latch signal.

[0012] In one embodiment of the present invention, the four-switch driving circuit includes: MOSFETs M1, M2, M3, M4, M5, and M6; among them, The source of the MOS transistor M1 is connected to the power supply voltage, and the gate is connected to the second bias voltage V. B1 The drain is connected to the source of the MOS transistor M2; The gate of the MOS transistor M2 is connected to a first bias voltage V. B0 The drain is connected to the source of MOS transistor M3, the source of MOS transistor M4, the source of MOS transistor M5, and the source of MOS transistor M6, respectively. The gate of the MOS transistor M3 is connected to the first control signal output by the random switch encoding circuit, and the drain of the MOS transistor M5 and the drain of the MOS transistor M5 serve as the first output terminal of the parallel-to-serial conversion circuit. The gate of the MOS transistor M4 is connected to the second control signal output by the random switch encoding circuit, and the drain of the MOS transistor M6 and the drain of the MOS transistor M6 serve as the second output terminal of the parallel-to-serial conversion circuit. The gate of the MOS transistor M5 is connected to the third control signal output by the random switch encoding circuit. The gate of the MOS transistor M6 is connected to the fourth control signal output by the random switch encoding circuit.

[0013] In one embodiment of the present invention, the DAC core adopts a segmented structure, wherein the high-order bits are encoded using thermometer encoding and the low-order bits are encoded using binary encoding.

[0014] The beneficial effects of this invention are: The solution provided by this invention effectively suppresses harmonic distortion introduced by current source mismatch nonlinearity and switching non-ideal effects through DEM dynamic matching decoding, multi-mode parallel-to-serial conversion, and randomized four-switch driving technology, achieving the requirements of high precision and high spurious-free dynamic range. Furthermore, NRZ and Mix are designed. With flexible switching between three working modes—Mode and 2×NRZ—and support for up to 16 times the digital clock sampling rate output, it fully meets the core requirements of RF direct transmission systems for high speed, high precision, high SFDR, and wide bandwidth. It breaks through the performance bottleneck of traditional DACs in high-speed RF applications and provides high-performance digital-to-analog conversion solutions for fields such as radar, wireless communication, and precision measurement. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating the principle of a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the principle of a DAC core in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter, provided in an embodiment of the present invention. Figures 3a-3b A comparison diagram of different decoding methods in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter, provided as an embodiment of the present invention; Figure 4 This invention provides a signal transmission path diagram for a DEM thermometer decoding to parallel-to-serial conversion circuit in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter. Figure 5 The schematic diagram of a random switching encoding circuit in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter is provided in an embodiment of the present invention. Figure 6 The schematic diagram of a four-switch drive circuit in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter is provided in an embodiment of the present invention. Figure 7 This is a timing diagram of control signals in a high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter, provided as an embodiment of the present invention. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0017] This invention provides a high-speed, high-precision digital-to-analog converter for use in direct radio frequency transmitters, such as... Figure 1 As shown, it may include: Clock module, SPI module, bias module, high-speed SerDes interface, digital signal processor (DSP) and DAC core; among which, The clock module is used to divide the external input clock signal and output the corresponding clock signal to the high-speed SerDes interface, digital signal processor (DSP), and DAC core. The SPI module is used to control the operating mode of the digital-to-analog converter. Bias module, used to generate temperature-independent current and bias voltage to the high-speed SerDes interface and DAC core; The high-speed SerDes interface is used to receive quadrature I and Q data of digital signals under the control of the clock module, and to transmit the status information back to the digital signal processor (DSP) via the LVDS interface as the data input of the DSP. A digital signal processor (DSP) is used, under the control of a clock module, to perform interpolation and mixing on its own data input and output transformed parallel data. The DAC core, under the control of the clock module, performs digital-to-analog conversion on the transformed parallel data through DEM dynamic matching decoding, multi-mode parallel-to-serial conversion, and randomized four-switch drive processing, and outputs the corresponding digital-to-analog conversion result.

[0018] A clock module may include: Clock receiver and clock divider; among which, A clock receiver is used to receive external input clock signals. A clock divider is used to divide an external input clock signal to generate a corresponding clock signal for the high-speed SerDes interface, digital signal processor (DSP), and DAC core.

[0019] The clock module is responsible for receiving high-speed clock signals from external input and performing frequency division to meet the requirements of the high-speed SerDes interface, digital signal processor, and DAC core. The highest external clock frequency is Fclk. After processing by the frequency divider, a four-phase half-rate clock is generated to supply the high-speed SerDes interface, and an independent half-rate clock is transmitted to the DAC core. In terms of chip control, this embodiment of the invention uses an SPI module to control the chip's operating state. Compared to I... 2The C module and the SPI module operate at higher frequencies, with peak frequencies reaching 50MHz, and can flexibly adjust each control bit independently based on the address of each register. This feature makes the SPI module a more convenient operating method when using chips with a large number of control bits.

[0020] On the bias path, a bandgap reference generates a reference voltage, which, combined with an LDO and external resistors, yields temperature-independent current and bias voltage, providing power to the high-speed SerDes interface and the DAC core. A sub-DAC is integrated within the bias module to adjust the DAC's output current.

[0021] In the data transmission path, this embodiment of the invention employs a dual-channel high-speed SerDes interface to receive orthogonal I and Q data respectively, and transmits status information back to the SerDes transmitter of the FPGA through two pairs of LVDS interfaces to ensure accurate data transmission. The received data is input to a digital signal processor for signal interpolation and mixing, ultimately outputting 16 parallel data channels. A parallel-to-serial converter then converts the data into a high-speed signal for input to the DAC core.

[0022] DAC core, such as Figure 2 As shown, it may include: The circuit includes a DEM decoding circuit, a parallel-to-serial conversion circuit, a random switch encoding circuit, and a four-switch drive circuit; among which... The DEM decoding circuit is used to perform format conversion and randomization processing on the parallel data output by the digital signal processor (DSP) to obtain low-speed parallel data. Parallel-to-serial conversion circuit is used to convert low-speed parallel data into high-speed serial data. The randomized switch encoding circuit is used to process high-speed serial data according to the randomized four-switch control logic and output corresponding control signals. The four-switch drive circuit is used to output a current signal based on the control signal and the bias voltage output by the bias module. After conversion by the load resistor, the corresponding analog voltage is output as the result of digital-to-analog conversion.

[0023] The DAC core can adopt a segmented structure, where the high-order bits use thermometer encoding and the low-order bits use binary encoding. During operation, the DAC core receives data from the digital signal processor and converts the binary code to thermometer code using a DEM decoding circuit. During this conversion, the DEM decoding circuit also randomizes the current units of the thermometer code to improve the overall performance of the DAC. In this randomization process, dynamic encoding matching technology is used to randomly select the current source of the thermometer code, reducing the nonlinear effects caused by current source mismatch in the thermometer code. This embodiment of the invention replaces the traditional binary-to-thermometer code circuit with a DEM decoding circuit. DEM, as a technique for eliminating offset noise in digital signal processing, converts nonlinear distortion caused by component mismatch into pseudo-random noise by adding scrambling elements to the digital-to-analog converter, thereby improving system performance. The DEM decoding circuit can reduce the errors generated by the digital-to-analog converter network and improve harmonic distortion.

[0024] A comparison chart of different decoding methods, such as... Figures 3a-3b As shown, where, Figure 3a This is a decoding diagram for a traditional thermometer. Figure 3b The image shows the DEM thermometer decoding diagram. Dynamic Code Matching (DEM) technology randomly selects the current source for the thermometer code, reducing the nonlinear effects caused by current source mismatch in the thermometer code. Since the current magnitudes of the current sources corresponding to the thermometer code are the same, there are multiple different combinations of current sources for a fixed input. In each working clock cycle, different combinations of current sources for the thermometer code are selected through a pseudo-random code, thus achieving randomization of the thermometer code.

[0025] Taking a 3-bit DAC as an example, its input signals are B2 to B0, corresponding to seven current sources C7 to C1. Assume that a series of input signals for the DAC over five clock cycles is 110, 011, 111, 100, 110. For traditional thermometer decoding, the relationship between the current sources and the input signals is fixed; the current source groups {C7, C6, C5, C4}, {C3, C2}, and {C1} correspond to B2, B1, and B0, respectively. For DEM thermometer decoding, the current sources are randomly selected. This randomization is achieved through rotation, including left-hand, right-hand, and bidirectional rotation. Each method achieves the same final effect. This embodiment uses right-hand rotation as an example for specific explanation. In the figure, R# represents the number of right-hand rotation steps. For a 3-bit DAC, the value of R# ranges from 0 to 7. For input numeric code 110 (R4), the current source groups {C7, C3, C2, C1}, {C6, C5}, and {C4} correspond to B2, B1, and B0 respectively, and six current sources {C7, C6, C5, C3, C2, C1} are selected; for input numeric code 011 (R5), the current source groups {C7, C6, C2, C1}, {C5, C4}, and {C3} correspond to B2, B1, and B0 respectively, and three current sources {C5, C4, C3} are selected. For input digital codes 111 and 000, all current sources are either selected or not selected. Therefore, regardless of the rightward rotation step size, the DEM thermometer decoding method is no different from the traditional thermometer decoding method. For input digital code 110 (R6), the current source groups {C7, C6, C5, C1}, {C4, C3}, and {C2} correspond to B2, B1, and B0, respectively, and six current sources {C7, C6, C5, C4, C3, C1} are selected. Compared to the digital code of the first working clock cycle, the input digital codes are the same, but the rotation step size is different, and the selected current sources are also different. In this process, the probability of each current source being selected is the same, and its selection signal is not correlated with any other signal. In this way, the mismatch error between the current sources in the thermometer code can be converted into white noise, which is represented in the spectrum as averaging the harmonics introduced by the current source mismatch onto the noise floor, thereby improving dynamic performance.

[0026] Parallel-to-serial conversion circuit, such as Figure 4 As shown, it may include: Two sets of 8-channel to 1-channel parallel-to-serial conversion modules; Each parallel-to-serial conversion module contains 31 parallel-to-serial conversion units.

[0027] The present invention designs a parallel-to-serial conversion circuit that divides 16 parallel data streams into two groups and uses two groups of 8-to-1 parallel-to-serial conversion modules to process these parallel data streams. Each group of parallel-to-serial conversion modules can contain 31 parallel-to-serial conversion units.

[0028] The operating modes of a digital-to-analog converter can include: NRZ mode, Mix-Mode mode, and 2×NRZ mode; In NRZ mode, the two parallel-to-serial conversion modules output the same data; In Mix-Mode, the data output by the two parallel-to-serial conversion modules are the same, but with opposite signs. In 2×NRZ mode, the two parallel-to-serial conversion modules output two parallel data streams.

[0029] The signal transmission path diagram of the DEM thermometer decoder to the parallel-to-serial converter circuit is as follows: Figure 4 As shown, assuming the 16 parallel data outputs from the digital signal processor are Din0, Din1, ..., Din15, and the serial data output from the parallel-to-serial converter is represented by Dout. In NRZ mode, the two parallel-to-serial modules output the same data. In this case, the first 8 and last 8 channels of the 16 data outputs from the digital signal processor are the same, i.e., Din0=Din8, Din1=Din9, ..., Din7=Din15, corresponding to a maximum DAC sampling rate of 8Fdig. In Mix-Mode mode, the data outputs from the two parallel-to-serial modules are the same but with opposite signs. In this case, among the 16 data channels, Din0=-Din8, Din1=-Din9, ..., Din7=-Din15. In 2×NRZ mode, the two parallel-to-serial modules output two parallel data channels. Compared to NRZ mode, the actual data rate processed subsequently doubles, thus achieving a maximum sampling rate of 16Fdig.

[0030] To improve the dynamic performance of the DAC, this invention proposes a random switch encoding circuit based on a four-switch structure, making the switching of the two switches in the same path random. The schematic diagram of the random switch encoding circuit is shown below. Figure 5 As shown, it can include: channel A, channel B and four 2:1 MUX multiplexers; channel A and channel B have similar structures, both including: DFF flip-flops, PRBS modules and four AND gates; the difference between the two channels is that channel A contains two-stage latches and channel B contains three-stage latches.

[0031] The process by which a randomized switch encoding circuit processes high-speed serial data according to randomized four-switch control logic and outputs corresponding control signals may include: High-speed serial data output from parallel-to-serial conversion circuit DoutA and DoutB Synchronization is achieved through DFF flip-flops and the signals are converted into differential signals. , , and ; For differential signals , , and Random code corresponding to the clock signal ( PRBSA , PRBSB Perform AND logic to obtain the corresponding control logic; the control logics are as follows: , , , , , , , ; DoutA The corresponding control logic passes through two stages of latches to obtain the A-channel latch signal; DoutB The corresponding control logic passes through a three-stage latch to obtain the B-channel latch signal; The A-channel latch signal and the B-channel latch signal are combined by a selector to obtain four pairs of complementary control signals.

[0032] The latch signals A and B have a phase difference of half a sampling clock cycle. Finally, a multiplexer combines the two latch signals A and B into a single signal, resulting in four pairs of complementary outputs used to control the switch drive circuit.

[0033] In this embodiment, the random code and the sampling clock CLK are kept synchronized. Therefore, for the same switch toggle control signals (S1 and S3, S2 and S4), the switch toggle controlled by CLK is transformed into a switch toggle controlled by the random code ( PRBSA or PRBSB The switch toggles under control. By combining the A and B control logics through a multiplexer, the switch selection is determined every half clock cycle. This means that the switching of the same path no longer follows a fixed timing sequence, but is associated with changes in the random code, transforming interference related to the digital code into interference related to the random code. Therefore, the interference introduced by the non-ideal switching effect is a randomized result, converting this interference into white noise, which manifests in the frequency spectrum as lower harmonics and higher background noise, effectively improving the dynamic performance of the DAC.

[0034] Four-switch drive circuit, such as Figure 6 As shown, it may include: MOSFETs M1, M2, M3, M4, M5, and M6; among them, The source of MOSFET M1 is connected to the power supply voltage, and the gate is connected to the second bias voltage V. B1 The drain is connected to the source of MOSFET M2; The gate of MOSFET M2 is connected to the first bias voltage V.B0 The drain is connected to the source of MOSFET M3, the source of MOSFET M4, the source of MOSFET M5, and the source of MOSFET M6, respectively. The gate of MOSFET M3 is connected to the first control signal output by the random switch encoding circuit, and the drain of MOSFET M5 and the drain of MOSFET M5 serve as the first output terminal of the parallel-to-serial conversion circuit. The gate of MOSFET M4 is connected to the second control signal output by the random switch encoding circuit, and the drain of MOSFET M6 and the drain of MOSFET M4 serve as the second output terminal of the parallel-to-serial conversion circuit. The gate of MOSFET M5 is connected to the third control signal output by the random switch encoding circuit; The gate of MOSFET M6 is connected to the fourth control signal output by the random switch encoding circuit.

[0035] Figure 6 In this embodiment, M1 and M2 are common-source, common-gate current source structures, with their gate terminals controlled by VB1 and VB0, respectively. This invention introduces two additional current switches based on traditional differential complementary switches, with one switch superimposed on each path. The output of the DAC is controlled by these two switches. The complementary input digital signals (...) DATA and ) and sampling clock signal ( CLK and Four switch control signals are obtained through NAND logic. , , and One switch is on every half clock cycle, so the DAC's output power is not lost.

[0036] Timing diagram of control signals in a high-speed, high-precision digital-to-analog converter, such as... Figure 7 As shown, for a DAC operating in NRZ mode, the switch will toggle consistently within one sampling clock cycle, even though the data remains unchanged, completing the switch state transition at the high and low levels of the clock. Therefore, the switching frequency is twice the sampling clock frequency. This method shifts relevant interference to a location twice the sampling clock frequency, placing it far above the signal bandwidth. In spectral analysis, this manifests as clutter components in the region adjacent to twice the sampling clock frequency, thus improving the DAC's dynamic characteristics.

[0037] However, when the DAC operates in 2×NRZ mode, the input digital code changes every half clock cycle, accompanied by a switch flipping. Since the switch flipping is fixed, the interference introduced by the non-ideal switching effect is the same when the same two adjacent digital codes switch within each signal cycle. This interference exhibits periodic characteristics and is closely related to the digital code, manifesting as clutter components in the vicinity of the output signal in spectral analysis, thus adversely affecting the dynamic performance of the DAC.

[0038] For DACs operating in Mix-Mode, although their interference is related to the input digital code, their input signal is usually located in the first Nyquist band, while the main output signal is located in the second and third Nyquist bands and is used after being filtered by a filter. Therefore, the impact of these interferences on the dynamic performance of the DAC can be ignored.

[0039] The high-speed, high-precision digital-to-analog converter provided in this invention effectively suppresses harmonic distortion introduced by current source mismatch nonlinearity and switching non-ideal effects through DEM dynamic matching decoding, multi-mode parallel-to-serial conversion, and randomized four-switch drive technology. This achieves the requirements of high precision and high spurious-free dynamic range, and incorporates NRZ and Mix technologies. With flexible switching between three working modes—Mode and 2×NRZ—and support for up to 16 times the digital clock sampling rate output, it fully meets the core requirements of RF direct transmission systems for high speed, high precision, high SFDR, and wide bandwidth. It breaks through the performance bottleneck of traditional DACs in high-speed RF applications and provides high-performance digital-to-analog conversion solutions for fields such as radar, wireless communication, and precision measurement.

[0040] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A high-speed, high-precision digital-to-analog converter for use in direct radio frequency transmitters, characterized in that, include: Clock module, SPI module, bias module, high-speed SerDes interface, digital signal processor (DSP) and DAC core; among which, The clock module is used to perform frequency division processing on the external input clock signal and output the corresponding clock signal to the high-speed SerDes interface, digital signal processor (DSP) and DAC core. The SPI module is used to control the operating mode of the digital-to-analog converter; The bias module is used to generate temperature-independent current and bias voltage to the high-speed SerDes interface and DAC core. The high-speed SerDes interface is used to receive quadrature I and Q data of digital signals under the control of the clock module, and to transmit the status information back to the digital signal processor (DSP) through the LVDS interface as the data input of the DSP. The digital signal processor (DSP) is used to perform interpolation and mixing processing on its own data input under the control of the clock module, and output transformed parallel data. The DAC core, under the control of the clock module, performs digital-to-analog conversion on the transformed parallel data through DEM dynamic matching decoding, multi-mode parallel-to-serial conversion, and randomized four-switch drive processing, and outputs the corresponding digital-to-analog conversion result.

2. The high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 1, characterized in that, The clock module includes: Clock receiver and clock divider; among which, The clock receiver is used to receive external input clock signals; The clock divider is used to divide the external input clock signal to generate a corresponding clock signal to the high-speed SerDes interface, digital signal processor (DSP), and DAC core.

3. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 1, characterized in that, The DAC core includes: The circuit includes a DEM decoding circuit, a parallel-to-serial conversion circuit, a random switch encoding circuit, and a four-switch drive circuit; among which... The DEM decoding circuit is used to perform format conversion and randomization processing on the parallel data output by the digital signal processor (DSP) to obtain low-speed parallel data. The parallel-to-serial conversion circuit is used to convert low-speed parallel data into high-speed serial data. The random switch encoding circuit is used to process high-speed serial data according to randomized four-switch control logic and output corresponding control signals. The four-switch drive circuit is used to output a current signal based on the control signal and the bias voltage output by the bias module, and after conversion by the load resistor, output the corresponding analog voltage as the result of digital-to-analog conversion.

4. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 3, characterized in that, During the randomization process, dynamic coding matching technology is used to randomly select the current source of the thermometer code, thereby reducing the nonlinear effects caused by current source mismatch in the thermometer code.

5. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 3, characterized in that, The parallel-to-serial conversion circuit includes: Two sets of 8-channel to 1-channel parallel-to-serial conversion modules; Each parallel-to-serial conversion module contains 31 parallel-to-serial conversion units.

6. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 5, characterized in that, The operating modes of the digital-to-analog converter include: NRZ mode, Mix-Mode mode, and 2×NRZ mode; In NRZ mode, the two parallel-to-serial conversion modules output the same data; In Mix-Mode, the data output by the two parallel-to-serial conversion modules are the same, but with opposite signs. In 2×NRZ mode, the two parallel-to-serial conversion modules output two parallel data streams.

7. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 3, characterized in that, The process by which the randomized switch encoding circuit processes high-speed serial data according to randomized four-switch control logic and outputs corresponding control signals includes: High-speed serial data output from parallel-to-serial conversion circuit DoutA and DoutB Synchronization is achieved through DFF flip-flops and the signals are converted into differential signals. , , and ; For differential signals , , and The random code corresponding to the clock signal is ANDed with the corresponding control logic; DoutA The corresponding control logic passes through two stages of latches to obtain the A-channel latch signal; DoutB The corresponding control logic passes through a three-stage latch to obtain the B-channel latch signal; The A-channel latch signal and the B-channel latch signal are combined by a selector to obtain four pairs of complementary control signals.

8. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 7, characterized in that, There is a phase difference of half a sampling clock cycle between the A-channel latch signal and the B-channel latch signal.

9. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 3, characterized in that, The four-switch drive circuit includes: MOSFETs M1, M2, M3, M4, M5, and M6; among them, The source of the MOS transistor M1 is connected to the power supply voltage, and the gate is connected to the second bias voltage V. B1 The drain is connected to the source of the MOS transistor M2; The gate of the MOS transistor M2 is connected to a first bias voltage V. B0 The drain is connected to the source of MOS transistor M3, the source of MOS transistor M4, the source of MOS transistor M5, and the source of MOS transistor M6, respectively. The gate of the MOS transistor M3 is connected to the first control signal output by the random switch encoding circuit, and the drain of the MOS transistor M5 and the drain of the MOS transistor M5 serve as the first output terminal of the parallel-to-serial conversion circuit. The gate of the MOS transistor M4 is connected to the second control signal output by the random switch encoding circuit, and the drain of the MOS transistor M6 and the drain of the MOS transistor M6 serve as the second output terminal of the parallel-to-serial conversion circuit. The gate of the MOS transistor M5 is connected to the third control signal output by the random switch encoding circuit. The gate of the MOS transistor M6 is connected to the fourth control signal output by the random switch encoding circuit.

10. A high-speed, high-precision digital-to-analog converter applied to a direct radio frequency transmitter according to claim 1, characterized in that, The DAC core adopts a segmented structure, where the high-order bits are encoded using thermometers and the low-order bits are encoded using binary.

Images