A step code encoding method for annular position detection

Abstract

The application discloses a step code encoding method for annular position detection. The method maps N logical adjacent input bit state signals into an annular closed loop logic state sequence with single state and double state alternately arranged by setting a logical adjacent effective input bit base d. The single state is that d logical adjacent input bits are simultaneously effective, and the double state is that d+1 logical adjacent input bits are simultaneously effective. The encoding method forms 2N closed loop logic states, and only one input bit state changes between adjacent logic states. The application can realize full stroke non-blind area, original fault self-diagnosis, and provides an encoding basis for subsequent position analysis, direction determination and abnormality identification.

Description

Technical Field

[0001] The present invention relates to the technical field of digital coding and position detection, and specifically relates to a Kui-step code coding method for converting an annular cyclic physical position into a digital signal, which is applicable to rotary encoders, annular position sensors, industrial control, automotive electronics, medical equipment and human-computer interaction devices. Term Definition

[0002] Kui-step code: The "Kui-step code" referred to in this application refers to a step code coding method. In this method, legal logical states include a single state and a dual state, the single state corresponds to "Kui", and the dual state corresponds to "step". The single states and the dual states are arranged alternately, and only one input bit state changes between adjacent states.

[0003] Input bit: The minimum state unit used to represent a position in the coding logic. The state of an input bit is mapped by the positional relationship, that is, whether the input bit is in a valid state or an invalid state is determined by the relative positional relationship between the physical sensing area corresponding to the position to be measured and the detection component. In physical implementation, the input bit may correspond to a mechanical contact, a Hall sensor, a photoelectric sensor, a capacitive sensor, etc.; its logical arrangement order and adjacency relationship are defined by the coding rule. The input bit responds to the change of the position to be measured and switches between the valid state and the invalid state.

[0004] Logically adjacent: It means that the input bits are adjacent in position in the coding logic sequence, and the first and last two input bits are logically adjacent to form a closed loop. In physical arrangement, the logically adjacent input bits may be arranged adjacently, or may be arranged across tracks or discretely, as long as their logical order in the coding sequence is adjacent. Based on this logically adjacent relationship, during the continuous change of the physical position, the switching of the valid states of the input bits is performed bit by bit following the logically adjacent order, so as to exclude the scenario of skipping the intermediate logically adjacent input bit and directly switching to a non-logically adjacent input bit.

[0005] Annular closed-loop logical state sequence: It refers to a logical state sequence formed by alternately arranging single states and dual states in an annular cyclic form. In this sequence, the first and last two input bits are logically adjacent, so that the last logical state and the first logical state are temporally successive to form a closed loop cycle. This sequence contains N single states and N dual states, with a total of 2N logical states, which cycle repeatedly without a fixed start point and end point; any one of the logical states can be used as the start state of the sequence, and the cycle phase of the logical state sequence is uniquely determined by the current physical position.

[0006] Logically adjacent valid input bit cardinality d: Defined as the number of valid input bits in a single state, and its value needs to satisfy d<N−1. Introducing the parameter d can adjust the number of valid bits without changing the alternate logic of single states and dual states, so as to improve design flexibility and anti-interference capability.

[0007] Single state: A state in an encoded sequence that serves as a static positioning reference. It refers to a state in which d logically adjacent input bits are simultaneously valid, while the remaining input bits are invalid. Where d=1 is a regular single state; d>1 is a generalized single state. In this application, unless otherwise specified, it is collectively referred to as "single state".

[0008] Bistate: A state in an encoded sequence that serves as a dynamic transition path. It refers to a state where d+1 logically adjacent input bits are simultaneously valid, while the remaining input bits are invalid. Where d=1 is a regular bistate; d>1 is a generalized bistate. In this application, unless otherwise specified, it is collectively referred to as "bistate".

[0009] "Switching in" refers to the process of a specific input bit changing from invalid to valid. In coding logic, switching in corresponds to the process of converting a single state to a two state; in physical motion, it represents a physical location entering the sensing area corresponding to that input bit.

[0010] Cut-out: refers to the process of switching the state of a certain input bit from valid to invalid. In coding logic, cut-out corresponds to the process of converting a two-state input to a single-state input; in physical motion, it means that the physical location moves away from the sensing area corresponding to the input bit.

[0011] Illegal state: refers to the input bit combination state other than single state and double state, including the combination of valid input bits not conforming to d or d+1, valid input bits not satisfying the logical adjacency relationship, and the state where all input bits are invalid.

[0012] Assurance State: The legal logical state that the system currently confirms it is in. During normal operation, the system uses the currently confirmed legal logical state as the assurance state, which serves as the basis for system position output and subsequent state determination. Background Technology

[0013] Absolute position encoding technology is one of the core technologies in industrial automation and precision measurement. Traditional absolute encoders, such as Gray code encoders, reduce encoding errors by changing only one bit between adjacent codewords and are widely used in position detection. However, in circular position detection scenarios, this type of encoding still has significant limitations. First, when physical motion passes through the transition area of ​​the encoded state, there is a detection blind zone, which usually requires software delay or filtering, resulting in detection latency. Second, the encoding itself does not carry direction information, requiring the storage and comparison of multiple frames of historical states to determine the direction of motion, increasing memory and computing resource overhead and limiting the real-time performance of the system. Third, traditional encoding schemes often use the entire encoding space for legal states, lacking redundancy, unable to distinguish between normal states and hardware fault states, and lacking native fault self-diagnosis capabilities.

[0014] Traditional sequential step codes, such as one-hot codes arranged in the order of 1-2-3-4-5, have detection "dead zones" between adjacent valid states due to physical separation of contacts, requiring delay filtering to avoid noise. They do not carry directional information themselves and must rely on comparison with historical states for direction determination. More seriously, a completely open contact state can be both a normal state and a fault state indicating a circuit break, and these two cannot be distinguished at the coding level, thus lacking native fault self-diagnosis capabilities.

[0015] m-sequence-based encoding schemes have also been applied in absolute position detection. However, m-sequence encoding typically requires long code channels or image recognition methods, resulting in a relatively complex encoding structure. The decoding process often relies on table lookups or sequence matching, leading to significant computational load and putting pressure on real-time performance under high-speed motion conditions. Furthermore, m-sequence encoding itself is not specifically designed for state transition blind spots, direction determination, and hardware fault self-diagnosis in ring position detection, making it difficult to directly meet the requirements of low-latency direction determination and native fault tolerance in ring position detection scenarios.

[0016] Some existing solutions utilize single-contact and double-contact states to generate position signals. While these solutions can generate a greater number of position states with fewer input bits, they are typically only used for linear or arc-shaped arrangements and do not form a closed-loop state sequence with consecutive beginnings and end. Furthermore, these solutions do not utilize the redundancy space between valid and invalid states for fault self-diagnosis. Some solutions even treat a state where all input bits are invalid as a valid state, making it impossible to distinguish between normal position intervals and hardware faults such as line breaks.

[0017] The aforementioned defects all stem from the coding rules themselves, rather than being fundamentally solved by simply improving manufacturing precision or adding filtering algorithms. The industry needs a dedicated coding rule for ring position detection scenarios that can simultaneously address issues such as over-detection blind spots, direction determination delays, and the lack of fault self-diagnosis at the coding level. Summary of the Invention

[0018] This invention provides a step-code encoding method. The core scheme is as follows: N sequentially arranged input bits are set, and a base number d of logically adjacent valid input bits is introduced to construct a circular closed-loop logic state sequence with alternating single-state and double-state states. Here, a single state corresponds to "step," meaning d logically adjacent input bits are valid; a double state corresponds to "step," meaning d+1 logically adjacent input bits are valid. Adjacent state switching involves only a single input bit change, forming a seamless, continuous motion trajectory.

[0019] This invention features native blind-zone-free characteristics. A single state serves as the static positioning reference, while a dual state acts as the dynamic transition path, with the two overlapping and covering each other in physical space. In the state transition region, the end time of the previous state is the start time of the next state, eliminating the detection blind zone caused by physical gaps in traditional encoding. Continuous, real-time position detection can be achieved without relying on software delay filtering.

[0020] This invention provides real-time direction determination capability. Based on the alternating pattern of single-state and dual-state states, the system can directly determine the motion direction solely based on the logical relationship between the current sampled state and the confirmed state: if the current sampled state is dual-state and contains the current confirmed single-state, an exit is determined, and the exit bit indicates the departure direction; if the current confirmed state is single-state, and the sampled state is a dual-state containing the valid bit of that single-state, an entry is determined, and the entry bit indicates the motion direction. This process eliminates the need to store multiple frames of historical states, significantly reducing memory overhead and improving system response speed.

[0021] This invention possesses native fault self-diagnosis and fault tolerance capabilities. At the encoding rule level, legal logical states only include single-state and double-state states; other combinations are considered illegal states. In particular, a state where all input bits are invalid is defined as illegal, which can be used to identify hardware faults such as open circuits, disconnected common terminals, or abnormal power supply.

[0022] This invention also possesses the capability to identify single-point anomalies. When a single-point anomaly occurs in the sampling state, the system can identify the unexpected isolated anomaly based on the alternating pattern of single-state and dual-state operation.

[0023] Furthermore, this invention can flexibly adapt to different application scenarios by adjusting the base d. When d=1, it corresponds to the most basic sliding window structure; when d>1, the increase in the number of effective input bits improves the signal-to-noise ratio and the system's anti-interference capability, achieving a balance between flexibility and robustness in coding design. Beneficial technical effects

[0024] 1. Generalized radix of adjacent valid input bits: By introducing the parameter d, the encoding rules of the step code can be applied to different adjacent valid input bits. The same single-state / double-state alternating logic structure is maintained under different d values, increasing the degree of design freedom.

[0025] 2. Zero blind spots throughout the entire stroke, fundamentally eliminating detection dead zones. By incorporating dual states (transition states) into the legal coding system, each point on the physical motion trajectory has a unique legal logical state corresponding to it. This fundamentally eliminates the detection blind spots caused by physical gaps or signal uncertainties in the transition area between adjacent code tracks in traditional encoders. It eliminates the need for software delay filtering or complex hardware compensation circuits, achieving zero-delay and continuous position detection.

[0026] 3. Native real-time orientation determination significantly reduces computational resource overhead. Based on the characteristic that only one bit changes between adjacent states in the coded sequence, the system can determine the motion direction within a single sampling period solely based on the logical relationship between the current sampled state and the confirmed state, eliminating the need to store and compare multiple frames of historical data as in traditional solutions. This feature greatly reduces the demand on controller memory and computing power, significantly improving the system's response speed and real-time performance, making it particularly suitable for high-speed motion control scenarios.

[0027] 4. Possesses native fault self-diagnosis capabilities, enhancing inherent system security. By clearly distinguishing between legal and illegal states, the system is endowed with "self-reflection" capabilities. In particular, defining the "completely invalid" state as illegal allows the system to instantly identify serious hardware faults such as open circuits, disconnected common terminals, or power supply failures without requiring any additional detection circuitry. This enables proactive reporting and rapid fault location, significantly improving system maintainability and security.

[0028] 5. Supports single-point anomaly identification and fault tolerance, resulting in more reliable operation. Under the condition of synchronously acquiring the independent state of each input bit, the system can utilize strict logical constraints of alternating single-state and double-state operations to identify isolated abnormal bits (single-point faults) in the sampled data. In the event of non-fatal interference, the system can maintain the correctness of the position output and output specific abnormal bit indications, achieving a leap from 'passive fault tolerance' to 'active early warning'.

[0029] 6. The hardware architecture is extremely simple, reducing design and manufacturing costs. The input bits only need to be arranged sequentially, and non-power-of-two bits (such as 10-bit and 12-bit bits) do not require complex code path adaptation as in traditional binary encoding. This encoding scheme perfectly adapts to the ring closed-loop structure, simplifying the design of the code disk and the difficulty of PCB routing, and effectively reducing hardware costs and assembly complexity. Attached Figure Description Figure 1 When N=6 and d=1, the circular structure diagram of the step code encoding method of the present invention shows the circular arrangement of the input bits, the distribution of single-state and double-state regions, and the logical adjacency relationship, which intuitively reflects the characteristics of the closed-loop logic state sequence. Figure 2 For N=6, d=1, the truth table corresponding to each input bit and the state number; Figure 3 For N=6 and d=2, the truth table corresponds to each input bit and the state number. Detailed Implementation Example 1: Circular loop pattern with d=1 (N=6)

[0030] Set N=6, d=1. A single state requires one consecutive input bit to be valid, and a double state requires two consecutive input bits to be valid. The state sequence is as follows: Bit 1 valid → Bits 1 and 2 valid simultaneously → Bit 2 valid → Bits 2 and 3 valid simultaneously → Bit 3 valid → Bits 3 and 4 valid simultaneously → Bit 4 valid → Bits 4 and 5 valid simultaneously → Bit 5 valid → Bits 5 and 6 valid simultaneously → Bit 6 valid → Bits 6 and 1 valid simultaneously → Back to Bit 1 valid.

[0031] There are a total of 6 single-state and 6 double-state states, for a total of 2N=12 states, which are connected end to end to form a closed loop. Among them, the closed-loop double state (bits 6 and 1 are valid at the same time) is an inherent logical state naturally derived from the closed-loop structure of the encoded sequence. It can be directly used as a stable absolute position position, so that N input bits can provide up to 2N absolute position positions. Example 2: Circular loop pattern with d=2 (N=6)

[0032] Set N=6 and d=2. A singlet state requires two consecutive input bits to be valid, and a doublet state requires three consecutive input bits to be valid. The state sequence is as follows: Bits 1 and 2 are valid → Bits 1, 2, and 3 are valid → Bits 2 and 3 are valid → Bits 2, 3, and 4 are valid → Bits 3 and 4 are valid → Bits 3, 4, and 5 are valid → Bits 4 and 5 are valid → Bits 4, 5, and 6 are valid → Bits 5 and 6 are valid → Bits 5, 6, and 1 are valid → Bits 6 and 1 are valid → Bits 6, 1, and 2 are valid → Back to bits 1 and 2 being valid.

[0033] There are a total of 6 single-state and 6 double-state states, for a total of 2N=12 states. The d=2 system is identical to the d=1 system in terms of logic structure, with only the number of effective input bits changing. The system's noise immunity is improved by increasing the effective bit width. Example 3: Implementation of the equivalent straight line in a circular loop shape

[0034] In an equivalent implementation, the N input bits are physically arranged in a straight line, but the first and last input bits are logically defined as adjacent, forming a logical loop. This implementation is equivalent to a circular loop configuration, with a state sequence containing N single states and N double states, for a total of 2N logical states. For example, when N=6 and d=1, the input bits are physically arranged in a straight line from bit 1 to bit 6, but logically bit 6 is adjacent to bit 1. Its state sequence is completely consistent with that of Embodiment 1. This implementation achieves the bit density of a circular encoding under a linear physical layout while maintaining the convenience of linear installation. Example 4: General Decoding and Real-time Direction Determination Process

[0035] After the system is powered on, it synchronously samples all N input bits to obtain the sampling status. If the sampling status is valid, it sets the sampling status as the current confirmed status; if the sampling status is invalid, it continues to sample until a valid status is obtained, then sets it as the current confirmed status, or triggers a fault alarm according to preset conditions.

[0036] During operation, the system acquires the sampling status through periodic scanning or interrupt triggering. When the sampled status is valid and differs from the currently confirmed status, the following decision and update logic is executed: If the current confidence state is a single state, and the sampled state is a double state containing the valid bit of the single state, then a cut-in is determined to have occurred; the cut-in bit indicates the side where the movement has arrived, and the confidence state is updated to the double state; If the current confidence state is a dual state and the sampled state is a single state contained within the range of the dual state, then a cut-out is determined to have occurred; the cut-out bit indicates the movement leaving the side, and the confidence state is updated to the single state.

[0037] This process only needs to identify the cut-in or cut-out event to complete the direction determination and position update within a single sampling period, without needing to query historical data. Example 5: Fault Diagnosis, Anomaly Identification, and Single-Point Error Correction

[0038] Valid states include only single-state and double-state states. If the number of valid input bits in the sampled state is not equal to d and not equal to d+1, or if the valid input bits do not satisfy the logical adjacency relationship, then it is determined to be an illegal state. For illegal states other than "all invalid", the system can maintain the current confirmed state, refuse to update the position output, and trigger an abnormal alarm.

[0039] For single-point anomaly correction: When an isolated valid input bit is detected in the sampling state (i.e., this bit is not adjacent to the other valid bits), but after removing the abnormal bit, the remaining valid bits form a valid single or double state, and this valid state meets the logical adjacency expectation of the previous confident state, the system can determine that the bit is a single-point interference and perform an error correction operation: update the valid state after removing the abnormal bit to the confident state, and output the abnormal bit indication. For example, in a system with d=1 and N=6, the confident state is a double state, i.e., "bits 1 and 2 are valid", and the sampling state is "bits 2 and 5 are valid". The system identifies "bit 5" as an isolated abnormal bit, determines "bit 2 is valid" as the correct state, and can perform an error correction update.

[0040] Special diagnosis for all invalid states: When the sampling state is that all input bits are invalid, the system can determine that it is a hardware fault (such as a broken circuit or loss of power supply), lock the current output position and report a serious fault code, and do not perform error correction.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A step code encoding method for ring position detection, characterized in that, comprising: acquiring status signals of N sequentially arranged input bits; wherein the input bits switch between a valid state and an invalid state in response to a physical position change; Adjacent input bits have a preset logical adjacency relationship, and the first and last input bits are logically adjacent, forming a logical closed loop of input bits; the logical adjacency refers to the positional adjacency relationship of the input bits in the coding logic sequence, and is independent of the actual arrangement manner of the input bits in the physical space; setting a cardinality d of logically adjacent valid input bits, wherein d is a positive integer; wherein the singlet state is a state in which d logically adjacent input bits are valid at the same time and the remaining input bits are invalid; the doublet state is a state in which d+1 logically adjacent input bits are valid at the same time and the remaining input bits are invalid; wherein N>2 and d<N−1, the status signals are mapped to a logical state sequence composed of singlet states and doublet states arranged alternately, the logical state sequence includes N singlet states and N doublet states, for a total of 2N logical states, and when switching from one logical state to the next logical state, only the status of one input bit changes.

2. The step code encoding method according to claim 1, characterized in that, d=1。 3. The step code encoding method according to claim 1, characterized in that, d=2, and N>3.

4. The step code encoding method according to claim 1, characterized in that, The input bits include contact position detection units or non-contact position detection units.

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