An LDPC deep neural network decoding method and system against power amplifier nonlinearity

Abstract

The application provides an LDPC deep neural network decoding method and system for anti-power amplifier nonlinearity, which inputs initial soft information obtained by soft demodulation of a received signal into a trained deep neural network, and outputs a decoded signal. The construction process of the deep neural network comprises the following steps: defining an extrinsic information processing unit based on non-zero elements of a check matrix, constructing a row and column adjacency list; configuring an input layer interface; building a learnable hidden layer, constructing an odd layer module with weighted summation and an activation function by using the column adjacency list, constructing an even layer module with an aggregation operator by using the row adjacency list, and alternately stacking the two to form a deep structure; and constructing an output layer aggregation logic. The application can effectively reduce the bit error rate under the power amplifier nonlinearity channel, reduce the power input backoff requirement, and improve the efficiency of the on-board power amplifier.

Description

Technical Field

[0001] This application belongs to the fields of satellite communication, radio communication, and channel coding and decoding, and specifically relates to an LDPC deep neural network decoding method and system that is resistant to power amplifier nonlinearity. Background Technology

[0002] Channel coding and decoding can eliminate bit errors caused by symbol decision, reduce the bit error rate, and improve the reliability of communication links. Currently, LDPC codes, with their near-Shannon limit performance and inherent high-speed parallelism, are widely used in satellite communication (such as DVB-S2 / S2X), terrestrial mobile communication (5G-NR), and spacecraft telemetry, tracking, and command (CCSDS) systems, becoming the most representative channel coding and decoding methods.

[0003] In satellite communication and spacecraft telemetry and control systems, high-order modulation is generally used in space-to-ground communication links to improve data transmission rates and spectral efficiency in bandwidth-constrained scenarios. High-order modulation waveforms require higher energy to maintain reliable symbol decision-making, necessitating increased signal transmission power to achieve the required signal-to-noise ratio. Furthermore, due to the large peak-to-average power ratio (PAPR) of high-order modulation waveforms, they are highly sensitive to power amplifier nonlinearity, easily generating amplitude and phase distortion. This leads to numerous errors in symbol decision-making at the receiver. These errors caused by power amplifier nonlinearity distortion are not random and do not conform to the characteristics of additive white Gaussian noise. Existing LDPC codes are designed based on the assumption of an additive white Gaussian noise channel, making them insufficiently adaptable to these types of errors and unable to effectively reduce the additional errors caused by power amplifier nonlinearity distortion. Therefore, high-order modulation typically requires greater backoff to ensure the power amplifier operates in the linear region, resulting in extremely low power conversion efficiency. The conditions for enabling high-order modulation are extremely stringent, which is why high-order modulation is rarely used in existing satellite communication systems and space-to-ground telemetry data transmission systems. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of existing LDPC decoding, which is unable to overcome the additional bit errors caused by high-order modulation in spaceborne TWTA nonlinear channels.

[0005] To achieve the above objectives, this application proposes a deep neural network decoding method for LDPC that is resistant to power amplifier nonlinearity, comprising: The received signal is softly demodulated to obtain initial soft information, which is then input into a trained deep neural network to output the decoded signal. The construction process of the deep neural network includes: Read the parity-check matrix of the LDPC code, and count the positions of all non-zero elements in the matrix in row-major order; define each non-zero element as an external information processing unit, i.e., a neuron node in a deep neural network; construct column adjacency lists and row adjacency lists; Configure the network input layer interface; Constructing a learnable hidden layer for the network includes: Constructing an odd-layer module: Using a column adjacency list, connect the current layer node to the previous layer node; set learnable weights on the inter-layer message connection and the original channel soft information input branch, perform weighted aggregation on the original channel soft information and the previous layer adjacency messages, and concatenate an activation function. ; Construct even-level modules: Use row adjacency lists to connect the current level nodes with the previous level nodes, and define aggregation operators in this level; The odd-numbered and even-numbered layer modules are stacked alternately multiple times, so that the output of the previous layer is connected to the input index of the next layer, forming a deep network structure. Construct the aggregation logic for the network output layer.

[0006] The construction of the column adjacency list and the row adjacency list includes: Traverse each column of the check matrix, record the index of the external information processing unit corresponding to all non-zero elements in that column, and establish directed connections between different processing units to form a column adjacency list; Traverse each row of the check matrix, record the index of the external information processing unit corresponding to all non-zero elements in that row, and establish directed connections between different processing units to form a row adjacency list.

[0007] The processing unit itself is excluded during the construction process to satisfy the principle of external information transmission in BP decoding.

[0008] Both the column adjacency list and the row adjacency list use "external information". The data is represented in the form of "target external information". Its internal data is the index of the external information processing unit, that is, the first row is the source index and the second row is the target index. It is sorted in ascending order of the source index first. If the source indexes are the same, it is sorted in ascending order of the target index.

[0009] As an improvement to the above method, the configuration of the network input layer interface includes: create n One input node, n The number of variable nodes; The first The value of the input node is copied and concatenated to all nodes belonging to the first hidden layer. j On the neurons of the column.

[0010] In the odd-numbered layer module, the current layer node simultaneously receives the output of the previous layer node and the original channel soft information of the corresponding variable node. The current layer node and the previous layer node are connected by a column adjacency list, that is, a connection is established when two nodes correspond to different non-zero elements in the same column of the parity check matrix. The original channel soft information is mapped to the current layer node corresponding to all non-zero elements in that column. In the even-numbered layer module, the current layer node and the previous layer node are connected by a row adjacency list, that is, a connection is established when two nodes correspond to different non-zero elements in the same row of the parity check matrix.

[0011] The aggregation operator is: First, perform a product operation on the input, then concatenate a... Activation function.

[0012] As an improvement to the above method, the aggregation logic for constructing the network output layer includes: create n One output node, n The number of variable nodes; The first The output node is connected to all nodes belonging to the last hidden layer. j The neurons in the column; A summation operator is added after each hidden layer neuron, and the original input is fused to form the final decision value.

[0013] The training process of the deep neural network includes: The transmitter randomly generates a sequence of information bits, which is then channel-coded and mapped to codeword bits. After modulation mapping, a complex baseband transmission symbol is obtained, which is then transmitted through a nonlinear channel. During network training, the SNR is randomly sampled within a given range and extended to each modulation symbol at the symbol level to enhance the model's adaptability to different channel conditions. The receiving end performs soft demodulation on the received signal to obtain initial soft information, which is then fed into a deep neural network to train and output posterior soft information before making a hard decision.

[0014] This application also provides an LDPC deep neural network decoding system that resists power amplifier nonlinearity, for implementing the above method, the system comprising: The decoding module is used to perform soft demodulation on the received signal to obtain initial soft information, which is then input into a trained deep neural network and outputs the decoded signal.

[0015] Compared with existing technologies, the advantages of this application are: The decoding method of this application can reduce the bit error rate in the nonlinear channel of the power amplifier, reduce the power input back-off requirement, and improve the efficiency of the on-board power amplifier. Attached Figure Description

[0016] Figure 1 The diagram shows the Tanner plot for the backpropagation (BP) algorithm; the plot includes 4 iterations. This constitutes one complete iteration; Figure 2 The image shows the adjacency list for the BP algorithm. Figure 1 Transformation format of Tanner graph, iterated 4 times, odd-numbered layers correspond to Even-numbered layers correspond to The odd-numbered layers are connected to the next even-numbered layers by row adjacency list. Connections are made between even-numbered layers and the next odd-numbered layer using a column adjacency list. Connect the dots; Figure 3 The diagram shown is of a backpropagation (BP) neural network; the leftmost layer is the input layer, the rightmost layer is the output layer, and all the layers in the middle are hidden layers. tanh + arctanh represents one iteration. Figure 4 The figure shows the BER value of WiFi standard 64QAM modulation + 1 / 2LDPC code (648 information bits); where the blue circle line is the AWGN-BP decoding result, the solid line is the TWTA-BP decoding result, and the dotted line is the TWTA-DNN decoding result. Figure 5 The image shows the TD values ​​of WiFi standard 64QAM modulation + 1 / 2LDPC code (648 information bits); where the blue line is the TWTA-BP decoded TD value and the orange line is the TWTA-DNN decoded TD value. Figure 6 The figure shows the BER values ​​of CCSDS standard 64APSK modulation + 1 / 2AR4JA code (information bit length 1024); where the blue circle line is the AWGN-BP decoding result, the solid line is the TWTA-BP decoding result, and the dashed line is the TWTA-DNN decoding result. Figure 7 The figure shows the TD values ​​of the CCSDS standard 64APSK modulation + 1 / 2AR4JA code (information bit length 1024); among them, the blue line is the TD value of TWTA-BP decoding, and the orange line is the TD value of TWTA-DNN decoding. Detailed Implementation

[0017] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0018] This application proposes an LDPC deep neural network decoding method to combat power amplifier nonlinearity. By expanding the BP iterative decoding process into a non-fully connected deep neural network, and training it on a power amplifier nonlinear channel dataset, optimized network weight parameters are obtained for (WIFI / CCSDS) modulation and coding schemes. The optimized deep neural network is then used for direct decoding, which reduces the bit error rate under power amplifier nonlinearity, lowers the power input back-off requirement, and improves the efficiency of on-board power amplifiers. The invented LDPC decoding network can be applied to satellite communication, deep space communication, and other radio communication fields.

[0019] Example 1 This application proposes an LDPC deep neural network decoding method that is resistant to power amplifier nonlinearity, including: The received signal is softly demodulated to obtain initial soft information, which is then input into a trained deep neural network to output the decoded signal. The process of building a deep neural network includes: Step 1: Read the parity check matrix of the LDPC code, and count the positions of all non-zero elements in the matrix in row-major order; define each non-zero element as an external information processing unit, i.e. a neuron node in a deep neural network; construct column adjacency lists and row adjacency lists.

[0020] The process of constructing the column adjacency list and row adjacency list includes: traversing each column of the parity-check matrix, recording the index of the external information processing unit corresponding to all non-zero elements in that column, and establishing directed connections between different processing units to form the column adjacency list; traversing each row of the parity-check matrix, recording the index of the external information processing unit corresponding to all non-zero elements in that row, and establishing directed connections between different processing units to form the row adjacency list. The processing unit itself is excluded during the construction process to satisfy the external information transmission principle of BP decoding.

[0021] Both column adjacency lists and row adjacency lists use "source external information". The data is represented in the form of "target external information". Its internal data is the index of the external information processing unit, that is, the first row is the source index and the second row is the target index. It is sorted in ascending order of the source index first. If the source indexes are the same, it is sorted in ascending order of the target index.

[0022] Step 2: Configure the network input layer interface; create n One input node, n The number of variable nodes; The first The value of the input node is copied and concatenated to all nodes belonging to the first hidden layer. j On the neurons of the column.

[0023] Step 3: Construct a learnable hidden layer for the network, including: Constructing an odd-layer module: Using a column adjacency list, connect the current layer node to the previous layer node, with the rule that a connection is established when two nodes correspond to different non-zero elements in the same column of the parity-check matrix; set learnable weights on the inter-layer message connections and the original channel soft information input branch, perform weighted aggregation on the original channel soft information and the adjacent messages from the previous layer, and concatenate an activation function. ; Construct an even-level module: Using a row adjacency list, connect the current-level node to the previous-level node, following the rule: establish a connection when two nodes correspond to different non-zero elements in the same row of the parity check matrix; define an aggregation operator in this level; the aggregation operator is: first perform a product operation on the input, then concatenate a... Activation function.

[0024] The odd-numbered and even-numbered layer modules are stacked alternately multiple times, so that the output of the previous layer is connected to the input index of the next layer, forming a deep network structure.

[0025] Step 4: Construct the network output layer aggregation logic.

[0026] create n One output node, n The number of variable nodes; The first The output node is connected to all nodes belonging to the last hidden layer. j The neurons in the column; A summation operator is added after each hidden layer neuron, and the original input is fused to form the final decision value.

[0027] The training process of a deep neural network includes: The transmitter randomly generates a sequence of information bits, which is then channel-coded and mapped to codeword bits. After modulation mapping, a complex baseband transmission symbol is obtained, which is then transmitted through a nonlinear channel. During network training, the SNR is randomly sampled within a given range and extended to each modulation symbol at the symbol level to enhance the model's adaptability to different channel conditions. The receiving end performs soft demodulation on the received signal to obtain initial soft information, which is then fed into a deep neural network to train and output posterior soft information before making a hard decision.

[0028] After the deep neural network is trained, the trainable parameters in the current network are determined as the target network parameters and stored. During the inference (i.e. decoding) process, these parameters are used to configure the network weights. The network weight parameters include: the original channel soft information and the learnable weights on the inter-layer connections based on the column adjacency list.

[0029] Example 2 This application proposes an LDPC deep neural network decoding method that is resistant to power amplifier nonlinearity, including: (1) Deployment of LDPC deep neural network Tanner graphs are bipartite graph representations of LDPC code parity-check matrices, consisting of variable nodes. (Representing codeword bits) and check nodes Composed of (representing verification constraints), let the verification matrix be... The matrix dimension is The number of non-zero elements is Then there are a total of in the Tanner diagram. 1 variable node One verification node and Edge. When At that time, the verification node With variable nodes There is an edge between them, and messages are transmitted bidirectionally along this edge.

[0030] With the verification matrix For example, the Tanner diagram is as follows: Figure 1 As shown, where 、 、 、 、 For variable nodes (columns). 、 、 This is a checksum node (row). All non-zero elements in the checksum matrix represent an edge in the Tanner graph, indicating extrinsic information during the BP iterative decoding process. This extrinsic information represents neurons in the subsequently unfolded deep neural network, and their numbers are denoted as follows: , Assign it a unique encoded value, which is determined in the following manner: k=0 for from 0 to m-1: for from 0 to n-1: if == 1: end end end Right now It equals the row number of the check node it is connected to multiplied by the number of variable nodes, plus the column number of the variable node it is connected to, corresponding to the row number of the check matrix. line, number The non-zero elements of the column. In other embodiments, other methods of obtaining non-repeating numbers, such as non-repeating random numbers, can also be used. Assign a value.

[0031] Row update adjacency matrix The non-zero elements are:

[0032] in, This indicates rounding down to the nearest integer.

[0033] express and There is an edge connecting them.

[0034] Column update adjacency matrix The non-zero elements are:

[0035] express and There is an edge connecting them.

[0036] Based on the connection relationship, and These can be represented as row adjacency lists. Adjacency list :

[0037]

[0038] Row adjacency list Adjacency list All adopt "external information" External information ( The internal data is represented in the form of ")", and its internal data is an external information processing unit. index That is, the first row is the source index, and the second row is the target index. They are first sorted in ascending order by source index; if the source indexes are the same, then sorted in ascending order by target index. In this example, the check matrix... H Corresponding row adjacency list Adjacency list They are respectively:

[0039]

[0040] The adjacency list expanded by the BP algorithm is as follows: Figure 2 As shown, where 、 、 、 、 、 、 、 、 This represents the external information processing unit (a neuron in a deep neural network), indicating the edge information transmitted in the Tanner graph. The leftmost bracket value indicates the coordinate value of the non-zero element in the check matrix. After iterative expansion, a non-fully connected neural network can be formed. Odd-numbered layer nodes. according to With upper-level nodes Connect the nodes (except for the first layer), sum the information in the same variable node except for the node connected to the target verification node, and obtain the nodes of that odd-numbered layer. The information value, i.e., the variable node in the Tanner diagram. Verify the edge information of the node; even-level nodes according to With upper-level nodes Connect the nodes by multiplying the information in the same verification node, excluding the node connected to the target variable, to obtain the even-numbered layer nodes. The information value, i.e., the verification node in the Tanner graph. Edge information of variable nodes.

[0041] The proposed LDPC deep neural decoding network, which is resistant to power amplifier nonlinearity, has the same adjacency list structure as the BP algorithm. However, it adds an input layer and an output layer, and modifies the original channel log-likelihood ratio and column adjacency list. middle The connections introduce learnable weights, as shown in the structure diagram. Figure 3 As shown, the specific message update rules are as follows: The number of input layer nodes is The log-likelihood ratio of the channel demodulation output is included. , Indicates the first The channel log-likelihood ratio of each variable node maps the log-likelihood ratio of the variable node to all edges connected to that variable node:

[0042] The number of intermediate layer nodes is , When it is odd, it indicates that it has passed through After the second iteration, the variable node Verify node edge information ( hour The activation function is :

[0043] When it is even, it indicates that it has passed through. Verification node after the next iteration Variable node edge information, activation function is :

[0044] Output layer node is ,through After the nth iteration, all edge information connecting a certain variable node is finally aggregated back to that variable node. The bit-decoding output is:

[0045] in The output information after processing by the node at this layer. The output information after processing by the upper-level node. Control the degree to which the original channel log-likelihood ratio affects the current message. Control upper-level nodes Messages to the current layer node The degree of influence number of intermediate layers , The total number of iterations is [number]. A hidden layer.

[0046] (2) Training of LDPC deep neural network To train learnable weights in a neural network, this invention constructs a bit-level communication simulation system under a TWTA nonlinear channel. The system consists of source generation, LDPC coding, modulation mapping, a TWTA nonlinear power amplifier, an AWGN physical channel, soft demodulation, and an LDPC deep neural decoding network. Except for the LDPC decoding network, the other modules are used to simulate actual communication links and do not participate in network parameter updates. During training, the data flow is as follows: the transmitter randomly generates a sequence of information bits. After channel coding, it is mapped to codeword bits. Then, through modulation mapping, the complex baseband transmission symbol is obtained. Subsequently, the signal is transmitted through a nonlinear channel, and the receiving end processes the received signal. Soft demodulation is performed to obtain initial soft information. The posterior soft information is then fed into the LDPC decoding network for training and output. Ultimately, a firm judgment was made. The system randomly samples within a given SNR range and extends this sampling to each modulation symbol at the symbol level, thereby enhancing the model's adaptability to different channel conditions.

[0047] This invention constructs a neural network based on the PyTorch framework and employs the Adam optimizer to process the channel-encoded codeword bits during the forward propagation stage. As a training supervision label, the training objective is composed of the cross-entropy loss of the initial soft information and the weighted cross-entropy of the posterior soft information in each iteration:

[0048]

[0049] BCEWithLogits BCEWithLogits in For code length, It is the initial soft information Compared to actual typing The basic binary cross-entropy loss, For the first Post-iteration soft information Compared to actual typing The supervised loss is calculated by performing an exponentially weighted sum of the losses from each round. As the number of iterations increases, the weights... Gradually increasing the weight enhances the discriminative power of later iterations, while earlier iterations still provide auxiliary supervision with smaller weights. After each training round, the validation loss and bit error rate are calculated using the validation set, and the models with the best accuracy, the best loss, and the latest model are saved respectively.

[0050] (3) Network weight parameters The network was trained using a modulation and coding scheme of WiFi standard 64QAM modulation + 1 / 2 LDPC code (648 information bits). A set of network weights was trained when the input back-off (IBO) was 2, 3, 4, 5, 6, and 7 dB respectively.

[0051] initial weight In the experiment, it was denoted as l_weight After training l_weight The dimension is (4644, 1). Taking the first 5 data items as an example, the specific content is shown in Table 1. The weight assignment method is as follows: l_weight The value assigned to the first edge_ idx Edge.

[0052] Table 1 l_weight Example of weight value

[0053] for Each pair Add trainable weights In the experiment, it was recorded as adj_weight After training adj_weight The dimension is (20, 22572), with 20 iterations, each containing 22572 updated weights. Taking the data from the first three iterations as an example, the details are shown in Tables 2, 3, and 4. The weight assignment method is as follows: adj_weight The value assigned to the first pair_idx right , Index is src_edge , Index is dst_edge .

[0054] Table 2 First Iteration adj_weight value( iter00 )

[0055] Table 3 Second Iteration adj_weight value( iter01 )

[0056] Table 4 Third Iteration adj_weight value( iter02 )

[0057] Similarly, experiments were conducted on the CCSDS standard 64APSK modulation + 1 / 2 AR4JA code (information bit length 1024) scheme, and the assignment logic rules were the same as above.

[0058] (4) Results Explanation The trained network weights were applied to two schemes: WiFi standard 64QAM modulation + 1 / 2 LDPC code (648 information bits) and CCSDS standard 64APSK modulation + 1 / 2 AR4JA code (1024 information bits).

[0059] The experimental results of WiFi standard 64QAM modulation + 1 / 2 LDPC code (information bit length is 648) are as follows: Figure 4 , 5 As shown, in the low IBO range (IBO=2, 3, 4dB), the system BER using the LDPC decoding network is significantly lower than that of the traditional BP decoding network. When IBO=2, 3, 4, 5, 6, 7dB, the system TD value using the LDPC decoding network is optimized compared to the system TD value of the traditional BP decoding network. The TD value of the LDPC decoding network at IBO=5dB is better than that of the traditional BP decoding network at IBO=6dB. Moreover, the LDPC decoding network still has a gain of about 0.2dB compared to the traditional BP decoding network at 6dB, reaching the optimal operating point.

[0060] The experimental results of CCSDS standard 64APSK modulation + 1 / 2AR4JA code (information bit length is 1024) are as follows: Figure 6 , 7 As shown, in the low IBO range (IBO=2, 3, 4dB), the BER of the system using the LDPC decoding network is significantly lower than that of the system using the traditional BP decoding network. When IBO=2, 3, 4dB, the TD value of the system using the LDPC decoding network is significantly better than that of the system using the traditional BP decoding network. As IBO increases to 5dB, the gain of the LDPC decoding network is still about 0.2dB compared to the traditional BP decoding network.

[0061] Therefore, the LDPC deep neural network proposed in this invention utilizes deep learning methods and a deep neural network expanded using the BP decoding algorithm. It learns on the nonlinear channel dataset of the onboard TWTA power amplifier to obtain optimized network weight parameters, which can reduce the bit error rate of high-order modulation in the nonlinear distortion channel of the power amplifier, reduce the power input back-off requirement, and improve the efficiency of the onboard power amplifier.

[0062] Example 3 This application also provides an LDPC deep neural network decoding system that resists power amplifier nonlinearity, for implementing the above method, the system comprising: The decoding module is used to perform soft demodulation on the received signal to obtain initial soft information, which is then input into a trained deep neural network and outputs the decoded signal.

[0063] This application may also provide a computer device, including: at least one processor, memory, at least one network interface, and a user interface. The various components in this device are coupled together via a bus system. It is understood that the bus system is used to implement communication between these components. In addition to a data bus, the bus system also includes a power bus, a control bus, and a status signal bus.

[0064] The user interface can include a display, keyboard, or clicking device. Examples include a mouse, trackball, touchpad, or touchscreen.

[0065] It is understood that the memory in the embodiments disclosed in this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memories described herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0066] In some implementations, the memory stores elements such as executable modules or data structures, or subsets thereof, or extended sets thereof: operating systems and applications.

[0067] The operating system includes various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic business functions and handle hardware-based tasks. The application programs include various applications, such as media players and browsers, used to implement various application functions. Programs implementing the methods of the embodiments of this disclosure can be included in the application programs.

[0068] In the above embodiments, the processor can also invoke programs or instructions stored in memory, specifically programs or instructions stored in an application program, for the following purposes: Follow the steps described above.

[0069] The above methods can be applied to or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the processor's hardware or by software instructions. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic diagrams disclosed above. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the disclosed methods can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0070] It is understood that the embodiments described in this application can be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in this application, or combinations thereof.

[0071] For software implementation, the technology of this application can be implemented by executing the functional modules (e.g., procedures, functions, etc.) of this application. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0072] This application may also provide a non-volatile storage medium for storing a computer program. When the computer program is executed by a processor, it can implement the steps in the above method embodiments.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application, and should all be covered within the scope of the claims of this application.

Claims

1. A deep neural network decoding method for LDPC that resists power amplifier nonlinearity, comprising: The received signal is softly demodulated to obtain initial soft information, which is then input into a trained deep neural network to output the decoded signal. The construction process of the deep neural network includes: Read the parity-check matrix of the LDPC code, and count the positions of all non-zero elements in the matrix in row-major order; define each non-zero element as an external information processing unit, i.e., a neuron node in a deep neural network; construct column adjacency lists and row adjacency lists; Configure the network input layer interface; Constructing a learnable hidden layer for the network includes: Constructing an odd-layer module: Using a column adjacency list, connect the current layer node to the previous layer node; set learnable weights on the inter-layer message connection and the original channel soft information input branch, perform weighted aggregation on the original channel soft information and the previous layer adjacency messages, and concatenate an activation function. ; Construct even-level modules: Use row adjacency lists to connect the current level nodes with the previous level nodes, and define aggregation operators in this level; The odd-numbered and even-numbered layer modules are stacked alternately multiple times, so that the output of the previous layer is connected to the input index of the next layer, forming a deep network structure. Construct the aggregation logic for the network output layer.

2. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, The construction of the column adjacency list and the row adjacency list includes: Traverse each column of the check matrix, record the index of the external information processing unit corresponding to all non-zero elements in that column, and establish directed connections between different processing units to form a column adjacency list; Traverse each row of the check matrix, record the index of the external information processing unit corresponding to all non-zero elements in that row, and establish directed connections between different processing units to form a row adjacency list; The processing unit itself is excluded during the construction process to satisfy the principle of external information transmission in BP decoding.

3. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, Both the column adjacency list and the row adjacency list use "external information". The data is represented in the form of "target external information". Its internal data is the index of the external information processing unit, that is, the first row is the source index and the second row is the target index. It is sorted in ascending order of the source index first. If the source indexes are the same, it is sorted in ascending order of the target index.

4. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, The configuration network input layer interface includes: create n One input node, n The number of variable nodes; The first The value of the input node is copied and concatenated to all nodes belonging to the first hidden layer. j On the neurons of the column.

5. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, In the odd-numbered layer module, the current layer node simultaneously receives the output of the previous layer node and the original channel soft information of the corresponding variable node. The current layer node and the previous layer node are connected by a column adjacency list, that is, a connection is established when two nodes correspond to different non-zero elements in the same column of the parity check matrix. The original channel soft information is mapped to the current layer node corresponding to all non-zero elements in that column. In the even-numbered layer module, the current layer node and the previous layer node are connected by a row adjacency list, that is, a connection is established when two nodes correspond to different non-zero elements in the same row of the parity check matrix.

6. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, The aggregation operator is: First, perform a product operation on the input, then concatenate a... Activation function.

7. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, The aggregation logic for constructing the network output layer includes: create n One output node, n The number of variable nodes; The first The output node is connected to all nodes belonging to the last hidden layer. j The neurons in the column; A summation operator is added after each hidden layer neuron, and the original inputs are fused together to form the final decision value.

8. The LDPC deep neural network decoding method for resisting power amplifier nonlinearity according to claim 1, characterized in that, The training process of the deep neural network includes: The transmitter randomly generates a sequence of information bits, which is then channel-coded and mapped to codeword bits. After modulation mapping, a complex baseband transmission symbol is obtained, which is then transmitted through a nonlinear channel. During network training, the SNR is randomly sampled within a given range and extended to each modulation symbol at the symbol level to enhance the model's adaptability to different channel conditions. The receiving end performs soft demodulation on the received signal to obtain initial soft information, which is then fed into a deep neural network to train and output posterior soft information before making a hard decision.

9. A deep neural network decoding system for LDPC that resists power amplifier nonlinearity, used to implement the method described in any one of claims 1-8, characterized in that, The system includes: The decoding module is used to perform soft demodulation on the received signal to obtain initial soft information, which is then input into a trained deep neural network and outputs the decoded signal.

Images