A decoding method, a decoder, an electronic device and a storage medium

Abstract

The application discloses a decoding method, a decoder, an electronic device and a storage medium, and relates to the technical field of data storage, and comprises the following steps: initializing the iteration number, decoding the to-be-decoded data according to a preset decoding algorithm to obtain a to-be-corrected value; checking the to-be-decoded data according to a check equation to obtain a check result; updating a current correction term, correcting the to-be-corrected value according to the updated correction term to obtain a corrected value; adjusting a normalization factor according to the iteration number and the check result, and performing weighted processing on the corrected value according to the normalization factor to obtain inter-node information; obtaining intermediate data according to the inter-node information and the to-be-decoded data, taking the intermediate data as the to-be-decoded data, updating the iteration number, and iteratively decoding the to-be-decoded data until the check result is all passed, to obtain decoded data of the to-be-decoded data. The problem that it is difficult to improve the decoding precision and error correction performance of LDPC decoding under the premise of controllable calculation complexity is solved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, specifically to a decoding method, decoder, electronic device, and storage medium. Background Technology

[0002] Low-density parity check (LDPC) codes have become a key error correction scheme for high-density flash memory due to their near-Shannon limit error correction performance and good hardware implementability. The core of LDPC decoding is the belief propagation (BP) algorithm, whose theoretical performance is close to the Shannon limit. However, the BP algorithm involves complex nonlinear operations, resulting in excessive computational complexity, making it difficult to meet the requirements of high throughput and low power consumption in hardware implementation. Currently, the min-sum algorithm (MSA) is used to simplify message update rules and reduce computational complexity, but the simplification of the MSA algorithm sacrifices some decoding accuracy, and its performance is significantly lower than that of the BP algorithm. Summary of the Invention

[0003] This invention provides a decoding method, decoder, electronic device, and storage medium to solve the problem of difficulty in improving the decoding accuracy and error correction performance of LDPC decoding under the premise of controllable computational complexity.

[0004] Firstly, this application provides a decoding method, which includes: Initialize the number of iterations, decode the data to be decoded according to the preset decoding algorithm, obtain the updated value, compare the updated value with the current corrected value, and obtain the value to be corrected under different data layers based on the comparison result; The data to be decoded is verified according to a preset number of verification equations, and the verification results corresponding to the verification equations are obtained. Get the current correction item, update the current correction item based on the difference between the updated value and the current corrected value to get the updated correction item, and correct the value to be corrected based on the updated correction item to get the corrected value; Based on the number of iterations and the verification results, the normalization factor corresponding to the verification equation is adjusted, and the corrected values ​​are weighted according to the normalization factor to obtain the information between nodes. Intermediate data is obtained based on the information between nodes and the data to be decoded. The intermediate data is used as the data to be decoded. The iteration count is increased by a first preset step size. The subsequent steps are executed starting from decoding the data to be decoded according to the preset decoding algorithm. The iteration ends when all verification results pass the verification and the decoded data corresponding to the data to be decoded is obtained.

[0005] Secondly, this application provides a decoder, which includes: a decoding module, a variable coefficient multiplication module, an incremental check module, a normalization factor selection module, and an iteration counting module; The iteration counting module is used to initialize the number of iterations. The decoding module is used to decode the data to be decoded according to a preset decoding algorithm, obtain an updated value, compare the updated value with the current corrected value, and obtain the corrected value under different data layers based on the comparison result. The incremental verification module is used to verify the data to be decoded according to a preset number of verification equations and obtain the verification result corresponding to the verification equation. The decoding module is used to obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value, obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value. The normalization factor selection module is used to adjust the normalization factor corresponding to the verification equation based on the number of iterations and the verification results. The variable coefficient multiplication module is used to weight the corrected values ​​according to the normalization factor to obtain the information between nodes; The decoding module is used to obtain intermediate data based on inter-node information and data to be decoded, and then use the intermediate data as data to be decoded. The iteration counting module is used to increment the iteration count by a first preset step size. The decoding module is used to execute subsequent steps from decoding the data to be decoded according to the preset decoding algorithm until all verification results pass, at which point the iteration ends and the decoded data corresponding to the data to be decoded is obtained.

[0006] Thirdly, this application provides a decoding apparatus, which includes: The decoding module is used to initialize the number of iterations, decode the data to be decoded according to the preset decoding algorithm, obtain the updated value, compare the updated value with the current corrected value, and obtain the value to be corrected under different data layers based on the comparison result. The verification module is used to verify the data to be decoded according to a preset number of verification equations and obtain the verification results corresponding to the verification equations. The correction module is used to obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value, obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value. The processing module is used to adjust the normalization factor corresponding to the verification equation according to the number of iterations and the verification results, and to perform weighted processing on the corrected values ​​according to the normalization factor to obtain the information between nodes. The iterative decoding module is used to obtain intermediate data based on the information between nodes and the data to be decoded. The intermediate data is used as the data to be decoded. The iteration count is increased by a first preset step size. The subsequent steps are executed starting from decoding the data to be decoded according to the preset decoding algorithm. The iteration ends when all verification results pass the verification and the decoded data corresponding to the data to be decoded is obtained.

[0007] Fourthly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the decoding method of the first aspect or any corresponding embodiment described above.

[0008] Fifthly, this application provides a computer-readable storage medium storing computer instructions that cause a computer to execute the decoding method of the first aspect or any corresponding embodiment described above.

[0009] In a sixth aspect, this application provides a computer program product, including computer instructions for causing a computer to execute the decoding method of the first aspect or any corresponding embodiment thereof.

[0010] This application addresses the challenge of improving the decoding accuracy and error correction performance of LDPC decoding while maintaining controllable computational complexity. The method initializes the iteration count, decodes the data to be decoded using a preset decoding algorithm to obtain an updated value, compares this updated value with the currently corrected value, and determines the corrected value for different data layers based on the comparison result. It then verifies the data to be decoded according to a check equation, obtaining a verification result. Next, it updates the current correction term based on the difference between the updated value and the currently corrected value, and corrects the data to be decoded based on the updated correction term, obtaining the corrected value. Finally, it adjusts the normalization factor based on the iteration count and verification result, and weights the corrected value based on the normalization factor to obtain inter-node information. Based on the inter-node information and the data to be decoded, it obtains intermediate data, uses this intermediate data as the data to be decoded, increases the iteration count by a first preset step, and iteratively decodes the data to be decoded until all verification results pass, yielding the decoded data corresponding to the data to be decoded. This method solves the problem of difficulty in improving the decoding accuracy and error correction performance of LDPC decoding while maintaining controllable computational complexity. Through dynamic normalization factor and correction term optimization, this method significantly improves error correction capability and reduces performance loss after quantization. Early iterations use a fixed factor to reduce computational load, while later iterations dynamically adjust the factor as needed to balance performance and power consumption. The normalization factor adapts to the number of iterations, accelerating convergence and reducing redundant computations. The iteration count is synchronized with the variable node update cycle for precise control of adjustment timing. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0012] Figure 1 This is a flowchart illustrating the decoding method according to an embodiment of this application; Figure 2 This is a performance comparison chart of four decoding algorithms according to embodiments of this application; Figure 3 This is a flowchart of the adaptive normalization factor based on the number of iterations according to an embodiment of this application; Figure 4 This is a flowchart of an optimized LDPC decoding method according to an embodiment of this application; Figure 5 This is a schematic diagram of the decoder according to an embodiment of this application; Figure 6 This is a structural block diagram of a decoding apparatus according to an embodiment of this application; Figure 7 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] With the surge in data storage demand, NAND flash memory has become the mainstream storage medium due to its high density and non-volatility. However, the increased storage density of NAND flash memory has led to a significant increase in the original bit error rate, placing higher demands on error correction coding. Low-density parity-check (LDPC) codes, due to their near-Shannon limit error correction performance and good hardware implementation, have become a key error correction scheme for high-density flash memory.

[0017] The core of LDPC code decoding is the belief propagation algorithm (BP), whose theoretical performance is close to the Shannon limit. However, the BP algorithm involves complex nonlinear operations (such as hyperbolic function calculation), resulting in excessively high computational complexity, making it difficult to meet the hardware implementation requirements of high throughput and low power consumption. To overcome this bottleneck, the minimum sum algorithm (MSA) was proposed by simplifying the message update rules, significantly reducing computational complexity and becoming the basic framework for hardware implementation. However, the simplification of MSA sacrifices some decoding accuracy, and its performance is significantly lower than that of the BP algorithm.

[0018] Other optimizations to the BP algorithm include storing multiple normalization factors and using different normalization factors for different check equations. However, since there are many check equations, if the algorithm for selecting normalization factors is too complex, it will significantly increase hardware complexity. Another better-performing improved algorithm is to add a correction term when calculating the minimum value, which is called the corrected minimum sum algorithm. Due to the introduction of the correction term, the floating-point performance of the algorithm has reached the theoretical limit, but there is still a performance loss after data quantization.

[0019] Based on the above, this application provides a decoding method using an LDPC decoding algorithm with a correction term. Each time a minimum / second smallest value comparison is performed, the correction term is calculated synchronously and added to the comparison result to obtain the corrected minimum and second smallest values. An adaptive normalization factor decoding algorithm is also used. The multiplier for the normalization factor and the minimum value is set as a variable coefficient multiplier, allowing for individual adjustment of the normalization factor used for each verification equation. The actual normalization factor used is determined by whether the current equation has been decoded successfully. This scheme is highly sensitive to verification results, requiring all verification results to be saved separately after each round of decoding; real-time verification results cannot be used. Saving verification results separately increases the complexity of the decoder. After a period of decoding iteration, the verification results tend to stabilize, at which point the current real-time verification results can be used, eliminating the need to save them separately. Real-time verification results can be obtained through incremental verification. Incremental verification calculates the difference between the old and new data after each new decoded data acquisition and updates the verification results accordingly, thus achieving immediate access to complete verification results after each data update. The incremental verification module is a standard component of the decoder. This method uses different normalization factors depending on the number of iterations. When verification fails, the normalization factor decreases with increasing iteration count. For verification equations that pass, the actual normalization factor used increases with increasing iteration count. This method improves the error correction capability of the decoding algorithm to near the theoretical limit of the belief propagation (BP) algorithm.

[0020] According to an embodiment of this application, a decoding method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, for example, a computer, a server, etc., and although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0021] This embodiment provides a decoding method. Figure 1 This is a flowchart of a decoding method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps: Step S101: Initialize the number of iterations, decode the data to be decoded according to the preset decoding algorithm, obtain the updated value, compare the updated value with the current corrected value, and obtain the value to be corrected under different data layers based on the comparison result.

[0022] Specifically, in this embodiment, the decoding method is executed by a decoder. The decoder uses an LDPC decoder with a correction term. The decoder's normalization factor can have multiple configurations. An incremental verification module is selected as the verification scheme for this decoder, and a software algorithm equivalent to this decoder is used as the optimal parameter selection tool. The number of iterations is initialized, for example, by setting the number of iterations to 0.

[0023] Data to be decoded, for example: raw data read from flash memory, such as the initial LLR (Log-Likelihood Ratio). Preset decoding algorithm, for example: LDPC decoding algorithm with correction terms.

[0024] The data to be decoded is decoded according to a preset decoding algorithm. During the decoding process, updated values ​​for variable nodes are calculated. Additionally, when calculating the verification node's feedback information (Lr), minimum / second smallest value comparison and correction term calculations are performed synchronously across different data layers. The updated values ​​are compared with the current corrected minimum and second smallest values ​​in the variable nodes. Based on the comparison results, new minimum and / or new second smallest values ​​are determined. For example, if an updated value is less than the current corrected minimum, that updated value is taken as the new minimum, and the current corrected minimum is taken as the new second smallest; if an updated value is less than the current corrected second smallest but greater than the current corrected minimum, that updated value is taken as the new second smallest, and the current corrected minimum continues to be taken as the minimum. The determined minimum and second smallest values ​​are then used as the values ​​to be corrected.

[0025] It should be noted that the current minimum value in the variable node is the minimum value corrected using the correction term in the previous iteration of decoding, and the current second minimum value is the second minimum value corrected using the correction term in the previous iteration of decoding. If this decoding round is the first iteration of decoding, only the minimum and second minimum values ​​can be selected from the updated values, and these selected minimum and second minimum values ​​can be used as the values ​​to be corrected.

[0026] The calculation of the check node feedback information (Lr) belongs to the C2V stage. In the C2V stage, the check node multiplies the corrected value by the adaptive normalization factor and then feeds the result back to the bit. In this stage, the normalized check node to variable node information (C2V information) can be calculated.

[0027] In addition, there is a V2C phase before the C2V phase. In the V2C phase, bits report information to the check node, and the check node simultaneously calculates the minimum and second-smallest values, and then adds a correction term. In the V2C phase, information from each layer of variable nodes to the check node (V2C information) can be calculated.

[0028] Step S102: Verify the data to be decoded according to a preset number of verification equations to obtain the verification results corresponding to the verification equations.

[0029] Specifically, the core carrier of LDPC is the parity check matrix H. For example, an LDPC code with a code rate of 89.6% has a parity check matrix. The closer the code rate is to 1, the fewer the error correction bits are, and the larger the space for storing effective data in flash memory. Each row of the parity check matrix H corresponds to one parity check equation, and each column corresponds to one bit in the codeword. Most of the positions in the matrix are 0, and only a few positions are 1, hence it is called a "low-density" matrix.

[0030] For example, the first row of the parity check matrix H is [1,0,1,1,0], and its corresponding first check equation is b1⊕b3⊕b4=0, where ⊕ represents the XOR operation; the second row is [0,1,1,0,1], and its corresponding second check equation is b2⊕b3⊕b5=0.

[0031] Step S103: Obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value, obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value.

[0032] Specifically, obtain the current correction term. For example, use the correction term used in the previous iteration of decoding as the current correction term. If this decoding round is the first iteration, use the initial correction term as the current correction term. The value of the initial correction term is set according to actual needs.

[0033] The current correction term is updated based on the difference between the updated value and the current corrected value, resulting in the updated correction term. For example, if the current corrected value includes the current minimum corrected value and the current second minimum corrected value, the difference between the updated value and the current minimum corrected value is used as the updated correction term; or, the difference between the updated value and the current second minimum corrected value is used as the updated correction term.

[0034] The value to be corrected is corrected according to the updated correction terms to obtain the corrected value. For example, the value to be corrected includes the minimum value to be corrected and the second smallest value to be corrected, and the corrected value includes the temporary corrected minimum value and the temporary corrected second smallest value. The temporary corrected minimum value is equal to the minimum value to be corrected plus the updated correction terms, and the temporary corrected second smallest value is equal to the second smallest value to be corrected plus the updated correction terms.

[0035] Step S104: Based on the number of iterations and the verification results, adjust the normalization factor corresponding to the verification equation, and perform weighted processing on the corrected values ​​according to the normalization factor to obtain the information between nodes.

[0036] Specifically, this embodiment dynamically adjusts the normalization factor: the normalization factor of each verification equation is adaptively adjusted based on the number of iterations and the real-time verification results (pass / fail). The adjustment of the normalization factor employs a piecewise optimization strategy: a fixed normalization factor is used in the initial iteration; after reaching a specific number of iterations, adaptive adjustment is initiated to achieve refined performance optimization.

[0037] The adaptive adjustment process includes: dynamically adjusting the normalization factor of each verification equation based on the real-time verification results (pass / fail) and the number of iterations: when the verification passes, the normalization factor increases with the number of iterations; when the verification fails, the normalization factor decreases with the number of iterations.

[0038] Inter-node information, such as C2V information, is obtained by weighting the corrected values ​​according to a normalization factor. For example, the corrected minimum value is multiplied by an adaptive normalization factor α, and the corrected second minimum value is multiplied by an adaptive normalization factor α. The result is the C2V information, which is then returned to the variable node.

[0039] Step S105: Obtain intermediate data based on the information between nodes and the data to be decoded. Use the intermediate data as the data to be decoded. Increase the iteration count by the first preset step size. Start executing subsequent steps from decoding the data to be decoded according to the preset decoding algorithm until all verification results pass the verification. Then the iteration ends and the decoded data corresponding to the data to be decoded is obtained.

[0040] Specifically, each variable node adds the data to be decoded from the previous round to the inter-node information (such as C2V) received from the check equations in the previous round, to obtain its latest intermediate data. For example, if the data to be decoded is the initial LLR, and assuming that variable node V1 corresponds to three check equations (such as C1, C2, and C3), variable node V1 will receive: C2V from C1. c1 Value, C2V from C2 c2 Value, C2V from C3 c3 Including the initial LLR of V1, there are a total of four information sources. Intermediate data = initial LLR + C2V c1 +C2V c2 +C2V c3 .

[0041] The first preset step size is, for example, 1. The iteration count is increased by the first preset step size. The intermediate data is used as the data to be decoded, and the process starts from "decode the data to be decoded according to the preset decoding algorithm" in step S101 above and executes the subsequent steps, that is, iteratively decodes the data to be decoded. During the iterative decoding process, if the verification result corresponding to each verification equation is a pass, the decoding is completed, the iteration process ends, and the data obtained by the current decoding is used as the decoded data corresponding to the data to be decoded.

[0042] Additionally, a maximum number of iterations can be set. If the maximum number of iterations is reached and the condition that "the verification result corresponding to each verification equation is verified as passed" is still not met, it indicates that the decoding has failed, and the iteration process will end and a decoding failure message will be output.

[0043] It should be noted that the decoding method in this embodiment employs a modified adaptive normalization factor scheme (hereinafter referred to as the modified adaptive 'a' algorithm), which offers superior decoding performance compared to other decoding algorithms in related technologies. Other decoding algorithms include the NMS (Normalized Min-Sum) algorithm, the NMS adaptive normalization factor algorithm, and the modified algorithm. Furthermore, the modification algorithm achieves a relatively low complexity improvement by controlling the number of iterations to optimize the adaptive normalization factor. Figure 2 Performance comparisons of four decoding algorithms are presented. All four algorithms use the same parity-check matrix, have a code rate of 89.6%, and use the same quantization bit width. Figure 2 As shown, when the raw bit error rate (RBER) is 0.009, the frame error rate (FER) decreases sequentially from the NMS algorithm, the NMS adaptive normalization factor algorithm, the modified algorithm, to the modified algorithm with adaptive a. It can be seen that the NMS adaptive normalization factor algorithm, the modified algorithm, and the modified algorithm with adaptive a all improve performance compared to the original NMS algorithm. The NMS adaptive normalization factor algorithm requires precise control of the checksum, which has a certain complexity and its performance is inferior to the modified algorithm. The modified algorithm's adaptive normalization factor has superior performance, and controlling the adaptive normalization factor with the number of iterations in the modified algorithm results in a lower complexity improvement.

[0044] The decoding method provided in this embodiment initializes the number of iterations, decodes the data to be decoded according to a preset decoding algorithm to obtain an updated value, compares the updated value with the current corrected value, and obtains the value to be corrected under different data layers based on the comparison result; verifies the data to be decoded according to a verification equation to obtain a verification result; updates the current correction term based on the difference between the updated value and the current corrected value, and corrects the value to be corrected based on the updated correction term to obtain the corrected value; adjusts the normalization factor according to the number of iterations and the verification result, and performs weighted processing on the corrected value according to the normalization factor to obtain inter-node information; obtains intermediate data based on the inter-node information and the data to be decoded, uses the intermediate data as the data to be decoded, increases the number of iterations by a first preset step, and iteratively decodes the data to be decoded until all verification results pass, obtaining the decoded data corresponding to the data to be decoded. This method significantly improves error correction capability and reduces performance loss after quantization through dynamic normalization factor and correction term optimization. Early iterations use a fixed factor to reduce computational load, while later iterations dynamically adjust the factor as needed to balance performance and power consumption. The normalization factor adapts to the number of iterations, accelerating convergence and reducing redundant computation. The iteration count is synchronized with the variable node update cycle, precisely controlling the timing of adjustments. This solves the problem of improving decoding accuracy and error correction performance of LDPC decoding while maintaining controllable computational complexity.

[0045] As an optional embodiment, the normalization factor corresponding to the verification equation is adjusted according to the number of iterations and the verification result, including: If the number of iterations is less than or equal to the second preset threshold, the first preset value is set as the normalization factor. If the number of iterations is greater than the second preset threshold, and the verification result corresponding to the verification equation is a verification failure, the normalization factor corresponding to the verification equation is reduced by the second preset step size. If the verification result corresponding to the verification equation is successful, increase the normalization factor corresponding to the verification equation by a second preset step size.

[0046] Specifically, in this embodiment, completing one parity check matrix constitutes one round, meaning that each parity check equation in the parity check matrix completes the verification process. The first few rounds of iterative decoding use the same normalization factor. The change in codewords can be used as an observation indicator; the change in codewords is larger in the first few rounds, and then decreases thereafter.

[0047] The second preset threshold represents the number of iterations, such as 5, 6, 7, or other values. If the number of iterations is less than or equal to the second preset threshold, it indicates that the current iteration is in its initial stage. Regardless of whether the validation passes, the same normalization factor is used, and the first preset value is set as the normalization factor. The first preset value is, for example, 0.03, 0.04, or other values.

[0048] When the iteration count reaches the first inflection point, before calculating the information (Lr) returned by the verification node, the verification result of the incremental verification module is checked. If the verification passes, the normalization factor used by the current verification node is increased; if the verification fails, the normalization factor used by the current verification node is decreased. In this embodiment, a second preset threshold is used to determine whether the iteration count has reached the first inflection point. If the iteration count is greater than the second preset threshold, it indicates that the iteration count has reached the first inflection point.

[0049] After the first inflection point is reached in the number of iterations, the actual normalization factor used changes with the incremental verification result as the number of iterations increases. If the verification passes, a larger normalization factor is used; if the verification fails, a smaller normalization factor is used. Furthermore, the normalization factor increases with the number of iterations when the verification passes and decreases with the number of iterations when the verification fails. Therefore, if the verification result corresponding to the verification equation is a failure, the normalization factor corresponding to the verification equation is subtracted by the second preset step size. For example, if the second preset step size is 0.01 and the normalization factor is 0.04, the adjusted normalization factor is 0.04 - 0.01 = 0.03. If the verification result corresponding to the verification equation is a success, the normalization factor corresponding to the verification equation is increased by the second preset step size. For example, if the second preset step size is 0.01 and the normalization factor is 0.04, the adjusted normalization factor is 0.04 + 0.01 = 0.05.

[0050] In addition, this embodiment can selectively adjust both sides, or only adjust the normalization factor when the verification passes or the normalization factor when the verification fails. The specific adjustment scheme and adjustment range can be adjusted according to the simulation test results of the software algorithm.

[0051] When implementing the decoding method of this embodiment in hardware, the internal arithmetic units and decoding pipeline of the decoder also need to be considered. This embodiment proposes a hardware implementation scheme for an adaptive normalization factor based on the number of iterations, combined with... Figure 3 The plan will be explained.

[0052] For a row-level decoder, while updating the variable-to-check (V2C) information at each level's variable node, the minimum and second-smallest values ​​for the current level can be calculated. This application selects a decoder with a correction term, and here the corrected minimum and second-smallest values ​​are calculated. After completing the calculation for one level, the corrected minimum and second-smallest values ​​can be output as input data for a variable-coefficient multiplier, such as... Figure 3 As shown, the temporary minimum and the temporary second minimum are determined by V2C calculation, and then corrected based on the layer count to obtain the corrected minimum and the corrected second minimum.

[0053] The check module of the row-level decoder calculates the check results for all rows, without any layering. Figure 3As shown, checksum calculations are performed to obtain checksums for level 1, level 2, ..., level L, where L represents multiple checksums. These checksums are mixed together. A level selector needs to be added to select all checksums and output the row checksum result corresponding to the current level, as shown. Figure 3 As shown, the layer selector selects the checksum based on the layer technology. Since all rows within a layer are computed in full parallel, the checksum selector is also configured to be fully parallel, requiring only selection based on the layer number. For the incremental checksum module, the update of the checksum result has a layer delay compared to the V2C update, and the incremental checksum result is constantly being updated, not stopping precisely at the moment when a certain layer's V2C computation is completed. However, as the number of iterations increases, the checksum result tends to stabilize, so the checksum result can be directly retrieved when the multiplier needs it.

[0054] The normalization factor used can be determined by the checksum and the number of iterations. The number of iterations can be counted according to the V2C calculation order; the iteration count is incremented by one after each round of V2C calculation. A normalization factor selector can be designed, such as... Figure 3 As shown, based on the check value selected by the layer selector and the number of iterations determined by the iterative technique, the normalization factor that should be used at the current time is selected.

[0055] After completing the numerical correction and normalization factor selection, the normalization correction value calculator can be used to calculate the normalized check node to variable node information (C2V), such as... Figure 3 As shown, the normalization correction value calculator calculates the C2V corresponding to different data strata based on the normalization factor, the correction minimum, and the correction second minimum. Based on the selected normalization factor, the normalized result of the input data is obtained. This includes the normalized correction minimum, the normalized correction second minimum, and the location of the minimum. After calculation, the result is stored in the C2V memory for subsequent calculations. Figure 3 The C2V memory shown stores the first layer of C2V, the second layer of C2V, ..., the Lth layer of C2V. Data that needs to be used immediately can be stored in registers, while data that needs to be used in subsequent processes is stored in static random access memory (SRAM) at a specified address.

[0056] It should be noted that, Figure 3 The presence of three non-overlapping rectangles is to indicate the direction during decoding. Figure 3 The logic of adaptive normalization factor based on iteration number can be set up to execute multiple total modules in parallel. Each rectangle represents a total module. The structure and task execution logic of each total module are the same. Multiple total modules can each perform tasks such as V2C calculation and check value calculation. Each total module contains components such as layer selector, normalization correction value calculator, and normalization factor selector.

[0057] In this embodiment, a unified normalization factor is used in the initial stage of decoding to ensure the stability of the iteration process. After reaching the turning point, the factor is adaptively adjusted based on the verification results to optimize the decoding message correction effect and improve error correction capability. The adjustment strategy can be flexibly configured according to simulation to adapt to high code rate LDPC decoding scenarios.

[0058] As an optional embodiment, if the number of iterations exceeds a second preset threshold, the method further includes: Based on the value to be corrected and the value already corrected, the amount of codeword change is obtained; If the change in codeword is less than the third preset threshold, the value of the second preset step size will be increased by the second preset value.

[0059] Specifically, the codeword change is obtained based on the value to be corrected and the value that has been corrected.

[0060] As the number of iterations increases, the amount of codeword change will further decrease. When the amount of codeword change decreases to a certain level, it is considered to have reached the second inflection point of the iteration count. This embodiment determines whether the second inflection point is met by setting a third preset threshold, such as 50, 100, or other values.

[0061] If the codeword change is less than the third preset threshold, the second inflection point is met. Before calculating Lr, the incremental verification result is checked. If the verification passes, the normalization factor that passed the verification is further increased; if the verification fails, the normalization factor that failed the verification is further decreased. The value of the second preset step size is increased by the second preset value. For example, if the second preset step size is 0.03 and the second preset value is 0.03, the modified second preset step size is 0.06. The specific values ​​of the second preset step size and the second preset value are set according to actual needs.

[0062] In addition, software algorithms can be used to segment inflection points with more iterations and to finely adjust the normalization factor.

[0063] By combining the logic of adjusting the normalization factor α in this embodiment, an optimized LDPC decoding method can be obtained, such as... Figure 4 As shown, the method includes: An LDPC decoder with a correction term is selected, which supports multiple normalization factor configurations, and an incremental check module is embedded to establish an equivalent software algorithm.

[0064] Input the parity check matrix and the number of errors, optimize using a software algorithm, and output the quantization bit width and the initial normalization factor α.

[0065] The first iteration uses fixed α decoding to monitor the change in codewords. If there is a significant decrease, it can be considered that the first turning point has been reached. The incremental verification result is checked. If it passes, α is increased; if it fails, α is decreased.

[0066] If the codeword change decreases significantly when using adaptive α-iterative decoding, it can be considered that the second turning point has been reached; if the incremental verification passes, α is further increased, and if it fails, α is further decreased.

[0067] After multiple iterations of decoding, all turning points and the normalization factors corresponding to the verification results are recorded to form a lookup table.

[0068] In this embodiment, an iteration number segmentation strategy is adopted to divide the decoding process into multiple stages, such as the initial stage and the turning point stage. Different normalization factor adjustment strategies are used in different stages to improve the convergence efficiency of the algorithm.

[0069] As an optional embodiment, after obtaining intermediate data based on inter-node information and the data to be decoded, the method further includes: Determine the difference between the data to be decoded and the intermediate data; Update the verification result corresponding to the verification equation based on the difference.

[0070] Specifically, this embodiment uses an incremental verification module to obtain real-time verification results. First, it calculates the difference between the new decoded data and the old data, i.e., the difference between the intermediate data and the data to be decoded. Then, it updates the verification results corresponding to the verification equations based on the data differences, achieving synchronization between the verification results and the decoding update. By comparing the new and old codewords, it identifies the bit that has been flipped. Only the verification equations containing the flipped bit are recalculated; verification results not involving the flipped bit are directly retained without needing to be recalculated entirely. For example, if the previous codeword (the data to be decoded) is [1,0,1,1], and the intermediate data is [1,1,1,1], only the second bit is flipped. Only the verification results corresponding to all verification equations using the second bit are recalculated; the remaining verification results remain unchanged.

[0071] In this embodiment, the incremental verification module is used to obtain the verification result in real time, eliminating the need to store historical data. The verification result is quickly updated by calculating the difference between the old and new data, which significantly reduces hardware complexity.

[0072] As an optional embodiment, after adjusting the normalization factor corresponding to the verification equation based on the number of iterations and the verification results, the method further includes: Based on the number of iterations, the verification results, and the normalization factor, a mapping lookup table for the normalization factor is generated. If a normalization factor needs to be configured, obtain the current iteration number and the current verification result, and determine the target normalization factor based on the mapping lookup table, the current iteration number, and the current verification result.

[0073] Specifically, based on the number of iterations, the verification results, and the normalization factor, a mapping lookup table is formed for the number of iterations, the verification results, and the normalization factor. The mapping lookup table is used to record the mapping relationship between the number of iterations, the verification results, and the normalization factor.

[0074] The normalization factor can be dynamically configured in the hardware decoder based on the mapping lookup table. For example, when the normalization factor needs to be configured, the current iteration number and the current verification result are obtained, the mapping relationship in the mapping lookup table is matched with the current iteration number and the current verification result, and the normalization factor in the successfully matched mapping relationship is used as the target normalization factor.

[0075] As an optional embodiment, after verifying the data to be decoded according to a preset number of verification equations and obtaining the verification results corresponding to the verification equations, the method further includes: Input the data layering and verification results into the parallel verification selector; By using a parallel verification selector, the verification results are filtered to determine the verification results corresponding to different data layers.

[0076] Specifically, the incremental check module outputs the check marks of all check rows of the entire matrix at once, and the check results of all layers are mixed together without layer distinction; the decoder pre-divides the complete check matrix into a fixed number of data layers, each layer containing several check rows that are processed in parallel.

[0077] This embodiment adds a parallel verification selector to select from all verification results and output the verification result for the row corresponding to the current layer. Since all rows within a layer are calculated in a fully parallel manner, the verification result selector is also configured to be fully parallel, requiring only selection according to the layer number.

[0078] The data layering and verification results are input into a parallel verification selector. This selector filters the verification results to determine the corresponding verification results for different data layers. For example, the parallel verification selector uses a fully parallel multiplexer circuit, with the number of channels corresponding one-to-one with the total number of decoding layers. Each layer is assigned a set of independent parallel filtering channels. When the hardware calculates V2C information for a certain layer, it simultaneously sends two inputs to the parallel verification selector: the layer number of the current computation layer; and all the mixed verification results from the incremental verification output. The circuit filters in parallel according to the layer number, retaining only the verification flags corresponding to the verification rows contained in that layer, and filtering out verification results irrelevant to other layers. After filtering, only the verification results specific to the current layer are output and sent to the normalization factor selector. Even if there is a timing delay in the incremental verification, the verification state tends to stabilize in the later stages of the iteration, and the filtered results can be used directly to complete the selection of the adaptive normalization factor normally.

[0079] For the incremental verification module, the update of the verification result has a layer of delay compared to the V2C update. Furthermore, the incremental verification result is constantly being updated and will not stop precisely at the moment when a certain layer of V2C computation is completed. Therefore, after determining the verification result corresponding to different data layers, the verification result will tend to stabilize as the number of iterations increases. Thus, the verification result can be directly retrieved when the multiplier needs it.

[0080] In this embodiment, a parallel verification selector is set to sort the global verification results, match the hierarchical operation requirements, and, in conjunction with the row-level hierarchical decoding structure, select the verification result of the current data layer in real time to ensure the stable operation of the row-level hierarchical decoding.

[0081] As an optional embodiment, before decoding the data to be decoded according to a preset decoding algorithm, the method further includes: Obtain the verification matrix and the number of errors, wherein a preset number of verification equations are contained in the verification matrix; Based on the parity check matrix and the number of errors, the decoding parameters are obtained, which are used to configure the preset decoding algorithm.

[0082] Specifically, in the preparation phase, an LDPC decoder with a correction term is selected. The decoder's normalization factor can have multiple configurations, and an incremental check module is chosen as the check scheme for this decoder. A software algorithm equivalent to this decoder is used as a tool for selecting the optimal parameters.

[0083] Obtain the parity check matrix and the error injection quantity. The parity check matrix is, for example, an LDPC code parity check matrix with a code rate of 89.6%, where each row of the parity check matrix H corresponds to one parity check equation. The error injection quantity is the raw bit error rate (RBER) of the flash memory, which refers to the proportion of raw stored bits that are erroneous when the flash memory chip has not undergone LDPC error correction.

[0084] Based on the parity-check matrix and the number of errors injected, software algorithms are used to select the optimal decoding parameters, such as bit quantization parameters and normalization factors. Iterative decoding begins using these parameters, which can be used to configure preset decoding algorithms. The optimal decoding parameters are selected using software algorithms, for example: writing a software simulation program consistent with the decoder logic, incorporating a min-sum algorithm with correction terms, incremental checksum, and segmented adaptive normalization to simulate the decoding behavior of a real decoder; importing fixed test conditions into the software simulation program, such as inputting a parity-check matrix with a target bit rate of 89.6% and the actual range of errors injected in flash memory, thus fixing the simulation environment; rotating various candidate parameters: different quantization bit widths, initial normalization factors, iteration inflection points, and normalization factor adjustment ranges; simulating a large number of codewords with random errors under each parameter set, calculating the frame error rate (FER), and generating multiple parameter combinations based on the candidate parameters; comparing the FER of all parameter combinations, selecting the parameter combination with the best error correction effect and the lowest hardware circuit overhead, and defining the parameters in this combination as the optimal decoding parameters.

[0085] In this embodiment, optimal parameters (such as the number of quantization bits and the normalization factor) are pre-selected using software algorithms to guide hardware implementation, resulting in high engineering feasibility. Furthermore, a clear hardware implementation plan (such as lookup table configuration and pipeline design) is provided to ensure the algorithm's feasibility for deployment.

[0086] This embodiment provides a decoder. Figure 5 This is a flowchart of a decoding method according to an embodiment of this application, such as... Figure 5 As shown, the decoder includes: a decoding module, a variable coefficient multiplication module, an incremental check module, a normalization factor selection module, and an iteration counting module; The iteration counting module is used to initialize the number of iterations. The decoding module is used to decode the data to be decoded according to a preset decoding algorithm, obtain an updated value, compare the updated value with the current corrected value, and obtain the corrected value under different data layers based on the comparison result. The incremental verification module is used to verify the data to be decoded according to a preset number of verification equations and obtain the verification result corresponding to the verification equation. The decoding module is used to obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value, obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value. The normalization factor selection module is used to adjust the normalization factor corresponding to the verification equation based on the number of iterations and the verification results. The variable coefficient multiplication module is used to weight the corrected values ​​according to the normalization factor to obtain the information between nodes; The decoding module is used to obtain intermediate data based on inter-node information and data to be decoded, and then use the intermediate data as data to be decoded. The iteration counting module is used to increment the iteration count by a first preset step size. The decoding module is used to execute subsequent steps from decoding the data to be decoded according to the preset decoding algorithm until all verification results pass, at which point the iteration ends and the decoded data corresponding to the data to be decoded is obtained.

[0087] Specifically, a variable coefficient multiplication module, such as a variable coefficient multiplier in a decoder, is configured to normalize the modified minimum and modified second minimum values ​​using a selected normalization factor.

[0088] The incremental verification module is configured to output verification results in real time. The decoding module is used to perform various data operations.

[0089] For example, a normalization factor selection module in a decoder is configured to dynamically select a normalization factor based on the number of iterations and the verification result.

[0090] An example of an iteration counting module is the iteration counter in a decoder. The iteration counter is synchronized with the update cycle of the variable node to the verification node (V2C) and counts the number of iterations.

[0091] The logic for executing the corresponding tasks by the above modules is described in the above embodiments and will not be repeated here.

[0092] In addition, the decoder uses a row-level hierarchical architecture and includes a parallel parity selector and a C2V memory. The parallel parity selector selects the parity result of the current layer in real time according to the layer number; the C2V memory stores the normalized parity node to variable node information (C2V).

[0093] The inputs to the variable coefficient multiplier include: the corrected minimum value, the corrected second minimum value, the location of the minimum value, and the dynamic normalization factor output by the normalization factor selector.

[0094] The decoder also includes a variable-coefficient multiplier and a parallel check selector. The variable-coefficient multiplier supports dynamic adjustment of the normalization factor. The parallel check selector, combined with the row-level decoding structure, selects the check result of the current layer in real time. An iteration counter is bound, and the number of iterations is synchronized with the variable node update (V2C) cycle, precisely controlling the timing of adjustments.

[0095] The decoder provided in this embodiment significantly improves error correction capabilities and reduces performance loss after quantization through dynamic normalization factor and correction term optimization. Early iterations use a fixed factor to reduce computational load, while later iterations dynamically adjust the factor as needed, balancing performance and power consumption. The normalization factor adaptively changes with the number of iterations, accelerating convergence and reducing redundant computation. The iteration count is synchronized with the variable node update cycle, precisely controlling the timing of adjustments. This solves the problem of difficulty in improving decoding accuracy and error correction performance of LDPC decoding while maintaining controllable computational complexity.

[0096] This embodiment also provides a decoding device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0097] This embodiment provides a decoding device, such as... Figure 6 As shown, it includes: The decoding module 601 is used to initialize the number of iterations, decode the data to be decoded according to the preset decoding algorithm, obtain the updated value, compare the updated value with the current corrected value, and obtain the value to be corrected under different data layers based on the comparison result. The verification module 602 is used to verify the data to be decoded according to a preset number of verification equations and obtain the verification result corresponding to the verification equations. The correction module 603 is used to obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value, obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value. The processing module 604 is used to adjust the normalization factor corresponding to the verification equation according to the number of iterations and the verification results, and to perform weighted processing on the corrected value according to the normalization factor to obtain the information between nodes. The iterative decoding module 605 is used to obtain intermediate data based on the information between nodes and the data to be decoded, use the intermediate data as the data to be decoded, increase the iteration number by a first preset step, and start executing subsequent steps from decoding the data to be decoded according to the preset decoding algorithm until all verification results pass the verification, then the iteration ends and the decoded data corresponding to the data to be decoded is obtained.

[0098] In some alternative implementations, the processing module 604 includes: The setting unit is used to set the first preset value as the normalization factor when the number of iterations is less than or equal to the second preset threshold. The first judgment unit is used to subtract the second preset step size from the normalization factor corresponding to the verification equation if the verification result of the verification equation is verification failure when the number of iterations is greater than the second preset threshold. The second judgment unit is used to increase the normalization factor corresponding to the verification equation by a second preset step size if the verification result corresponding to the verification equation is successful.

[0099] In some alternative implementations, the processing module 604 further includes: The unit is used to obtain the codeword change based on the value to be corrected and the corrected value; The adjustment unit is used to increase the value of the second preset step by the second preset value if the change in codeword is less than the third preset threshold.

[0100] In some alternative embodiments, the device further includes: The difference determination module is used to determine the difference between the data to be decoded and the intermediate data; The update module is used to update the verification result corresponding to the verification equation based on the difference.

[0101] In some alternative embodiments, the device further includes: The lookup table generation module is used to generate a mapping lookup table for the normalization factor based on the number of iterations, the verification results, and the normalization factor. The normalization factor determination module is used to obtain the current iteration number and the current verification result when the normalization factor needs to be configured, and to determine the target normalization factor based on the mapping lookup table, the current iteration number, and the current verification result.

[0102] In some alternative embodiments, the device further includes: The input module is used to input data layering and verification results into the parallel verification selector; The filtering module is used to filter the verification results using a parallel verification selector to determine the verification results corresponding to different data layers.

[0103] In some alternative embodiments, the device further includes: The data acquisition module is used to acquire the verification matrix and the number of errors, wherein a preset number of verification equations are contained in the verification matrix; The module is used to obtain decoding parameters based on the check matrix and the number of errors injected. The decoding parameters are used to configure the preset decoding algorithm.

[0104] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0105] In this embodiment, the decoding device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0106] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0107] The following is a detailed reference. Figure 7 This diagram illustrates a suitable structural schematic for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 701, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 702 or a program loaded from memory 708 into random access memory (RAM) 703. The RAM 703 also stores various programs and data required for the operation of the electronic device. The processor 701, ROM 702, and RAM 703 are interconnected via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0108] Typically, the following devices can be connected to the I / O interface 705: input devices 706 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 707 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; memory devices 708 including, for example, magnetic tape, hard disk, etc.; and communication devices 709. Communication device 709 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 7 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0109] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 709, or installed from a memory 708, or installed from a ROM 702. When the computer program is executed by the processor 701, it performs the functions defined in the decoding method of the embodiments of the present invention.

[0110] Figure 7The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0111] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described decoding method embodiments at runtime.

[0112] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0113] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described decoding method embodiments.

[0114] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described decoding method embodiments.

[0115] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0116] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] The decoding method, decoder, electronic device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A decoding method, characterized in that, The method includes: Initialize the number of iterations, decode the data to be decoded according to the preset decoding algorithm to obtain the updated value, and compare the updated value with the current corrected value. Based on the comparison result, obtain the value to be corrected under different data layers. The data to be decoded is verified according to a preset number of verification equations to obtain the verification result corresponding to the verification equations. Obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value to obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value; Based on the number of iterations and the verification results, the normalization factor corresponding to the verification equation is adjusted, and the corrected value is weighted according to the normalization factor to obtain the inter-node information. Intermediate data is obtained based on the inter-node information and the data to be decoded. The intermediate data is used as the data to be decoded. The number of iterations is increased by a first preset step. Subsequent steps are executed starting from the decoding of the data to be decoded according to the preset decoding algorithm. The iteration ends when all the verification results pass the verification. The decoded data corresponding to the data to be decoded is obtained.

2. The method according to claim 1, characterized in that, The step of adjusting the normalization factor corresponding to the verification equation based on the number of iterations and the verification result includes: If the number of iterations is less than or equal to the second preset threshold, the first preset value is set as the normalization factor; If the number of iterations is greater than the second preset threshold, and the verification result corresponding to the verification equation is a verification failure, the normalization factor corresponding to the verification equation is reduced by the second preset step size. If the verification result corresponding to the verification equation is successful, increase the normalization factor corresponding to the verification equation by a second preset step size.

3. The method according to claim 2, characterized in that, If the number of iterations exceeds the second preset threshold, the method further includes: Based on the value to be corrected and the value already corrected, the codeword change amount is obtained; If the change in codeword is less than the third preset threshold, the value of the second preset step size is increased by the second preset value.

4. The method according to claim 1, characterized in that, After obtaining intermediate data based on the inter-node information and the data to be decoded, the method further includes: Determine the difference between the data to be decoded and the intermediate data; The verification result corresponding to the verification equation is updated based on the difference.

5. The method according to claim 1, characterized in that, After adjusting the normalization factor corresponding to the verification equation based on the number of iterations and the verification result, the method further includes: Based on the number of iterations, the verification result, and the normalization factor, a mapping lookup table for the normalization factor is generated; If the normalization factor needs to be configured, the current iteration number and the current verification result are obtained, and the target normalization factor is determined based on the mapping lookup table, the current iteration number, and the current verification result.

6. The method according to claim 1, characterized in that, After verifying the data to be decoded according to a preset number of check equations and obtaining the check result corresponding to the check equation, the method further includes: The data layering and the verification results are input into the parallel verification selector; The parallel verification selector is used to filter the verification results and determine the verification results corresponding to different data layers.

7. The method according to claim 1, characterized in that, Before decoding the data to be decoded according to the preset decoding algorithm, the method further includes: Obtain the verification matrix and the number of errors, wherein a preset number of the verification equations are contained in the verification matrix; Based on the verification matrix and the error injection quantity, decoding parameters are obtained, wherein the decoding parameters are used to configure the preset decoding algorithm.

8. A decoder, characterized in that, The decoder includes: a decoding module, a variable coefficient multiplication module, an incremental check module, a normalization factor selection module, and an iteration counting module; The iteration counting module is used to initialize the number of iterations; The decoding module is used to decode the data to be decoded according to a preset decoding algorithm, obtain an updated value, compare the updated value with the current corrected value, and obtain the value to be corrected under different data layers based on the comparison result. The incremental verification module is used to verify the data to be decoded according to a preset number of verification equations, and obtain the verification result corresponding to the verification equation. The decoding module is used to obtain the current correction item, update the current correction item according to the difference between the updated value and the current corrected value to obtain the updated correction item, and correct the value to be corrected according to the updated correction item to obtain the corrected value. The normalization factor selection module is used to adjust the normalization factor corresponding to the verification equation according to the number of iterations and the verification result. The variable coefficient multiplication module is used to perform weighted processing on the corrected value according to the normalization factor to obtain inter-node information; The decoding module is used to obtain intermediate data based on the inter-node information and the data to be decoded, and to use the intermediate data as the data to be decoded. The iteration counting module is used to increase the number of iterations by a first preset step size; The decoding module is used to execute subsequent steps from the point where the data to be decoded is decoded according to the preset decoding algorithm until all the verification results pass the verification, at which point the iteration ends and the decoded data corresponding to the data to be decoded is obtained.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the decoding method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the decoding method according to any one of claims 1 to 7.

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