A high speed parallel BCH codec enhancement circuit and method for a direct digital frequency synthesis system
Patent Information
- Application Number
- CN202610994785.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-06
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]首先，在高频切换条件下，并行数据总线易受走线串扰、电源完整性波动及封装寄生参数影响，导致瞬态电平偏移，从而引入误码
[0024]首先，在结构层面，本发明采用全并行编码与并行解码结构，避免串行移位寄存器式编码带来的时延累积问题，使纠错操作能够嵌入高速并行链路而不成为性能瓶颈。其次，通过链路级时序增强单元对关键路径进行分割与逻辑重排，使高位宽BCH编码网络在GHz级时钟环境下仍可实现时序闭合，从而突破传统BCH结构难以适配高速并行链路的限制。再次，本发明将纠错结构嵌入DDS至DAC物理链路内部，在数字域内消除瞬态误码，从源头抑制因数据错误导致的DAC模拟输出杂散分量，有助于提升频率合成系统的频谱纯度与系统稳定性。此外，由于本发明支持参数化位宽配置，可根据不同应用场景灵活调整纠错能力与硬件资源消耗，实现面积、功耗与可靠性之间的工程优化平衡。综上所述，本发明不仅提供了一种适用于高速并行链路的BCH纠错结构，而且通过结构化时序增强机制解决了高频环境下逻辑深度过大的问题，具有明显的工程实用价值与推广前景。
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of high-speed digital integrated circuits and data integrity protection, specifically relating to a high-speed parallel BCH encoding and decoding enhancement circuit and method for direct digital frequency synthesis systems. Background Technology
[0002] In high-speed direct digital frequency synthesis (DDS) systems, the multi-bit parallel amplitude data output by the DDS is typically transmitted to the DAC input at clock rates exceeding hundreds of MHz or even GHz. As the system sampling rate and data bit width increase, the setup and hold time margins of the data link significantly narrow. Physical factors such as wiring parasites, power supply noise, crosstalk coupling, and clock jitter can easily lead to bit flips or transient errors. When these errors directly enter the DAC, they manifest as amplitude quantization anomalies or codeword mutations, resulting in significant spurious components at the analog output, reducing spectral purity and the system signal-to-noise ratio.
[0003] In practical engineering implementation, this high-speed parallel link faces the following physical and timing issues:
[0004] First, under high-frequency switching conditions, the parallel data bus is susceptible to trace crosstalk, power integrity fluctuations, and package parasitic parameters, which can lead to transient level shifts and introduce bit errors.
[0005] Secondly, as the bit width increases, the XOR network and data path fan-out increase significantly, leading to an increase in combinational logic depth. Critical path latency becomes the determining factor limiting the system's maximum operating frequency.
[0006] Furthermore, traditional BCH implementations often employ serial or semi-parallel shift register structures, whose inherent multi-cycle computational characteristics make them difficult to adapt to the requirements of single-cycle high-speed parallel links.
[0007] Furthermore, if occasional bit errors occur in the data link, it will directly affect the analog waveform output by the DAC, causing an increase in harmonic components, spurious enhancement, and a decrease in spurious-free dynamic range (SFDR), which will significantly degrade the signal quality from a system-level perspective.
[0008] Therefore, a structured data integrity enhancement circuit is needed specifically for high-speed parallel DDS to DAC link scenarios to improve link stability and timing margin without significantly increasing hardware area. Summary of the Invention
[0009] This invention addresses the issue that existing BCH encoding technologies, typically used in storage or communication systems, often employ serial shift register structures or iterative algorithm-based decoding structures. These implementations prioritize a balance between throughput and error correction capabilities, rather than meeting the low-latency, single-cycle requirements of ultra-high-speed parallel on-chip data links. Directly introducing traditional BCH structures into DDS-DAC links can fail to meet high-speed timing closure requirements due to excessively deep combinational logic layers, long critical paths, or high decoding delays. This invention provides a high-speed parallel BCH encoding / decoding enhancement circuit and method for direct digital frequency synthesis systems, improving data integrity while maintaining operating frequency.
[0010] To solve the above technical problems, the present invention provides the following technical solution: a high-speed parallel BCH encoding / decoding enhancement circuit for a direct digital frequency synthesis system, wherein the circuit is connected in series between the amplitude data output terminal of the direct digital frequency synthesizer and the digital signal input terminal of the digital-to-analog converter, comprising:
[0011] A parameterized configurable parallel BCH coding unit is used to receive k-bit parallel amplitude data from a direct digital frequency synthesizer, calculate r-bit parity bits through a fully parallel XOR combination network constructed based on finite field generator polynomials, and output n=k+r-bit coded data words.
[0012] A link-level timing enhancement unit is located inside the parallel BCH encoding unit and on the output path. It is used to perform logical rearrangement, critical path segmentation and register retiming processing on the fully parallel XOR combinational network, dividing it into multiple equivalent logical sub-levels to reduce the maximum combinational logic depth.
[0013] The parallel BCH decoding unit is located at the input of the digital-to-analog converter. It is used to receive the n-bit encoded data word, and through the parallel synergistic computing network, parallel error location logic and parallel correction logic, it completes automatic correction of no more than t-bit errors in a single clock cycle or a multi-stage pipeline cycle, and outputs the corrected k-bit amplitude data.
[0014] Furthermore, the aforementioned link-level timing enhancement unit employs a multi-stage adjustable pipelined register array to perform equivalent decomposition of combinational logic paths without altering the BCH generator polynomial structure, thereby reducing the maximum combinational logic level and increasing the highest clock frequency that the system can close.
[0015] Furthermore, both the aforementioned parallel BCH encoding unit and the parallel BCH decoding unit are implemented using a fully parallel combinational logic structure and do not include a serial shift register-based computation path.
[0016] Furthermore, the aforementioned codec enhancement circuit also includes a configuration register, which is used to dynamically adjust the parameters of information bit width k, parity bit number r, and error correction capability t without interrupting the operation of the system master clock.
[0017] The present invention also provides a high-speed parallel BCH encoding and decoding enhancement method for a direct digital frequency synthesis system, applied in an enhancement circuit connected in series between a direct digital frequency synthesizer and a digital-to-analog converter, comprising the following steps:
[0018] S1. Encoding Step: Receive k-bit parallel amplitude data from the direct digital frequency synthesizer, and calculate r-bit parity bits through a fully parallel XOR combination network constructed based on a finite field generator polynomial, forming an n=k+r bit encoded data word; S2. Timing Enhancement Step: During the encoding process, perform logic rearrangement, critical path segmentation, and register retiming on the fully parallel XOR combination network, dividing it into multiple equivalent logic sub-levels to reduce the maximum combinational logic depth and increase the system's highest operating frequency;
[0019] S3. Decoding steps: Receive the n-bit encoded data word, and through a parallel synergistic computing network, parallel error location logic, and parallel correction logic, complete the automatic correction of no more than t-bit errors within a single clock cycle or a multi-stage pipeline cycle, and output the corrected k-bit amplitude data to the input terminal of the digital-to-analog converter.
[0020] Furthermore, the aforementioned timing enhancement steps also include: using a multi-level configurable pipeline register array to perform equivalent decomposition of the combinational logic path without changing the BCH generator polynomial structure, so as to reduce the maximum combinational logic level.
[0021] Furthermore, both the aforementioned encoding and decoding steps are implemented using a fully parallel combinational logic structure and do not include a serial shift register-based computation path.
[0022] Furthermore, the aforementioned high-speed parallel BCH encoding and decoding enhancement method also includes a parameter configuration step: without interrupting the operation of the system master clock, the information bit width k, the number of parity bits r, and the error correction capability t are dynamically adjusted through the configuration register.
[0023] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:
[0024] First, at the structural level, this invention employs a fully parallel encoding and parallel decoding structure, avoiding the latency accumulation problem caused by serial shift register encoding, allowing error correction operations to be embedded in high-speed parallel links without becoming a performance bottleneck. Second, by segmenting and logically rearranging the critical path through a link-level timing enhancement unit, the high-bit-width BCH encoding network can still achieve timing closure in GHz-level clock environments, thus overcoming the limitation of traditional BCH structures being difficult to adapt to high-speed parallel links. Third, this invention embeds the error correction structure into the DDS within the DAC physical link, eliminating transient errors in the digital domain and suppressing spurious components in the DAC analog output caused by data errors at the source, which helps improve the spectral purity and system stability of the frequency synthesis system. Furthermore, because this invention supports parameterized bit-width configuration, the error correction capability and hardware resource consumption can be flexibly adjusted according to different application scenarios, achieving an engineering optimization balance between area, power consumption, and reliability. In summary, this invention not only provides a BCH error correction structure suitable for high-speed parallel links, but also solves the problem of excessive logic depth in high-frequency environments through a structured timing enhancement mechanism, possessing significant engineering practical value and promising prospects for widespread application. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the system-level architecture of the present invention in the high-speed parallel link from DDS to DAC;
[0026] Figure 2 This is a schematic diagram of a fully parallel BCH coding network structure;
[0027] Figure 3 This is a schematic diagram of the link-level timing enhancement unit structure;
[0028] Figure 4 This is a schematic diagram of a parallel decoding structure. Detailed Implementation
[0029] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.
[0030] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.
[0031] like Figure 1As shown, it illustrates the connection relationships between the DDS output, encoding unit, link timing enhancement unit, parallel transmission bus, decoding unit, and DAC input.
[0032] In this embodiment, the circuit of the present invention is connected in series between the amplitude output terminal of the direct digital frequency synthesizer (DDS) and the digital input terminal of the digital-to-analog converter (DAC). The DDS module outputs k-bit parallel amplitude data, which enters the BCH encoding unit under the drive of the system master clock. After encoding, it forms an n-bit encoded data word containing r parity bits, which is transmitted to the BCH decoding unit on the DAC side through the on-chip high-speed parallel link. After error correction, it is output to the DAC.
[0033] In this embodiment, assuming the DDS output bit width is 16 bits, the BCH(n,k,t) parameter is selected as (21,16,1), which adds 5 parity bits to achieve single-bit error correction capability. It should be noted that this parameter is only an example, and the present invention does not limit the specific error correction capability.
[0034] like Figure 2 As shown, it illustrates the XOR network topology based on the generator matrix expansion.
[0035] 1. Parallel BCH encoding structure implementation
[0036] The encoding unit constructs a generator matrix G based on the finite field GF(2^m) generator polynomial. Unlike the traditional serial shift register implementation, this invention expands and maps the generator matrix, transforming the parity bit calculation into an XOR combinational logic network within the Boolean field.
[0037] Specifically, each check bit is a modulo-2 linear combination of several information bits:
[0038] r_i = d_0 ⊕ d_3 ⊕ d_7 ⊕…,
[0039] Where r_i represents the i-th parity bit, i=0,1,…,r-1, d_j represents the j-th information bit, j=0,1,…,k-1, ⊕ represents the modulo-2 addition operation on the finite field GF(2), i.e., the XOR logical operation; the ellipsis indicates that the specific terms of the linear combination are determined by the position of the non-zero element in the corresponding row of the generator matrix, and each parity bit is the XOR sum of several specific information bits.
[0040] The matrix can be mapped to a multi-input XOR tree structure using synthesis tools. To avoid high fan-out and excessive logic depth, this embodiment restructures the XOR tree by balancing it, making its hierarchy close to a log2(N) structure rather than a non-linear cascade structure, thereby reducing the maximum combined path latency.
[0041] This encoding structure completes the mapping from information bits to encoded bits within one clock cycle, achieving fully parallel computation without introducing serial delay.
[0042] like Figure 3 As shown, this illustrates critical path segmentation, register retiming, and the layout of a multi-stage pipelined register array.
[0043] 2. Link-level timing enhancement structure
[0044] When the bit width increases to 32 bits or higher, the logical size of the parallel XOR network grows exponentially. If implemented directly, the critical path may become the system frequency bottleneck.
[0045] This invention achieves timing enhancement through the following structural optimization mechanism:
[0046] First, the original generator matrix is grouped by column, and the parity bit calculation is divided into multiple local sub-modules, with each sub-module processing only a portion of the information bits. Second, one or more pipeline register arrays are inserted at the output of the sub-modules to divide the long combination path into multiple short paths. Third, register retiming technology is used to distribute the registers in the middle layer of the XOR tree, rather than just at the input or output, thereby achieving balanced logic depth.
[0047] Through the above structural adjustments, the maximum combinational logic level can be reduced from the original N levels to approximately log2(N) levels, and the longest path delay can be compressed into a single-cycle clock budget.
[0048] It should be noted that the number of pipeline stages can be parameterized according to the target process and target frequency. In a 65nm process, when the target frequency is 1GHz, 2 to 3 pipeline stages can be set to meet timing closure requirements.
[0049] like Figure 4 As shown, a schematic diagram of the parallel decoding structure is presented, including a companion parallel computing network, error location logic, and a parallel correction path. The high-speed parallel BCH encoding / decoding enhancement method for direct digital frequency synthesis systems provided in this embodiment comprises the following steps:
[0050] S1. Encoding Step: Receive k-bit parallel amplitude data from the direct digital frequency synthesizer, and calculate r-bit parity bits through a fully parallel XOR combination network constructed based on a finite field generator polynomial, forming an n=k+r bit encoded data word; S2. Timing Enhancement Step: During the encoding process, perform logic rearrangement, critical path segmentation, and register retiming on the fully parallel XOR combination network, dividing it into multiple equivalent logic sub-levels to reduce the maximum combinational logic depth and increase the system's highest operating frequency;
[0051] S3. Decoding steps: Receive the n-bit encoded data word, and through a parallel synergistic computing network, parallel error location logic, and parallel correction logic, complete the automatic correction of no more than t-bit errors within a single clock cycle or a multi-stage pipeline cycle, and output the corrected k-bit amplitude data to the input terminal of the digital-to-analog converter.
[0052] 3. Parallel BCH Decoding Structure
[0053] The decoding unit is located at the input of the DAC, and its structure includes a comprehensive calculation module, an error location module, and an error correction execution module.
[0054] The synthesis module performs parallel finite field computation on the received n-bit encoded data to obtain the synthesis vector S. Similar to the encoding unit, this invention uses matrix expansion to construct the synthesis logic, enabling single-cycle or multi-stage pipeline completion.
[0055] In this embodiment, when the error correction capability is single-bit, the error location module directly determines the location of the erroneous bit by finding the mapping relationship between the synthesis and the error location. For multi-bit error correction, it can be implemented through a parallelized Chien search structure or an equivalent search network.
[0056] The error correction module flips the corresponding bits based on the location result to correct the error. The corrected k-bit data is latched in a register and then sent to the DAC input.
[0057] To avoid decoding delays affecting system throughput, this invention allows the decoding structure to adopt a pipeline configuration symmetrical to the encoding structure, keeping its delay constant and predictable.
[0058] 4. Parameterized and Configurable Implementation Methods
[0059] The circuit of this invention supports parameterized implementation. The information bit width k, the number of parity bits r, and the error correction capability t can all be set through synthesis parameters or configuration registers.
[0060] In RTL implementations, configurable structures can be implemented in the following ways:
[0061] Generate polynomials by defining parameters;
[0062] The verification matrix is automatically expanded by generating statements;
[0063] Automatically insert pipeline stages based on the target frequency;
[0064] Supports selecting different optimization strategies (area priority or speed priority) during synthesis.
[0065] This parameterization mechanism allows the present invention to be adapted to different resolution DACs (12-bit, 14-bit, 16-bit or higher) and different system frequency requirements.
[0066] 5. Explanation of the mechanism for improving system spectral performance
[0067] When a single-bit error occurs in the DDS output data during high-speed transmission, the DAC input codeword undergoes a sudden change, equivalent to an amplitude step disturbance. This disturbance manifests as a transient error in the time domain and as broadband spurious or discrete spectral lines in the frequency domain.
[0068] The real-time error correction mechanism of this invention can complete the correction before the data enters the DAC, preventing errors from propagating to the analog domain and thus reducing spurious components in the output signal. For FMCW or high linear frequency modulation systems, this improvement can enhance SFDR and system dynamic range.
[0069] The high-speed parallel BCH encoding / decoding enhancement circuit and method described in the above embodiments produce the following beneficial effects:
[0070] 1. Increase the maximum operating frequency of the high-speed DDS system;
[0071] 2. Improve the timing margin of high-speed DDS systems;
[0072] 3. Reduce the bit error rate of high-speed DDS systems;
[0073] 4. Improve the purity of the DAC output spectrum;
[0074] 5. Reduce spurious enhancement caused by occasional bit errors in high-speed DDS systems.
[0075] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A high-speed parallel BCH encoding / decoding enhancement circuit for a direct digital frequency synthesis system, characterized in that, The circuit is connected in series between the amplitude data output terminal of the direct digital frequency synthesizer and the digital signal input terminal of the digital-to-analog converter, and includes: A parameterized configurable parallel BCH coding unit is used to receive k-bit parallel amplitude data from a direct digital frequency synthesizer, calculate r-bit parity bits through a fully parallel XOR combination network constructed based on finite field generator polynomials, and output n=k+r-bit coded data words. A link-level timing enhancement unit is located inside the parallel BCH encoding unit and on the output path. It is used to perform logical rearrangement, critical path segmentation and register retiming processing on the fully parallel XOR combinational network, dividing it into multiple equivalent logical sub-levels to reduce the maximum combinational logic depth. The parallel BCH decoding unit is located at the input of the digital-to-analog converter. It is used to receive the n-bit encoded data word, and through the parallel synergistic computing network, parallel error location logic and parallel correction logic, it completes automatic correction of no more than t-bit errors in a single clock cycle or a multi-stage pipeline cycle, and outputs the corrected k-bit amplitude data.
2. The high-speed parallel BCH encoding / decoding enhancement circuit for a direct digital frequency synthesis system according to claim 1, characterized in that, The link-level timing enhancement unit employs a multi-stage adjustable pipelined register array to perform equivalent decomposition of combinational logic paths without altering the BCH generator polynomial structure, thereby reducing the maximum combinational logic level and increasing the highest clock frequency that the system can close.
3. The high-speed parallel BCH encoding / decoding enhancement circuit for a direct digital frequency synthesis system according to claim 1, characterized in that, Both the parallel BCH encoding unit and the parallel BCH decoding unit are implemented using a fully parallel combinational logic structure and do not include a serial shift register-based computation path.
4. The high-speed parallel BCH encoding / decoding enhancement circuit for a direct digital frequency synthesis system according to claim 1, characterized in that, The encoding / decoding enhancement circuit also includes a configuration register, which is used to dynamically adjust the parameters of information bit width k, parity bit number r, and error correction capability t without interrupting the operation of the system master clock.
5. A high-speed parallel BCH encoding / decoding enhancement method for direct digital frequency synthesis systems, characterized in that, For use in an enhancement circuit connected in series between a direct digital frequency synthesizer and a digital-to-analog converter, the following steps are included: S1. Encoding Step: Receive k-bit parallel amplitude data from the direct digital frequency synthesizer, and calculate r-bit parity bits through a fully parallel XOR combination network constructed based on a finite field generator polynomial, forming an n=k+r bit encoded data word; S2. Timing Enhancement Step: During the encoding process, perform logic rearrangement, critical path segmentation, and register retiming on the fully parallel XOR combination network, dividing it into multiple equivalent logic sub-levels to reduce the maximum combinational logic depth and increase the system's highest operating frequency; S3. Decoding steps: Receive the n-bit encoded data word, and through a parallel synergistic computing network, parallel error location logic, and parallel correction logic, complete the automatic correction of no more than t-bit errors within a single clock cycle or a multi-stage pipeline cycle, and output the corrected k-bit amplitude data to the input terminal of the digital-to-analog converter.
6. The high-speed parallel BCH encoding / decoding enhancement method according to claim 5, characterized in that, The timing enhancement step further includes: using a multi-level configurable pipelined register array to perform equivalent decomposition of the combinational logic path without changing the BCH generator polynomial structure, so as to reduce the maximum combinational logic level.
7. The high-speed parallel BCH encoding / decoding enhancement method according to claim 5, characterized in that, Both the encoding and decoding steps are implemented using a fully parallel combinational logic structure and do not include a serial shift register-based computation path.
8. The high-speed parallel BCH encoding / decoding enhancement method according to claim 5, characterized in that, The method also includes a parameter configuration step: without interrupting the operation of the system master clock, the parameters of information bit width k, parity bit number r, and error correction capability t are dynamically adjusted by configuring registers.