Driving circuit with non-linear compensation function and control method thereof, signal transmitter

Abstract

The present application relates to a driving circuit of a signal transmitter, and in particular to a driving circuit with a nonlinear compensation function, a control method thereof and a signal transmitter, which solves the technical problem that existing driving circuits are difficult to actively compensate for nonlinear distortion caused by a load, or have large power consumption and area overhead. The present application actively generates an asymmetric waveform complementary to the nonlinear load by independently adjusting the gate bias voltage of a P-type cascode tube and an N-type cascode tube, significantly reduces the distortion of the load output signal, and improves the signal quality. At the same time, the nonlinear compensation is realized by a pure analog circuit, only the independently adjusted gate bias voltage of the P-type cascode tube and the N-type cascode tube is needed, no digital pre-distortion or closed-loop control circuit is introduced, the structure is simple, the power consumption and area overhead are small, and it is conducive to realizing a high-speed signal transmitter.

Description

Technical Field

[0001] This invention relates to the drive circuit of a signal transmitter, specifically to a drive circuit with nonlinear compensation function, its control method, and a signal transmitter. Background Technology

[0002] With the rapid development of data centers, artificial intelligence, and 5G / 6G communication technologies, the data transmission rate of high-speed signal transmission systems has evolved to 200Gbps and even higher. In high-speed signal transmission links, the driver circuit, as the core module for signal transmission, directly determines the signal transmission quality. However, the loads driven by the driver circuit (such as optical modulators, transmission lines, and electrical channels) often have inherent nonlinear characteristics, leading to nonlinear distortion in the output signal.

[0003] Taking optical modulators as an example, the electro-optic transfer function of a micro-ring modulator is Lorentz-type. In multi-level modulation such as PAM4, the relationship between the driving voltage and the output optical power is nonlinear, resulting in uneven spacing between the four levels of the optical eye diagram and severely degrading the bit error rate. Similarly, in electrical transmission lines, the skin effect and dielectric loss also introduce nonlinear distortion, affecting signal integrity.

[0004] Currently, feedforward equalization (FFE) or digital predistortion are commonly used to compensate for nonlinearity. However, these methods require complex digital processing circuits, resulting in high power consumption, large area requirements, and limited ability to compensate for phase distortion at high speeds. Furthermore, traditional drive circuits often employ symmetrical output structures, which cannot actively complement the nonlinearity of the load, leading to limited compensation effects. Another approach is to add a closed-loop control module to dynamically lock the operating point, but this introduces significant power consumption overhead, as well as area overhead for both digital and analog chips. Therefore, there is an urgent need for a drive circuit structure capable of actively generating asymmetrical waveforms that complement the nonlinearity of the load, effectively compensating for nonlinearity while maintaining high bandwidth, and improving signal transmission quality. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems that existing drive circuits are difficult to actively compensate for nonlinear distortion caused by the load, or have large power consumption and area overhead, and to provide a drive circuit with nonlinear compensation function, its control method, and a signal transmitter.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A drive circuit with nonlinear compensation function is characterized in that it includes a first drive branch, which includes an input stage, a common source cascode output stage and an independent bias adjustment unit.

[0008] The input stage includes a P-type transistor T. IPand N-type transistor T IN The common-source cascode output stage includes a P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN ;

[0009] The P-type transistor T IP The gate and N-type transistor T IN After their gates are connected, they together serve as signal input terminals for connecting input signals;

[0010] The P-type transistor T IP The source is connected to the reference voltage VDD, and the drain is connected to a P-type cascode transistor T. CP The source of the P-type cascode transistor T CP The gate is connected to the first output terminal of the independent bias adjustment unit;

[0011] The N-type transistor T IN The source is biased to ground through the tail current source, and the drain is connected to an N-type common-source cascode transistor T. CN The source; N-type cascode transistor T CN The gate is connected to the second output terminal of the independent bias adjustment unit, and the drain is connected to the P-type cascode transistor T. CP The drain terminal is used as the drive signal output terminal to connect to the load;

[0012] The independent bias adjustment unit is used to independently adjust the output to the P-type common source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage causes the waveform of the drive signal to exhibit asymmetry in order to compensate for nonlinear distortion of the load or channel.

[0013] Furthermore, the first drive branch also includes a protection transistor unit, which includes an N-type transistor T. PN and P-type transistor T PP ;

[0014] The N-type transistor T PN Gate-connected P-type transistor T IP The gate and source are connected to the first output terminal of the independent bias adjustment unit, and the drain is connected to the P-type cascode transistor T. CP The source pole;

[0015] The P-type transistor T PP Gate-connected N-type transistor T IN The gate and source are connected to the second output terminal of the independent bias adjustment unit, and the drain is connected to the N-type cascode transistor T. CN The source pole.

[0016] Furthermore, the independent bias adjustment unit includes mutually independent bias voltage sources VBH and bias voltage source V BL ;

[0017] The bias voltage source V BH The output terminal is connected to the P-type common source cascode transistor T. CP The gate is used to supply power to the P-type cascode transistor T. CP Provides an independently adjustable gate bias voltage;

[0018] The bias voltage source V BL The output terminal is connected to the N-type common source cascode transistor T. CN The gate is used to supply power to the N-type cascode transistor T. CN Provides an independently adjustable gate bias voltage.

[0019] Furthermore, it also includes a second drive branch with the same structure as the first drive branch. The first drive branch and the second drive branch form a differential topology. The signal input terminals of the first drive branch and the second drive branch are used to input differential signals, and the drive signal output terminals are respectively connected to the two ends of the load.

[0020] Furthermore, when using a differential structure, an impedance matching unit is also included, which includes an impedance matching resistor R. t T-coil1 and T-coil2 are T-type coil inductance peaking networks.

[0021] The impedance matching resistor R t The two ends are respectively connected to one end of the T-coil1 and T-coil2 peaking networks; the middle taps of the T-coil1 and T-coil2 peaking networks are respectively connected to the P-type common source cascode transistor T in the first drive branch and the second drive branch. CP The drain of one end is used as the drive signal output terminal for the first drive branch and the second drive branch, respectively.

[0022] The present invention also provides a control method for the above-mentioned drive circuit with nonlinear compensation function, which is characterized by including the following steps:

[0023] S1. Obtain the nonlinear characteristics of the load and determine the nonlinear distortion mode of the load;

[0024] S2. Based on the nonlinear distortion mode of the load, adjust the output of the independent bias adjustment unit to the P-type common source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage causes the drive circuit to output a drive signal with an asymmetric waveform.

[0025] S3. Apply the drive signal to the load and use the complementary effect of the inherent nonlinearity of the drive signal and the load to compensate for the nonlinear distortion of the load.

[0026] Furthermore, in S2, if the nonlinear distortion mode of the load is low-level saturation nonlinearity, then the independent bias adjustment unit outputs to the P-type cascode transistor T. CP The gate bias voltage is lowered, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, so that the low-level region of the drive signal is actively compressed, forming a low-level compression mode.

[0027] If the nonlinear distortion mode of the load is high-level saturation nonlinearity, then the independent bias adjustment unit output is sent to the P-type cascode transistor T. CP The gate bias voltage is increased, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, which actively compresses the high-level region of the drive signal, forming a high-level compression mode.

[0028] Furthermore, the drive circuit with nonlinear compensation function also includes a second drive branch. In S2, the first drive branch and the second drive branch are configured differently, that is, when the first drive branch adopts a high-level compression mode, the second drive branch adopts a low-level compression mode; when the first drive branch adopts a low-level compression mode, the second drive branch adopts a high-level compression mode.

[0029] Furthermore, it also includes S4:

[0030] S4. By detecting the signal characteristics at the load output terminal, the closed-loop adjustment unit outputs to the P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage is adjusted until a uniform load output signal is obtained.

[0031] The present invention also provides a signal transmitter, comprising an input matching network, a variable gain amplifier, a continuous-time linear equalizer, an output driver stage, and an output network connected in sequence, wherein the input terminal of the input matching network is used to connect to an input signal, and the output terminal of the output network is used to connect to a load; its special feature is that:

[0032] The output drive stage is the aforementioned drive circuit with nonlinear compensation function;

[0033] When the driving circuit for the nonlinear compensation function includes a first driving branch, the output network includes a parallel AC coupling capacitor C. C And bypass switch SW, AC coupling capacitor C C One end of the bypass switch SW is connected to a P-type common source cascode transistor T.CP The drain of the capacitor is connected to the load at one end, and the bypass switch SW is used to short-circuit the AC coupling capacitor C when driving a resistive load. C Correspondingly, when the driving circuit for nonlinear compensation adopts a differential structure, the output network also adopts a differential structure, with both branches using the aforementioned structure.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The driving circuit with nonlinear compensation function provided by the present invention can actively generate an asymmetric waveform that is complementary to the nonlinearity of the load by independently adjusting the gate bias voltage of the P-type cascode transistor and the N-type cascode transistor, which significantly reduces the distortion of the load output signal and improves the signal quality.

[0036] 2. The driving circuit with nonlinear compensation function provided by the present invention achieves nonlinear compensation through pure analog circuit. It only needs to provide independently adjustable gate bias voltage for P-type cascode transistors and N-type cascode transistors. It does not introduce digital predistortion or closed-loop control circuit. The structure is simple, and the power consumption and area overhead are small, which is conducive to realizing high-speed signal transmitters.

[0037] 3. The driving circuit with nonlinear compensation function provided by the present invention adopts a protection transistor unit to ensure that the P-type common source cascode transistor and the N-type common source cascode transistor still operate within a safe voltage range under asymmetrical bias, thereby improving the reliability of the circuit.

[0038] 4. The driving circuit with nonlinear compensation function provided by the present invention has a flexible control method. It can select the corresponding mode according to the nonlinear characteristics of different loads, and has universality. It can be applied to the inherent nonlinear distortion of various nonlinear loads or electrical channels, such as optical modulators, electrical channels, and transmission lines.

[0039] 5. The signal transmitter provided by this invention has an output network integrated bypass switch, which enables the drive circuit to drive both high-resistivity and capacitive loads and resistive loads for electrical testing, making it compatible with a variety of application scenarios. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the drive circuit with nonlinear compensation function in Embodiment 1 of the present invention;

[0041] Figure 2 The diagram shows the equivalent schematic of the driving circuit with nonlinear compensation function in Embodiment 1 of the present invention, where (a) and (b) represent the high-level compression mode and the low-level compression mode, respectively.

[0042] Figure 3This is a schematic diagram of the compressed eye diagram simulation results of the driving circuit with nonlinear compensation function in Embodiment 1 of the present invention, wherein (a) and (b) are respectively using high-level compression mode and low-level compression mode;

[0043] Figure 4 This is a schematic diagram of the signal transmitter in Embodiment 1 of the present invention;

[0044] Figure 5 This is a circuit diagram of the signal transmitter output network in Embodiment 1 of the present invention;

[0045] Figure 6 This is a schematic diagram of the drive circuit with nonlinear compensation function in Embodiment 2 of the present invention;

[0046] Figure 7 This is a schematic diagram of the drive circuit with nonlinear compensation function in Embodiment 3 of the present invention. Detailed Implementation

[0047] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a driving circuit and its control method with nonlinear compensation function, as well as a signal transmitter, according to the present invention. Those skilled in the art should understand that these embodiments are merely used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] Example 1

[0049] A drive circuit with nonlinear compensation function, such as Figure 1 As shown, the system includes a first drive branch, a second drive branch, and an impedance matching unit. The first and second drive branches have identical structures, together forming a differential topology. The signal input terminals of the first and second drive branches are used to input differential signals, and the drive signal output terminals are respectively connected to the two ends of the load. The first drive branch includes an input stage, a common-source cascode output stage, a protection transistor unit, and an independent bias adjustment unit. The input stage includes a P-type transistor T... IP and N-type transistor T IN The common-source cascode output stage includes a P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN The protection transistor unit includes an N-type transistor T. PN and P-type transistor T PP The independent bias adjustment unit includes mutually independent bias voltage sources V BH and bias voltage source V BL .

[0050] P-type transistor T IPGate, N-type transistor T PN Gate, N-type transistor T IN Gate, P-type transistor T PP The gates of the two transistors are connected and together serve as the signal input terminals for connecting input signals. P-type transistor T IP The source is connected to the reference voltage VDD, and the drain is connected to the N-type transistor T. PN Drain, P-type common source cascode transistor T CP The source of the P-type cascode transistor T CP Gate, N-type transistor T PN The source is connected to the bias voltage source V. BH The output terminal.

[0051] N-type transistor T IN The source is biased to ground through the tail current source, and the drain is connected to the P-type transistor T. PP The drain of the N-type common source cascode transistor T CN The source of the N-type cascode transistor T. CN Gate, P-type transistor T PP The source is connected to the bias voltage source V. BL The output terminal of the N-type common source cascode transistor T CN Drain-connected P-type common source cascode transistor T CP The drain terminal is used as the drive signal output terminal to connect to the load.

[0052] Bias voltage source V BH Used for P-type common source cascode transistor T CP Provides an independently adjustable gate bias voltage, bias voltage source V BL Used for N-type common source cascode transistor T CN Provides an independently adjustable gate bias voltage, which is output to the P-type cascode transistor T through independent adjustment. CP and N-type common source cascode transistor T CN The gate bias voltage causes the waveform of the drive signal to exhibit asymmetry in order to compensate for nonlinear distortion of the load or channel. At the same time, the independent bias adjustment units of the first drive branch and the second drive branch perform differentiated configuration of the gate bias voltage, so that the compression direction of the output waveform of the first drive branch and the second drive branch is opposite, in order to maintain the symmetry of the differential output.

[0053] The impedance matching unit includes an impedance matching resistor R. t T-coil1 and T-coil2 are T-type coil inductance peaking networks. Impedance matching resistor R. tThe two ends are respectively connected to the input terminals of T-coil1 and T-coil2 of the T-type coil inductor peaking network; the middle taps of T-coil1 and T-coil2 are respectively connected to the P-type common source cascode transistor T in the first drive branch and the second drive branch. CP The drain and output terminals serve as the drive signal output terminals for the first and second drive branches, respectively. Impedance matching resistor R t By combining T-coil1 and T-coil2, broadband impedance matching can be achieved, making the drive circuit compatible with wired copper cable communication and chip interconnection applications.

[0054] The first and second drive branches operate on the same principle. Taking the first drive branch as an example, the N-type transistor T... IN and P-type transistor T IP The input voltage signal is converted into a current signal by biasing with a tail current source. P-type cascode transistor T CP and N-type common source cascode transistor T CN The output impedance is increased by using a cascode structure to withstand higher supply voltages. The supply voltage is shared by multiple transistors and a tail current source, ensuring a large output swing while each transistor operates within a safe voltage range. N-type transistor T PN and P-type transistor T PP When the differential input signal transitions, the transistor turns on, clamping the corresponding node voltage to the reference voltage to prevent transistor breakdown. Specifically, when the input is low, the output node is pulled up, and the N-type transistor T... PN Turn on the N-type cascode transistor T CN The source is clamped to prevent the N-type cascode transistor T from being clamped. CN The source-drain voltage is too high; when the input is high, the output node is pulled down, and the P-type transistor T... PP Turn on, turning on the P-type cascode transistor T CP The source is clamped to prevent the P-type cascode transistor T from being clamped to the source. CP The source-drain voltage is too high.

[0055] In traditional Cascode drive circuits, the gate bias of both P-type and N-type Cascode transistors is typically set to 1 / 2 VDD, resulting in a symmetrical output waveform that cannot actively compensate for load nonlinearity. This embodiment proposes a separate bias scheme, where the gate bias of the P-type Cascode transistor T is adjusted independently. CP and N-type common source cascode transistor T CN The gate bias voltage causes the drive signal waveform to become asymmetrical, which complements the nonlinearity of the load.

[0056] The equivalent schematic diagram of the drive circuit with nonlinear compensation function provided in this embodiment is as follows: Figure 2 As shown, the simulation results of the compressed eye diagram are as follows: Figure 3 As shown. In high-level compression mode, as Figure 2 As shown in (a), when the P-type cascode transistor T CP The gate bias voltage is increased (e.g., set to 3 / 4 VDD), and the N-type cascode transistor T... CN When the gate bias voltage remains constant (still 1 / 2 VDD), the input signal is low, and the P-type transistor T... IP On, N-type transistor T IN Shut down. Due to the P-type common source cascode transistor T CP Increased on-resistance leads to voltage division with the load resistance, making it difficult for the output node voltage to rise to a normal high level, resulting in active compression of the rising edge. The simulation results of the compressed eye diagram are as follows: Figure 3 As shown in (a), at this time, in the PAM4 eye diagram output by the driving circuit, the high level amplitude is compressed to about 0.4V, and the low level reaches 1.2V, forming a clear high-level compressed waveform.

[0057] In low-level compression mode, such as Figure 2 As shown in (b), when the N-type cascode transistor T... CN When the gate bias voltage of the N-type transistor is reduced (e.g., set to 1 / 4 VDD) and the gate bias of the P-type cascode transistor remains unchanged (still 1 / 2 VDD), the input signal is high, and the N-type transistor T... IN On, P-type transistor T IP Off. N-type common source cascode transistor T CN The increased on-resistance makes it difficult to pull the output node voltage down to a normal low level, resulting in active compression of the falling edge. Simulation results are as follows: Figure 3 As shown in (b), in the PAM4 eye diagram output by the driving circuit at this time, the low level amplitude is compressed to about 0.4V, and the high level reaches 1.2V, forming a clear low-level compressed waveform.

[0058] This embodiment also provides a control method for the above-mentioned drive circuit with nonlinear compensation function, including the following steps:

[0059] S1. Obtain the nonlinear characteristics of the load and determine the nonlinear distortion mode of the load.

[0060] S2. Based on the nonlinear distortion mode of the load, adjust the output of the independent bias adjustment unit to the P-type common source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage causes the drive circuit to output a drive signal with an asymmetric waveform.

[0061] In S2, if the nonlinear distortion mode of the load is low-level saturation nonlinearity, then the independent bias adjustment unit outputs to the P-type cascode transistor T. CP The gate bias voltage is lowered, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, so that the low-level region of the drive signal is actively compressed, forming a low-level compression mode.

[0062] If the nonlinear distortion mode of the load is high-level saturation nonlinearity, then the independent bias adjustment unit output is sent to the P-type cascode transistor T. CP The gate bias voltage is increased, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, which actively compresses the high-level region of the drive signal, forming a high-level compression mode.

[0063] Meanwhile, differentiated configurations are adopted for the first drive branch and the second drive branch to keep the differential output symmetrical. That is, when the first drive branch adopts the high-level compression mode, the second drive branch adopts the low-level compression mode; when the first drive branch adopts the low-level compression mode, the second drive branch adopts the high-level compression mode.

[0064] S3. Apply the drive signal to the load and use the complementary effect of the inherent nonlinearity of the drive signal and the load to compensate for the nonlinear distortion of the load.

[0065] S4. By detecting the signal characteristics at the load output terminal, the closed-loop adjustment unit outputs to the P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage is adjusted until a uniform output signal is obtained at the load output terminal.

[0066] Through the above bias adjustment, the drive circuit can accurately generate a compressed waveform that matches the nonlinear characteristics of the load, thereby achieving nonlinear compensation and significantly improving the uniformity of the load output signal.

[0067] This embodiment also provides a signal transmitter, such as Figure 4 As shown, the circuit includes an input matching network, a variable gain amplifier, a continuous-time linear equalizer, an output driver stage, and an output network connected in sequence. The input terminal of the input matching network is used to connect to the input signal, and the output terminal of the output network is used to connect to the load. The output driver stage is the aforementioned driver circuit with nonlinear compensation function.

[0068] The input matching network employs a T-coil structure for broadband impedance matching. A variable gain amplifier based on a Cherry-Hooper structure adjusts the gain to ensure link linearity. A continuous-time linear equalizer compensates for link bandwidth. The output driver stage drives the load, providing sufficient drive amplitude while achieving non-linear adjustment. The signal transmitter and load can be packaged using gold wire bonding or copper pillar flip-chip technology.

[0069] The output network is used to adapt to different types of loads, such as Figure 5 As shown, the output network adopts a differential structure, with the two branches having identical structures. Each branch includes a parallel AC coupling capacitor C. C And bypass switch SW, AC coupling capacitor C C One end of the bypass switch SW is connected to the output terminal of either the T-coil1 or T-coil2 T-coil inductor peaking network, and the other end is connected to the load. The bypass switch SW is used to short-circuit the AC coupling capacitor C when driving a resistive load. C When a signal transmitter is used to drive an optical modulator, the output network's accompanying circuitry also includes a resistor R. C Inductor L Bump and capacitor C Pad resistance R C One end is connected to the bias voltage required by the optical modulator, and the other end is connected to the AC coupling capacitor C. C The other end, inductor L Bump one end and capacitor C Pad One end of the capacitor C Pad The other end is grounded, inductor L Bump The other end is used to connect the load. When driving a high resistive-capacitive load, the bypass switches SW of both branches are open, and the modulation signal passes through the AC coupling capacitor C. C Coupled to the load; when performing electrical tests while driving a resistive load, the bypass switches SW of both branches are closed, short-circuiting the AC coupling capacitor C. C This eliminates the low-frequency cutoff effect and makes the drive circuit compatible with wired communication applications.

[0070] Example 2

[0071] The difference between this embodiment and Embodiment 1 is that this embodiment uses a single-ended drive structure, such as... Figure 6 As shown, only the first drive branch is included, and the P-type common source cascode transistor T is adjusted independently. CP and N-type common source cascode transistor T CN The gate bias voltage enables asymmetric compression of the drive signal waveform, compensating for load nonlinearity.

[0072] Example 3

[0073] like Figure 7 As shown, this embodiment, based on embodiment two, removes the protection transistor unit, simplifies the circuit structure, and can still achieve nonlinear compensation function when the required driving voltage is small.

Claims

1. A drive circuit with nonlinear compensation function, characterized in that: The first drive branch includes an input stage, a common source cascode output stage, and an independent bias adjustment unit. The input stage includes a P-type transistor T. IP and N-type transistor T IN The common-source cascode output stage includes a P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN ; The P-type transistor T IP The gate and N-type transistor T IN After their gates are connected, they together serve as signal input terminals for connecting input signals; The P-type transistor T IP The source is connected to the reference voltage VDD, and the drain is connected to a P-type cascode transistor T. CP The source of the P-type cascode transistor T CP The gate is connected to the first output terminal of the independent bias adjustment unit; The N-type transistor T IN The source is biased to ground through the tail current source, and the drain is connected to an N-type common-source cascode transistor T. CN The source; N-type cascode transistor T CN The gate is connected to the second output terminal of the independent bias adjustment unit, and the drain is connected to the P-type cascode transistor T. CP The drain terminal is used as the drive signal output terminal to connect to the load; The independent bias adjustment unit is used to independently adjust the output to the P-type common source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage causes the waveform of the drive signal to exhibit asymmetry in order to compensate for nonlinear distortion of the load or channel.

2. The drive circuit with nonlinear compensation function according to claim 1, characterized in that: The first drive branch also includes a protection transistor unit, which includes an N-type transistor T. PN and P-type transistor T PP ; The N-type transistor T PN Gate-connected P-type transistor T IP The gate and source are connected to the first output terminal of the independent bias adjustment unit, and the drain is connected to the P-type cascode transistor T. CP The source pole; The P-type transistor T PP Gate-connected N-type transistor T IN The gate and source are connected to the second output terminal of the independent bias adjustment unit, and the drain is connected to the N-type cascode transistor T. CN The source pole.

3. The drive circuit with nonlinear compensation function according to claim 2, characterized in that: The independent bias adjustment unit includes mutually independent bias voltage sources V BH and bias voltage source V BL ; The bias voltage source V BH The output terminal is connected to the P-type common source cascode transistor T. CP The gate is used to supply power to the P-type cascode transistor T. CP Provides an independently adjustable gate bias voltage; The bias voltage source V BL The output terminal is connected to the N-type common source cascode transistor T. CN The gate is used to supply power to the N-type cascode transistor T. CN Provides an independently adjustable gate bias voltage.

4. The drive circuit with nonlinear compensation function according to any one of claims 1-3, characterized in that: It also includes a second drive branch with the same structure as the first drive branch. The first drive branch and the second drive branch form a differential topology. The signal input terminals of the first drive branch and the second drive branch are used to input differential signals, and the drive signal output terminals are respectively connected to the two ends of the load.

5. The drive circuit with nonlinear compensation function according to claim 4, characterized in that: It also includes an impedance matching unit, which includes an impedance matching resistor R. t T-coil1 and T-coil2 are T-type coil inductance peaking networks. The impedance matching resistor R t The two ends are respectively connected to one end of the T-coil1 and T-coil2 peaking networks; the middle taps of the T-coil1 and T-coil2 peaking networks are respectively connected to the P-type common source cascode transistor T in the first drive branch and the second drive branch. CP The drain of one end is used as the drive signal output terminal for the first drive branch and the second drive branch, respectively.

6. A control method for a drive circuit with nonlinear compensation function as described in any one of claims 1-5, characterized in that, Includes the following steps: S1. Obtain the nonlinear characteristics of the load and determine the nonlinear distortion mode of the load; S2. Based on the nonlinear distortion mode of the load, adjust the output of the independent bias adjustment unit to the P-type common source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage causes the drive circuit to output a drive signal with an asymmetric waveform. S3. Apply the drive signal to the load and use the complementary effect of the inherent nonlinearity of the drive signal and the load to compensate for the nonlinear distortion of the load.

7. The control method for a drive circuit with nonlinear compensation function according to claim 6, characterized in that: In S2, if the nonlinear distortion mode of the load is low-level saturation nonlinearity, then the independent bias adjustment unit outputs to the P-type cascode transistor T. CP The gate bias voltage is lowered, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, so that the low-level region of the drive signal is actively compressed, forming a low-level compression mode. If the nonlinear distortion mode of the load is high-level saturation nonlinearity, then the independent bias adjustment unit output is sent to the P-type cascode transistor T. CP The gate bias voltage is increased, and the independent bias adjustment unit outputs to the N-type cascode transistor T. CN The gate bias voltage remains constant, which actively compresses the high-level region of the drive signal, forming a high-level compression mode.

8. The control method for a drive circuit with nonlinear compensation function according to claim 7, characterized in that: The driving circuit with nonlinear compensation function also includes a second driving branch. In S2, the first driving branch and the second driving branch are configured differently. That is, when the first driving branch adopts a high-level compression mode, the second driving branch adopts a low-level compression mode; when the first driving branch adopts a low-level compression mode, the second driving branch adopts a high-level compression mode.

9. The control method for a drive circuit with nonlinear compensation function according to any one of claims 6-8, characterized in that, Also includes S4: S4. By detecting the signal characteristics at the load output terminal, the closed-loop adjustment unit outputs to the P-type common-source cascode transistor T. CP and N-type common source cascode transistor T CN The gate bias voltage is adjusted until a uniform load output signal is obtained.

10. A signal transmitter, comprising an input matching network, a variable gain amplifier, a continuous-time linear equalizer, an output driver stage, and an output network connected in sequence, wherein the input terminal of the input matching network is used to connect to an input signal, and the output terminal of the output network is used to connect to a load; characterized in that: The output drive stage is a drive circuit with nonlinear compensation function as described in any one of claims 1-5; The output network includes parallel AC coupling capacitors C C And bypass switch SW, AC coupling capacitor C C One end of the bypass switch SW is connected to a P-type common source cascode transistor T. CP The drain of the capacitor is connected to the load at one end, and the bypass switch SW is used to short-circuit the AC coupling capacitor C when driving a resistive load. C .

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