A mixer-preferred dual-mode reconfigurable radio frequency receiving front end, receiving system and working method

Abstract

The application discloses a mixer-preferred dual-mode reconfigurable radio frequency receiving front end, a receiving system and a working method, comprising a common radio frequency input, two passive mixing branches, a local oscillator selection circuit, two mixing post-processing circuits and a mode control circuit; in a data receiving mode, a polyphase local oscillator drives the two mixing branches, a shared transimpedance core and a second mixing post-processing circuit respectively perform I / Q linear transimpedance conversion, and a rectification branch is isolated; in a wake-up receiving mode, a differential local oscillator drives a first mixing branch, a second branch is closed, a bias of the shared transimpedance core, equivalent device size or load state is adjusted and an active rectification branch is accessed, and signals with envelope information are down-converted and rectified. The application multiplexes radio frequency inputs, mixing branches and mixing post-analog cores, replaces two originally independent radio frequency front ends with one hardware circuit, eliminates hardware redundancy from the root, and takes into account linear data receiving and low-power wake-up detection.

Description

Technical Field

[0001] This invention relates to the fields of radio frequency integrated circuits and low-power wireless receiver technology, and particularly to a mixer-priority dual-mode reconfigurable radio frequency receiver front-end, a receiver system including the front-end, and a method for operating the same. Background Technology

[0002] IoT sensor nodes, wearable devices, and distributed wireless terminals are typically powered by batteries with limited capacity. Because communication arrival times are difficult to predict, continuously keeping the main radio frequency receiver on to listen to the channel can result in significant idle listening power consumption.

[0003] A wake-up receiver (WuRX) can continuously or periodically listen for low-speed wake-up signals while the main receiver is in sleep mode, and start the main receiver upon detecting a valid wake-up sequence. To balance sensitivity and power consumption, existing wake-up receivers employ envelope detection, self-mixing, low-IF, or uncertain-IF architectures; the main data receiver, on the other hand, typically requires good linearity, noise performance, and quadrature demodulation capabilities.

[0004] Because data reception and wake-up monitoring have different requirements for linearity, bandwidth, noise, and power consumption, common implementations configure separate main receive paths and wake-up receive paths. Another approach is to share antenna interfaces, matching networks, or parts of the mixer for both, but the analog processing chain after mixing may still be set up separately, increasing chip area, bias circuitry, load networks, and the number of interfaces.

[0005] The mixer-first receiver architecture connects a passive mixer directly or via a simplified matching network to the RF input and utilizes a low-input-impedance transimpedance circuit after the mixer to achieve frequency conversion, impedance matching, and baseband filtering. This architecture is suitable for achieving high linearity at low power consumption; however, the I / Q transimpedance stage in existing mixer-first data receivers is typically used for linear processing, and the rectification or envelope detection stage in existing wake-up receivers is usually set up as a separate circuit. There is still room for improvement in how to make the same circuit satisfy both linear quadrature data reception and nonlinear wake-up detection without replicating the post-mixer analog core. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a mixer-priority dual-mode reconfigurable RF receiver front end, which enables the common RF input and at least part of the mixed analog core to be multiplexed between data reception mode and wake-up reception mode, and enables the shared core to perform linear differential transimpedance conversion in one mode and participate in nonlinear active rectification or envelope detection in another mode by coordinating the switching of local oscillator source, signal branch, bias state and rectifier load.

[0007] To address the aforementioned technical problems, this invention provides a dual-mode reconfigurable radio frequency (RF) receiver front end, comprising a common RF input, first and second passive mixer branches, a local oscillator selection circuit, first and second mixer post-processing circuits, and a mode control circuit. The first mixer post-processing circuit includes a shared transimpedance core and an selectable active rectifier branch.

[0008] In the first operating mode, the mode control circuit selects the first local oscillator group, which includes multiphase signals, to drive the first and second passive mixing branches. The shared transimpedance core in the first mixing post-processing circuit and the second mixing post-processing circuit respectively perform linear transimpedance conversion on the two mixed signals. The active rectifier branch is isolated, thereby forming an orthogonal data receiving path.

[0009] In the second operating mode, the mode control circuit selects the second local oscillator group including the differential signal to drive the first passive mixer branch, shuts down the second passive mixer branch or the second mixer post-processing circuit, and changes at least one of the bias state, equivalent device size and load state of the shared transimpedance core. At the same time, it connects the active rectification branch to form a nonlinear active rectification path to recover the envelope or baseband wake-up signal from the RF input signal.

[0010] Preferably, the first local oscillator group is a four-phase local oscillator signal generated by buffering and frequency division of an external local oscillator, and the second local oscillator group is a differential local oscillator signal generated by an on-chip oscillator. The term "external" refers to something outside the core of the RF front-end, which can be other modules located on the same chip or provided by an external signal source.

[0011] Preferably, the shared transimpedance core includes a common-gate or low-input-impedance differential current input stage, a current mirror stage, a folded self-biased load, and an RC low-pass network; the active rectifier branch includes a rectifier transistor driven by the differential output of the shared transimpedance core, a controllable bias transistor, a load capacitor, and an adjustable load resistor.

[0012] Preferably, the mode control circuit also adjusts at least one of the input stage, current mirror, bias transistor, rectifier transistor, and load resistor. The adjustable device may consist of parallel units controlled by binary weighting or thermometer codes to optimize linearity, noise, power consumption, input matching, gain, and rectification efficiency in both modes, and to compensate for process, supply voltage, and temperature variations.

[0013] The present invention also provides a method for operating a dual-mode reconfigurable radio frequency receiver front end: in response to a first mode command, a multi-phase local oscillator is selected, two passive mixing branches are enabled, two transimpedance circuits are set to a linear state and the rectifier branch is isolated; in response to a second mode command, a differential local oscillator is selected, the second branch is turned off, the shared transimpedance core is set to a low-power or high nonlinear state and connected to the rectifier branch.

[0014] This invention also provides a dual-mode radio frequency receiving system. In wake-up monitoring mode, the system operates the shared transimpedance core and the active rectifier branch, making a wake-up decision based on the rectified output; upon detecting a valid wake-up signal, it switches to a two-channel orthogonal linear data receiving mode.

[0015] Compared to the scheme of setting up two separate sets of analog chains after mixing by only sharing antennas or matching networks, the present invention reuses the first passive mixer branch and the subsequent shared transimpedance core, and uses the active rectifier branch as an optional incremental circuit, which can reduce the number of redundant transimpedance input stages, bias and load units.

[0016] Since the local oscillator source, Q-path enable, shared core bias, and rectifier load are switched collaboratively by the mode control circuit, the first mode can maintain orthogonal linear reception, while the second mode can reduce the activity of branches that do not participate in wake-up detection and enable the low-IF signal to drive the rectifier after the shared core gain, thereby improving the detectable output amplitude under low input signal conditions.

[0017] By using an adjustable device array and an adjustable RC load, this invention can also calibrate the input impedance, transimpedance gain, noise, and rectified output time constant for both modes, reducing the impact of PVT variations on dual-mode operation.

[0018] The present invention will be further described below with reference to specific embodiments. Attached Figure Description

[0019] Figure 1 This is a block diagram of the overall structure of the dual-mode reconfigurable radio frequency receiver front-end of the present invention.

[0020] Figure 2 This is a schematic diagram of a transistor-level circuit according to an embodiment of the present invention.

[0021] Figure 3 This is a curve showing the input reflection coefficient in data receiving mode according to an embodiment of the present invention.

[0022] Figure 4 This is a curve showing the input reflection coefficient in wake-up receiving mode according to an embodiment of the present invention.

[0023] Figure 5 This is a noise figure curve for an embodiment of the present invention in wake-up receiving mode.

[0024] Figure 6 This is a conversion gain result curve in wake-up receiving mode according to an embodiment of the present invention.

[0025] Figure 7 This is a flowchart of the mode control process for the dual-mode radio frequency receiving system of the present invention. Detailed Implementation

[0026] Example

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0029] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0030] like Figure 1 As shown, the mixer-priority dual-mode reconfigurable RF receiver front-end provided by this solution includes a common RF input, a first passive mixer branch, a second passive mixer branch, a local oscillator selection circuit, a first mixer post-processing circuit, a second mixer post-processing circuit, and a mode control circuit.

[0031] For ease of description, the first branch is called the I-path and the second branch is called the Q-path. This naming does not limit the absolute phase of the branches, as long as the two branches can form orthogonal or polyphase linear reception in the first operating mode.

[0032] A common RF input is used to receive RF input signals. This common RF input can be connected to an antenna or RF test terminal via an external inductor L. The external inductor L, along with the input parasitic capacitance, the mixer switch on-resistance, and the equivalent impedance after mixing, forms the input matching. In other implementations, an on-chip inductor, transformer, acoustic resonator, adjustable capacitor network, or a combination thereof can be used to replace the external inductor without altering the fundamental relationship of the common RF input being multiplexed by two modes.

[0033] The RF terminals of both the first and second passive mixing branches are connected to the common RF input. Specifically, in this embodiment, the first passive mixing branch includes a pair of mixing switches NI1 and NI2, and the second passive mixing branch includes a pair of mixing switches NQ1 and NQ2. The RF terminals of NI1, NI2, NQ1, and NQ2 are connected to the common RF input, and the baseband or intermediate frequency terminals respectively form two differential current paths. The mixing switches can be NMOS, PMOS, complementary transmission gates, or switching devices suitable for the corresponding process technology.

[0034] Taking an NMOS mixer switch as an example, its gate receives the bias voltage VDDH through bias resistors RPI, RNI, RPQ, and RNQ, and receives the corresponding local oscillator signal through coupling capacitors CPI, CNI, CPQ, and CNQ. The bias network superimposes the AC swing of the local oscillator onto the DC bias and can adjust the on-resistance of the mixer switch. Capacitors CI1 and CQ1 can be set between the differential intermediate frequency nodes for baseband filtering, charge-hold, or stabilizing the differential common mode.

[0035] The local oscillator selection circuit is used to select the local oscillator signal between a first local oscillator group and a second local oscillator group. The first local oscillator group includes a multiphase signal for quadrature downconversion, and the second local oscillator group includes a pair of differential signals.

[0036] In this embodiment, the local oscillator selection circuit receives a first local oscillator group and a second local oscillator group. In this embodiment, the first local oscillator group can be generated by a 4.8 GHz external clock through a buffer and a divider to produce four-phase signals LOPI, LONI, LOPQ, and LONQ; the second local oscillator group can be generated by an on-chip local oscillator to produce differential signals LOP and LON. Switches SPI, SNI, SP, SN, or equivalent transmission gates selectively connect the first or second local oscillator group to the I-channel mixer switch control terminal. The Q-channel receives LOPQ and LONQ in the first mode and does not receive valid local oscillators or is turned off in the second mode.

[0037] A first mixer post-processing circuit is connected to the intermediate frequency terminal of the first passive mixer branch. The first mixer post-processing circuit includes a shared transimpedance core and an active rectifier branch that can be selectively coupled to the shared transimpedance core.

[0038] The second post-mixing processing circuit is connected to the intermediate frequency terminal of the second passive mixer branch and is used for linear transimpedance conversion.

[0039] The shared transimpedance core of the first mixer post-processing circuit is connected to the intermediate frequency terminals of NI1 and NI2. Figure 2 In the illustrated embodiment, the shared transimpedance core includes PMOS transistors PI1-PI6, PI9, and PI10, NMOS transistors NI3-NI6, resistors RI1 and RI2, and capacitors CI2 and CI3. PI1-PI4 form a differential low input impedance current buffer / common gate input stage, PI5, PI6, and NI3-NI6 form a bias and current mirror stage, and PI9 and PI10, along with RI1 and RI2, form a folded self-biased load. TIAOUTIP and TIAOUTIN are the two differential output nodes of the shared transimpedance core, and CI2 and CI3 form a low-pass response with their respective loads.

[0040] The second post-mixer circuit connects to the intermediate frequency terminals of NQ1 and NQ2 and can adopt a structure that is basically symmetrical to the shared transimpedance core. It includes PMOS transistors PQ1-PQ6, PQ9, and PQ10, NMOS transistors NQ3-NQ6, resistors RQ1 and RQ2, and capacitors CQ2 and CQ3, and outputs TIAOUTQP and TIAOUTQN. The symmetrical structure is beneficial for obtaining similar gain, bandwidth, and phase characteristics for the I / Q paths in the first mode.

[0041] The active rectifier branch is located on the shared transimpedance core side, instead of being replicated in the Q path. In one embodiment, the active rectifier branch includes PMOS rectifier diodes PI7 and PI8, an NMOS controllable bias transistor NI7, a load capacitor CI6, an adjustable load resistor R3, and mode switches S1, S1B, S2, and S3. The control terminals of PI7 and PI8 are driven by TIAOUTIP and TIAOUTIN, respectively, thus receiving the differential low-IF signal amplified by the shared transimpedance core; the co-current rectified current generated by PI7 and PI8 is selectively fed into RectifierOUT via S2 and S3. CI6 integrates the rectified current, and R3 provides a discharge path and, together with CI6, determines the envelope output bandwidth.

[0042] S1 and S1B represent a set of complementary controlled connections and do not need to be two physical switches with the same name. In the first mode, this set of switches puts NI7 in a cutoff or near-cutoff state; in the second mode, it connects the control terminal of NI7 to the corresponding bias, enabling NI7 to provide the bias or current loop required by the rectifier branch. S2 and S3 are open in the first mode to isolate the rectifier load, and closed or turned on in a predetermined combination in the second mode, allowing the rectified current to flow into RectifierOUT. The switch polarity can be reversed depending on the transistor type and level definition, as long as the same functional state is achieved.

[0043] The mode control circuit is connected to the local oscillator selection circuit, the first mixer post-processing circuit, and the second mixer post-processing circuit.

[0044] In the first working mode, the mode control circuit enables the first local oscillator group to drive the first passive mixer branch and the second passive mixer branch, and enables the shared transimpedance core and the second mixer post-processing circuit to perform linear transimpedance conversion on the two mixed signals respectively, and isolates the active rectifier branch from the shared transimpedance core.

[0045] In the second operating mode, the mode control circuit causes the second local oscillator group to drive the first passive mixer branch, causing the second passive mixer branch or the second mixer post-processing circuit to stop signal processing. By changing the bias state, equivalent device size and load state of the shared transimpedance core, the shared transimpedance core and the active rectifier branch are made to form a nonlinear active rectifier path, so as to output an envelope signal or baseband wake-up signal from the RF input signal.

[0046] The common RF input is connected to the antenna terminal through a matching network, which includes an off-chip inductor, an adjustable capacitor network, or a combination thereof. The first passive mixer branch and the second passive mixer branch reuse the matching network. The first local oscillator group includes four-phase local oscillator signals with a phase difference of 90°, generated by an external local oscillator signal via a buffer and a frequency divider. The second local oscillator group is generated by an on-chip oscillator. The local oscillator selection circuit includes a transmission gate or a MOS switch for selectively coupling the four-phase local oscillator signal or the differential local oscillator signal to the control terminal of the switch transistor of the corresponding passive mixer branch. The first passive mixer branch and the second passive mixer branch respectively include a first pair of mixer switches and a second pair of mixer switches. The control terminal of each mixer switch receives the local oscillator signal through an AC coupling capacitor and receives a DC bias voltage through a bias resistor to adjust the on-resistance of the mixer switch and the equivalent input impedance of the common RF input.

[0047] The shared transimpedance core includes a differential current input stage, a current mirror stage, and a self-biased load stage. The differential current input stage receives the differential intermediate frequency current output from the first passive mixer branch. The self-biased load stage includes a resistor network connected between two differential output nodes. The two differential output nodes are grounded through filter capacitors to form transimpedance amplification and low-pass filtering functions.

[0048] The active rectifier branch includes a first rectifier transistor, a second rectifier transistor, a controllable bias transistor, a load capacitor, and an adjustable load resistor. The control terminals of the first rectifier transistor and the second rectifier transistor are respectively driven by the two differential output nodes of the shared transimpedance core. The rectified current generated by the first rectifier transistor and the second rectifier transistor is fed into the rectifier output node under the control of the mode switch, and forms the envelope signal or baseband wake-up signal on the load capacitor and the adjustable load resistor.

[0049] The mode switch includes a first switch group controlled by a complementary mode control signal and a second switch group for connecting or isolating the active rectifier branch from the load capacitor and the adjustable load resistor. The complementary mode control signals are provided with non-overlapping time periods to suppress shoot-through current and local oscillator crosstalk during mode switching.

[0050] In the first operating mode, the second mixer post-processing circuit and the shared transimpedance core have a symmetrical differential transimpedance structure. The first local oscillator group simultaneously drives the first passive mixer branch and the second passive mixer branch. The shared transimpedance core and the second mixer post-processing circuit are both in a linear bias state. The rectifier transistor and its controllable bias transistor of the active rectifier branch are turned off, and the active rectifier branch is isolated from the rectifier output node. The first mixer post-processing circuit and the second mixer post-processing circuit output in-phase differential intermediate frequency signals and quadrature differential intermediate frequency signals, respectively.

[0051] In the second operating mode, the second local oscillator group drives the first passive mixer branch to downconvert the RF input signal with envelope information into a low intermediate frequency or ultra-low intermediate frequency signal. The quadrature branch is shut down by at least one of stopping the local oscillator of the second passive mixer branch, turning off the bias of the second mixer post-processing circuit, and cutting off the power supply of the second mixer post-processing circuit. The shared transimpedance core operates at a lower quiescent current than in the first operating mode and drives the active rectifier branch to perform envelope detection.

[0052] At least one of the input transistor, current mirror transistor, bias transistor, rectifier transistor of the active rectifier branch, and adjustable load resistor in the shared transimpedance core is composed of multiple units that can be selectively connected in parallel. These multiple units can be configured as a binary weighted array, a thermometer code array, or a combination thereof, to adjust the equivalent device size, bias current, transimpedance gain, rectification efficiency, noise figure, or input impedance under the control of a digital calibration word. The digital calibration word is generated based on process corner, power supply voltage, temperature, input matching, output amplitude, or bit error detection results.

[0053] In this scheme, the first working mode is a data receiving mode, and the second working mode is a wake-up receiving mode; the data receiving mode is used to receive frequency shift keying, phase shift keying or quadrature amplitude modulation signals, and the wake-up receiving mode is used to receive on / off keying, amplitude shift keying or wake-up signals with detectable envelopes.

[0054] Specifically, in this embodiment, in the first operating mode, i.e., the data reception RX mode, the mode control circuit selects an external four-phase local oscillator and enables NI1, NI2, NQ1, NQ2, and two transimpedance biases. The I-channel and Q-channel mixer switches down-convert the RF signal into two quadrature differential intermediate frequency currents. The shared transimpedance core and the second mixer post-processing circuit perform current-to-voltage conversion in the linear bias region and output TIAOUTIP / TIAOUTIN and TIAOUTQP / TIAOUTQN respectively. Rectifier diodes PI7 and PI8 and bias diode NI7 are turned off, and S2 and S3 isolate RectifierOUT to prevent the rectifier load from reducing the gain or bandwidth of the linear mode.

[0055] The first mode can be used for Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), Phase Shift Keying (PSK), Quadrature Amplitude Modulation (QAM), or other signals requiring linear I / Q demodulation. Subsequent baseband components may include programmable gain amplifiers, filters, analog-to-digital converters, and digital demodulators; these subsequent modules are not essential limitations of the front-end of this invention.

[0056] In the second operating mode, namely the wake-up receiver WuRX mode, the mode control circuit selects the on-chip differential local oscillator LOP and LON and couples them to NI1 and NI2. The Q-channel local oscillator is gated, and / or the Q-channel bias and power supply are turned off. The RF signal with OOK, ASK, or other envelope information is down-converted to low-IF or ultra-low-IF differential current via the I-channel and enters the shared transimpedance core.

[0057] In the second mode, the shared transimpedance core reduces the quiescent current of the current mirror and bias stage, and alters the equivalent width-to-length ratio of PI1-PI4 by connecting parallel device units, enabling the input stage to operate in the subthreshold region, deep subthreshold region, or other operating regions suitable for low power consumption and high transconductance. The shared transimpedance core continues to provide low input impedance and pre-gain, and its differential output drives PI7 and PI8 to generate nonlinear rectified current. Therefore, the so-called "reconfiguration to active rectification" does not mean that the entire TIA is bypassed or discarded, but rather that the bias / size / load state of the shared transimpedance core changes, forming an envelope detection path together with the newly added active rectification branch.

[0058] R3 and CI6 determine the response speed, ripple, and hold time of RectifierOUT. For lower OOK bit rates, R3 or CI6 can be increased to improve the integral gain; for higher bit rates, the equivalent time constant can be decreased to improve rise / fall times. R3 can be implemented using a 3-bit binary weighted resistor array, or it can be implemented using any number of bits, thermometer code, MOS pseudo-resistors, or continuously adjustable transconductance devices.

[0059] PI7, PI8, and at least a portion of PI1-PI6 and NI3-NI7 may employ selectable parallel transistor cells. The mode controller or calibration controller selects the number of cells via a digital calibration word to change the effective aspect ratio and bias current.

[0060] In one implementation, PI7, PI8, RI1, RI2, and R3 all use a 3-bit binary weighted array; however, 3-bit is merely an example and does not limit the invention.

[0061] Calibration can be performed at the factory, upon power-on, during temperature transitions, or during reception. Calibration objectives may include: ensuring the input reflection coefficients of both modes meet thresholds; ensuring RectifierOUT reaches a target level with a known calibration signal; reducing I / Q channel gain difference and phase error; or reducing quiescent current while maintaining sensitivity. The calibration word can be stored in a fuse, non-volatile memory, or register.

[0062] Mode switching preferably uses non-overlapping control. When switching from WuRX to RX, the rectifier load should be isolated and NI7 turned off first, then the on-chip differential local oscillator should be turned off, followed by enabling the external multiphase local oscillator and Q-path bias. When switching from RX to WuRX, the Q-path and external multiphase local oscillator should be turned off first, then the on-chip differential local oscillator, the low-power bias of the shared transimpedance core, and the rectifier branch should be enabled. The specific order can be adjusted, but simultaneous conduction of two local oscillator groups or linear / rectifier loads should be avoided when not desired.

[0063] This solution also provides a method for operating a dual-mode reconfigurable RF receiver front-end. The RF receiver front-end includes a common RF input, first and second passive mixer branches, a shared transimpedance core connected to the first passive mixer branch, an active rectifier branch selectively coupled to the shared transimpedance core, and a linear transimpedance circuit connected to the second passive mixer branch. The method of operation includes:

[0064] In response to the first mode command, the multi-phase local oscillator is selected to drive the first passive mixer branch and the second passive mixer branch, the shared transimpedance core and the linear transimpedance circuit are set to linear operation, the active rectifier branch is isolated from the shared transimpedance core, and two quadrature differential signals are output; and

[0065] In response to the second mode command, the differential local oscillator is selected to drive the first passive mixer branch, the second passive mixer branch or the linear transimpedance circuit is turned off, at least one of the bias state, equivalent device size and load state of the shared transimpedance core is changed, the active rectifier branch is connected to the shared transimpedance core, and an envelope signal or baseband wake-up signal is output.

[0066] In response to the first mode command, the active rectifier branch is first isolated and its bias is turned off, and then the multiphase local oscillator and the two linear transimpedance biases are enabled; in response to the second mode command, the local oscillator of the second passive mixer branch is first disabled and the corresponding linear transimpedance bias is turned off, and then the differential local oscillator, the low-power bias of the shared transimpedance core, and the active rectifier branch are enabled; when the envelope signal or baseband wake-up signal meets the preset wake-up conditions, a wake-up request is generated and the system switches from the second mode to the first mode; when data reception is completed or a preset timeout period is reached, the system switches back from the first mode to the second mode, and both switches are configured with a local oscillator non-overlapping period and a signal path non-overlapping period.

[0067] In the second mode, at least one of the following is adjusted based on the rectified output amplitude, the input matching detection value, the bit error detection value, or the pre-stored calibration parameters: the equivalent device size of the shared transimpedance core, the rectifier transistor size of the active rectifier branch, and the adjustable load resistance, in order to compensate for process, power supply voltage, and temperature variations.

[0068] This solution also provides a dual-mode radio frequency receiving system, including a main receiving controller, a wake-up decision circuit, and a mixer-priority radio frequency receiving front end;

[0069] The mixer priority RF receiving front end includes a common RF input, first and second passive mixing branches connected in parallel to the common RF input, a first mixing post-processing circuit connected to the first passive mixing branch and having a shared transimpedance core and an active rectifier branch that can be selectively accessed, a second mixing post-processing circuit connected to the second passive mixing branch, and a mode control circuit.

[0070] The mode control circuit is configured to drive the first passive mixer branch, shut down the second passive mixer branch or the second mixer post-processing circuit by differential local oscillator in the wake-up listening state, and make the shared transimpedance core and the active rectifier branch form a nonlinear active rectifier path.

[0071] The wake-up decision circuit generates a wake-up request based on the envelope signal or baseband wake-up signal output by the nonlinear active rectifier circuit.

[0072] In response to the wake-up request, the main receiver controller causes the multiphase local oscillator to drive the first and second passive mixer branches, enabling the shared transimpedance core and the second mixer post-processing circuit to perform two-way linear transimpedance conversion, and isolates the active rectifier branch to enter the data reception state.

[0073] Figure 3 The results for the input reflection coefficient S11 in RX mode are shown for an example implementation. S11 is generally below -10 dB in the range of approximately 2.4–2.5 GHz.

[0074] Figure 4 The S11 results for the same implementation example in WuRX mode are shown, maintaining input matching below -10 dB in the approximately 2.4–2.5 GHz range. These results demonstrate that the common RF input and its matching path can continue to operate in both modes.

[0075] Figure 5 The results show the noise figure of this implementation example in WuRX mode with a carrier or local oscillator frequency of approximately 2.4 GHz as a function of intermediate frequency / baseband frequency. Within the frequency range shown, the noise figure decreases with increasing frequency, reaching approximately 21 dB at the high end.

[0076] Figure 6 The conversion gain results shown are for WuRX mode, with a center frequency of approximately 2.400 GHz, a peak frequency of approximately 48 dB, a -3 dB bandwidth of approximately 3 MHz, and a gain drop of approximately 6 dB over a total range of approximately 5 MHz on both sides of the center frequency. The values ​​listed are results for one implementation example and are not intended to limit the scope of the claims.

[0077] Figure 7The control flow of a receiving system incorporating the front-end of this invention is illustrated. After power-on, the system enters the WuRX listening state, using an on-chip differential local oscillator and disabling the Q-channel. The envelope output is processed by a comparator, analog-to-digital converter, correlator, or wake-up code decision circuit. When a valid wake-up condition is detected, a wake-up request is generated, controlling the main receiver clock, power supply, and external multiphase local oscillator to start, and switching the front-end to the RX state. After data reception is complete or a timeout occurs, the system returns to the WuRX listening state.

[0078] Wake-up decisions can be based on single-threshold energy detection, or on multi-level thresholds, pulse width, address code, correlation peak values, or false wake-up suppression rules. The wake-up decision circuit can be integrated into the same chip as the front-end of this invention, or it can be located in the baseband control chip. Regardless of the decision method used, as long as the main receiving state is triggered based on the output formed by the shared core and the active rectifier branch, it can be implemented in conjunction with this invention.

[0079] In other embodiments, the first mode may also employ zero-IF, low-IF, or complex bandpass reception; the first local oscillator group may be a two-phase, four-phase, or more than four-phase local oscillator; the second mode may also retain a portion of the Q path for image suppression or interference detection. As long as unnecessary branches are disabled in at least one low-power wake-up state, and the shared transimpedance core of the first branch forms a nonlinear detection path with the rectifier branch, it falls within the scope of this invention.

[0080] In other embodiments, the active rectifier may be implemented by NMOS, PMOS, complementary devices, dynamic threshold devices, subthreshold devices, or rectifier transconductance units; the rectified output may be single-ended or differential; the low input impedance of the shared transimpedance core may be implemented by a common gate stage, a negative feedback amplifier, an inverter-type transimpedance stage, a current transmitter, or a feedforward transconductance enhancement structure.

[0081] In other embodiments, the present invention can be used in the 2.4 GHz ISM band, Sub-GHz ISM band, medical implant communication band, or other licensed / unlicensed bands. The local oscillator frequency, matching components, device size, power supply voltage, data rate, and load time constant should be designed according to the target process and communication standards, and are not limited to the values ​​in this embodiment.

[0082] The embodiments described above are merely one implementation method of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A mixer-priority dual-mode reconfigurable radio frequency receiver front end, characterized in that, include: Common radio frequency input, used to receive radio frequency input signals; The first passive mixer branch and the second passive mixer branch, the radio frequency terminals of the first passive mixer branch and the second passive mixer branch are both connected to the common radio frequency input; Local oscillator selection circuit is used to select a local oscillator signal between a first local oscillator group and a second local oscillator group. The first local oscillator group includes a multiphase signal for quadrature downconversion, and the second local oscillator group includes a pair of differential signals. A first mixer post-processing circuit is connected to the intermediate frequency terminal of the first passive mixer branch. The first mixer post-processing circuit includes a shared transimpedance core and an active rectifier branch that can be selectively coupled to the shared transimpedance core. The second post-mixing processing circuit is connected to the intermediate frequency terminal of the second passive mixer branch and is used for linear transimpedance conversion. The mode control circuit is connected to the local oscillator selection circuit, the first mixer post-processing circuit, and the second mixer post-processing circuit. In the first working mode, the mode control circuit enables the first local oscillator group to drive the first passive mixer branch and the second passive mixer branch, and enables the shared transimpedance core and the second mixer post-processing circuit to perform linear transimpedance conversion on the two mixed signals respectively, and isolates the active rectifier branch from the shared transimpedance core. In the second operating mode, the mode control circuit causes the second local oscillator group to drive the first passive mixer branch, causing the second passive mixer branch or the second mixer post-processing circuit to stop signal processing. By changing the bias state, equivalent device size and load state of the shared transimpedance core, the shared transimpedance core and the active rectifier branch are made to form a nonlinear active rectifier path, so as to output an envelope signal or baseband wake-up signal from the RF input signal.

2. The dual-mode reconfigurable radio frequency receiver front end according to claim 1, characterized in that, The common RF input is connected to the antenna terminal through a matching network, which includes an off-chip inductor, an adjustable capacitor network, or a combination thereof. The first passive mixer branch and the second passive mixer branch reuse the matching network. The first local oscillator group includes four-phase local oscillator signals with a phase difference of 90°, generated by an external local oscillator signal via a buffer and a frequency divider. The second local oscillator group is generated by an on-chip oscillator. The local oscillator selection circuit includes a transmission gate or a MOS switch for selectively coupling the four-phase local oscillator signal or the differential local oscillator signal to the control terminal of the switch transistor of the corresponding passive mixer branch. The first passive mixer branch and the second passive mixer branch respectively include a first pair of mixer switches and a second pair of mixer switches. The control terminal of each mixer switch receives the local oscillator signal through an AC coupling capacitor and receives a DC bias voltage through a bias resistor to adjust the on-resistance of the mixer switch and the equivalent input impedance of the common RF input.

3. The dual-mode reconfigurable radio frequency receiver front end according to claim 1, characterized in that: The shared transimpedance core includes a differential current input stage, a current mirror stage, and a self-biased load stage. The differential current input stage receives the differential intermediate frequency current output from the first passive mixer branch. The self-biased load stage includes a resistor network connected between two differential output nodes. The two differential output nodes are grounded through filter capacitors to form transimpedance amplification and low-pass filtering functions. The active rectifier branch includes a first rectifier transistor, a second rectifier transistor, a controllable bias transistor, a load capacitor, and an adjustable load resistor. The control terminals of the first rectifier transistor and the second rectifier transistor are respectively driven by the two differential output nodes of the shared transimpedance core. The rectified current generated by the first rectifier transistor and the second rectifier transistor is fed into the rectifier output node under the control of the mode switch, and forms the envelope signal or baseband wake-up signal on the load capacitor and the adjustable load resistor. The mode switch includes a first switch group controlled by a complementary mode control signal and a second switch group for connecting or isolating the active rectifier branch from the load capacitor and the adjustable load resistor. The complementary mode control signals are provided with non-overlapping time periods to suppress shoot-through current and local oscillator crosstalk during mode switching.

4. The dual-mode reconfigurable radio frequency receiver front end according to claim 1, characterized in that: In the first operating mode, the second mixer post-processing circuit and the shared transimpedance core have a symmetrical differential transimpedance structure. The first local oscillator group simultaneously drives the first passive mixer branch and the second passive mixer branch. The shared transimpedance core and the second mixer post-processing circuit are both in a linear bias state. The rectifier transistor and its controllable bias transistor of the active rectifier branch are turned off, and the active rectifier branch is isolated from the rectifier output node. The first mixer post-processing circuit and the second mixer post-processing circuit output in-phase differential intermediate frequency signals and quadrature differential intermediate frequency signals, respectively. In the second operating mode, the second local oscillator group drives the first passive mixer branch to downconvert the RF input signal with envelope information into a low intermediate frequency or ultra-low intermediate frequency signal. The quadrature branch is shut down by at least one of stopping the local oscillator of the second passive mixer branch, turning off the bias of the second mixer post-processing circuit, and cutting off the power supply of the second mixer post-processing circuit. The shared transimpedance core operates at a lower quiescent current than in the first operating mode and drives the active rectifier branch to perform envelope detection.

5. The dual-mode reconfigurable radio frequency receiver front end according to claim 1, characterized in that, At least one of the input transistor, current mirror transistor, bias transistor, rectifier transistor of the active rectifier branch, and adjustable load resistor of the shared transimpedance core is composed of multiple units that can be selectively connected in parallel. These multiple units can be configured as a binary weighted array, a thermometer code array, or a combination of both, to adjust the equivalent device size, bias current, transimpedance gain, rectification efficiency, noise figure, or input impedance under the control of a digital calibration word. The digital calibration word is generated based on process corner, power supply voltage, temperature, input matching, output amplitude, or bit error detection results.

6. The dual-mode reconfigurable radio frequency receiver front end according to any one of claims 1 to 5, characterized in that, The first working mode is a data receiving mode, and the second working mode is a wake-up receiving mode; the data receiving mode is used to receive frequency shift keying, phase shift keying or quadrature amplitude modulation signals, and the wake-up receiving mode is used to receive on / off keying, amplitude shift keying or wake-up signals with detectable envelopes.

7. A method for operating a dual-mode reconfigurable radio frequency receiver front-end, characterized in that, The radio frequency receiving front end includes a common radio frequency input, first and second passive mixer branches, a shared transimpedance core connected to the first passive mixer branch, an active rectifier branch selectively coupled to the shared transimpedance core, and a linear transimpedance circuit connected to the second passive mixer branch. The operating method includes: In response to the first mode command, the multi-phase local oscillator is selected to drive the first passive mixer branch and the second passive mixer branch, the shared transimpedance core and the linear transimpedance circuit are set to linear operation, the active rectifier branch is isolated from the shared transimpedance core, and two quadrature differential signals are output; and In response to the second mode command, the differential local oscillator is selected to drive the first passive mixer branch, the second passive mixer branch or the linear transimpedance circuit is turned off, at least one of the bias state, equivalent device size and load state of the shared transimpedance core is changed, the active rectifier branch is connected to the shared transimpedance core, and an envelope signal or baseband wake-up signal is output.

8. The working method according to claim 7, characterized in that, In response to the first mode command, the active rectifier branch is first isolated and its bias is turned off, and then the multiphase local oscillator and the two linear transimpedance biases are enabled; in response to the second mode command, the local oscillator of the second passive mixer branch is first disabled and the corresponding linear transimpedance bias is turned off, and then the differential local oscillator, the low-power bias of the shared transimpedance core, and the active rectifier branch are enabled; when the envelope signal or baseband wake-up signal meets the preset wake-up conditions, a wake-up request is generated and the system switches from the second mode to the first mode; when data reception is completed or a preset timeout period is reached, the system switches back from the first mode to the second mode, and both switches are configured with a local oscillator non-overlapping period and a signal path non-overlapping period.

9. The working method according to claim 7, characterized in that, In the second mode, at least one of the following is adjusted based on the rectified output amplitude, the input matching detection value, the bit error detection value, or the pre-stored calibration parameters: the equivalent device size of the shared transimpedance core, the rectifier transistor size of the active rectifier branch, and the adjustable load resistance, in order to compensate for process, power supply voltage, and temperature variations.

10. A dual-mode radio frequency receiving system, characterized in that, This includes the main receiver controller, wake-up decision circuit, and mixer priority RF receiver front end; The mixer priority RF receiving front end includes a common RF input, first and second passive mixing branches connected in parallel to the common RF input, a first mixing post-processing circuit connected to the first passive mixing branch and having a shared transimpedance core and an active rectifier branch that can be selectively accessed, a second mixing post-processing circuit connected to the second passive mixing branch, and a mode control circuit. The mode control circuit is configured to drive the first passive mixer branch, shut down the second passive mixer branch or the second mixer post-processing circuit by differential local oscillator in the wake-up listening state, and make the shared transimpedance core and the active rectifier branch form a nonlinear active rectifier path. The wake-up decision circuit generates a wake-up request based on the envelope signal or baseband wake-up signal output by the nonlinear active rectifier circuit. In response to the wake-up request, the main receiver controller causes the multiphase local oscillator to drive the first and second passive mixer branches, enabling the shared transimpedance core and the second mixer post-processing circuit to perform two-way linear transimpedance conversion, and isolates the active rectifier branch to enter the data reception state.

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