Equalization circuit and method of determining parameters

Abstract

The application provides an equalization circuit and a method for determining parameters. The first non-reference capacitor in the first branch and the second non-reference capacitor in the second branch of the equalization circuit are not standard components, have no lead inductance and resistance, have small parasitic effects, are suitable for high frequency and low frequency, have good equalization degree and good insertion loss performance. In addition, the first resistance and the second resistance in the equalization circuit can absorb the reflected signals of the original circuit, have small energy reflection and good echo performance.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to equalization circuits and methods for determining parameters in the field of electronic technology. Background Technology

[0002] In existing communication systems, both the transmitting and receiving ends need to use radio frequency (RF) circuits to send and receive signals. Due to the routing and / or components in the RF circuits, the gain of the RF link decreases as the frequency increases, resulting in a degradation in the performance of the RF circuits.

[0003] To improve the performance of radio frequency (RF) circuits, equalization circuits can be used to compensate for them. However, existing equalization circuits exhibit significant parasitic effects, especially in high-frequency scenarios, where at least one RF performance indicator, such as equalization, insertion loss, or echo, deteriorates severely. Summary of the Invention

[0004] This application provides an equalization circuit and a method for determining its parameters. The equalization circuit and the method for determining its parameters are applicable to high-frequency scenarios, and the equalization, insertion loss, and echo performance indicators are relatively good at high frequencies.

[0005] In a first aspect, an equalization circuit is provided, comprising: a first reference capacitor, a first branch, and a second branch, wherein the first branch is connected in parallel to the input terminal of the first reference capacitor, and the second branch is connected in parallel to the output terminal of the first reference capacitor; the first branch includes a first resistor, a first inductor, and a first non-reference capacitor, wherein the first non-reference capacitor is connected in parallel to the output terminal of the first resistor, the output terminal of the first resistor is connected in series with the input terminal of the first inductor, and the output terminal of the first inductor is grounded; the second branch includes a second resistor, a second inductor, and a second non-reference capacitor, wherein the second non-reference capacitor is connected in parallel to the output terminal of the second resistor, the output terminal of the second resistor is connected in series with the input terminal of the second inductor, and the output terminal of the second inductor is grounded.

[0006] The first non-reference capacitor in the first branch and the second non-reference capacitor in the second branch of the equalization circuit provided in this application embodiment are not standard components. They have no leaded inductors or resistors, resulting in relatively small parasitic effects. They are suitable for both high and low frequencies, and offer good equalization and insertion loss performance. Furthermore, the first and second resistors in the equalization circuit can absorb signals reflected from the original circuit, resulting in low energy reflection and good echo performance.

[0007] In one possible implementation, the first non-reference capacitor is fan-shaped, rectangular, or elliptical.

[0008] In one possible implementation, the first non-reference capacitor is a microstrip capacitor, and / or the second non-reference capacitor is a microstrip capacitor.

[0009] In the embodiments of this application, the first non-reference capacitor and / or the second non-reference capacitor are microstrip capacitors. The microstrip capacitor can be formed by a specific arrangement of microstrip linear structures, resulting in a relatively small parasitic effect, which makes the equalization circuit more balanced and the insertion loss performance better.

[0010] In one possible implementation, the first resistor and the second resistor have the same resistance value; and / or, the first inductor and the second inductor have the same inductance value; and / or, the first non-reference capacitor and the second non-reference capacitor have the same capacitance value.

[0011] In the embodiments of this application, the first resistor and the second resistor have the same resistance value, and / or the first inductor and the second inductor have the same inductance value, and the first non-reference capacitor and the second non-reference capacitor have the same inductance value, which can simplify the design of the equalization circuit.

[0012] In one possible implementation, the equalization circuit includes a third resistor, the input of which is connected in parallel with the input of the first reference capacitor, and the output of which is connected in parallel with the output of the first reference capacitor.

[0013] In this embodiment, the third resistor can adjust the slope of the equalization circuit, so that the insertion loss curve of the RF circuit can be better compensated after the equalization circuit is added, thereby improving the insertion loss performance of the RF circuit.

[0014] In one possible implementation, the third resistor is placed parallel to the first reference capacitor.

[0015] In this embodiment, placing the third resistor in the equalization circuit parallel to the first reference capacitor makes the layout of the equalization circuit on the PCB board more reasonable.

[0016] Secondly, an equalization circuit is provided, comprising: a first reference capacitor, a first branch, a second branch, and a third resistor; the first branch is connected in parallel to the input terminal of the third resistor, the second branch is connected in parallel to the output terminal of the third resistor, the input terminal of the first reference capacitor is connected in parallel to the input terminal of the third resistor, and the output terminal of the first reference capacitor is connected in parallel to the output terminal of the first reference capacitor; the first branch includes a first resistor, a first inductor, and a first non-reference capacitor; the first non-reference capacitor is connected in parallel to the output terminal of the first resistor, the output terminal of the first resistor is connected in series with the input terminal of the first inductor, and the output terminal of the first inductor is grounded; the second branch includes a second resistor, a second inductor, and a second non-reference capacitor; the second non-reference capacitor is connected in parallel to the output terminal of the second resistor, the output terminal of the second resistor is connected in series with the input terminal of the second inductor, and the output terminal of the second inductor is grounded.

[0017] The first non-reference capacitor in the first branch and the second non-reference capacitor in the second branch of the equalization circuit provided in this application embodiment are not standard components. They have no leaded inductors or resistors, resulting in relatively small parasitic effects. They are suitable for both high and low frequencies, and offer good equalization and insertion loss performance. Furthermore, the first and second resistors in the equalization circuit can absorb signals reflected from the original circuit, resulting in low energy reflection and good echo performance. In addition, the third resistor can adjust the slope of the equalization circuit, allowing for better compensation of the insertion loss curve of the RF circuit after adding the equalization circuit, thereby improving the insertion loss performance of the RF circuit.

[0018] In one possible implementation, the third resistor is placed parallel to the first reference capacitor.

[0019] In this embodiment, placing the third resistor in the equalization circuit parallel to the first reference capacitor makes the layout of the equalization circuit on the PCB board more reasonable.

[0020] In one possible implementation, the first non-reference capacitor is fan-shaped, rectangular, or elliptical.

[0021] In one possible implementation, the first non-reference capacitor is a microstrip capacitor, and / or the second non-reference capacitor is a microstrip capacitor.

[0022] In the embodiments of this application, the first non-reference capacitor and / or the second non-reference capacitor are microstrip capacitors. The microstrip capacitor can be formed by a specific arrangement of microstrip linear structures, resulting in a relatively small parasitic effect, which makes the equalization circuit more balanced and the insertion loss performance better.

[0023] In one possible implementation, the first resistor and the second resistor have the same resistance value; and / or, the first inductor and the second inductor have the same inductance value; and / or, the first non-reference capacitor and the second non-reference capacitor have the same capacitance value.

[0024] In the embodiments of this application, the first resistor and the second resistor have the same resistance value, and / or the first inductor and the second inductor have the same inductance value, and the first non-reference capacitor and the second non-reference capacitor have the same inductance value, which can simplify the design of the equalization circuit.

[0025] Thirdly, a method for determining parameters is provided, comprising: obtaining a first slope of the insertion loss curve of the original circuit at a first frequency value; determining a second slope of the equalization circuit of the first or second aspect at the first frequency domain value based on the first slope; and determining the capacitance value of the first reference capacitor and / or the resistance value of the third resistor based on the second slope.

[0026] In the above scheme, the second slope of the equalization circuit at the first frequency value can be determined based on the first slope of the first frequency value of the insertion loss curve of the original circuit, and the capacitance value of the first reference capacitor and the resistance value of the third resistor can be determined based on the second slope. That is to say, the first slope of the insertion loss curve of the original circuit without the added equalization circuit at a certain frequency value can be obtained first. Since the purpose of adding the equalization circuit is to compensate for the insertion loss of the original circuit, it is necessary to determine the slope of the insertion loss curve of the equalization circuit based on the slope of the insertion loss curve of the original circuit. This makes the insertion loss curve of the RF circuit after adding the equalization circuit flatter, thereby improving the insertion loss performance of the RF circuit.

[0027] Optionally, a circuit without an added equalization circuit is called a raw circuit, or a raw radio frequency circuit.

[0028] Optionally, determining the capacitance value of the first reference capacitor and / or the resistance value of the third resistor based on the second slope includes: determining the capacitance value of the first reference capacitor based on the second slope and the relationship between the second slope and the first reference capacitor, and / or determining the resistance value of the third resistor based on the second slope and the relationship between the second slope and the third resistor.

[0029] Optionally, the second slope is inversely proportional to the first reference capacitance.

[0030] Optionally, the second slope is inversely proportional to the third resistance.

[0031] In one possible implementation, the method further includes: obtaining a first insertion loss value of the insertion loss curve of the original circuit at the first frequency value; determining a second insertion loss value of the equalization circuit at the first frequency value based on the first insertion loss value; wherein, determining the capacitance value of the first reference capacitor based on the second slope includes: determining the capacitance value of the first reference capacitor based on the second insertion loss value and the second slope.

[0032] Optionally, the first reference capacitor may be related to the second insertion loss value and the second slope. Therefore, the capacitance value of the first reference capacitor can be determined based on the second insertion loss value and the second slope.

[0033] Optionally, the first reference capacitor may be related to the second insertion loss value, or it may be related to the second slope, or it may be related to both the second insertion loss value and the second slope. The capacitance value of the first reference capacitor can be determined based on these relationships. This provides a method for determining the capacitance value of the first reference capacitor.

[0034] In one possible implementation, the method further includes: determining the value of at least one of the following based on the second insertion loss value: the first resistor, the second resistor, the third resistor, the first inductor, and the second inductor.

[0035] In the above scheme, the second insertion loss value of the equalization circuit's insertion loss curve at the first frequency value can be determined based on the first insertion loss value of the original circuit's insertion loss curve at the first frequency value. Then, at least one of the first resistor, second resistor, third resistor, first inductor, or second inductor of the equalization circuit can be determined based on the second insertion loss value. In other words, the second insertion loss value of the equalization circuit is related to at least one of the first resistor, second resistor, third resistor, first inductor, or second inductor.

[0036] Optionally, the value of at least one of the following can be determined based on the second insertion loss value: the first resistor, the second resistor, the third resistor, the first inductor, and the second inductor. This can be done without relying on determining the capacitance value of the first reference capacitor based on the second frequency. In other words, the value of at least one of the following can be determined directly based on the second insertion loss value: the first resistor, the second resistor, and the third resistor, regardless of how the capacitance value of the first reference capacitor is determined.

[0037] Optionally, the third resistor can be determined based on the second slope and / or the second insertion loss value. That is, the third resistor can be related to the second slope, or to the second insertion loss value, or to both the second slope and the second insertion loss value.

[0038] Optionally, determining the third resistor may not depend on determining the capacitance value of the first reference capacitor based on the second frequency. That is, the parameters determined in this application can be the capacitance value of the first reference capacitor, the resistance value of the third resistor, the resistance value of the first resistor, the resistance value of the second resistor, the capacitance value of the first non-reference capacitor, the capacitance value of the second non-reference capacitor, or at least one of the first or second inductor. Different parameters may or may not be dependent on each other, and this application does not limit this.

[0039] In one possible implementation, the method further includes: determining the value of at least one of the following based on the first frequency value: the first non-reference capacitor, the second non-reference capacitor, the first inductor, and the second inductor.

[0040] In the above scheme, in order to make the equalization circuit suitable for the frequency range of the original circuit, the value of at least one of the first non-reference capacitor, the second non-reference capacitor, the first inductor, or the second inductor in the equalization circuit can be adjusted according to the first frequency value in the frequency range of the original circuit, so that the frequency of the equalization circuit can match the first frequency value.

[0041] Optionally, the inductance values ​​of the first inductor and / or the second inductor can be determined based on the second insertion loss value and / or the first frequency value. That is, the first inductor and / or the second inductor can be related to the second insertion loss value, or to the first frequency value, or to both the second insertion loss value and the first frequency value. This application embodiment does not impose any restrictions on this.

[0042] Fourthly, a device for determining parameters is provided, which has the function of implementing any one of the third aspects above. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions. For example, a transceiver module or unit, a processing module or unit, an acquisition module or unit, etc.

[0043] Fifthly, embodiments of this application provide an apparatus for determining parameters, comprising: a memory and a processor, wherein the memory is used to store a computer program; and the processor is used to cause the apparatus to execute any of the methods described in the third aspect when the computer program is invoked.

[0044] Sixthly, embodiments of this application provide a radio frequency (RF) circuit, including an equalization circuit as described in any one of the first aspects or any one of the second aspects. Optionally, the RF circuit may further include at least one of a driver amplifier, a power amplifier, a low-noise amplifier module, or a filter.

[0045] In a seventh aspect, embodiments of this application provide a chip system including a processor coupled to a memory, wherein the processor executes a computer program stored in the memory to implement the method of any of the third aspects described above.

[0046] The chip system can be a single chip or a chip module composed of multiple chips.

[0047] Eighthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method of any one of the third aspects described above.

[0048] Ninthly, embodiments of this application provide a computer program product that, when run on a communication device, causes the communication device to perform the method of any one of the third aspects described above.

[0049] It is understood that the beneficial effects of aspects four through nine above can be found in the relevant descriptions of aspects one through three above, and will not be repeated here. Attached Figure Description

[0050] Figure 1 This is an architecture diagram of the communication module provided in an embodiment of this application.

[0051] Figure 2 This is a schematic diagram of the equalization circuit provided in an embodiment of this application.

[0052] Figure 3 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0053] Figure 4 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0054] Figure 5 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0055] Figure 6 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0056] Figure 7 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0057] Figure 8 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0058] Figure 9 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0059] Figure 10 This is a schematic diagram of another equalization circuit provided in an embodiment of this application.

[0060] Figure 11 This is a schematic diagram of the method for determining parameters provided in the embodiments of this application.

[0061] Figure 12 Figure (a) is a schematic diagram of the insertion loss curve of the original circuit provided in the embodiment of this application.

[0062] Figure 12 Figure (b) is a schematic diagram of the insertion loss curve of the equalization circuit provided in the embodiment of this application.

[0063] Figure 12 Figure (c) is a schematic diagram of the insertion loss curve of the radio frequency circuit with added equalization circuit provided in the embodiment of this application.

[0064] Figure 13 This is a schematic diagram of the insertion loss curve and echo curve of the equalization circuit provided in the embodiments of this application.

[0065] Figure 14 This is a schematic diagram of a filter circuit provided in an embodiment of this application.

[0066] Figure 15 This is a schematic diagram of another filtering circuit provided in an embodiment of this application.

[0067] Figure 16 This is a schematic diagram of the attenuation circuit provided in an embodiment of this application.

[0068] Figure 17 This is a schematic diagram of another attenuation circuit provided in an embodiment of this application.

[0069] Figure 18 A schematic block diagram of an apparatus for determining parameters provided in an embodiment of this application. Detailed Implementation

[0070] It should be understood that the methods, situations, categories, and classifications of embodiments in this application are for the convenience of description only and should not constitute a special limitation. Various methods, categories, situations, and features in embodiments can be combined without contradiction.

[0071] It should also be understood that the terms "first," "second," and "third" in the embodiments of this application are for distinction only and should not constitute any limitation on this application. It should also be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0072] In this application embodiment, the number of nouns, unless otherwise specified, refers to "singular nouns or plural nouns," that is, "one or more." "At least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. For example, A / B means: A or B. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0073] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0074] It should be noted that in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0075] The methods and apparatus provided in this application are based on the same or similar technical concepts. Since the methods and apparatus solve problems in similar ways, the implementation of the apparatus and methods can refer to each other, and repeated parts will not be described again.

[0076] like Figure 1 The diagram illustrates the architecture of a communication module provided in an embodiment of this application. The communication module can also be referred to as a radio frequency (RF) circuit. The terminal device or network device of the communication system may include the communication module. Figure 1As shown, the communication module includes an RF transceiver chip, a driver amplifier, a first equalization circuit, a power amplifier, a filter, an antenna, a low-noise amplifier module, and a second equalization circuit. The first equalization circuit is for the transmit link, and the second equalization circuit is for the receive link. For the transmit link, the RF transceiver chip generates and processes the transmit signal. The driver amplifier amplifies the signal transmitted by the RF transceiver chip. The first equalization circuit equalizes the transmit signal generated by the RF transceiver chip. The power amplifier amplifies the signal processed by the equalization circuit. The filter filters the signal amplified by the power amplifier, and the filtered signal can be transmitted through the antenna. For the receive link, after the antenna receives the signal, it is processed by the filter and then enters the low-noise amplifier module for noise reduction. The noise-reduced signal is then equalized by the second equalization circuit, and the equalized signal can then be processed by the RF transceiver chip. Furthermore, the RF circuit may also include at least one of a power supply module, a clock module, or an application-specific integrated circuit (ASIC) module. (To avoid further details...) Figure 1 Not shown in the image. Figure 1 In the transmission link, the gain of the RF transceiver chip, driver amplifier, power amplifier, and filters decreases as the frequency increases, leading to an increase in the gain difference between high and low frequencies. Similarly, the gain of the filters and low-noise amplifier module in the reception link decreases as the frequency increases. Therefore, Figure 1 The first equalization circuit in the circuit can compensate for the unevenness of the transmitting link, and the second equalization circuit can compensate for the unevenness of the receiving link.

[0077] Existing equalization circuits are lumped devices with relatively narrow bandwidth and significant parasitic effects. Due to the presence of parasitic capacitance or resistance in inductors, or parasitic resistance or inductance in capacitors, especially at high frequencies, parasitic effects can cause a large deviation between the actual amplitude-frequency response and the theoretical expectation.

[0078] The following is combined with Figure 2 Describe the equalization circuit in this application. Wherein, Figure 1 The first equalization circuit in the process can be Figure 2 equalization circuit or Figure 1 The second equalization circuit in the system can be Figure 2 The equalization circuit in [the system]. For example, [the circuitry used in this context]. Figure 2 As shown, the equalization circuit is as follows Figure 2As shown. The equalization circuit includes: a first reference capacitor, a first branch, and a second branch. The first branch is connected in parallel to the input terminal of the first reference capacitor, the second branch is connected in parallel to the output terminal of the first reference capacitor, a first non-reference capacitor is connected in parallel to the output terminal of the first resistor, the output terminal of the first resistor is connected in series with the input terminal of the first inductor, and the output terminal of the first inductor is grounded. Figure 2 As shown, the first branch includes a first resistor, a first inductor, and a first non-reference capacitor. The second branch includes a second resistor, a second inductor, and a second non-reference capacitor. The second non-reference capacitor is connected in parallel to the output terminal of the second resistor. The output terminal of the second resistor is connected in series with the input terminal of the second inductor. The output terminal of the second inductor is grounded.

[0079] exist Figure 2 In the equalization circuit shown, the first non-reference capacitor in the first branch and the second non-reference capacitor in the second branch are not standard components. They utilize microstrip transmission line equivalent capacitance, have no lead inductance or resistance, and exhibit relatively small parasitic effects, making them suitable for high-frequency applications. Furthermore, as... Figure 2 The first and second resistors in the equalization circuit can absorb the signal reflected from the original circuit, resulting in less energy reflection and thus improving the performance of the link.

[0080] Optionally, the first inductor, the second inductor, the first non-reference capacitor, and the second non-reference capacitor can form the resonant point of the resonator. The inductance value of the first inductor, the inductance value of the second inductor, the capacitance value of the first non-reference capacitor, and the capacitance value of the second non-reference capacitor can be determined to make the resonant frequency match the frequency required by the radio frequency circuit.

[0081] Optionally, the first inductor and the second inductor have the same inductance value. Alternatively, the first inductor and the second inductor may have different inductance values; this embodiment does not impose any limitation on this. For example, the values ​​of the first inductor and the second inductor can be between 1 and 10 nanohenries.

[0082] Optionally, the first and second non-reference capacitors are not standard capacitor components. Therefore, the parasitic effects of the first and second non-reference capacitors are small, especially at higher frequencies, resulting in lower link losses in the RF circuit. Optionally, the first and second non-reference capacitors can be in the form of microstrip open circuits. That is, the first non-reference capacitor can be a microstrip capacitor, and the second non-reference capacitor can be a microstrip capacitor. The microstrip capacitor can be a capacitance effect formed by a specific arrangement of microstrip linear structures. Figure 2Taking the first and second non-reference capacitors as a sector shape as an example, the first and second non-reference capacitors can also be other shapes, such as rectangles or ellipses. This application embodiment does not limit this. Optionally, the capacitance values ​​of the first and second non-reference capacitors are the same. Optionally, the capacitance values ​​of the first and second non-reference capacitors can also be different. This application embodiment does not limit this. For example, the values ​​of the first and second non-reference capacitors can be between 0.1 and 10 picofarads.

[0083] Optionally, the first resistor and the second resistor are used to match the impedance in the original circuit and optimize the echo of the original circuit. The original circuit can be the RF circuit before the addition of the equalization circuit. Optionally, the first resistor and the second resistor have the same resistance value. Optionally, in some embodiments, the resistance values ​​of the first resistor and the second resistor may also be different, and this application embodiment does not limit this. For example, the values ​​of the first resistor and the second resistor are between 50 and 300 ohms.

[0084] Optionally, the equalization circuit may also include a third resistor, such as Figure 3 As shown, the input terminal of the third resistor is connected in parallel with the input terminal of the first reference capacitor, and the output terminal of the third resistor is connected in parallel with the output terminal of the first reference capacitor. Optionally, the third resistor and the first reference capacitor are placed parallel to each other, which makes the layout of the equalization circuit on the printed circuit board (PCB) more reasonable. Optionally, in some embodiments, the positions of the third resistor and the first reference capacitor can be interchanged, for example, the interchanged equalization circuit is as follows. Figure 4 As shown, Figure 4 and Figure 3 The difference lies in the fact that the positions of the first non-reference capacitor and the third resistor have been swapped. Figure 4 The third resistor and the first non-reference capacitor can also be placed in parallel.

[0085] The above Figures 2-4 The equalization circuit in the diagram is a third-order equalization circuit consisting of two parallel branches and one series branch. In some embodiments, the equalization circuit can be extended to more order equalization circuits, such as... Figure 5 The equalization circuit shown can be Figure 2 The corresponding fifth-order equalization circuit, Figure 5 relative to Figure 2 A fifth resistor, a third non-reference capacitor, and a third inductor were added. For example... Figure 6 The equalization circuit shown can be Figure 2 The corresponding Nth-order equalization circuit. For example... Figure 7 The equalization circuit shown is Figure 3 The corresponding fifth-order equalization circuit, Figure 7 Compared to Figure 3A fifth resistor, a fourth resistor, a second reference capacitor, a third non-reference capacitor, and a third inductor were added. Figure 8 The equalization circuit shown can be Figure 3 The corresponding Nth-order equalization circuit. Figure 9 The equalization circuit shown is Figure 4 The corresponding fifth-order equalization circuit, Figure 9 Compared to Figure 4 A second reference capacitor, a fifth resistor, a fourth resistor, a third non-reference capacitor, and a third inductor were added. Figure 10 The equalization circuit shown can be Figure 4 The corresponding Nth-order equalization circuit. Optional, Figure 5 , Figure 7 and Figure 9 The resistance value of the fourth resistor can be the same as or different from the resistance value of the first resistor, and the resistance value of the fourth resistor can be the same as or different from the resistance value of the second resistor. Optionally, Figure 5 , Figure 7 and Figure 9 The capacitance value of the second reference capacitor can be the same as or different from the capacitance value of the first reference capacitor; this embodiment does not impose such a limitation. Optionally, Figure 5 , Figure 7 and Figure 9 The capacitance value of the third non-reference capacitor may be the same as or different from that of the first non-reference capacitor, and the capacitance value of the third non-reference capacitor may be the same as or different from that of the second non-reference capacitor. This embodiment of the application does not impose such limitations. Optionally, the inductance value of the third inductor may be the same as or different from that of the first inductor, and the inductance value of the third inductor may be the same as or different from that of the second inductor. This embodiment of the application does not impose such limitations. Figure 5 , Figure 7 and Figure 9 The equalization circuit shown is a fifth-order equalization circuit consisting of three parallel branches and two series branches.

[0086] The above Figures 2-10 The equalization circuit provided in the embodiment of this application is shown below, in conjunction with... Figure 11 The present application describes a method for adjusting parameters based on an equalization circuit, which can be executed by an electronic device, such as an electronic device for implementing electrical adjustability. Figure 11 As shown, the methods for determining the parameters include:

[0087] S1110, obtain the first slope of the insertion loss curve of the original circuit at the first frequency value.

[0088] The original circuit can be an RF circuit without an added equalization circuit. In other words, before adding an equalization circuit, it is necessary to determine the first slope of the first frequency value of the insertion loss curve of the original circuit.

[0089] Optionally, the x-axis of the insertion loss curve of the original circuit represents frequency, and the y-axis represents gain. The insertion loss curve consists of multiple frequencies, and the first frequency value can be any one of the multiple frequency values ​​in the insertion loss curve. Optionally, the insertion loss curve of the equalization circuit can also be determined based on the insertion loss curve of the original circuit.

[0090] S1120, determine the second slope of the equalization circuit at the first frequency value based on the first slope.

[0091] Optionally, to flatten the insertion loss curve of the RF circuit in the equalization circuit, the electronic device can determine a second slope based on a first slope of the first frequency value. For example, if the first slope is k, then the second slope can be 1 / k. Similarly, the electronic device can determine the slope of each frequency value in the equalization circuit based on the slope corresponding to each frequency value in the insertion loss curve of the original circuit.

[0092] S1130, determine the capacitance value of the first reference capacitor based on the second slope.

[0093] Optionally, the relationship between the second slope and the capacitance value of the first reference capacitor determines the capacitance value of the first reference capacitor. Optionally, the second slope is inversely proportional to the capacitance value of the first reference capacitor. For example, if the second slope is k, the capacitance value of the first reference capacitor is 1 / k.

[0094] Optionally, the electronic device can also determine the resistance value of the third resistor in the equalization circuit based on the second slope. For example, the electronic device can determine the resistance value of the third resistor based on the relationship between the second slope and the third resistor. Optionally, the second slope and the third resistor are inversely proportional. For example, if the second slope is k, the resistance value of the third resistor is 1 / k. Optionally, S1130 can be an optional step; the electronic device can determine the resistance value of the third resistor based on the second slope, and the capacitance value of the first reference capacitor can be determined in other ways, which is not limited in this embodiment.

[0095] Optionally, the electronic device can obtain a first insertion loss value from the insertion loss curve of the original circuit at a first frequency. The electronic device can determine a second insertion loss value for the equalization circuit at the first frequency based on the first insertion loss value. The electronic device determines the capacitance value of the first reference capacitor based on the second insertion loss value and the second slope. That is, the capacitance value of the first reference capacitor can be related to the second insertion loss value and the second slope, and the electronic device can determine the capacitance value of the first reference capacitor by combining the second insertion loss value and the second slope.

[0096] Optionally, the electronic device can determine the value of at least one of the first resistor, second resistor, third resistor, first inductor, or second inductor in the equalization circuit based on the second insertion loss value. For example, if the second insertion loss value is directly proportional to the third resistor, the electronic device can determine the third resistor based on the second insertion loss value. Alternatively, the second insertion loss value can be inversely proportional to the first resistor, or directly proportional to the first inductor, or directly proportional to the second inductor.

[0097] Optionally, the electronic device can also determine the value of at least one of the following based on the first frequency value: a first non-reference capacitor, a second non-reference capacitor, a first inductor, or a second inductor. Alternatively, the electronic device can also determine the first frequency value based on the value of at least one of the first non-reference capacitor, the second non-reference capacitor, the first inductor, or the second inductor. That is, the frequency value in the equalization circuit is related to one or more of the first non-reference capacitor, the second non-reference capacitor, the first inductor, or the second inductor. Especially when the frequency value of the original circuit is relatively high, the electronic device can determine the value of at least one of the following based on the frequency value of the original circuit: a first non-reference capacitor, a second non-reference capacitor, a first inductor, or a second inductor. For example, if the inductance values ​​of the first inductor and the second inductor are equal, the capacitance values ​​of the first non-reference capacitor and the second non-reference capacitor are equal. Wherein, the first frequency value f can be... Where L is the inductance value of the first inductor or the second inductor, and C is the capacitance value of the first non-reference capacitor or the second non-reference capacitor. In other words, to adapt to the high frequency of the original circuit, the electronic device can adjust the capacitance values ​​of the first inductor, the second inductor, and the first or second non-reference capacitor to determine the frequency value of the equalization circuit to match the high frequency of the original circuit. Thus, the equalization circuit provided in this embodiment is also applicable to high-frequency scenarios. Furthermore, since the first and second non-reference capacitors are not standard components, their parasitic effects in high-frequency scenarios are relatively small. Therefore, the equalization circuit provided in this embodiment is applicable to both high-frequency and low-frequency scenarios. For example, the equalization circuit provided in this embodiment is applicable to scenarios from 1 to 10 GHz. Therefore, the equalization circuit provided in this embodiment can adapt to a relatively large frequency range.

[0098] In this embodiment, the first frequency value can be any frequency value of the insertion loss curve of the original circuit. The electronic device can determine the slope of the equalization circuit corresponding to the slope of each frequency value of the insertion loss curve of the original circuit, and determine the reference capacitor value or the third resistor corresponding to each frequency value in the equalization circuit based on the slope of the equalization circuit corresponding to each frequency value. Furthermore, the first resistor, second resistor, first inductor, and second inductor corresponding to each frequency value of the equalization circuit can be determined based on the insertion loss value corresponding to each frequency value. This ensures that the insertion loss curve of the RF circuit after adding the equalization circuit does not fluctuate too much; for example, the insertion loss curve of the RF circuit with the added equalization circuit can be flat. For example, as... Figure 12 As shown, Figure 12 Figure (a) can be the insertion loss curve of the original circuit. Figure 12 Figure (b) can be the insertion loss curve of the equalization circuit. Figure 12 Figure (c) shows the insertion loss curve of the RF circuit after adding the equalization circuit, where... Figure 12 In graphs (a), (b), and (c), the horizontal axis represents frequency (f), and the vertical axis represents gain (G). For example, Figure 13 The insertion loss curve and echo curve of the equalization circuit provided in this application embodiment are shown. The dashed line represents the insertion loss curve, and the solid line represents the echo curve. The insertion loss curve is basically flat, and the echo curve's return loss is less than 10dB. Therefore, compared to traditional equalization circuits, the equalization effect of the equalization circuit provided in this application embodiment is better. Furthermore, in this application embodiment... Figures 2-10 The equalization circuit in the design is a microstrip plus lumped device, which is suitable for high frequency scenarios, has high integration, is easy to manufacture, and its performance in actual board tests also meets application requirements.

[0099] This application also provides a filtering circuit, such as... Figure 14 As shown, the filter circuit includes: a third reference capacitor, a third branch, and a fourth branch. The third branch is connected in parallel to the input terminal of the third reference capacitor, and the fourth branch is connected in parallel to the output terminal of the third reference capacitor. The third branch includes a fourth inductor, a fifth inductor, and a fourth non-reference capacitor. The fourth non-reference capacitor is connected in parallel to the output terminal of the fourth inductor, and the output terminal of the fourth inductor is connected in series with the input terminal of the fifth inductor. The output terminal of the fifth inductor is grounded. The fourth branch includes a sixth inductor, a seventh inductor, and a fifth non-reference capacitor. The fifth non-reference capacitor is connected in parallel to the output terminal of the sixth inductor, and the output terminal of the sixth inductor is connected in series with the input terminal of the seventh inductor. The output terminal of the seventh inductor is grounded. Optionally, the filter circuit may also include an eighth inductor, such as... Figure 15 As shown, the input terminal of the eighth inductor is connected in parallel to the input terminal of the third reference capacitor, and the output terminal of the eighth capacitor is connected in parallel to the output terminal of the third reference capacitor.

[0100] This application also provides an attenuator circuit, such as... Figure 16 As shown, the attenuator circuit includes: a sixth resistor, a fifth branch, and a sixth branch. The fifth branch is connected in parallel to the input of the sixth resistor, and the sixth branch is connected in parallel to the output of the sixth resistor. The fifth branch includes a seventh resistor, a sixth non-reference capacitor, and an eighth resistor. The sixth non-reference capacitor is connected in parallel to the output of the seventh resistor. The output of the seventh resistor is connected in series with the input of the eighth resistor, and the output of the eighth resistor is grounded. The sixth branch includes a ninth resistor, a fifth non-reference capacitor, and a tenth resistor. The seventh non-reference capacitor is connected in parallel to the output of the ninth resistor. The output of the ninth resistor is connected in series with the input of the tenth resistor, and the output of the tenth resistor is grounded. Optionally, the attenuator circuit may also include an eleventh resistor, such as... Figure 17 As shown, the input terminal of the eleventh resistor is connected in parallel to the input terminal of the sixth resistor, and the output terminal of the eleventh resistor is connected in parallel to the output terminal of the sixth resistor.

[0101] Figure 18 This is a schematic block diagram of a device 1800 for determining parameters provided in an embodiment of this application. Figure 18 As shown, the device 1800 may include a processing unit 1810 and a communication unit 1820. The communication unit 1820 can implement corresponding communication functions, which can be internal communication within the device 1800 or communication between the device 1800 and other devices; the processing unit 1810 can implement corresponding processing functions. The communication unit 1820 may also be referred to as a communication interface or transceiver unit. Optionally, the communication device 1800 may further include a storage unit, which can be used to store instructions and / or data. The processing unit 1810 can read the instructions and / or data in the storage unit to enable the device to implement the aforementioned method embodiments.

[0102] The communication device 1800 can be the one described above. Figure 11 The electronic device in the embodiments can also be a module or chip applied to an electronic device. The communication device 1800 can be used to execute the steps or processes performed by the electronic device in the above method embodiments.

[0103] For details regarding the steps or processes executed by each unit in the communication device 1800, please refer to the embodiments of the method described above; they will not be elaborated here.

[0104] It should be understood that the "unit" in the communication device 1800 can be implemented in hardware, software, or by hardware executing corresponding software. For example, the "unit" can refer to an application-specific integrated circuit (ASIC), electronic circuits, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functions.

[0105] Optionally, another apparatus is provided in the embodiments of this application. This apparatus may be an electronic device, or a chip, chip system, or processor that supports the electronic device in implementing the above methods. This apparatus can be used to implement the methods described in the above method embodiments; for details, please refer to the descriptions in the above method embodiments.

[0106] The device may include one or more processors, also known as processing units, which can perform certain control functions. The processor can be a general-purpose processor or a dedicated processor, for example, a baseband processor or a central processing unit (CPU). The baseband processor can be used to process communication protocols and communication data, while the CPU can be used to control communication devices (e.g., base stations, baseband chips, user chips, DUs or CUs, etc.), execute software programs, and process data from the software programs.

[0107] In an alternative design, the processor may also store instructions and / or data that can be executed by the processor to cause the device to perform the methods described in the above method embodiments.

[0108] In another alternative design, the communication device may include a communication interface for implementing receiving and transmitting functions. For example, this communication interface may be a transceiver circuit, interface, interface circuit, or transceiver. The transceiver circuit, interface, interface circuit, or transceiver for implementing receiving and transmitting functions may be separate or integrated. The aforementioned transceiver circuit, interface, interface circuit, or transceiver may be used for reading and writing code / data, or it may be used for transmitting or relaying signals.

[0109] Optionally, the communication device may include one or more memories storing instructions that can be executed on a processor to cause the device to perform the methods described in the above method embodiments. Optionally, the memories may also store data. Optionally, the processor may also store instructions and / or data. The processor and memory may be configured separately or integrated together.

[0110] In a practical device, multiple processors and memories may exist. Memory can also be called storage medium or storage device, etc., and the embodiments of this application do not limit this.

[0111] For example, a processor may include a baseband processor and a central processing unit (CPU). The baseband processor is mainly used for processing communication protocols and communication data, while the CPU is mainly used for controlling the entire terminal device, executing software programs, and processing data from those programs. The processor integrates the functions of both the baseband processor and the CPU. Those skilled in the art will understand that the baseband processor and the CPU can also be independent processors interconnected via technologies such as buses. Those skilled in the art will understand that a terminal device may include multiple baseband processors to adapt to different network standards, and multiple CPUs to enhance its processing capabilities. The various components of the terminal device can be connected via various buses. The baseband processor can also be described as a baseband processing circuit or a baseband processing chip. The CPU can also be described as a central processing circuit or a central processing chip. The function of processing communication protocols and communication data can be built into the processor or stored as software programs in a storage unit, with the processor executing the software programs to implement the baseband processing function.

[0112] It should be understood that, in one possible design, the steps in the method embodiments provided in this application can be implemented by integrated logic circuits in the processor's hardware or by instructions in software form. The steps of the methods disclosed in the embodiments of this application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are not provided here.

[0113] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0114] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0115] This application also provides a computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform the various steps or processes performed by the electronic device in any of the above method embodiments.

[0116] This application also provides a computer-readable storage medium storing program code that, when run on a computer, causes the computer to perform the various steps or processes performed by the electronic device in any of the above method embodiments.

[0117] This application also provides an electronic device, including a processor and an interface for sending and / or receiving signals, causing the processor to perform various steps or processes performed by the electronic device in any of the above method embodiments.

[0118] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0119] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0120] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0121] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0122] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An equalization circuit, characterized in that, include: A first reference capacitor, a first branch, and a second branch, wherein the first branch is connected in parallel to the input terminal of the first reference capacitor, and the second branch is connected in parallel to the output terminal of the first reference capacitor; The first branch includes a first resistor, a first inductor, and a first non-reference capacitor. The first non-reference capacitor is connected in parallel to the output terminal of the first resistor. The output terminal of the first resistor is connected in series with the input terminal of the first inductor. The output terminal of the first inductor is grounded. The second branch includes a second resistor, a second inductor, and a second non-reference capacitor. The second non-reference capacitor is connected in parallel to the output terminal of the second resistor. The output terminal of the second resistor is connected in series with the input terminal of the second inductor. The output terminal of the second inductor is grounded.

2. The equalization circuit according to claim 1, characterized in that, The first non-reference capacitor has a fan-shaped, rectangular, or elliptical shape.

3. The equalization circuit according to claim 1 or 2, characterized in that, The first non-reference capacitor is a microstrip capacitor, and / or the second non-reference capacitor is a microstrip capacitor.

4. The equalization circuit according to any one of claims 1 to 3, characterized in that, The first resistor and the second resistor have the same resistance value; and / or, the first inductor and the second inductor have the same inductance value; and / or, the first non-reference capacitor and the second non-reference capacitor have the same capacitance value.

5. The equalization circuit according to any one of claims 1 to 4, characterized in that, The equalization circuit includes a third resistor, the input of which is connected in parallel to the input of the first reference capacitor, and the output of which is connected in parallel to the output of the first reference capacitor.

6. The equalization circuit according to claim 5, characterized in that, The third resistor is placed parallel to the first reference capacitor.

7. An equalization circuit, characterized in that, include: A first reference capacitor, a first branch, a second branch, and a third resistor, wherein the first branch is connected in parallel to the input terminal of the third resistor, the second branch is connected in parallel to the output terminal of the third resistor, the input terminal of the first reference capacitor is connected in parallel to the input terminal of the third resistor, and the output terminal of the first reference capacitor is connected in parallel to the output terminal of the first reference capacitor. The first branch includes a first resistor, a first inductor, and a first non-reference capacitor. The first non-reference capacitor is connected in parallel to the output terminal of the first resistor. The output terminal of the first resistor is connected in series with the input terminal of the first inductor. The output terminal of the first inductor is grounded. The second branch includes a second resistor, a second inductor, and a second non-reference capacitor. The second non-reference capacitor is connected in parallel to the output terminal of the second resistor. The output terminal of the second resistor is connected in series with the input terminal of the second inductor. The output terminal of the second inductor is grounded.

8. The equalization circuit according to claim 7, characterized in that, The third resistor is placed parallel to the first reference capacitor.

9. The equalization circuit according to claim 7 or 8, characterized in that, The first non-reference capacitor has a fan-shaped, rectangular, or elliptical shape.

10. The equalization circuit according to any one of claims 7 to 9, characterized in that, The first non-reference capacitor is a microstrip capacitor, and / or the second non-reference capacitor is a microstrip capacitor.

11. The equalization circuit according to any one of claims 7 to 10, characterized in that, The first resistor and the second resistor have the same resistance value; and / or, the first inductor and the second inductor have the same inductance value; and / or, the first non-reference capacitor and the second non-reference capacitor have the same capacitance value.

12. A method for determining parameters, characterized in that, include: Obtain the first slope of the insertion loss curve of the original circuit at the first frequency value; A second slope of the equalization circuit as described in any one of claims 1 to 11 in the first frequency domain value is determined based on the first slope; The capacitance value of the first reference capacitor is determined based on the second slope.

13. The method according to claim 12, characterized in that, The method further includes; The resistance value of the third resistor included in the equalization circuit is determined based on the second slope.

14. The method according to claim 13, characterized in that, The second slope is inversely proportional to the resistance value of the third resistor.

15. The method according to any one of claims 12 to 14, characterized in that, The second slope is inversely proportional to the capacitance value of the first reference capacitor.

16. The method according to any one of claims 12 to 15, characterized in that, The method further includes: Obtain the first insertion loss value of the insertion loss curve of the original circuit at the first frequency value; Determine the second insertion loss value of the equalization circuit at the first frequency value based on the first insertion loss value; The step of determining the capacitance value of the first reference capacitor based on the second slope includes: The capacitance value of the first reference capacitor is determined based on the second insertion loss value and the second slope.

17. The method according to claim 16, characterized in that, The method further includes: The value of at least one of the following is determined based on the second insertion loss value: the first resistor, the second resistor, the third resistor of the equalization circuit, the first inductor, and the second inductor.

18. The method according to any one of claims 13 to 15, characterized in that, The method further includes: The value of at least one of the following is determined based on the first frequency value: the first non-reference capacitor, the second non-reference capacitor, the first inductor, and the second inductor.

19. An electronic device, characterized in that, Includes a unit that performs the method as described in any one of claims 12 to 18.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the method as described in any one of claims 12 to 18.

21. A chip, characterized in that, The chip includes a processor connected to a memory for storing a computer program, and the processor is configured to execute the computer program stored in the memory to cause the chip to perform the method as described in any one of claims 12 to 18.

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