A wireless communication system based on fast frequency hopping and dynamic synchronization mechanism

Abstract

The application discloses a wireless communication system based on a fast frequency hopping and dynamic synchronization mechanism, relates to the wireless communication field, and aims to solve the problems of poor anti-interference ability, slow response speed and fragile communication in the prior art.The technical scheme is that ARM processors, FPGA chips and DSP chips are connected two by two, the FPGA chip is connected with a double phase-locked loop frequency synthesis circuit, and the frame structure emitted by the DSP chip adopts a combination of synchronous time slots and data transmission time slots, so that high-speed frequency hopping is realized, the anti-interference ability is improved, the three chips are directly connected, the response speed is improved, and the synchronization search timing in the frequency hopping communication is searched one by one for each frequency, and the search is performed in a 16 times slow hopping mode, so that the synchronization time is greatly shortened.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, specifically to a wireless communication system based on a fast frequency hopping and dynamic synchronization mechanism. Background Technology

[0002] Frequency hopping technology is an important branch of spread spectrum communication. By rapidly changing the communication carrier frequency in a pseudo-random sequence over a wide bandwidth, it can effectively combat narrowband interference and frequency-selective fading, significantly improving the reliability and security of communication. However, traditional frequency hopping technology still faces the following challenges: 1. Hop rate limitation: The hop rate of a conventional medium-hop radio is usually less than 500 hops / s, which limits its anti-interference capability; 2. Frame structure efficiency: The frame structure design of conventional frequency hopping systems is not efficient enough in carrying and coordinating data, synchronization and control information in high-speed hopping environments. Service frames account for more than 20%, which affects the effective bandwidth utilization and system response speed. 3. Synchronization vulnerability: Traditional synchronization methods are prone to failure in complex electromagnetic environments, and link reconstruction takes more than 500ms, affecting real-time communication. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the existing defects and provide a wireless communication system based on fast frequency hopping and dynamic synchronization mechanism, which can effectively solve the problems in the background art.

[0004] To achieve the above objectives, this invention discloses a wireless communication system based on a fast frequency hopping and dynamic synchronization mechanism. The technical solution includes an ARM processor connected to an FPGA chip and a DSP chip. The DSP chip is also connected to an audio analog-to-digital converter (AADC). The AADC is connected to a voice codec chip and an audio interface. The voice codec chip is connected to the DSP chip. The ARM processor is connected to a terminal. The FPGA chip is connected to a radar digital-to-analog converter (DAC), and the DAC is then connected to a radio frequency transceiver. The FPGA chip and the DSP chip are electrically connected. The FPGA chip is also electrically connected to a dual phase-locked loop (PLL) frequency synthesis circuit. The ARM implements system-level data synthesis and scheduling, the DSP implements further frequency hopping data control and participates in modulation, demodulation, and error correction coding, and the FPGA performs basic timing control, realizing real-time control of the frequency hopping sequence and the synthesis and switching of radio frequency. The frame structure used by the DSP chip to send frame data to the audio analog-to-digital converter and voice codec chip includes synchronization time slots and multiple sets of data transmission time slots. The synchronization time slots consist of 70 hops, and each set of data transmission time slots has 18 hops. This is used to maintain the synchronization mechanism of the frequency hopping network, enabling frequency hopping acquisition and tracking.

[0005] In a preferred embodiment of the present invention, the dual phase-locked loop frequency synthesis circuit includes a crystal oscillator. An FPGA chip is connected to a first phase detector and a second phase detector, both of which are connected to the crystal oscillator. The first phase detector is connected to a first low-pass filter and a D / A converter. The first low-pass filter and the D / A converter are connected to a first voltage-controlled oscillator, which generates a local oscillator. The second phase detector is connected to a second low-pass filter, which is connected to a second voltage-controlled oscillator, which generates a dual local oscillator. The loop lock-in time is less than 130µs, allowing for rapid frequency switching and achieving a high-speed frequency hopping of 500 hops.

[0006] As a preferred embodiment of the present invention, the synchronization time slot includes a 5*7 hop correlation sequence field, a 5 hop frame synchronization field, a 2*5 hop networking field, a 2*5 hop TODL field, and a 10 hop reserved field.

[0007] As a preferred embodiment of the present invention, the related sequence is a single-hop time slot structure, which includes a 60μs frequency switching time, a 30μs power settling time, a 30μs AGC adjustment time, an 1800μs M sequence time, a 60μs multipath protection time, a 10μs power drop time, and a 10μs protection time.

[0008] As a preferred embodiment of the present invention, the data transmission time slot includes 1 protection jump, 15 data jumps and 2 protection jumps.

[0009] As a preferred embodiment of the present invention, the symbol rate per hop is 32k, the number of symbols per hop is 64, the frequency switching time for 5 symbols is 156.25μs, and the data time for 59 symbols is 1843.75μs.

[0010] As a preferred embodiment of the present invention, the synchronous transmission timing sequence transmitted by the FPGA chip through the radio frequency transceiver includes a first transmission beat and a second transmission beat. The first transmission beat involves repeating each frequency in the WALSH sequence twice, then repeating the entire sequence eight times, forming a 7*2*8 hops, creating a synchronous frequency sweep unit, which is then repeated twice. The second transmission beat consists of a WALSH sequence and a synchronization information sequence, where the WALSH sequence has 7*1 hops and the synchronization information sequence has 7*3 hops, for a total of 7*4 hops. The synchronization information sequence includes TOD (Transit-Oriented Development) information.

[0011] As a preferred embodiment of the present invention, the synchronous search timing sequence executed by the FPGA chip through the radio frequency transceiver includes a first search cycle and a second search cycle. The first search cycle consists of 2 hops per frequency, repeated 8 times, and the search is performed sequentially. The second search cycle is consistent with the first search cycle.

[0012] As a preferred embodiment of the present invention, the synchronous reception timing executed by the FPGA chip through the radio frequency transceiver includes receiving a first beat and receiving a second beat. In the first beat, the transmitting end repeats each frequency in the WALSH sequence twice, and then repeats the whole sequence eight times, forming a 7*2*8 hop. The receiving end repeats each frequency in the WALSH sequence twice, and then repeats it eight times, with each frequency being processed one by one. In the second beat, both the transmitting end and the receiving end form a 7*1+7*3 hop consisting of the WALSH sequence and the synchronization information sequence.

[0013] Compared with existing technologies, the beneficial effects of this invention are as follows: By directly connecting the ARM processor, FPGA chip, and DSP chip in pairs, this invention enables more efficient data interaction, making control and operation more coordinated and increasing radio frequency flexibility. Combined with the frame structure composed of synchronization time slots and data transmission time slots, it can maintain the synchronization mechanism of the frequency hopping network, achieving frequency hopping acquisition and tracking. By using a dual phase-locked loop frequency synthesis circuit, the loop locking time is less than 130µs, allowing for rapid frequency switching and achieving high-speed frequency hopping of 500 hops / s, thereby improving anti-interference capability and system response speed. Furthermore, it compresses the proportion of service frames to less than 10%, allowing for the transmission of more data within the same bandwidth, thus improving effective bandwidth utilization.

[0014] Furthermore, by searching each frequency one by one and using a 16x slow hop method during the search, the synchronization time is significantly shortened. In addition, by extending the dwell time, the ability to capture weak signals is improved, the synchronization reliability is ensured, and the overall communication performance is indirectly improved. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating the system principle of the present invention; Figure 2 This is a block diagram of the frequency synthesizer of the present invention; Figure 3 This is a diagram showing the frame structure composition in the frequency hopping communication of this invention; Figure 4 This is a diagram showing the composition of the frequency hopping format in the frequency hopping communication of this invention; Figure 5 This is a timing diagram for synchronous transmission in frequency hopping communication according to the present invention; Figure 6 This is a timing diagram for synchronization search in frequency hopping communication according to the present invention; Figure 7 This is a timing diagram for synchronous reception in frequency hopping communication according to the present invention.

[0016] In the diagram: 1. ARM processor; 2. FPGA chip; 3. DSP chip; 4. Audio analog-to-digital converter; 5. Voice codec chip; 6. Radar digital-to-analog converter; 7. Radar analog-to-digital converter; 8. Audio interface; 9. Terminal; 10. RF transceiver; 11. First phase detector; 12. Second phase detector; 13. Crystal oscillator; 14. First low-pass filter; 15. D / A converter; 16. First voltage-controlled oscillator; 17. Second low-pass filter; 18. Second voltage-controlled oscillator. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0018] like Figure 1 As shown, this invention discloses a wireless communication system based on a fast frequency hopping and dynamic synchronization mechanism. The technical solution includes an ARM processor 1 and an audio analog-to-digital converter 4. The ARM processor 1 is connected to a DSP chip 3 via an HPI high-speed parallel line. After processing a segment of data, the DSP chip 3 sends an interrupt request to the ARM processor 1 via an INT signal, notifying the ARM processor 1 to read the result. The audio analog-to-digital converter 4 is connected to an audio interface 8 and a voice codec chip 5. The voice codec chip 5 uses an AMBE2000 chip, and both it and the audio analog-to-digital converter 4 interact with the DSP chip 3 via an MCBSP (Multi-channel Buffered Serial Port).

[0019] ARM processor 1 connects to terminal 9 and to FPGA chip 2 via SLAVE SERIAL. FPGA chip 2 connects to DSP chip 3 via EMIF (External Memory Interface). After processing a segment of data, FPGA chip 2 sends an interrupt request to DSP chip 3 via the INT signal, notifying DSP chip 3 to read the result. FPGA chip 2 also connects to RF transceiver 10 via radar digital-to-analog converter 6. RF transceiver 10 performs transmit / receive channel processing and connects to FPGA chip 2 via radar analog-to-digital converter 7. FPGA chip 2 performs channel control on RF transceiver 10.

[0020] like Figure 2As shown, the FPGA chip 2 is also connected to a dual phase-locked loop frequency synthesis circuit, which includes a crystal oscillator 13. Specifically, the FPGA chip 2 is connected to a first phase detector 11 and a second phase detector 12. The crystal oscillator 13 is connected to both the first phase detector 11 and the second phase detector 12. The first phase detector 11 is connected to a first low-pass filter 14. The back end of the first low-pass filter 14 is connected to a first voltage-controlled oscillator 16. The first phase detector 11 is also connected to a D / A converter 15. One end of the D / A converter 15 is also connected to the first low-pass filter 14. The back end of the D / A converter 15 is connected to the first voltage-controlled oscillator 16. One output port of the first voltage-controlled oscillator 16 outputs a local oscillator frequency of 154.8~212.775MHz, and the other output port is connected to the first phase detector 11.

[0021] The second phase detector 12 is connected to the second low-pass filter 17. The second low-pass filter 17 is connected to the second voltage-controlled oscillator 18. One output port of the second voltage-controlled oscillator 18 outputs a 124.416MHz local oscillator, and the other output port is connected to the second phase detector 12.

[0022] In this embodiment, the frame structure used by the frame data sent by the DSP chip 3 to the audio analog-to-digital converter 4 and the voice codec chip 5 is as follows: Figure 3 As shown, it includes one group of 70-hop synchronization time slots and 53 groups of 18-hop data transmission time slots. The 70-hop synchronization time slot structure includes a 5*7-hop correlation sequence field, a 5-hop frame synchronization field, a 2*5-hop networking field, a 2*5-hop TODL field, and a 10-hop reserved field. The 5*7-hop correlation sequence field includes a single-hop time slot structure repeated 5 times. The single-hop time slot structure consists of 7 time segments: 60μs frequency switching time, 30μs power setup time, 30μs AGC adjustment time, 1800μs M-sequence time, 60μs multipath protection time, 10μs power decline time, and 10μs protection time. The 18-hop data transmission time slots include one protection hop, 15 data hops, and two protection hops.

[0023] like Figure 4 As shown, the dwell time per hop is 2ms, the hopping speed is 500hop / s, if the symbol rate per hop is 32k, and there are 64 symbols per hop, the switching time for 5 symbols is 156.25μs, and the data time for 59 symbols is 1843.75μs.

[0024] FPGA chip 2 performs channel control on RF transceiver 10. When RF transceiver 10 is in transmit mode, its synchronous transmission timing structure is as follows: Figure 5As shown, the first beat and the second beat are transmitted. The first beat is transmitted by repeating each frequency in the WALSH sequence twice, then repeating the whole sequence eight times, forming a 7*2*8 hop, and then repeating it twice. The second beat is transmitted by transmitting the WALSH sequence and the synchronization information sequence, where the WALSH sequence is 7*1 hops and the synchronization information sequence is 7*3 hops, for a total of 7*4 hops.

[0025] When the radio frequency transceiver 10 is in the search state, its synchronous search timing structure is as follows: Figure 6 As shown, the search includes a first search cycle and a second search cycle. The first search cycle consists of 2 hops per frequency, repeated 8 times, searching sequentially, meaning each search frequency maintains 16 hops, performed at a 16x slower hop rate. The second search cycle is identical to the first. The first search cycle searches for the initial synchronization header in normal working mode, while the second search cycle searches for the initial synchronization header in emergency mode.

[0026] When the radio frequency transceiver 10 is in receiving mode, its synchronous receiving timing structure is as follows: Figure 7 As shown, the process includes receiving the first and second beats. In the first beat, which is the initial search phase, the transmitter (TX) repeats each frequency in the WALSH sequence twice, and then repeats the entire sequence eight times, forming a 7*2*8 hop. A slow search is performed at 16 times the period. After synchronization with the WALSH sequence, the synchronization information transmitted at the repeated frequencies is deciphered. This step simplifies the synchronization signal, reduces complexity, and facilitates rapid detection by the receiver (SR). The receiver repeats each frequency in the WALSH sequence twice, then eight times, performing each frequency sequentially. This step is a blind search mode. In the second beat, both the transmitter and receiver form a 7*1+7*3 hop sequence using the WALSH sequence and synchronization information sequence. The transmitter uses a complete synchronization signal, simulating the transition patterns of actual communication. TOD (Time of Detail) information is added to the sequence for the receiver to calibrate the low-order time (microsecond level) of its local clock, improving synchronization accuracy. Similarly, in the second beat, after synchronization with the first transmitted WALSH sequence, the complete TOD and synchronization information carried in the receiving repeated frequencies are located. The receiver is in tracking mode, continuously detecting the signal, parsing the TOD information, and correcting the local time to ensure that the frequency hopping time and frame timing of the receiver are completely aligned with the TX. When the synchronization accuracy meets the requirements, the SR notifies the master receiver to "synchronization established" and switches to normal data reception.

[0027] By separating the TX and SR, the SR can only process the synchronization signal and not the data, while the main receiver performs data demodulation, thus avoiding delays or errors caused by functional mixing.

[0028] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A wireless communication system based on a fast frequency hopping and dynamic synchronization mechanism, comprising an ARM processor (1), the ARM processor (1) being connected to an FPGA chip (2) and a DSP chip (3), the DSP chip (3) being further connected to an audio analog-to-digital converter (4), the audio analog-to-digital converter (4) being connected to a voice codec chip (5) and an audio interface (8), the voice codec chip (5) being connected to the DSP chip (3), the ARM processor (1) being connected to a terminal (9), the FPGA chip (2) being connected to a radar digital-to-analog converter (6) and a radar analog-to-digital converter (7) and then connected to a radio frequency transceiver (10), characterized in that: The FPGA chip (2) and the DSP chip (3) are electrically connected; the FPGA chip (2) is also electrically connected to a dual phase-locked loop frequency synthesis circuit; The frame structure used by the DSP chip (3) to send frame data to the audio analog-to-digital converter (4) and the voice codec chip (5) includes a synchronization time slot and multiple sets of data transmission time slots, wherein the synchronization time slot has 70 hops and each set of data transmission time slots has 18 hops.

2. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The dual phase-locked loop frequency synthesis circuit includes a crystal oscillator (13), an FPGA chip (2) connected to a first phase detector (11) and a second phase detector (12), both the first phase detector (11) and the second phase detector (12) are connected to the crystal oscillator (13), the first phase detector (11) is connected to a first low-pass filter (14) and a D / A converter (15), the first low-pass filter (14) and the D / A converter (15) are connected to a first voltage-controlled oscillator (16), the first voltage-controlled oscillator (16) generates a local oscillator; the second phase detector (12) is connected to a second low-pass filter (17), the second low-pass filter (17) is connected to a second voltage-controlled oscillator (18), the second voltage-controlled oscillator (18) generates a dual local oscillator.

3. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The synchronization time slot includes a 5*7 hop related sequence field, a 5 hop frame synchronization field, a 2*5 hop networking field, a 2*5 hop TODL field, and a 10 hop reserved field.

4. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 3, characterized in that: The relevant sequence is a single-hop time slot structure, which includes a 60μs frequency switching time, a 30μs power settling time, a 30μs AGC adjustment time, an 1800μs M sequence time, a 60μs multipath protection time, a 10μs power drop time, and a 10μs protection time.

5. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The data transmission time slot includes 1 protection jump, 15 data jumps and 2 protection jumps.

6. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to any one of claims 1-5, characterized in that: The dwell time per hop is 2ms, and the hopping frequency is 500 hops / s.

7. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 6, characterized in that: The symbol rate per hop is 32k, with 64 symbols per hop. The frequency switching time for 5 symbols is 156.25μs, and the data time for 59 symbols is 1843.75μs.

8. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The synchronous transmission timing sequence sent by the FPGA chip (2) through the radio frequency transceiver (10) includes a first transmission beat and a second transmission beat. The first transmission beat is to repeat each frequency in the WALSH sequence twice, and then repeat the whole sequence eight times to form a 7*2*8 hop, forming a synchronous frequency sweep unit, and then repeat the synchronous frequency sweep unit twice. The second transmission beat consists of a WALSH sequence and a synchronization information sequence. The WALSH sequence is 7*1 hops, and the synchronization information sequence is 7*3 hops, for a total of 7*4 hops. The synchronization information sequence includes TOD information.

9. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The synchronous search timing performed by the FPGA chip (2) through the radio frequency transceiver (10) includes a first search cycle and a second search cycle. The first search cycle consists of 2 hops per frequency, repeated 8 times, and the search is performed one by one. The second search cycle is consistent with the first search cycle.

10. The wireless communication system based on fast frequency hopping and dynamic synchronization mechanism according to claim 1, characterized in that: The synchronous reception timing executed by the FPGA chip (2) through the radio frequency transceiver (10) includes receiving the first beat and receiving the second beat. In the first beat, the transmitter repeats each frequency in the WALSH sequence twice, and then repeats the whole sequence eight times to form a 7*2*8 hop. The receiver repeats each frequency in the WALSH sequence twice, and then repeats it eight times, with each frequency being processed one by one. In the second beat, both the transmitter and receiver form a 7*1+7*3 hop consisting of the WALSH sequence and the synchronization information sequence.

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