A HPLC dual-mode communication module and channel switching method based on channel quality prediction

Abstract

This invention discloses an HPLC dual-mode communication module and channel switching method based on channel quality prediction. The module includes a dual-mode communication SoC chip for acquiring physical layer channel quality parameters and using a trend prediction algorithm to obtain channel quality prediction results, outputting matching level switching commands, digital predistortion coefficient update commands, and dual-mode channel switching commands; a low-voltage side dual-level matching network for selecting the corresponding matching network according to the matching level; a digital predistortion processing module for reading the corresponding digital predistortion coefficients according to the current matching level and performing digital predistortion processing on the baseband transmission signal; and a data buffer and switching control unit for buffering data to be transmitted. This invention avoids the engineering challenges of high-voltage side impedance matching through coordinated compensation of low-voltage side dual-level matching and digital predistortion, reducing bill of materials costs. Simultaneously, it achieves low-latency, zero-loss predictive dual-mode channel switching through lightweight physical layer trend prediction.

Description

Technical Field

[0001] This invention relates to the field of power line carrier communication technology, and in particular to an HPLC dual-mode communication module and channel switching method based on channel quality prediction. Background Technology

[0002] Power line carrier communication (PLC) uses existing power lines as the transmission medium, requiring no additional wiring, making it a low-cost solution for electricity consumption information collection, transformer topology identification, and distributed energy management. High-speed power line carrier communication (HPLC) and high-speed radio frequency (HRF) dual-mode communication are important means to solve the communication blind spots of the single HPLC mode in low-voltage distribution networks.

[0003] Regarding impedance matching, in order to cope with the dynamic changes in power line impedance, existing technologies have proposed setting up an adaptive impedance matching network by setting up a PIN diode switch and an adjustable capacitor array on the power line side. However, this technical solution has the following engineering defects: (1) If the matching network is located on the power line side, the switching device needs to withstand 220V high voltage and surge impact. There is a lack of suitable devices on the market that simultaneously meet the requirements of high voltage withstand, low on-resistance, high frequency characteristics and fast switching speed; (2) The on-resistance (typical value 1~5Ω) and parasitic capacitance of the PIN diode switch will pollute the matching network parameters and affect the matching accuracy; (3) The combination of adjustable capacitor array and adjustable inductor leads to a significant increase in BOM cost, and the parasitic parameters of each board are inconsistent and need to be calibrated board by board, resulting in high mass production costs and making it difficult to promote in cost-sensitive application scenarios. In addition, if a fixed impedance matching network is used (such as designed according to 50Ω or 75Ω), it cannot adapt to the wide range of dynamic changes in actual line impedance, and the signal transmission efficiency is seriously reduced.

[0004] Regarding dual-mode channel switching, most existing dual-mode communication modules implement channel switching through the protocol layer, adopting a passive strategy of "failure first, then switch". This strategy only initiates switching after the HPLC channel quality deteriorates, resulting in severely degraded communication quality before switching, long switching delay (500ms~2s), and wasted transmission power and time due to the ping-pong effect.

[0005] To address the shortcomings of passive handover, existing technologies propose a scheme that predicts channel degradation probability based on frame-level statistical features (frame error rate, retransmission count, ACK ratio) combined with Hidden Markov Models (HMMs). While this scheme introduces the concept of "predictive handover," it employs complex models for prediction, placing high demands on the computing power and storage resources of the SoC chip, making it difficult to achieve efficient deployment in cost- and resource-constrained embedded communication modules.

[0006] Therefore, how to achieve adaptive and efficient matching of HPLC channel impedance without increasing significant hardware costs or relying on high-voltage devices, and at the same time achieve low-latency, zero-loss dual-mode channel switching through a lightweight prediction algorithm with low computational overhead, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] To address the aforementioned shortcomings of existing technologies, this invention provides an HPLC dual-mode communication module and channel switching method based on channel quality prediction. By using a dual-level matching network on the low-voltage side and digital pre-distortion collaborative compensation, it solves the problems of unavailability and high mass production cost of adaptive impedance matching devices on the high-voltage side. At the same time, it achieves predictive dual-mode channel switching through lightweight trend prediction at the physical layer, solving the problems of large delay in passive switching and excessively high computing power requirements of existing prediction schemes.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] An HPLC dual-mode communication module based on channel quality prediction includes:

[0010] A dual-mode communication SoC chip is used to acquire physical layer channel quality parameters, and based on the physical layer channel quality parameters, a trend prediction algorithm is used to obtain channel quality prediction results, and outputs matching gear switching instructions, digital predistortion coefficient update instructions and dual-mode channel switching instructions.

[0011] A low-voltage side dual-stage matching network is located between the power amplifier output terminal and the coupling transformer of the dual-mode communication SoC chip. It is used to receive the matching stage switching command and select the corresponding matching network according to the matching stage.

[0012] The digital predistortion processing module is used to receive the digital predistortion coefficient update command and the baseband transmission signal, read the corresponding digital predistortion coefficient according to the current matching gear, and perform digital predistortion processing on the baseband transmission signal.

[0013] The data caching and switching control unit is used to receive the dual-mode channel switching command and cache the data to be sent into the dual-port cache random access memory included in the data caching and switching control unit.

[0014] Furthermore, the low-voltage side dual-level matching network includes two matching networks and a low-voltage radio frequency switch. Each matching network is a π-type network composed of a fixed inductor and a fixed capacitor, which are used to match the preset equivalent impedance range of the power amplifier output terminal. The low-voltage radio frequency switch is connected between the power amplifier output terminal and the two matching networks, and is used to receive the matching level switching command and select the matching network according to the matching level.

[0015] Furthermore, the digital predistortion processing module employs a memory polynomial model for digital predistortion processing, and the mathematical expression of the memory polynomial model is:

[0016] ;

[0017] In the formula: The signal after digital predistortion processing; For baseband transmission signals; represents the digital predistortion coefficients of the k-th order nonlinearity and the m-th level memory depth; It is a nonlinear order; For memory depth.

[0018] Furthermore, the digital predistortion coefficients are extracted during the module factory calibration stage according to the following steps:

[0019] Based on the matching gear in the low-voltage side dual-gear matching network, the digital predistortion processing module is set to bypass mode.

[0020] Training signals are transmitted through the digital-to-analog conversion channel of the dual-mode communication SoC chip, while the output signal of the power amplifier is sampled through the coupling loop;

[0021] A basis matrix is ​​constructed based on the training signal, and an observation vector is constructed based on the power amplifier output signal.

[0022] The digital predistortion coefficients are solved using the least squares method, and the solved digital predistortion coefficients are written into Flash, and the digital predistortion processing module is enabled; the Flash is used to store the digital predistortion coefficients corresponding to different matching gears.

[0023] Furthermore, the method of solving the digital predistortion coefficients using the least squares method is expressed as follows:

[0024] ;

[0025] In the formula: For digital predistortion coefficients; It is a basis matrix; for The conjugate transpose of; This is the observation vector.

[0026] Furthermore, the coordinated timing of the dual-mode communication SoC chip outputting the matching gear switching instruction and the digital predistortion coefficient update instruction is as follows:

[0027] The dual-mode communication SoC chip pauses the transmission of the current frame and temporarily stores the data to be transmitted in the dual-port buffer random access memory; the dual-mode communication SoC chip reads the digital predistortion coefficient corresponding to the switched matching level from Flash and outputs the digital predistortion coefficient update instruction to the digital predistortion processing module; the dual-mode communication SoC chip outputs the matching level switching instruction to the low-voltage RF switch of the low-voltage side dual-level matching network through the general input / output interface; after the low-voltage RF switch stabilizes, the dual-mode communication SoC chip enables the switched digital predistortion coefficient and resumes frame transmission.

[0028] Furthermore, during the switching process of digital predistortion coefficients, the digital predistortion processing module uses a linear gradual interpolation method to achieve a smooth transition of the digital predistortion coefficients:

[0029] ;

[0030] In the formula: The actual digital predistortion coefficient used at the nth sampling point during the gradual transition process; The digital predistortion coefficients before the switch; The digital predistortion coefficients after switching; These are linear weighting coefficients; This is the preset number of sampling points for the gradual transition.

[0031] Furthermore, the dual-port cache random access memory is connected to the data bus of the dual-mode communication SoC chip via a direct memory access controller.

[0032] A channel switching method based on channel quality prediction, applied to the aforementioned HPLC dual-mode communication module based on channel quality prediction, includes the following steps:

[0033] S1. The physical layer channel quality parameters are periodically collected through the physical layer channel quality parameter reading interface of the dual-mode communication SoC chip, and the physical layer channel quality parameters are stored in the sliding window buffer to obtain the historical physical layer channel quality parameter sequence.

[0034] S2. Using a trend prediction algorithm, the short-term mean and trend of channel quality are calculated based on the historical physical layer channel quality parameter sequence to obtain the channel quality prediction result.

[0035] S3. Based on the channel quality prediction result, the matching level of the low-voltage side dual-level matching network is switched by the low-voltage radio frequency switch, and the digital predistortion coefficient corresponding to the current matching level is read synchronously to update the digital predistortion coefficient used by the digital predistortion processing module.

[0036] S4. Determine whether dual-mode channel switching is required based on the channel quality prediction result. If dual-mode channel switching is required, buffer the data to be transmitted in the current channel and enable the backup channel, and perform dual-mode channel switching.

[0037] S5. After performing dual-mode channel switching, periodically detect the received signal strength indicator of the current channel. When the received signal strength indicator of the current channel returns to normal and remains stable for a period of time, switch back to the current channel and return to step S1.

[0038] As a preferred embodiment, in step S2, the changing trend includes the changing trend of signal-to-noise ratio and the changing trend of packet error rate;

[0039] Step S4 specifically includes: when the channel quality prediction result meets the handover preparation conditions, entering the handover preparation state, copying the data to be transmitted in the current channel to the dual-port buffer random access memory, and pre-activating the backup channel; wherein, the handover preparation conditions are that the signal-to-noise ratio decreases by more than the decrease rate threshold, or the packet error rate increases by more than the increase rate threshold; when the channel quality prediction result meets the handover conditions, performing dual-mode channel handover, closing the current channel, and enabling the backup channel; wherein, the handover conditions are that the signal-to-noise ratio is lower than the signal-to-noise ratio threshold, or the packet error rate is higher than the packet error rate threshold, or the acknowledgment frame times out continuously.

[0040] Compared with the prior art, the present invention has the following technical effects:

[0041] 1. This invention moves the matching network from the high-voltage side of the power line to the low-voltage side of the power amplifier output. It uses a low-voltage RF switch to switch between two fixed-parameter π-type matching networks, thereby avoiding the engineering problems of insufficient withstand voltage of high-voltage side switching devices and parasitic parameter contamination of the network. Moreover, it can be mass-produced without board-by-board calibration. On this basis, the digital predistortion coefficient is updated synchronously when the matching level is switched. A memory polynomial model is used to predistort the baseband transmission signal to compensate for the nonlinear distortion of the power amplifier caused by the sudden change in load impedance. This digital predistortion processing is completed in the digital domain, which can significantly improve the transmission efficiency and communication success rate without increasing the additional hardware cost.

[0042] 2. This invention extracts the digital predistortion coefficients corresponding to each matching level and writes them into Flash during the module factory calibration stage, eliminating the need for board-by-board calibration and solving the problem of uncontrolled mass production costs; at the moment of coefficient switching, a linear gradual interpolation method is used to achieve a smooth transition, ensuring that the switching process does not affect the communication quality.

[0043] 3. This invention abandons the heavy prediction method of combining frame-level statistical features with hidden Markov models, and instead uses physical layer real-time parameters with sliding window and linear extrapolation algorithms to predict future channel quality, reducing computational overhead and enabling efficient operation in resource-constrained SoCs; when the predicted channel quality degradation trend exceeds the threshold, it enters the handover preparation state in advance, buffers the data to be sent and pre-activates the backup channel; when the channel quality deteriorates to the threshold, it immediately performs dual-mode channel handover, with handover latency far superior to traditional passive handover schemes, achieving zero data loss.

[0044] 4. The two matching ranges of this invention together cover the main variation range of power line impedance within the HPLC working frequency band. The range selection logic is directly linked to the channel quality prediction results. It automatically switches to the matching range that is suitable for the current load scenario based on the signal-to-noise ratio and packet error rate, and can complete adaptive matching without relying on reflected wave detection hardware.

[0045] 5. After switching to the backup channel, the present invention continuously detects the received signal strength indication of the original channel. After the signal strength returns to normal, it switches back to the original channel, forming a complete closed loop. Through the synergy of "low-voltage side dual-level matching to avoid high-voltage device problems, digital pre-distortion to compensate for level switching distortion, and physical layer lightweight trend prediction to achieve low-latency and zero-loss switching", impedance adaptive matching and seamless channel switching are achieved under the conditions of minimal hardware cost increment and controllable computational overhead. Attached Figure Description

[0046] To make the objectives, technical solutions, and advantages of the invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0047] Figure 1 This is a diagram illustrating the overall architecture of the HPLC dual-mode communication module based on channel quality prediction in an embodiment of the present invention.

[0048] Figure 2 This is a diagram showing the topology and parameter design of the low-voltage side dual-stage matching network circuit in an embodiment of the present invention.

[0049] Figure 3 This is a circuit schematic diagram of the low-voltage side dual-stage matching network and digital predistortion processing module in an embodiment of the present invention.

[0050] Figure 4 This is a schematic diagram illustrating the nonlinear distortion mechanism of PA and the impact of gear shifting in an embodiment of the present invention: Figure 4 (a) shows the AM / AM characteristic curve of PA. Figure 4 (b) shows the AM / PM characteristic curve of PA. Figure 4 (c) is a comparison of the third-order cross-modulation distortion suppression effect of PA;

[0051] Figure 5This is a timing diagram of the coordinated update of gear shifting and digital predistortion coefficients in an embodiment of the present invention;

[0052] Figure 6 This is a flowchart of the channel switching method based on channel quality prediction in an embodiment of the present invention. Detailed Implementation

[0053] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0055] Example:

[0056] Existing HPLC dual-mode communication modules have the following limitations in impedance matching and channel switching: First, existing adaptive impedance matching schemes attempt to address dynamic changes in power line impedance by setting PIN diode switches and adjustable capacitor arrays on the high-voltage side of the power line. However, the high-voltage side switching devices are difficult to balance in terms of withstand voltage, on-resistance, and high-frequency characteristics. The combination of adjustable components leads to a significant increase in BOM (Bill of Materials) costs, and mass production requires calibration board by board. Meanwhile, fixed impedance matching networks cannot adapt to a wide range of dynamic changes in line impedance. Second, existing dual-mode channel switching adopts a passive strategy of "failure first, then switch," resulting in switching delays of hundreds of milliseconds to several seconds, which cannot meet the needs of business scenarios with high real-time requirements. Even if existing technologies propose using Hidden Markov Models for predictive switching, the complexity of these models places unbearable demands on SoC computing power and storage resources in cost-sensitive embedded modules.

[0057] To address the aforementioned problems and shortcomings, this invention proposes an HPLC dual-mode communication module and channel switching method based on channel quality prediction, offering solutions from three dimensions: At the hardware architecture level, the impedance matching network is moved from the high-voltage side to the low-voltage side of the power amplifier output, and a low-voltage RF switch switches between two fixed-parameter π-type matching networks, fundamentally avoiding the engineering challenges of high-voltage devices; at the signal compensation level, digital predistortion technology is applied to the HPLC power amplifier range switching scenario, synchronously updating the digital predistortion coefficient during range switching to compensate for the nonlinear distortion exacerbated by sudden changes in load impedance; at the channel switching level, a lightweight trend prediction algorithm is adopted based on real-time physical layer parameters to proactively complete data caching and backup channel warm-up before channel quality deteriorates, achieving low-latency, zero-loss dual-mode channel switching.

[0058] The embodiments of the present invention relate to an HPLC dual-mode communication module and its channel switching method, wherein the hardware architecture of the dual-mode communication module and the software flow of the channel switching method cooperate with each other to jointly realize adaptive impedance matching and low-latency channel switching based on channel quality prediction.

[0059] The following sections will further introduce and explain the HPLC dual-mode communication module and its channel switching method.

[0060] I. HPLC Dual-Mode Communication Module

[0061] like Figure 1 As shown, the HPLC dual-mode communication module in this embodiment includes a dual-mode communication SoC chip, a low-voltage side dual-level matching network, a digital predistortion processing module, a power line coupling circuit, an HRF radio frequency front end, a power management unit, a data buffer and switching control unit, a four-level protection circuit, and an external interface.

[0062] The dual-mode communication SoC chip adopts the existing State Grid certified dual-mode SoC chip, which integrates a RISC-V core (200MHz), an HPLC baseband processor (supporting OFDM modulation / demodulation, BPSK to 64-QAM adaptive modulation and coding, and a communication rate of up to 2.4Mbps), an HRF radio frequency transceiver (470MHz~510MHz band, 2-FSK / GFSK modulation, maximum transmit power +20dBm), a 12-bit ADC, a 10-bit DAC, a channel quality monitoring interface (real-time reading of received signal strength indication, signal-to-noise ratio and packet error rate), dual-channel DMA and hardware CRC check.

[0063] The low-voltage side dual-stage matching network is located between the power amplifier output of the dual-mode communication SoC chip and the primary winding of the coupling transformer. It includes two π-type matching networks with fixed parameters and a low-voltage RF switch, which are used to select the corresponding matching network according to the matching stage to adapt to different line impedances.

[0064] The data caching and switching control unit includes a dual-port cache random access memory (4KB capacity) and a switching controller. The switching controller is implemented based on the general input / output interface and hardware timer of the dual-mode communication SoC chip, with a response time of less than 100 microseconds.

[0065] The power line coupling circuit adopts a series coupling method and includes a coupling capacitor (0.1μF / 630V, X2 safety capacitor), a parallel discharge resistor (100 kΩ / 2W) and a discharge tube (90V DC breakdown voltage).

[0066] The HRF radio frequency front end includes a power amplifier (+20dBm), a low-noise amplifier (noise figure of about 3dB), a single-pole double-throw radio frequency switch (switching time of less than 1μs), a surface acoustic wave filter (490MHz / 2MHz), and a printed circuit board inverted F antenna (gain of about 2.2dBi) built into the dual-mode communication SoC chip.

[0067] The power management unit adopts a single-stage DC-DC step-down plus multi-stage LDO architecture, which directly reduces the 12V input to 3.3V and supports four power management modes from PM0 to PM3. In the PM3 deep monitoring mode, the dual-mode communication SoC chip core is in a hold state and the HPLC receiving front end is intermittently turned on, with a static power consumption of no more than 250mW.

[0068] The data caching and switching control unit includes a dual-port cached random access memory (4KB capacity) and a switching controller. The switching controller is implemented based on the general input / output interface and hardware timer of the dual-mode communication SoC chip, with a response time of less than 100 microseconds, and is used to cache the data to be sent before the dual-mode channel switching.

[0069] The four-level protection circuit adopts a four-level progressive architecture of front-end interface protection, coupling back-end protection, ESD protection, and overcurrent and overtemperature protection to meet the interface surge protection level requirements.

[0070] The external interfaces include a universal asynchronous transceiver interface (9600–115200 bps), an SPI interface (4-wire, 50 MHz), a universal input / output interface (12 channels), and a JTAG / SWD debug interface, used for communication and debugging with external devices.

[0071] The printed circuit board of the module adopts a 6-layer design, with the second and fourth layers being complete ground planes. The distance between the HRF radio frequency front end and the HPLC analog front end is not less than 5mm and is isolated by an independent grounding island. The impedance of the radio frequency trace is controlled at 50Ω, and the impedance of the analog signal trace is controlled at 100Ω.

[0072] 1. Overall Module Architecture

[0073] In this embodiment, the dual-mode communication SoC chip is used to acquire physical layer channel quality parameters, obtain channel quality prediction results based on the physical layer channel quality parameters using a trend prediction algorithm, and output matching gear switching instructions, digital predistortion coefficient update instructions, and dual-mode channel switching instructions.

[0074] A low-voltage side dual-stage matching network is located between the power amplifier output terminal and the coupling transformer of the dual-mode communication SoC chip. It is used to receive the matching stage switching command and select the corresponding matching network according to the matching stage.

[0075] The digital predistortion processing module is used to receive the digital predistortion coefficient update command and the baseband transmission signal, read the corresponding digital predistortion coefficient according to the current matching gear, and perform digital predistortion processing on the baseband transmission signal.

[0076] The data caching and switching control unit is used to receive the dual-mode channel switching command and cache the data to be sent into the dual-port cache random access memory included in the data caching and switching control unit.

[0077] 2. Low-voltage side dual-range matching network

[0078] In this embodiment, the low-voltage side dual-stage matching network is located between the power amplifier (PA) output of the dual-mode communication SoC chip and the coupling transformer. The coupling transformer transforms the power line impedance to the power amplifier side, and the equivalent impedance of the power amplifier side... ,in For electric field line impedance, and All of these refer to the number of transformer turns. In this implementation, the transformer turns ratio is set as follows: : = 4:1, then the equivalent impedance on the PA side is: ;when =1.5~5Ω (equivalent to low-voltage side) = 24~80Ω. Therefore, this embodiment only needs to design two fixed matching positions on the PA side to cover the main working scenarios.

[0079] In practice, the low-voltage side dual-stage matching network includes two π-type matching networks with fixed parameters and a low-voltage radio frequency switch.

[0080] Gear A matching network, consisting of a fixed inductor and fixed capacitor It forms a π-type network, which is suitable for power amplifier side equivalent impedance range of 15Ω to 35Ω (corresponding to heavy load at the near end and peak power consumption periods).

[0081] Gear B matching network, consisting of a fixed inductor and fixed capacitor It forms a π-type network, suitable for power amplifier side equivalent impedance range of 35Ω to 80Ω (corresponding to light load at the far end and low load at night).

[0082] Both are π-type matching networks with fixed LC parameters. The parameters are determined through simulation and field measurement during the module design stage and do not require online adjustment.

[0083] The low-voltage radio frequency (RF) switch uses a low-voltage single-pole double-throw RF switch chip with an operating voltage not exceeding 5V, an on-resistance of less than 2Ω, and a switching time of less than 100ns. The low-voltage RF switch is connected between the power amplifier output and the matching networks for range A and range B, selecting the matching range according to the instructions of the dual-mode communication SoC chip. The on-resistance of the low-voltage RF switch is included as part of the source impedance in the parameter calculation of each range's π-type network. That is, the π-type networks for range A and range B are designed with the sum of the power amplifier output impedance and the switch on-resistance as the source impedance to absorb the influence of the on-resistance on the matching accuracy.

[0084] The gear selection logic is automatically completed by the software of the dual-mode communication SoC chip based on channel quality parameters, rather than relying on the reflected wave detection hardware: when the received signal strength indication is high and the signal-to-noise ratio is good, corresponding to the working condition of close-range strong coupling and low line equivalent impedance, gear A is selected; when the received signal strength indication is low and the packet error rate increases, corresponding to the working condition of long-distance weak coupling and high line equivalent impedance, gear B is selected; the default gear is A upon initial power-on, and the optimal gear is determined within 10 seconds.

[0085] In specific implementation, such as Figure 2 As shown, for a π-type network, let the source impedance be... = 50 ohms (PA output impedance), target load impedance working center frequency = 3MHz (HPLC center frequency band), then the parameters of the π-type network element are calculated as follows:

[0086] ;

[0087] ;

[0088] ;

[0089] ;

[0090] ;

[0091] In the formula: For quality factor; The center angular frequency; For series inductance reactance; It is a series inductor; The value of the parallel capacitor at the input terminal; This is the value of the parallel capacitor at the output terminal.

[0092] In this specific embodiment, the series inductance of the matching network for gear A is 1.33μH, the source capacitance is 1.06nF, and the load capacitance is 2.12nF, used to match the equivalent impedance of a load of 15Ω~35Ω; the series inductance of the matching network for gear B is 1.33μH, the source capacitance is 1.06nF, and the load capacitance is 0.53nF, used to match the equivalent impedance of a load of 50Ω~80Ω. Gear A covers the low impedance range (15Ω~35Ω), corresponding to direct power line coupling or short-range strong signal scenarios; gear B covers the high impedance range (50Ω~80Ω), corresponding to long-distance or weak coupling scenarios; both gears together cover the design target impedance range of 15Ω~80Ω, of which the load equivalent impedance in the 35Ω~50Ω transition range is covered by the two gears in a mismatch tolerance manner. The matching efficiency (reflection coefficient) of each gear in its adaptation range is better than -10dB at the center frequency of the carrier band (voltage standing wave ratio VSWR < 2.0).

[0093] 3. Digital predistortion processing module and memory polynomial model

[0094] Based on the low-voltage side dual-range matching network, this embodiment also introduces a digital pre-distortion (DPD) processing module to compensate for the nonlinear distortion of the power amplifier during range switching, forming a collaborative scheme of "dual-range matching + digital pre-distortion", as shown below. Figure 3 As shown.

[0095] Power amplifiers exhibit two core types of nonlinear distortion during operation: AM / AM distortion and AM / PM distortion. When the matching mode on the power amplifier side is switched, the load impedance changes, causing the load line of the power amplifier to shift. Increased load impedance leads to a larger voltage swing, making the power amplifier more prone to entering the saturation region. Simultaneously, both the gain and phase characteristic curves shift. For example... Figure 4As shown, the third-order intermodulation distortion can worsen by 5–8 dB and the error vector amplitude by 3–5 dB during gear switching. If only power back-off is used to address the linearity issue, the power amplifier output power needs to be backed down by 3–6 dB, resulting in a significant decrease in transmission efficiency and failing to effectively compensate for the sudden distortion during gear switching. Therefore, performing digital pre-distortion processing on the baseband transmission signal before the power amplifier, by pre-injecting inverse distortion components to cancel the nonlinear distortion of the power amplifier, is an effective way to solve the linearity degradation caused by gear switching.

[0096] In this embodiment, when the matching position is switched from A to B, the load impedance of the PA changes instantaneously, and its nonlinear characteristics change accordingly. The DPD (Digital Signal Processor) pre-injects an inverting distortion component when the DAC generates the transmit signal to counteract the signal distortion caused by the PA's nonlinearity, thus restoring the linearity of the PA's amplified output signal. The pre-distortion coefficients are written to the Flash memory during the module's factory calibration phase. Each matching position corresponds to a set of pre-distortion coefficients (including AM / AM and AM / PM characteristic compensation coefficients), requiring only one calibration and eliminating the need for board-by-board calibration. During matching position switching, the dual-mode communication SoC chip synchronously updates the DPD coefficients (reading the corresponding coefficient set from the Flash memory), with a switching time of less than 1ms. The computational overhead is handled in real-time by the SoC's built-in DSP (Digital Signal Processor), with additional overhead of less than 5%, which does not affect the communication rate.

[0097] In this embodiment, the digital predistortion processing module employs a memory polynomial model for digital predistortion processing. Compared to a memoryless polynomial model, the memory polynomial model can simultaneously compensate for the static nonlinearity (AM / AM, AM / PM) and dynamic memory effects (caused by the power amplifier's thermal effects and bias circuitry), making it more suitable for broadband OFDM signals. The mathematical expression of the memory polynomial model is:

[0098] ;

[0099] In the formula: The signal after digital predistortion processing; For baseband transmission signals; represents the digital predistortion coefficients of the k-th order nonlinearity and the m-th level memory depth; It is a nonlinear order; For memory depth.

[0100] In specific implementation, the nonlinear order K=5 of the memory polynomial model, covering 1st (linear), 3rd, and 5th (nonlinear) orders; the memory depth M=2, covering the memory effect of the current sampling point and the previous sampling point. A total of K×M=10 sets of digital predistortion coefficients are required, with a storage requirement of approximately 80 bytes, stored in the built-in Flash of the dual-mode communication SoC chip.

[0101] In practical implementation, the signal processing link of the digital predistortion processing module is as follows:

[0102] The dual-mode communication SoC chip receives the baseband transmission signal, and the digital predistortion processing module uses the memory polynomial model to perform digital predistortion calculation on the baseband transmission signal to obtain the signal after digital predistortion processing.

[0103] The digital-to-analog conversion channel of the dual-mode communication SoC chip converts the digitally pre-distorted signal into an analog signal, which is then amplified by the power amplifier and output to the low-voltage side dual-range matching network.

[0104] During the module's factory calibration phase, the output of the power amplifier is sampled by the coupling loop and sent to the analog-to-digital conversion channel of the dual-mode communication SoC chip to extract the digital predistortion coefficients.

[0105] Predistortion processing is performed in the digital domain without changing the original RF hardware link. It only increases the computational overhead of the digital signal processor in the dual-mode communication SoC chip, with the additional overhead being less than 5% and not affecting the communication rate.

[0106] 4. Calibration of digital predistortion coefficients

[0107] In order to ensure that the digital predistortion processing module has the corresponding digital predistortion coefficient in each matching gear, this embodiment performs the following calibration process during the module factory calibration stage.

[0108] In this embodiment, the digital predistortion coefficients are written to the flash memory of the dual-mode communication SoC chip once during the module's factory calibration stage, and each matching level corresponds to an independent set of digital predistortion coefficients. The calibration environment is set up as follows: a signal generator generates standard OFDM test frames (1024 subcarriers, QPSK modulation, bandwidth 12MHz); a spectrum analyzer observes the power amplifier output spectrum and measures the adjacent channel power ratio and IMD3 index; the control PC communicates with the module through a universal asynchronous transceiver interface, sends calibration commands and receives sampling data; in the coupling sampling loop, the power amplifier output is sampled by a -30dB directional coupler and sent to the 12-bit ADC built into the dual-mode communication SoC chip.

[0109] In this embodiment, the calibration steps (executed independently for each range) are as follows:

[0110] Based on the matching gear in the low-voltage side dual-gear matching network, the digital predistortion processing module is set to bypass mode.

[0111] Training signals are transmitted through the digital-to-analog conversion channel of the dual-mode communication SoC chip, while the output signal of the power amplifier is sampled through the coupling loop;

[0112] A basis matrix is ​​constructed based on the training signal, and an observation vector is constructed based on the power amplifier output signal.

[0113] The digital predistortion coefficients are solved using the least squares method, and the solved digital predistortion coefficients are written into Flash. The Flash is used to store the digital predistortion coefficients corresponding to different matching levels.

[0114] The digital predistortion coefficients, obtained using the least squares method, are expressed as follows:

[0115] ;

[0116] In the formula: For digital predistortion coefficients; It is a basis matrix; for The conjugate transpose of; This is the observation vector.

[0117] Enable the digital predistortion processing module and verify the improvement in communication quality before and after enabling the digital predistortion processing module. The verification standard is: the improvement in adjacent channel power ratio is greater than 10dB. If the verification is not met, repeat steps two to five (up to 3 iterations).

[0118] 5. Coordinated timing of gear shifting and digital predistortion coefficient updates

[0119] When calibration is complete and the system is functioning normally, the gear shifting and digital predistortion coefficient updates need to be precisely coordinated. The coordination timing between the two is described in detail below.

[0120] When the software of the dual-mode communication SoC chip determines that a matching level needs to be switched based on the channel quality parameters, it simultaneously completes the RF switch switching and DPD coefficient update to ensure the continuity and linearity of the transmitted signal.

[0121] The specific coordination timing is as follows: the dual-mode communication SoC chip pauses the transmission of the current frame and temporarily stores the data to be transmitted in the dual-port buffer random access memory; the dual-mode communication SoC chip reads the digital predistortion coefficient corresponding to the switched matching level from Flash and outputs the digital predistortion coefficient update instruction to the digital predistortion processing module; the dual-mode communication SoC chip outputs the matching level switching instruction to the low-voltage RF switch of the low-voltage side dual-level matching network through the general-purpose input / output interface; after the low-voltage RF switch stabilizes, the dual-mode communication SoC chip activates the switched digital predistortion coefficient and resumes frame transmission. The total switching time is approximately 200µs, much less than 1ms.

[0122] During the switching process of digital predistortion coefficients, such as Figure 5 As shown, the digital predistortion processing module uses a linear gradual interpolation method to achieve a smooth transition of the digital predistortion coefficients, so as to avoid the predistortion signal from having a step jump and generating transient spikes:

[0123] ;

[0124] In the formula: The actual digital predistortion coefficient used at the nth sampling point during the gradual transition process; The digital predistortion coefficients before the switch; The digital predistortion coefficients after switching; These are linear weighting coefficients; The preset number of gradient transition sampling points (in this embodiment) =32, approximately 0.64µs@50MHz), n increases from 0 to Gradual interpolation can suppress switching transient spikes to below -40 dBc.

[0125] II. Channel switching method based on the module

[0126] The hardware architecture of the HPLC dual-mode communication module and the specific implementation of each module have been described above. Based on the module, this embodiment also provides a channel switching method based on channel quality prediction. This method utilizes the functions of each module in the module to achieve low-latency, zero-data-loss dual-mode channel switching. The implementation process of each step in this method is described in detail below.

[0127] like Figure 6 As shown, the channel switching method includes the following steps:

[0128] S1. The physical layer channel quality parameters are periodically collected through the physical layer channel quality parameter reading interface of the dual-mode communication SoC chip, and the physical layer channel quality parameters are stored in the sliding window buffer to obtain the historical physical layer channel quality parameter sequence.

[0129] In this embodiment, the software of the dual-mode communication SoC chip periodically reads three physical layer channel quality parameters: received signal strength indication, signal-to-noise ratio, and packet error rate, with a collection period of T=100ms.

[0130] S2. Using a trend prediction algorithm, the short-term mean and trend of channel quality are calculated based on the historical physical layer channel quality parameter sequence to obtain the channel quality prediction result.

[0131] In this embodiment, the quality trend prediction algorithm maintains a sliding window (N=20, corresponding to 2 seconds of historical data) and calculates the short-term mean of the received signal strength indication. Short-term mean of signal-to-noise ratio Short-run mean of error rate The trend of signal-to-noise ratio ,in, The average signal-to-noise ratio for the most recent window. The mean signal-to-noise ratio is the value of the signal-to-noise ratio in the early window; linear extrapolation is used to predict the channel quality in the next 500ms.

[0132] The prediction and determination rules are as follows:

[0133] (1) When > 15dB and When < 1%, the HPLC channel is considered to be in good condition, and HPLC mode should be maintained;

[0134] (2) When The downward trend is greater than 3dB / s or When the upward trend exceeds 5% / s, it is predicted that the HPLC will deteriorate and a switchover preparation will be triggered.

[0135] (3) When < 8dB or If the value is >10%, the HPLC channel is deemed unreliable and should be switched immediately.

[0136] (4) When the HPLC confirms the frame timeout three times in a row, the HPLC link is determined to be interrupted and the connection is switched immediately.

[0137] The computational cost of the lightweight prediction algorithm described above is less than 1 ms.

[0138] S3. Based on the channel quality prediction result, the matching level of the low-voltage side dual-level matching network is switched by the low-voltage radio frequency switch, and the digital predistortion coefficient corresponding to the current matching level is read synchronously to update the digital predistortion coefficient used by the digital predistortion processing module.

[0139] S4. Determine whether dual-mode channel switching is required based on the channel quality prediction result. If dual-mode channel switching is required, buffer the data to be transmitted in the current channel and enable the backup channel, and perform dual-mode channel switching.

[0140] In this embodiment, the need for dual-mode channel switching is determined based on the channel quality prediction result: when the channel quality prediction result meets the switching preparation conditions, the system enters the switching preparation state, copies the data to be transmitted in the current channel to the dual-port buffer random access memory, and pre-activates the backup channel; wherein, the switching preparation conditions are that the signal-to-noise ratio decreases by more than the decrease rate threshold, or the packet error rate increases by more than the increase rate threshold.

[0141] Specifically, the handover preparation phase: when the signal-to-noise ratio decreases by more than 3dB / s or the packet error rate increases by more than 5% / s, the handover preparation state is entered.

[0142] (1) The direct memory access controller copies the data to be sent in the current channel to the dual-port buffer random access memory;

[0143] (2) Pre-activate the HRF receiving front-end of the backup channel;

[0144] (3) Send a channel switching announcement frame to the peer node.

[0145] When the channel quality prediction result meets the switching conditions, a dual-mode channel switching is performed, the current channel is closed, and the backup channel is enabled; wherein, the switching conditions are that the signal-to-noise ratio is lower than the signal-to-noise ratio threshold, or the packet error rate is higher than the packet error rate threshold, or the acknowledgment frame times out continuously.

[0146] Specifically, during the immediate switching phase: when the signal-to-noise ratio is less than 8dB, the packet error rate is greater than 10%, or the continuous acknowledgment frame times out, dual-mode channel switching is performed.

[0147] (1) Close the current channel;

[0148] (2) Activate the backup channel;

[0149] (3) The direct memory access controller sends the data to be transmitted in the dual-port buffer random access memory to the backup channel transmission buffer for continued transmission.

[0150] The switching delay is less than 100 microseconds, achieving zero data loss during the switching process.

[0151] S5. After performing dual-mode channel switching, periodically detect the received signal strength indicator of the current channel. When the received signal strength indicator of the current channel returns to normal and remains stable for a period of time, switch back to the current channel and return to step S1.

[0152] In this embodiment, after the dual-mode channel switching is performed, when the dual-mode communication module is in HRF mode, the HPLC receiving front-end maintains low-power monitoring: it detects the received signal strength indication of the HPLC channel every 200 milliseconds. If the received signal strength indication of the HPLC channel returns to normal and lasts for 3 seconds, it is determined that the HPLC channel has recovered, and a predictive preparation mechanism is used to switch back to the HPLC channel. If more than 16 consecutive communication failures occur in HRF mode, an abnormal alarm frame is reported through the Universal Asynchronous Receiver / Transmitter interface.

[0153] III. Overview

[0154] In summary, this embodiment proposes an HPLC dual-mode communication module and channel switching method based on channel quality prediction. By setting a low-voltage dual-level matching network on the output side of the power amplifier and using a low-voltage RF switch to switch between two fixed-parameter π-type matching networks, the unavailability of high-voltage adaptive matching devices and the problem of uncontrollable mass production costs are avoided. At the same time, a digital predistortion processing module is introduced to update the digital predistortion coefficients synchronously when switching matching levels, effectively compensating for the nonlinear distortion of the power amplifier caused by sudden changes in load impedance. During the factory calibration stage, the least squares method is used to extract the digital predistortion coefficients corresponding to each matching level in one go and write them to Flash. Only one calibration is required, and no board-by-board calibration is needed, ensuring mass production feasibility.

[0155] At the channel switching level, this embodiment abandons the heavy prediction method of combining frame-level statistical features with hidden Markov models, and instead uses physical layer channel quality parameters with sliding windows and linear extrapolation algorithms to achieve lightweight trend prediction, which can run efficiently in resource-constrained embedded SoCs. When a channel quality degradation is predicted, the system enters the switching preparation state in advance, buffers the data to be transmitted in a dual-port buffered random access memory, and pre-activates the backup channel, achieving low-latency, zero-data-loss predictive dual-mode channel switching.

[0156] This embodiment achieves impedance adaptive matching and seamless channel switching through a triple collaborative mechanism of "low-voltage side dual-level matching + digital pre-distortion compensation + lightweight trend prediction at the physical layer" with minimal increase in hardware cost and controllable computational overhead. It can be widely used in power line carrier communication scenarios such as smart distribution terminals, distributed energy monitoring nodes, and smart meter terminals at the edge of distribution areas, and has good industrial practical value and prospects for promotion and application.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. An HPLC dual-mode communication module based on channel quality prediction, characterized in that, include: A dual-mode communication SoC chip is used to acquire physical layer channel quality parameters, and based on the physical layer channel quality parameters, a trend prediction algorithm is used to obtain channel quality prediction results, and outputs matching gear switching instructions, digital predistortion coefficient update instructions and dual-mode channel switching instructions. A low-voltage side dual-stage matching network is located between the power amplifier output terminal and the coupling transformer of the dual-mode communication SoC chip. It is used to receive the matching stage switching command and select the corresponding matching network according to the matching stage. The digital predistortion processing module is used to receive the digital predistortion coefficient update command and the baseband transmission signal, read the corresponding digital predistortion coefficient according to the current matching gear, and perform digital predistortion processing on the baseband transmission signal. The data caching and switching control unit is used to receive the dual-mode channel switching command and cache the data to be sent into the dual-port cache random access memory included in the data caching and switching control unit.

2. The HPLC dual-mode communication module based on channel quality prediction according to claim 1, characterized in that, The low-voltage side dual-level matching network includes two matching networks and a low-voltage RF switch. Each matching network is a π-type network composed of a fixed inductor and a fixed capacitor, which are used to match the preset equivalent impedance range of the power amplifier output terminal. The low-voltage RF switch is connected between the power amplifier output terminal and the two matching networks, and is used to receive the matching level switching command and select the matching network according to the matching level.

3. The HPLC dual-mode communication module based on channel quality prediction according to claim 1, characterized in that, The digital predistortion processing module uses a memory polynomial model for digital predistortion processing. The mathematical expression of the memory polynomial model is: ； In the formula: The signal after digital predistortion processing; For baseband transmission signals; represents the digital predistortion coefficients of the k-th order nonlinearity and the m-th level memory depth; It is a nonlinear order; For memory depth.

4. The HPLC dual-mode communication module based on channel quality prediction according to claim 3, characterized in that, The digital predistortion coefficients are extracted during the module factory calibration stage according to the following steps: Based on the matching gear in the low-voltage side dual-gear matching network, the digital predistortion processing module is set to bypass mode. Training signals are transmitted through the digital-to-analog conversion channel of the dual-mode communication SoC chip, while the output signal of the power amplifier is sampled through the coupling loop; A basis matrix is ​​constructed based on the training signal, and an observation vector is constructed based on the power amplifier output signal. The digital predistortion coefficients are solved using the least squares method, and the solved digital predistortion coefficients are written into Flash, and the digital predistortion processing module is enabled; the Flash is used to store the digital predistortion coefficients corresponding to different matching gears.

5. The HPLC dual-mode communication module based on channel quality prediction according to claim 4, characterized in that, The digital predistortion coefficients, obtained using the least squares method, are expressed as follows: ； In the formula: For digital predistortion coefficients; It is a basis matrix; for The conjugate transpose of; This is the observation vector.

6. The HPLC dual-mode communication module based on channel quality prediction according to claim 1, characterized in that, The coordinated timing of the dual-mode communication SoC chip outputting the matching gear switching command and the digital predistortion coefficient update command is as follows: The dual-mode communication SoC chip pauses the transmission of the current frame and temporarily stores the data to be transmitted in the dual-port buffer random access memory; the dual-mode communication SoC chip reads the digital predistortion coefficient corresponding to the switched matching level from Flash and outputs the digital predistortion coefficient update instruction to the digital predistortion processing module; the dual-mode communication SoC chip outputs the matching level switching instruction to the low-voltage RF switch of the low-voltage side dual-level matching network through the general input / output interface; after the low-voltage RF switch stabilizes, the dual-mode communication SoC chip enables the switched digital predistortion coefficient and resumes frame transmission.

7. The HPLC dual-mode communication module based on channel quality prediction according to claim 6, characterized in that, During the switching process of digital predistortion coefficients, the digital predistortion processing module uses a linear gradual interpolation method to achieve a smooth transition of the digital predistortion coefficients: ； In the formula: The digital predistortion coefficients actually used at the nth sampling point during the gradual transition process; The digital predistortion coefficients before the switch; The digital predistortion coefficients after switching; These are linear weighting coefficients; This is the preset number of sampling points for the gradual transition.

8. The HPLC dual-mode communication module based on channel quality prediction according to claim 1, characterized in that, The dual-port cache random access memory is connected to the data bus of the dual-mode communication SoC chip via a direct memory access controller.

9. A channel switching method based on channel quality prediction, applied to an HPLC dual-mode communication module based on channel quality prediction as described in any one of claims 1 to 8, characterized in that, Includes the following steps: S1. The physical layer channel quality parameters are periodically collected through the physical layer channel quality parameter reading interface of the dual-mode communication SoC chip, and the physical layer channel quality parameters are stored in the sliding window buffer to obtain the historical physical layer channel quality parameter sequence. S2. Using a trend prediction algorithm, the short-term mean and trend of channel quality are calculated based on the historical physical layer channel quality parameter sequence to obtain the channel quality prediction result. S3. Based on the channel quality prediction result, the matching level of the low-voltage side dual-level matching network is switched by the low-voltage radio frequency switch, and the digital predistortion coefficient corresponding to the current matching level is read synchronously to update the digital predistortion coefficient used by the digital predistortion processing module. S4. Determine whether dual-mode channel switching is required based on the channel quality prediction result. If dual-mode channel switching is required, buffer the data to be transmitted in the current channel and enable the backup channel, and perform dual-mode channel switching. S5. After performing dual-mode channel switching, periodically detect the received signal strength indicator of the current channel. When the received signal strength indicator of the current channel returns to normal and remains stable for a period of time, switch back to the current channel and return to step S1.

10. The channel switching method based on channel quality prediction according to claim 9, characterized in that, In step S2, the changing trend includes the changing trend of signal-to-noise ratio and the changing trend of packet error rate; Step S4 specifically includes: when the channel quality prediction result meets the handover preparation conditions, entering the handover preparation state, copying the data to be transmitted in the current channel to the dual-port buffer random access memory, and pre-activating the backup channel; wherein, the handover preparation conditions are that the signal-to-noise ratio decreases by more than the decrease rate threshold, or the packet error rate increases by more than the increase rate threshold; when the channel quality prediction result meets the handover conditions, performing dual-mode channel handover, closing the current channel, and enabling the backup channel; wherein, the handover conditions are that the signal-to-noise ratio is lower than the signal-to-noise ratio threshold, or the packet error rate is higher than the packet error rate threshold, or the acknowledgment frame times out continuously.

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