FPGA-based reconfigurable intelligent surface real-time beamforming control system and method

Abstract

The application provides a reconfigurable intelligent surface real-time beamforming control system and method based on FPGA, which comprises a parameter configuration module, a phase initialization module, an active set screening module, a candidate phase optimization module, a phase storage module and an output control module. The parameter configuration module is used for obtaining array parameters, propagation direction parameters and channel parameters of the reconfigurable intelligent surface; the phase initialization module generates initial phases of each array element according to the array element position and the propagation direction and maps the initial phases into discrete phase states; the active set screening module selects key array elements according to the cascade channel contribution degree of each array element; the candidate phase optimization module only searches discrete candidate phases of the key array elements and updates equivalent channels and interference items in an incremental manner; the phase storage module saves the current phase state of each array element; and the output control module converts the final phase state into array element bias control information, and outputs the control information to the reconfigurable intelligent surface array through data analysis, phase-voltage mapping, caching, handshake control, multi-channel serial driving and digital-to-analog converter addressing. The application combines phase solving and array element driving link into a fixed-point, localized and determined time delay process suitable for FPGA implementation, can reduce the hardware overhead caused by full-array discrete search and division comparison, and makes the system total delay determined by parameters such as the number of array elements, the size of the active set, the number of candidate phases and the number of iterations, so that the application is suitable for real-time beamforming control.

Description

Technical Field

[0001] This invention relates to the field of wireless communication and hardware acceleration technology, specifically to a reconfigurable smart surface real-time beamforming control system and method based on FPGA. Background Technology

[0002] A reconfigurable smart surface is a novel wireless propagation environment control device composed of a large number of controllable electromagnetic elements. By adjusting the reflection phase of each array element, the reconfigurable smart surface can change the propagation direction and superposition mode of incident electromagnetic waves, thereby achieving functions such as coverage enhancement, beamforming, and interference suppression.

[0003] In beamforming control of reconfigurable smart surfaces, the phase configuration of each array element needs to be determined based on the communication scenario, incident direction, target reflection direction, and channel state. Existing research often employs methods such as continuous phase optimization, alternating optimization, positive semidefinite relaxation, and heuristic search to solve for the phase. However, these methods typically rely on floating-point computation, matrix operations, division operations, or numerous iterations, making them suitable for offline simulation but difficult to deploy directly on hardware platforms such as field-programmable gate arrays (FPGAs).

[0004] On the other hand, practically reconfigurable smart surface array elements typically only provide a finite number of discrete phase states. For example, 3-bit phase control corresponds to only 8 phase states. If optimization is still performed based on continuous phases, and the results are then quantized into discrete states, it will not only cause inconsistencies between the algorithm model and the hardware control method, but may also introduce quantization losses. If a discrete candidate search is directly performed on all array elements, the search scale increases rapidly with the number of array elements, making it difficult to meet real-time control requirements.

[0005] Furthermore, evaluation metrics such as signal-to-interference-plus-noise ratio (SINR) are typically in fractional form. Implementing a high-bit-width divider directly in an FPGA would result in significant resource consumption and long computational latency, hindering timing convergence. For near-field testing or short-range reflection scenarios, traditional far-field linear phase models may differ from actual spherical wave propagation, requiring a phase initialization method that considers both far-field and near-field conditions.

[0006] Meanwhile, a practical reconfigurable smart surface system not only needs to solve for the phase, but also needs to convert the phase state into array element bias voltages, digital-to-analog converter control codes, and specific chip select and channel addressing timings. If the phase optimization results are implemented separately from the underlying drive link, it can easily lead to inconsistent data formats, unpredictable control delays, and incorrect array element address mappings.

[0007] Therefore, there is an urgent need for a reconfigurable intelligent surface phase control scheme for FPGA hardware implementation, which can complete phase initialization, key array element selection, discrete candidate phase optimization, phase-voltage conversion, and multi-channel array element driving output with a certain time delay under limited hardware resources. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a reconfigurable intelligent surface real-time beamforming control system and method based on FPGA.

[0009] This invention proposes a reconfigurable intelligent surface real-time beamforming control system based on FPGA, comprising:

[0010] The system comprises a parameter configuration module, a phase initialization module, a phase storage module, an active set selection module, a candidate phase optimization module, and an output control module. The parameter configuration module acquires the array size, operating frequency, incident direction, reflection direction, element spacing, and channel parameters of the reconfigurable smart surface. The phase initialization module generates the initial phase state of each element based on the incident direction, reflection direction, and element position. The phase storage module stores the current discrete phase state of each element. The active set selection module selects several key elements from all elements to form an active set based on the channel contribution of each element. The candidate phase optimization module performs discrete candidate phase search on the key elements in the active set and updates the phase state of the corresponding elements based on the evaluation results. The output control module converts the final phase state into element bias control information and outputs it to the drive control link of the reconfigurable smart surface via BRAM buffering, multiple SPI timing, and digital-to-analog converter addressing.

[0011] Preferably, the phase initialization module generates the far-field geometric phase based on the array element coordinates and the incident and reflection directions. For array elements in a two-dimensional array... Its far-field geometric phase can be expressed as:

[0012]

[0013] in, and These represent the sinusoidal gradients of the propagation direction in the two array directions, respectively.

[0014] Preferably, the phase initialization module uses a fixed-point recursive structure to generate the phase. Within the same row, the phase is accumulated step-by-step by the column direction increment; during row switching, the starting phase of the next row is updated by the row direction increment. This method avoids repeatedly performing multiplication operations on each array element.

[0015] Preferably, the phase initialization module also supports near-field phase correction. When the transmitter or receiver is located in the near-field region of the reconfigurable smart surface, the phase initialization module can generate a spherical wave phase based on the distance from the transmitter to the array element and the distance from the array element to the receiver, or receive near-field correction data pre-calculated by the processor.

[0016] Preferably, the active set filtering module employs a streaming filtering method. This module maintains an ordered register queue, and as the element contributions are input one by one, it retains a number of elements with higher contributions in real time through parallel comparison and insertion / shift operations. Compared to full sorting, this method reduces the comparison scale and wiring complexity.

[0017] Preferably, the candidate phase optimization module only searches for candidate phases for key array elements in the active pool. For the current key array element, instead of recalculating the equivalent channel contribution of all array elements, it incrementally updates the phase based on the change between the candidate phase and the original phase. This approach reduces redundant calculations.

[0018] Preferably, during the candidate phase evaluation process, the candidate phase optimization module converts the fractional form of signal-to-interference-plus-noise ratio comparison into a cross-multiplication comparison, thereby avoiding the implementation of a divider in the FPGA.

[0019] Preferably, the output control module is implemented collaboratively by a processing system and a programmable logic unit. The processing system receives multiple array element phase values ​​or voltage values, performs discrete quantization and phase-voltage mapping on the phase values, converts the bias voltage into digital-to-analog converter control codes, and writes them into a shared buffer. After a handshake signal is triggered, the programmable logic unit reads multiple control codes from the buffer, divides them into several groups, and sends them to a multi-channel digital-to-analog converter or a compatible voltage output device through several serial control channels. The multi-channel digital-to-analog converter or the compatible voltage output device then outputs multiple array element bias voltages.

[0020] This invention also proposes a real-time beamforming control method for reconfigurable smart surfaces based on FPGA, the method comprising the following steps:

[0021] Step S1: Obtain the array parameters, propagation direction parameters, and channel parameters of the reconfigurable smart surface;

[0022] Step S2: Generate the initial phase state of each array element based on the element position and propagation direction;

[0023] Step S3: Store the initial phase state to the phase storage module;

[0024] Step S4: Based on the channel contribution of each array element, select several key array elements from all array elements to form an active set;

[0025] Step S5: Perform discrete candidate phase search on the key array elements in the active set in sequence;

[0026] Step S6: Update the equivalent channel corresponding to the candidate phase in an incremental manner based on the phase change caused by the candidate phase;

[0027] Step S7: Determine the preferred phase based on the evaluation results corresponding to the candidate phases, and write the preferred phase back to the phase storage module;

[0028] Step S8: After completing the preset iteration conditions, output the final phase state of each array element, parse the final phase state into multiple array element phase values, quantize the array element phase values ​​and map them into array element bias voltages, convert the array element bias voltages into digital-to-analog converter control codes, pass them to the programmable logic terminal for reading through buffer and handshake signals, and send them to the multi-channel digital-to-analog converter through a multi-channel serial interface to drive the reconfigurable smart surface array.

[0029] The beneficial effects of this invention are: This invention provides an initial state for discrete phase optimization through geometric phase initialization, reducing the computational burden of random search or continuous optimization. Active set filtering performs local optimization only on key array elements, avoiding a full candidate search for all array elements. Incremental updating of the equivalent channel corresponding to candidate phases avoids repeated full array calculations. Cross-multiplication enables signal-to-interference-plus-noise ratio comparison, avoiding hardware dividers and reducing resource consumption. Phase-voltage mapping, caching, handshake triggering, and multi-path parallel driving directly convert phase optimization results into reconfigurable smart surface element bias voltages, reducing format conversion and timing uncertainties between upper-layer phase algorithms and lower-layer driving links. All of these designs are suitable for implementation using fixed-point arithmetic and finite state machines, enabling phase solving and element driving processes for reconfigurable smart surfaces to have deterministic latency and good hardware implementability. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the relevant drawings of the embodiments of the present invention are described below. It should be understood that the drawings described below are only used to explain some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the overall structure of the FPGA-based reconfigurable intelligent surface real-time beamforming control system in this embodiment of the invention.

[0033] Figure 2 This is a schematic diagram of the phase initialization module in an embodiment of the present invention;

[0034] Figure 3This is a schematic diagram of the active set filtering module in an embodiment of the present invention;

[0035] Figure 4 This is a flowchart illustrating the candidate phase optimization module in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the phase-voltage mapping and multi-channel SPI output control link in an embodiment of the present invention; Figure 6 This is a schematic diagram of the mapping between the RIS array PCB element number and the AD5767 channel in an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention.

[0039] This invention provides a real-time beamforming control system for reconfigurable smart surfaces based on FPGA. This system can be applied to reconfigurable smart surface arrays of different sizes; in one embodiment, the array size is 16×16, with a total of 256 elements. Each element employs discrete phase control, and in one embodiment, 3-bit phase control is used, meaning each element has 8 phase states.

[0040] like Figure 1 As shown, the system includes a parameter configuration module, a phase initialization module, a phase storage module, an active set filtering module, a candidate phase optimization module, and an output control module. The parameter configuration module can be configured by an on-chip processing system, an external processor, or a host computer via a bus interface; in one embodiment, it can be implemented by the Zynq processing system. The phase initialization module, phase storage module, active set filtering module, and candidate phase optimization module can be deployed on the FPGA programmable logic side; the output control module can be implemented collaboratively by the data parsing and mapping logic on the processing system side and the cache reading and serial drive logic on the programmable logic side.

[0041] The real-time beamforming control method of this invention can be executed according to the following steps:

[0042] Step S1: Obtain the array parameters, propagation direction parameters, and channel parameters of the reconfigurable smart surface;

[0043] Step S2: Generate the initial phase state of each array element based on the element position and propagation direction;

[0044] Step S3: Store the initial phase state to the phase storage module;

[0045] Step S4: Based on the channel contribution of each array element, select several key array elements from all array elements to form an active set;

[0046] Step S5: Perform discrete candidate phase search on the key array elements in the active set in sequence;

[0047] Step S6: Update the equivalent channel corresponding to the candidate phase in an incremental manner based on the phase change caused by the candidate phase;

[0048] Step S7: Determine the preferred phase based on the evaluation results corresponding to the candidate phases, and write the preferred phase back to the phase storage module;

[0049] Step S8: After completing the preset iteration conditions, output the final phase state of each array element, parse the final phase state into multiple array element phase values, quantize the array element phase values ​​and map them into array element bias voltages, convert the array element bias voltages into digital-to-analog converter control codes, pass them to the programmable logic terminal for reading through buffer and handshake signals, and send them to the multi-channel digital-to-analog converter through a multi-channel serial interface to drive the reconfigurable smart surface array.

[0050] In this embodiment of the invention, the phase initialization module is used to generate an initial phase based on scene parameters. For far-field scenes, the incident and reflected waves can be approximated as plane waves, and the phase is mainly determined by the array element coordinates and propagation direction. Assuming the array element spacing is half a wavelength, then the array elements... The corresponding phase can be represented by a sinusoidal gradient. In hardware implementation, the sinusoidal gradient can be pre-quantized into a fixed-point number, and the phase of each array element can be generated step-by-step through a row-column recursive structure. This structure mainly consists of a counter, an adder, and a shift quantization unit, and is suitable for FPGA implementation.

[0051] In near-field scenarios, the distances from the transmitter and receiver to each array element vary non-linearly with the element position. To improve near-field control accuracy, this embodiment of the invention introduces near-field phase correction. Specifically, the spherical wave path length can be calculated based on the transmitter coordinates, receiver coordinates, and array element coordinates, and the phase can be obtained from the path length. This near-field phase can be pre-calculated by the processor or host computer and then written into the FPGA, or it can be calculated internally by the FPGA when hardware resources permit. In this way, the system can support both far-field plane wave phase initialization and near-field spherical wave phase initialization.

[0052] In this embodiment of the invention, the phase storage module is used to store the current discrete phase state of each array element. The phase storage module can be implemented using a register array, distributed RAM, or block RAM. In one embodiment, for a 16×16 array, each of the 256 array elements occupies 3 bits, and the phase storage capacity is 768 bits. During the phase initialization phase, the initial phase is written to the phase storage module; during the candidate phase optimization phase, the current array element phase is read and the preferred phase is written back; during the output phase, the phase states of all array elements are read and sent to the drive link.

[0053] In this embodiment of the invention, the active set selection module is used to select key array elements that have a significant impact on the beamforming results. The element contribution can be characterized by the cascaded channel gain, the sum of the absolute values ​​of the channel gains, or the sensitivity of the objective function. The active set selection module adopts a streaming input method, receiving one element contribution and its index each clock cycle. Internally, the module maintains an ordered register queue of length K, which stores the K array elements with the highest current contributions. For a newly input contribution, the module compares it in parallel with the contributions in the queue to determine the insertion position, and completes the insertion or removal through shift updates. After all array elements have been input, the array elements stored in the queue constitute the active set.

[0054] In this embodiment of the invention, the candidate phase optimization module refines the phase of key array elements in the active pool. For each key array element, the candidate phase optimization module sequentially enumerates all discrete phase states of that element and calculates the evaluation result corresponding to each candidate phase. Since only the phase of one array element is changed each time, the equivalent channel corresponding to the candidate phase can be obtained by adding the increment caused by the phase change of that array element to the current equivalent channel, without having to re-accumulate the contributions of all array elements.

[0055] In one embodiment, the current key array element is The current phase is Candidate phase is The cascaded channel constant corresponding to this array element is Then the equivalent channel under the candidate phase satisfies:

[0056]

[0057] With this incremental expression, the candidate phase evaluation process only needs to process the relevant terms of the current key array element, reducing the amount of computation.

[0058] In scenarios with interference sources, the interference equivalent term can also be updated using a similar incremental approach. The candidate phase optimization module calculates the candidate phase evaluation results based on the updated target equivalent channel and interference equivalent term. The evaluation results can be signal-to-noise ratio, signal-to-interference-plus-noise ratio, or other indicators related to beamforming performance.

[0059] In this embodiment of the invention, if the evaluation metric is the signal-to-interference-plus-noise ratio (SIR), its form is typically the numerator divided by the denominator. To avoid implementing a divider in the FPGA, this invention converts the SIR comparison between two candidate phases into a cross-multiplication comparison. Let the numerator and denominator corresponding to the current candidate phase be... , The numerators and denominators corresponding to the candidate phases have been recorded as follows: , ,when

[0060]

[0061] When the current candidate phase is determined to be superior, this method preserves the equivalence of fractional comparisons and is more suitable for fixed-point hardware implementation.

[0062] In this embodiment of the invention, the system is controlled by a finite state machine. The finite state machine sequentially completes the following states: idle waiting, parameter initialization, phase initialization, active set screening, key array element selection, candidate phase enumeration, candidate phase evaluation, preferred phase write-back, iterative judgment, and completion output. To describe the system delay, let... This indicates the number of elements in the reconfigurable smart surface. Indicates the size of the active set. This represents the number of candidate phases that can be enumerated for each array element. This indicates the number of optimization iterations. All periods below are measured in system clock cycles.

[0063] The active set screening period is denoted as Each clock cycle inputs the contribution of one array element, with a length of [missing information]. When performing parallel comparisons on an ordered register queue,

[0064]

[0065] in ( The overhead includes fixed costs for insertion shifting, pipeline startup, and pipeline termination; if serial comparison is used, then... It can be represented as The magnitude is a deterministic function. Therefore, the active set selection period is determined by... , And the number of fixed flow stages is determined.

[0066] The candidate phase search period is denoted as .right Each active array element is enumerated separately. When there are n candidate phases, the candidate phase search period for a single iteration can be expressed as:

[0067]

[0068] in The time required to evaluate a single candidate phase. The startup and termination overhead of the pipeline is evaluated for candidate phases. In the implementation of the pipeline achieving one candidate throughput per cycle,

[0069]

[0070] therefore

[0071]

[0072] The preferred phase write-back period is denoted as Each key element completes... After comparing each candidate phase, the preferred phase is written back once. Therefore, the write-back period for a single iteration can be expressed as:

[0073]

[0074] in The period required to write back the phase of a single array element. This is to account for write-back control overhead. When the phase storage module supports single-cycle write-back,

[0075]

[0076] therefore

[0077]

[0078] The BRAM write and SPI output cycle is denoted as... .set up This represents the number of parallel SPI channels. Control word width for a single digital-to-analog converter. Given the division factor of the SPI serial clock relative to the system clock, the processing system sequentially writes... The period of a control code can be expressed as

[0079]

[0080] The SPI output period of the programmable logic terminal can be expressed as:

[0081]

[0082] therefore

[0083]

[0084] for , , Fixed hardware implementation, BRAM write and SPI output cycles are A definite function.

[0085] In summary, when the active set is re-selected in each iteration, the total system delay can be expressed as:

[0086]

[0087] The active set is filtered only once and then... If the time remains constant throughout the iterations, the total system delay can be expressed as:

[0088]

[0089] in For parameter initialization and phase initialization period, This includes fixed control overhead such as state transitions and handshake waiting. Therefore, the total system delay can be calculated from... , , , With fixed hardware pipeline parameters and a defined time delay, it is suitable for real-time FPGA control.

[0090] In this embodiment of the invention, the output control module is used to output the final phase state to the reconfigurable smart surface driving link. In one embodiment, the processing system receives a phase sequence containing 256 array elements via a serial port, parses it, performs 3-bit quantization on the phase of each array element, and maps the quantized phase state to the corresponding control voltage. The phase quantization can use the midpoint of adjacent discrete phases as the decision boundary, that is, 0° to 22.5° and 337.5° to 360° are mapped to 0°, 22.5° to 67.5° are mapped to 45°, 67.5° to 112.5° are mapped to 90°, 112.5° to 157.5° are mapped to 135°, 157.5° to 202.5° are mapped to 180°, 202.5° to 247.5° are mapped to 225°, 247.5° to 292.5° are mapped to 270°, and 292.5° to 337.5° are mapped to 315°.

[0091] In one specific hardware embodiment, the reconfigurable smart surface is implemented using a 16×16 RIS array PCB, which includes 256 controllable reflective elements and their corresponding bias voltage output networks; the drive link uses 16 AD5767 multi-channel voltage output digital-to-analog converters, each AD5767 providing 16 voltage output channels, and the 16 AD5767s correspond to form 256 element bias outputs from DAC_OUT_0 to DAC_OUT_255.

[0092] In this embodiment, the AD5767 is a 12-bit, 16-channel voltage output DAC. Its serial interface includes a 24-bit shift register, and the control word may include a command field, a channel address field, a voltage data field, and a reserved field. In this embodiment, the AD5767 is configured with an output range of 0V to -20V to cover the negative bias voltage required by the RIS array element. The above chip model, output range, and number of channels are used to illustrate the specific implementation of the fabricated hardware prototype and do not limit the use of other multi-channel voltage output devices with the same function in this invention.

[0093] like Figure 6 As shown, in the hardware embodiment, the 16×16 RIS array PCB can be numbered and mapped into 4×4 array elements, with each 4×4 array element corresponding to 16 output channels of an AD5767; SPI channel A corresponds to DAC_OUT_0 to DAC_OUT_63, SPI channel B corresponds to DAC_OUT_64 to DAC_OUT_127, SPI channel C corresponds to DAC_OUT_128 to DAC_OUT_191, and SPI channel D corresponds to DAC_OUT_192 to DAC_OUT_255. Therefore, the 256 control codes written by the processing system can be mapped to the corresponding RIS array element bias terminals according to the DAC_OUT number.

[0094] In one embodiment, based on the calibration results of the fabricated RIS array PCB and AD5767 driver link, the eight discrete phase states 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° correspond to array element bias voltages of 0V, -6.80V, -8.48V, -9.29V, -9.61V, -9.98V, -11.38V, and -18.78V, respectively. The processing system converts the bias voltages into 12-bit digital-to-analog converter control codes; where 0V can correspond to a preset full-scale code, and other bias voltages can be converted into digital-to-analog converter control codes according to the output range of 0V to -20V and calibration coefficients. The above specific voltage values ​​are one embodiment of the hardware prototype. In practical applications, the phase-voltage mapping table can be adjusted according to the RIS unit structure, operating frequency, and calibration data.

[0095] In one embodiment, the processing system sequentially writes 256 digital-to-analog converter (DAC) control codes into a shared BRAM and notifies the programmable logic (PLC) to read them via a GPIO handshake signal. Upon detecting the handshake trigger, the PLC's BRAM read unit divides the control codes in the BRAM into four groups (A, B, C, and D) according to four read methods, with each group containing 64 control codes. The four groups of data are then sent to four SPI control channels, each including four chip select pins. In the hardware embodiment, each chip select pin corresponds to one AD5767 or a compatible 16-channel multi-channel DAC, thereby forming 16 DACs providing bias voltage outputs to 256 RIS array elements.

[0096] In one embodiment, the programmable logic SPI control channel is controlled by a finite state machine, sequentially executing reset, configuration, initial voltage setting, and element voltage setting. For the AD5767 embodiment, the SPI control channel transmits a 24-bit control word, which includes a command field, a channel address field, a 12-bit voltage data field, and a reserved field. For element voltage setting, the SPI control channel sequentially transmits the control code for the corresponding element based on the current chip select pin and channel count value, and outputs a processing completion handshake signal after the current group is sent.

[0097] In one specific embodiment, the phase optimization system is implemented on a Xilinx Zynq-7020 device, with an array size of 16×16 (256 elements), 4 base station antennas, 2 interference sources, 8 candidate phases, and an active set size of 10. In simulation, the system's delay from startup to output completion is 4703 clock cycles. Synthetic results show that, under a 50 MHz clock constraint, the design meets timing constraints, with resource usage including approximately 1079 Slice LUTs, 959 registers, 65 DSP48E1s, and 0 BRAMs, and an estimated on-chip power consumption of approximately 0.112 W. Furthermore, the RIS element drive control link can be implemented on the same Zynq on-chip system. The processing system handles phase or voltage data reception, parsing, mapping, and BRAM writing, while the programmable logic handles BRAM group reading, four-channel SPI parallel timing, 16-chip digital-to-analog converter chip select addressing, and 256-channel element bias output. The above results demonstrate that the system described in this invention has low resource consumption, a complete control link, and real-time implementation capabilities.

[0098] In summary, this invention transforms the phase solution for reconfigurable smart surface beamforming into a hardware process suitable for FPGA implementation through phase initialization, active set screening, discrete candidate phase search, incremental evaluation, and division-free comparison. Furthermore, by employing phase-voltage mapping, caching, handshaking between the processing system and programmable logic, multi-channel serial driving, and digital-to-analog converter addressing, the phase optimization results are directly implemented as multi-channel element bias control for the reconfigurable smart surface. In a 16×16 array embodiment, this invention can achieve 256-channel element bias control, enabling real-time phase solution and real-time element driving with limited resources.

[0099] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to the embodiments of the present invention without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A reconfigurable intelligent surface real-time beamforming control system based on FPGA, characterized in that, include: The system comprises a parameter configuration module, a phase initialization module, a phase storage module, an active set selection module, a candidate phase optimization module, and an output control module. The parameter configuration module acquires the array size, operating frequency, incident direction, reflection direction, element spacing, and channel parameters of the reconfigurable smart surface. The phase initialization module generates the initial phase state of each element based on the incident direction, reflection direction, and the position of each element in the reconfigurable smart surface. The phase storage module stores the current discrete phase state of each element. The active set selection module selects several key elements from all elements to form an active set based on the channel contribution of each element. The candidate phase optimization module performs discrete candidate phase search on the key elements in the active set and updates the phase state in the phase storage module based on the evaluation results of the candidate phases. The output control module outputs the final phase state from the phase storage module to the drive control link of the reconfigurable smart surface.

2. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 1, characterized in that, The phase initialization module includes a geometric phase generation unit and a discrete phase quantization unit; The geometric phase generation unit generates an initial geometric phase based on the two-dimensional coordinates of the array element, the incident direction, and the reflection direction. The discrete phase quantization unit maps the initial geometric phase into a finite number of discrete phase states.

3. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 2, characterized in that, The initial geometric phase includes a far-field phase, which satisfies: in, and These are the column and row coordinates of the array element in the two-dimensional array, respectively. This is the sum of the sinusoidal gradients of the incident and reflected directions along the column direction. It is the sum of the sinusoidal gradients of the incident and reflected directions in the row direction; The geometric phase generation unit also generates the initial geometric phase using a fixed-point recursive method. Within the same row, update the phase of the current array element step by step using the column direction increment; During row switching, the starting phase of the next row is updated by the row direction step amount; The fixed-point recursion method is implemented by addition, shifting, and counting control.

4. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 2, characterized in that, The phase initialization module also includes a near-field phase correction unit; The near-field phase correction unit generates a near-field spherical wave phase based on the distance from the transmitter to the array element and the distance from the array element to the receiver, or receives a near-field spherical wave phase correction amount pre-calculated by the processor. The phase initialization module generates a near-field initial phase state based on the near-field spherical wave phase or the near-field spherical wave phase correction amount. The phase of the near-field spherical wave satisfies: in, For operating frequency, At the speed of light, For transmitter to array element distance, For array element Distance to the receiver This is for phase offset.

5. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 1, characterized in that, The active set filtering module includes an ordered register queue, a parallel comparison unit, an insertion position determination unit, and a shift update unit; The ordered register queue is used to store the contribution scores and indexes of the currently selected array elements; The parallel comparison unit is used to compare the contribution of the input array element with the contribution in the ordered register queue in parallel. The insertion position determination unit is used to determine the insertion position of the input array element in the ordered register queue based on the comparison result. The shift update unit is used to insert, maintain, or evict the ordered register queue according to the insertion position; The contribution of the array element is at least one of the following: the cascaded channel gain corresponding to the array element, the absolute value of the channel gain, or the sensitivity of the objective function.

6. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 1, characterized in that, The candidate phase optimization module includes a candidate phase enumeration unit, an incremental update unit, and a preferred phase determination unit. The candidate phase enumeration unit is used to enumerate multiple discrete candidate phases for the current key array elements in the active set. The incremental update unit is used to update the equivalent channel corresponding to the candidate phase according to the phase change between the current phase and the candidate phase; The preferred phase determination unit is used to compare the evaluation results corresponding to different candidate phases and determine the preferred phase of the current key array element. The incremental update unit updates the equivalent channel in the following manner: in, The equivalent channel corresponding to the candidate phase. For the current benchmark equivalent channel, This refers to the cascaded channel constants corresponding to the current key array elements. As a candidate phase, This refers to the phase before the current key array element is updated; When comparing the signal-to-interference-plus-noise ratios corresponding to candidate phases, the preferred phase determination unit does not perform division operations, but instead converts the fractional comparison into a cross-multiplication comparison. When the following conditions are met: When the current candidate phase is determined to be superior to the previously recorded candidate phase, it is considered superior. in, and These are the numerator and denominator of the signal-to-interference-plus-noise ratio (SIR) corresponding to the current candidate phase, respectively. and These are the numerator and denominator of the signal-to-interference-plus-noise ratio (SIR) corresponding to the recorded candidate phases, respectively.

7. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 1, characterized in that, The output control module includes a data receiving and parsing unit, a phase-voltage mapping unit, a digital code conversion unit, a buffer writing unit, a handshake triggering unit, a buffer reading unit, a multi-channel serial timing unit, and a digital-to-analog converter addressing unit. The data receiving and parsing unit receives multiple array element phase values ​​or multiple array element voltage values. The phase-voltage mapping unit converts the array element phase values ​​into corresponding bias voltages. The digital code conversion unit converts the bias voltages into digital-to-analog converter control codes. The buffer writing unit writes the control codes into a buffer. The handshake triggering unit issues a read-out trigger signal after writing is complete. The buffer reading unit reads the control codes according to the read-out trigger signal. The multi-channel serial timing unit sends the read control codes to the multi-channel digital-to-analog converter. The digital-to-analog converter addressing unit generates chip select signals and channel address signals.

8. The FPGA-based reconfigurable intelligent surface real-time beamforming control system according to claim 7, characterized in that, The phase-voltage mapping unit quantizes the input phase into one of multiple discrete phases according to a finite-bit discrete phase state, and maps the discrete phase to the corresponding array element bias voltage according to a preset phase-bias voltage mapping table or calibration lookup table; in one embodiment, the finite-bit discrete phase state is a 3-bit phase state, and the multiple discrete phases include 0°, 45°, 90°, 135°, 180°, 225°, 270° and 315°; Furthermore, the cache reading unit divides the multiple array element control codes into several groups and sends them into several serial control channels respectively; each serial control channel includes at least one chip select terminal, each chip select terminal corresponds to a multi-channel digital-to-analog converter, and each multi-channel digital-to-analog converter includes multiple output channels, thereby forming bias control for multiple reconfigurable smart surface array elements. In one embodiment, the plurality of array element control codes are 256 array element control codes, and the plurality of groups are four groups A, B, C, and D, each group including 64 control codes; each serial control channel includes four chip select terminals and is used to control four 16-channel multi-channel digital-to-analog converters, thereby forming 16 multi-channel digital-to-analog converters to bias control 256 reconfigurable smart surface array elements; The control word sent by the multi-channel serial timing unit includes a command field, a channel address field, a voltage data field, and a reserved field; In one implementation, the control word is a 24-bit control word, and the voltage data field is a 12-bit digital-to-analog converter control code.

9. A real-time beamforming control method for reconfigurable smart surfaces based on FPGA, characterized in that, Includes the following steps: Step S1: Obtain the array parameters, propagation direction parameters, and channel parameters of the reconfigurable smart surface; Step S2: Generate the initial phase state of each array element based on the element position and propagation direction; Step S3: Store the initial phase state to the phase storage module; Step S4: Based on the channel contribution of each array element, select several key array elements from all array elements to form an active set; Step S5: Perform discrete candidate phase search on the key array elements in the active set in sequence; Step S6: Update the equivalent channel corresponding to the candidate phase in an incremental manner based on the phase change caused by the candidate phase; Step S7: Determine the preferred phase based on the evaluation results corresponding to the candidate phases, and write the preferred phase back to the phase storage module; Step S8: After completing the preset iteration conditions, output the final phase state of each array element, parse the final phase state into multiple array element phase values, quantize the array element phase values ​​and map them into array element bias voltages, convert the array element bias voltages into digital-to-analog converter control codes, pass them to the programmable logic terminal for reading through buffer and handshake signals, and send them to the multi-channel digital-to-analog converter through a multi-channel serial interface to drive the reconfigurable smart surface.

10. The FPGA-based reconfigurable smart surface real-time beamforming control method according to claim 9, characterized in that, The discrete candidate phase search in step S5 is performed under a preset finite-bit discrete phase constraint, and the phase state of each array element belongs to a state in the preset discrete phase set; in one embodiment, the finite-bit discrete phase constraint is a 3-bit phase constraint, and the preset discrete phase set includes 8 discrete phase states.

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