Satellite signal reception chip system

Abstract

The embodiment of the present disclosure discloses a satellite signal receiving chip system, the system comprises: a radio frequency front end module, an analog-to-digital conversion module, a digital down conversion module, a baseband processing module and an on-chip control unit; the radio frequency front end module is used for receiving satellite radio frequency signals and performing front-end processing on the satellite radio frequency signals, and outputting analog intermediate frequency signals; the analog-to-digital conversion module performs analog-to-digital conversion on the analog intermediate frequency signals and outputs digital intermediate frequency signals; the digital down conversion module is used for performing digital down conversion and decimation filter processing on the digital intermediate frequency signals and outputs symbol-level complex baseband data sequences; the baseband processing module performs baseband processing on the symbol-level complex baseband data sequences, outputs demodulated and decoded service data and baseband processing state information; the on-chip control unit identifies the current channel scene according to the baseband processing state information output by the baseband processing module, and determines a parameter adjustment strategy based on the current channel scene; the parameter adjustment strategy is used for adjusting and storing underlying processing parameters.

Description

Technical Field

[0001] This disclosure relates to the fields of satellite communication and integrated circuit design technology, specifically to a satellite signal receiving chip system. Background Technology

[0002] The Fengyun-4 (FY-4) series of satellites is a new generation of geostationary meteorological satellite system. Its EWAIB channel is used to broadcast meteorological monitoring information, major disaster early warning information, and scalable navigation enhancement information to ground terminals. Because this type of service is designed for wide-area broadcasting, its receiving terminals often need to be deployed in mountainous areas, islands, remote agricultural areas, unattended monitoring points, and mobile platforms. Therefore, extremely high requirements are placed on the power consumption, size, cost, reliability, and long-term operational capability of the receiving system. In existing technologies, ground terminals for EWAIB (Emergency Weather Alarm Information Broadcast) or similar satellite broadcast signals mostly adopt a discrete device implementation, with a typical structure of "RF unit + FPGA baseband processing board + embedded host". This solution can complete signal reception and protocol processing, but it has the following problems: First, the cascading of multiple boards results in a large system size, many peripheral components, and complex wiring, making it difficult to embed in miniaturized terminals; second, the FPGA and general-purpose processor operate at high frequencies for extended periods, with overall power consumption generally in the watt range or even higher, making it unsuitable for long-term unattended applications powered by solar energy or batteries; third, the multi-chip and multi-board structure increases BOM costs, assembly costs, testing costs, and maintenance costs, which is not conducive to the large-scale deployment of terminals.

[0003] On the other hand, while redesigning a dedicated ASIC chip to adapt to the Fengyun-4 EWAIB signal system could theoretically achieve higher integration, it would also introduce new problems. First, the EWAIB signal has its own characteristics in terms of operating frequency, spreading code, synchronization sequence, frame structure, and channel coding, making it impossible to directly apply existing dedicated chips designed for other narrowband satellite services. Second, redesigning a chip for this signal system requires a complete process including architecture design, front-end and back-end implementation, verification, tape-out, packaging, and testing, resulting in a long development cycle, high non-repetitive engineering costs, and the technical and economic risks of re-tape-out if design deviations occur. Third, once the dedicated chip is finalized, its adaptability to algorithms and processes in different application scenarios is weak, hindering rapid product iteration and multi-scenario promotion.

[0004] Furthermore, while implementations based on general-purpose servers, industrial control computers, or board-based software radio platforms can switch between different algorithms through software upgrades, the signal processing in these solutions typically runs on an operating system or high-level application environment. Their processing chain relies heavily on external memory bandwidth, bus transmission, and multi-level software scheduling. This implementation approach is essentially geared towards "system-level function implementation" rather than "on-chip physical layer real-time closed-loop processing." In weak satellite signal reception scenarios, carrier synchronization, code synchronization, correlation detection, equalization, and decoding require extremely high precision in timing, processing latency, and resource response speed. Server or board-based solutions struggle to achieve tightly coupled adjustments to front-end filtering, baseband integration length, equalizer parameters, and decoding complexity within milliseconds or even shorter timescales. Therefore, the problem with these solutions is not merely their large size and high power consumption; more importantly, their implementation path cannot achieve on-chip real-time reconfiguration capabilities for the physical layer signal processing flow.

[0005] Furthermore, most existing receiving systems employ a fixed processing pipeline. Regardless of whether the channel quality is excellent or deteriorated, the system often uses the same filtering bandwidth, synchronization window, equalization strength, and decoding complexity. Under favorable channel conditions, this fixed process generates unnecessary energy consumption; in scenarios with low signal-to-noise ratio, frequency offset fluctuations, multipath interference, or sudden interference, the fixed process often struggles to balance detection sensitivity, synchronization stability, and error rate performance. Especially for geostationary satellite broadcasting services like Fengyun-4 EWAIB, although the terminal typically does not move at high speeds, practical applications still encounter problems such as terminal local oscillator error, environmental temperature drift, obstruction, antenna attitude changes, building reflections, adjacent channel interference, and local electromagnetic noise variations. This results in the receiving channel not remaining constant but exhibiting switching between various typical scenarios. Therefore, a technical solution is needed that goes beyond simply "making the device a chip," but rather enables real-time control and adaptive reconstruction of the signal processing pipeline on existing chip platforms. Summary of the Invention

[0006] This disclosure provides a satellite signal receiving chip system.

[0007] In a first aspect, this disclosure provides a satellite signal receiving chip system, including: a radio frequency front-end module, an analog-to-digital conversion module, a digital down-conversion module, a baseband processing module, and an on-chip control unit; The radio frequency front-end module is used to receive satellite radio frequency signals and perform front-end processing on the satellite radio frequency signals to output analog intermediate frequency signals; The analog-to-digital conversion module is used to perform analog-to-digital conversion on the analog intermediate frequency signal and output a digital intermediate frequency signal; The digital downconversion module is used to perform digital downconversion and decimation filtering on the digital intermediate frequency signal, and output a symbol-level complex baseband data sequence. The baseband processing module performs baseband processing on the symbol-level complex baseband data sequence and outputs the demodulated and decoded service data and baseband processing status information. The on-chip control unit identifies the current channel scenario based on the baseband processing status information output by the baseband processing module, and determines a parameter adjustment strategy based on the current channel scenario. The parameter adjustment strategy is used to adjust and store the underlying processing parameters for use by at least one of the RF front-end module, the digital down-conversion module, and the baseband processing module when processing subsequent input signals.

[0008] Furthermore, the underlying processing parameters include at least one of the following: NCO frequency control word, digital low-pass filter parameters, Farrow interpolation coefficients, baseband synchronization and tracking parameters, synchronization correlation parameters, dynamic threshold, decision feedback equalizer parameters, and decoding parameters.

[0009] Furthermore, the baseband processing module includes a frame synchronization unit, a spread spectrum despreading unit, a demodulation unit, and a channel decoding unit, which are used to sequentially perform synchronization, despreading, demodulation, and decoding on the symbol-level baseband complex data sequence, and recover the baseband processing of the service data.

[0010] Furthermore, the frame synchronization unit adopts a three-level synchronization mechanism, namely: coarse synchronization detection based on carrier synchronization code, fine synchronization detection based on spreading code guide sequence, and frame header validity verification based on unique code.

[0011] Furthermore, the frame synchronization unit employs a three-level synchronization mechanism, including: The received symbol-level complex baseband data sequence is correlated and matched point by point with the locally pre-stored carrier synchronization code to obtain coarse synchronization candidate positions; The spreading code search window is determined based on the coarse synchronization candidate positions; Within the spreading code search window, the received symbol-level complex baseband data sequence is correlated and matched with the locally pre-stored spreading code guide sequence to obtain the spreading code fine synchronization position; The unique code candidate position is determined based on the spread spectrum code fine synchronization position; Starting from the candidate unique code position, read a sequence of the same length as the locally predicted unique code from the symbol-level complex baseband data sequence, and perform correlation matching with the unique code to determine the effective frame header position.

[0012] Furthermore, the spreading and despreading unit performs correlation integration on the symbol-level complex baseband data sequence after frame synchronization and the locally predicted spreading code, wherein the on-chip control unit dynamically adjusts the integration length of the correlation integration according to the current channel scenario.

[0013] Furthermore, the demodulation unit is used to output decision information with confidence level for each bit of the symbol-level complex baseband data sequence after it has been spread and despread by the spreading and despreading unit.

[0014] Furthermore, the digital down-conversion module includes: a numerically controlled oscillator that generates a digital local oscillator signal based on the digital intermediate frequency signal, and the on-chip control unit dynamically corrects the frequency control word of the numerically controlled oscillator based on the residual frequency offset estimate and phase compensation amount in the baseband processing status information.

[0015] Furthermore, the frequency control word of the numerically controlled oscillator is dynamically corrected as follows: The baseband processing module estimates the residual frequency offset and the phase compensation amount; The on-chip control unit converts the residual frequency offset estimate into a correction value for the frequency control word and writes it into the configuration register of the numerically controlled oscillator; The numerically controlled oscillator generates a digital local oscillator signal in the next symbol period or the next processing window based on the frequency control word updated by the correction amount of the frequency control word. The digital mixer of the digital down-conversion module uses the digital local oscillator signal to perform complex mixing on the subsequent input signal to achieve carrier frequency offset compensation.

[0016] Furthermore, the baseband processing module also includes a frequency offset and phase correction unit, which includes a residual frequency offset estimation unit, a phase error estimation unit, and a complex multiplier or a phase rotator. The residual frequency offset estimation unit obtains the residual frequency offset estimate based on the synchronization sequence in the frame header and / or the phase changes of multiple consecutive input signals; The phase error estimation unit obtains a phase deviation estimate based on the phase difference between the synchronization sequence and the input signal; wherein, the residual frequency offset estimate and the phase error estimate are used by the on-chip control unit to update the frequency control word and phase compensation amount of the numerically controlled oscillator; The complex multiplier or phase rotator uses the digital local oscillator signal and phase compensation amount to perform point-by-point rotation compensation on the symbol-level complex baseband data sequence after frame synchronization, so as to obtain the symbol-level complex baseband data sequence after frequency offset and phase correction, and input it into the subsequent spread spectrum despreading unit.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0018] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings: Figure 1A structural block diagram of a satellite signal receiving chip system according to an embodiment of the present disclosure is shown.

[0019] Figure 2 This diagram illustrates a hardware implementation structure of a satellite communication on-chip system according to an embodiment of the present disclosure. Detailed Implementation

[0020] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of the exemplary embodiments have been omitted from the drawings.

[0021] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and do not preclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0022] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0023] This disclosure relates to a satellite signal receiving chip system and its adaptive signal processing system, which is applicable to the EWAIB (Emergency Weather Alert Information Broadcast) service signal of the Fengyun-4 satellite. More specifically, this disclosure relates to a low-power, high-sensitivity receiving technology based on an existing software-defined radio architecture satellite communication chip platform. By coordinating the adjustment of the on-chip RF front-end, digital baseband processing link, filter parameters, equalizer parameters, and synchronization and decoding resources, it achieves adaptive matching for different typical satellite channel scenarios without the need for re-fabrication.

[0024] This disclosure covers both traditional communication physical layer processing stages such as radio frequency reception, analog and digital filtering, spread spectrum despreading, synchronization detection, equalization, and decoding, as well as resource scheduling and control technologies for on-chip control units and hardware accelerators. It belongs to the cross-disciplinary technology direction of satellite receiver chips, low-power system-on-chips, and software-defined signal processing. This technology can be applied to scenarios such as meteorological information receiving terminals, unattended meteorological monitoring terminals, agricultural IoT terminals, low-altitude economic drone communication terminals, and emergency disaster early warning terminals.

[0025] The purpose of this disclosure is to provide a satellite signal receiving chip system with an adaptive scheduling mechanism. By introducing physical layer-oriented adaptive processing flow control on the basis of existing software radio architecture satellite communication SoC chips, it can improve receiving capabilities and optimize power consumption without re-fabrication. This solves the problems of high power consumption, large size, high cost, long development cycle of existing device-level solutions, as well as the difficulty of traditional fixed processing chains to adapt to various actual channel scenarios of Fengyun satellites.

[0026] The technical problems to be further addressed by this disclosure include: 1. How to achieve real-time control of the physical layer processing link in the hardware environment of existing chip system platforms rather than on servers or boards, so that the system has chip-level closed-loop processing capabilities; 2. How to abstract the actual satellite signal reception environment into identifiable typical channel scenarios and dynamically adjust processing parameters for different scenarios; 3. How to construct an adaptive filter mechanism for the entire link from analog front-end to digital baseband to equalizer; 4. How to achieve a high receiving sensitivity on the order of approximately -140dBm through multi-level collaborative technology; 5. How to maintain the continuous stability of the synchronization, demodulation, and decoding processes under dynamic channel conditions, avoiding link interruptions and drastic performance fluctuations.

[0027] The details of the embodiments of this disclosure are described in detail below through specific examples.

[0028] Figure 1 A structural block diagram of a satellite signal receiving chip system according to an embodiment of the present disclosure is shown. Figure 1 As shown, the system includes: an RF front-end module 101, an analog-to-digital conversion module 102, a digital down-conversion module 103, a baseband processing module 104, and an on-chip control unit 105; wherein, The radio frequency front-end module is used to receive satellite radio frequency signals and perform front-end processing on the satellite radio frequency signals to output analog intermediate frequency signals; The analog-to-digital conversion module is used to perform analog-to-digital conversion on the analog intermediate frequency signal and output a digital intermediate frequency signal; The digital downconversion module is used to perform digital downconversion and decimation filtering on the digital intermediate frequency signal, and output a symbol-level complex baseband data sequence. The baseband processing module performs baseband processing on the symbol-level complex baseband data sequence and outputs the demodulated and decoded service data and baseband processing status information. The on-chip control unit identifies the current channel scenario based on the baseband processing status information output by the baseband processing module, and determines a parameter adjustment strategy based on the current channel scenario. The parameter adjustment strategy is used to adjust and store the underlying processing parameters for use by at least one of the RF front-end module, the digital down-conversion module, and the baseband processing module when processing subsequent input signals.

[0029] In some embodiments, the service data includes meteorological monitoring information, disaster early warning information, and / or navigation enhancement information broadcast by satellite, and the baseband processing status information includes at least one of the following: synchronization sequence correlation peak value, peak-sidelobe ratio, noise floor estimate, residual frequency offset estimate, phase compensation amount, LLR statistics, decoding status, and equalization error; digital low-pass filter parameters. In some embodiments, the underlying processing parameters include at least one of the following: NCO frequency control word, digital low-pass filter parameters, Farrow interpolation coefficients, baseband synchronization and tracking parameters, synchronization correlation parameters, dynamic threshold, decision feedback equalizer parameters, and decoding parameters.

[0030] This disclosure is implemented in the satellite communication on-chip system platform environment, that is, the satellite signal receiving chip system is implemented by the on-chip system. Figure 2 This diagram illustrates a hardware implementation structure of a satellite communication on-chip system according to an embodiment of the present disclosure. The present disclosure does not address the problem by redesigning and fabricating a new dedicated chip, but rather by structurally modifying the on-chip signal processing flow without fundamentally changing the existing chip hardware resources. This results in a real-time closed-loop processing system consisting of "channel scene identification—filtering and synchronization parameter adaptation—equalization and decoding resource adjustment—state maintenance and continuous tracking."

[0031] See Figure 2 As shown (some modules are not shown), the baseband processing module includes a frame synchronization unit, a spreading and despreading unit, a demodulation unit, and a channel decoding unit. It is used to sequentially synchronize, despread, demodulate, and decode the symbol-level baseband complex data sequence, and recover the baseband processing data of the service data. In other embodiments, the baseband processing module also includes a frequency offset and phase correction unit, a carrier synchronization and tracking unit, and a decision feedback equalizer (DFE). Some computationally intensive units in the above-mentioned baseband processing module can be implemented by hardware acceleration units, such as the correlation operation unit, the spreading and despreading correlator, the decision feedback equalizer, and the Viterbi decoding acceleration unit; the remaining control logic and parameter scheduling logic can be implemented through firmware. The hardware acceleration unit is used to undertake computationally intensive physical layer processing tasks such as correlation operations, filtering, equalization, and decoding.

[0032] The radio frequency front-end module is used to perform front-end processing on the received satellite radio frequency signals to obtain analog intermediate frequency signals; the analog-to-digital conversion module is used to convert the analog intermediate frequency signals into digital intermediate frequency signals; the digital down-conversion module is used to perform down-conversion processing and decimation filtering processing on the digital intermediate frequency signals; the on-chip control unit is used to realize channel scene identification, adaptive calculation and scheduling control of underlying processing parameters; the hardware acceleration unit is used to undertake physical layer processing tasks; and the on-chip storage unit is used to store parameter configuration tables.

[0033] In some embodiments, the front-end processing includes receiving, amplifying, filtering, and down-converting satellite radio frequency signals; the analog-to-digital converter (ADC) module is used to convert analog intermediate frequency signals into digital intermediate frequency signals; the digital down-conversion module is used to shift the digital intermediate frequency signals to the zero intermediate frequency baseband and perform down-conversion processing such as filtering, interpolation, and decimation; the baseband processing module performs baseband processing on the symbol-level complex baseband data sequence obtained from the down-conversion processing to obtain demodulated and decoded service data and baseband processing status information; wherein, the service data includes meteorological monitoring information, disaster early warning information, and / or navigation enhancement information broadcast by the satellite. The on-chip control unit, implemented by a programmable DSP, is used to extract channel characteristic parameters and identify the current channel scenario based on the baseband processing status information output by the baseband processing module. Based on the current channel scenario, it determines a parameter adjustment strategy, which is used to adjust underlying processing parameters. For example, it adjusts the NCO frequency control word, digital low-pass filter parameters (such as the filter bandwidth of the RF front-end module), Farrow interpolation coefficients, decimation filter parameters (such as the decimation rate and filter coefficients of the digital down-conversion module), synchronization correlation integral length, decision feedback equalizer taps (one type of equalizer parameter), and Viterbi decoding window, etc., based on the physical layer parameters of the received sequence. The on-chip storage unit stores filter coefficients, synchronization status, equalizer taps, decoding status, and parameter configuration tables for different channel scenarios. (Digital low-pass filter parameters, decision feedback equalizer) The difference between this disclosure and existing chip platforms is not simply adding new hardware modules, but rather utilizing existing hardware resources to establish an on-chip closed-loop processing mechanism of "channel scene identification - parameter adaptive adjustment - state maintenance - continuous tracking", enabling the originally fixed or semi-fixed physical layer processing links to have adaptive scheduling capabilities.

[0034] Compared to server or board-based solutions, the technical solution disclosed herein is not simply about miniaturization and integration. Instead, it involves directly embedding the processing logic into the on-chip physical layer link. The object being controlled is not the application layer task, but rather the low-level processing parameters of the digital low-pass filter. Since these low-level processing parameters directly determine whether the signal can be processed by the physical layer, such as synchronization, despreading, demodulation, and decoding, this disclosure implements an on-chip real-time adaptive mechanism oriented towards the physical layer processing flow. This mechanism features deterministic timing, fast response, short internal data transfer time, minimal memory access, low power consumption, and closed-loop stability—features that are difficult to achieve in server and board-based systems.

[0035] Existing system platforms typically use fixed physical layer links, which complete "downconversion-filtering-synchronization-despreading-demodulation-decoding" with fixed parameters. However, this disclosure adds real-time feedback and parameter reconfiguration mechanisms between the above stages, enabling each processing stage to dynamically adjust according to changes in the channel scenario, rather than simply executing a fixed process.

[0036] In some embodiments, the RF front-end module includes a preamplifier section, an RF filter section, and a mixer and local oscillator section. The preamplifier section is implemented using a low-noise amplifier (ELNA), the RF filter section is implemented using an RF bandpass filter (RF BPF), and the mixer and local oscillator section is implemented using a mixer and a PLL. In some embodiments, the RF front-end also includes an intermediate frequency gain amplifier (GB) and an intermediate frequency bandpass filter (IF BPF).

[0037] In some embodiments, the RF front-end can be used to receive EWAIB broadcast signals in the approximately 1697MHz frequency band. The antenna interface can adopt a 50-ohm standard matching structure, and the input impedance matching can be improved through a π-type network to enhance the efficiency of weak signal input. Depending on the deployment method of unattended terminals and mobile terminals, the system can support directional antennas or omnidirectional antennas. In other embodiments, in addition to being used for Fengyun-4 EWAIB broadcast signals, the system can also be applied to satellite spread spectrum broadcast signals with similar characteristics of spread spectrum, narrowband broadcast, low data rate, and weak signal reception. However, to ensure a clear description of the technical solutions of this disclosure, the embodiments still primarily focus on the Fengyun-4 EWAIB broadcast signal.

[0038] In some embodiments, a low-noise amplifier (ELNA) is used in the pre-amplification stage to amplify the weak signal received by the antenna. Since the front-end noise figure has a significant impact on the overall system sensitivity under signal input conditions on the order of -140 dBm, the front-end noise figure can be controlled at a low level while ensuring an effective gain of over 20 dB and high third-order intermodulation performance to reduce compression and intermodulation effects caused by strong adjacent-channel interference. To avoid saturation of the receiving link due to strong spurious signals in the environment, the front-end can also be configured with automatic gain adjustment or segmented gain control structures, enabling the input dynamic range to cover the coexistence of weak signals and occasional strong interference.

[0039] In some embodiments, the radio frequency (RF) filtering section employs a bandpass filter to suppress out-of-band interference and adjacent-channel signals. Unlike fixed filtering schemes, this disclosure introduces a tunable radio frequency bandpass filter (RF BPF) into the RF filtering section. Figure 2 (Not shown in the image), it can be placed between the low-noise amplifier (ELNA) and the mixer to suppress out-of-band interference and adjacent-channel signals, allowing the center frequency and equivalent bandwidth to be adjusted within a certain range. Its purpose is not to change the service frequency, but rather to maintain the passage of useful signal energy by appropriately adjusting the passband position and passband width when terminal local oscillator error, temperature drift, or actual frequency offset exists, while simultaneously enhancing the suppression capability of adjacent-channel and image interference. It enables the filter to adapt in the analog domain.

[0040] In some optional embodiments, the mixing and local oscillator section employs a low-IF architecture. This section generates a stable local oscillator signal via a phase-locked loop (PLL). This stable local oscillator signal is mixed with an RF signal in a mixer to obtain an IF signal. The RF signal is amplified by a low-noise amplifier (ELNA) and filtered by an RF bandpass filter (RF BPF). This RF signal is then mixed with the local oscillator signal generated by the PLL to obtain an approximately 12MHz analog IF signal. The analog IF signal is then processed by an IF gain amplifier (GB) and an IF bandpass filter (IF BPF) before entering the analog-to-digital converter (ADC). For example, a signal near 1697MHz is converted to an approximately 12MHz IF. This low-IF scheme reduces the DC bias problem encountered in direct-downconversion and facilitates subsequent digital processing. The mixed IF signal is then fed into the ADC after passing through the IF gain amplifier (GB) and the IF bandpass filter (IF BPF) to improve the effective signal-to-noise ratio and out-of-band rejection capability.

[0041] In some alternative embodiments, the analog-to-digital converter (ADC) module may employ a sampling rate matching the subsequent decimation and symbol processing, such as 14.7456 MHz, and possess sufficient resolution to ensure dynamic range in weak signal conditions. This sampling rate has an integer ratio to the subsequent 1.8432 Msps symbol-level processing, facilitating digital filtering and decimation.

[0042] The sampling rate of the analog-to-digital converter (ADC) is determined based on the EWAIB broadcast signal system parameters, intermediate frequency (IF), and the chip's internal clock configuration. The digital down-conversion module converts the ADC sampled data into a symbol-level sampling rate that matches the subsequent baseband processing through a decimation filter and a downsampling unit. In one embodiment, the ADC sampling rate is 14.7456 MHz, which, after decimation by 8 times, yields a symbol-level complex baseband data sequence of 1.8432 Msps.

[0043] In this embodiment, the system utilizes a numerically controlled oscillator (NCO) to generate a digital local oscillator (LoU) signal. The NCO performs complex mixing on the digital intermediate frequency (IF) signal output from the RF front-end module, thereby shifting the digital IF signal to the zero-IF baseband to generate the digital LoU signal. Unlike fixed NCO parameter schemes, the frequency control word of the NCO in this disclosure is not statically fixed, but dynamically corrected based on the residual frequency offset and phase rotation trend obtained from channel estimation. This ensures that the baseband carrier remains trackable even in the presence of LoU errors, terminal temperature drift, slight Doppler fluctuations, or environmental disturbances. In some implementations, dynamic correction of the NCO frequency control word can be achieved through the following process: the baseband processing module estimates the residual frequency offset estimate and phase compensation amount during frame synchronization or Gold code correlation; the on-chip control unit converts the residual frequency offset estimate into the NCO frequency control word correction amount and writes it into the NCO configuration register, so that the digital local oscillator frequency approximates the actual carrier frequency; after the on-chip control unit writes the NCO frequency control word correction amount into the NCO configuration register, the digitally controlled oscillator (NCO) generates a digital local oscillator signal according to the updated frequency control word in the next symbol period or the next processing window; the digital mixer of the digital downconverter module uses the digital local oscillator signal to perform complex mixing on the subsequent input signal to achieve carrier frequency offset compensation.

[0044] The residual frequency offset estimate and phase compensation amount serve as feedback values ​​for the on-chip control unit to update the NCO frequency control word, and are used to calculate the NCO frequency control word correction amount to correct the digital local oscillator frequency.

[0045] If the phase difference between adjacent correlated peaks in the digital intermediate frequency signal determined by multiple consecutive baseband modulation symbols or synchronization sequences is Δφ, and the interval time between adjacent correlated peaks is Δt, then the residual frequency offset estimate is Δf=Δφ / (2πΔt). The on-chip control unit updates the NCO frequency control word according to Δf, thereby realizing carrier tracking.

[0046] After the aforementioned complex mixing, the signal is passed through a digital low-pass filter (LPF) to remove high-frequency images and irrelevant noise components, yielding the baseband sampled signal. This digital low-pass filter also employs an adaptive mechanism; its cutoff frequency, transition bandwidth, and filter order can be adjusted based on the estimated signal bandwidth, noise level, and interference conditions. In high signal-to-noise ratio (SNR) stable channel scenarios, the filter bandwidth can be appropriately widened and the filter order reduced to decrease computational load. In low SNR or narrowband interference scenarios, the effective passband can be appropriately narrowed and stopband attenuation enhanced to improve signal-to-noise separation capability. This achieves the filter's adaptive capability in the digital baseband domain.

[0047] In the sampling rate conversion stage, this disclosure employs a Farrow (structural fractional delay interpolation filter) to achieve fractional delay interpolation. The Farrow's input is the baseband sampled signal after digital low-pass filtering, and its output is the baseband signal after sampling phase correction. This signal then enters decimation filtering and downsampling processing, ultimately yielding a symbol-level complex baseband data sequence. This Farrow structure not only improves time resolution but, more importantly, allows for dynamic adjustment of the interpolation coefficients based on the current synchronization error and optimal sampling point offset, achieving fine-grained correction of the sampling phase. Subsequently, decimation filtering and downsampling reduce the data rate to a symbol-level sampling rate more suitable for subsequent baseband processing. During this process, the coefficients and decimation parameters of the anti-aliasing filter can also be adjusted according to the current signal bandwidth and noise conditions, enabling the filter to adapt during downsampling.

[0048] The digital downconverter module includes a numerically controlled oscillator (NCO), a digital mixer, a digital low-pass filter (LPF), a Farrow fractional delay interpolation filter, a decimation filter (or an anti-aliasing filter), and a downsampling unit.

[0049] The NCO is used to generate a digital local oscillator signal; the digital mixer is used to perform complex mixing between the digital intermediate frequency signal and the digital local oscillator signal to obtain a zero-IF complex baseband sampling signal; the digital low-pass filter (LPF) is used to filter out high-frequency images and out-of-band noise generated after complex mixing; the Farrow structure fractional delay interpolation filter is used to perform fractional delay interpolation on the baseband sampling signal according to the sampling phase error to obtain a baseband signal after sampling phase correction; the decimation filter / anti-aliasing filter is used to filter out high-frequency components that may be aliased into the target baseband bandwidth before downsampling; the downsampling unit is used to reduce the sampling rate according to a preset decimation factor, and finally output a symbol-level complex baseband data sequence.

[0050] Given the relatively stable communication channels of the Fengyun-4 satellite, which only have a few typical scenarios, this disclosure identifies these channel scenarios and dynamically adjusts the corresponding processing parameters based on their characteristics. These typical channel scenarios guide the parameter adjustments of the RF front-end and digital down-conversion module, as well as the selection of synchronization, equalization, and decoding strategies for the subsequent baseband processing module. In other words, the system does not abstractly switch between several operating modes, but rather first identifies the current channel scenario based on physical layer parameters and then adjusts the relevant processing steps accordingly.

[0051] For example, in high signal-to-noise ratio (SNR) stable scenarios, the filtering order of the digital low-pass filter (LPF) in the digital down-conversion module can be reduced, the correlation integration length of the correlation operation unit in the baseband processing module can be shortened, and the number of equalizer taps can be reduced. In extremely low SNR scenarios, the digital filtering bandwidth of the digital low-pass filter (LPF) in the digital down-conversion module can be narrowed, the synchronization and despreading integration length can be extended, and decoding resources can be enhanced. In frequency offset scenarios, the NCO frequency control word and the carrier loop parameters of the carrier synchronization and tracking unit in the baseband processing module can be updated, instead of corresponding to a separate digital low-pass filter or decimation filter. This unit is used to continuously track the carrier state based on residual frequency offset and phase error, and control the NCO or phase rotator to complete compensation.

[0052] In multipath scenarios, the number of DFE taps in the equalizer can be increased and the equalization step size can be adjusted; in sudden interference scenarios, the dynamic threshold can be increased and the unique code verification can be enhanced. The dynamic threshold is the decision parameter of the frame synchronization unit in the baseband processing module.

[0053] The following sections introduce several typical channel scenarios.

[0054] The first category is a high signal-to-noise ratio (SNR) stable channel scenario. This scenario typically occurs under conditions of stable antenna pointing, no obstructions, low ambient electromagnetic noise, and stable local oscillator state. Its characteristics include received power fluctuations less than a set power threshold, synchronization correlation peak amplitude greater than a set amplitude threshold, bit error rate lower than a set code rate threshold, and frequency offset variation less than a set variation threshold. In this scenario, the system can achieve stable reception by maintaining only appropriate filtering and synchronization parameters without using the strongest equalization and the longest integration length.

[0055] The second category is weak signal scenarios with extremely low signal-to-noise ratios. This scenario typically occurs in applications with limited antenna gain, poor weather conditions, edge coverage at the installation location, or where the terminal itself is limited by a small antenna. Its characteristics include the useful signal approaching the system's sensitivity limit, insignificant correlation peaks, and low soft-bit confidence before decoding. In this scenario, improving correlation integration time, enhancing filtering and noise suppression capabilities, and strengthening equalization and soft-decision decoding can ensure detectability and decodeability under weak signal conditions.

[0056] The third category is frequency offset and phase disturbance scenarios. This scenario may be caused by terminal local oscillator error, temperature drift, device aging, or slight movement, manifesting as residual frequency offset with varying carrier frequencies (such as continuous or slow changes) and abnormal phase rotation speed. In this case, it is necessary to enhance carrier tracking, dynamically correct the NCO frequency control word, optimize loop bandwidth, and maintain the continuity of phase estimation.

[0057] The fourth category is multipath and reflection interference scenarios. This scenario is common at the edge of cities, around buildings, during low-altitude drone flights, and in complex terrain deployments. It manifests as broadened correlation peaks, increased inter-symbol crosstalk, and rising equalization errors, which can severely lead to synchronization errors and degraded decoding performance. In this scenario, the equalizer's adaptive capability can be enhanced, and the filter bandwidth and synchronization decision strategy can be appropriately adjusted.

[0058] The fifth category is sudden interference or adjacent-channel interference scenarios. These scenarios may be caused by temporary electromagnetic noise, the activation of nearby communication equipment, or strong pulse interference, manifesting as a sudden rise in the noise floor, a deterioration in the sidelobe ratio, and an increased probability of false alarms. In this scenario, anti-interference capabilities can be improved through front-end filtering adjustments, digital filtering suppression, dynamic threshold updates, and multi-level verification mechanisms.

[0059] After digital down-conversion and preliminary filtering, the system obtains a symbol-level complex baseband data sequence. This symbol-level complex baseband data sequence enters the baseband processing module. The main tasks of the baseband processing module include frame synchronization, frequency offset and phase correction, spread spectrum despreading, QPSK demodulation, and channel decoding.

[0060] In some embodiments, a three-level synchronization mechanism can be used for frame synchronization. First, a sliding correlation is performed using a 64-bit all-"1" carrier synchronization code as a template to calculate the correlation value R(τ), and a dynamic threshold is constructed based on the noise variance. Sliding correlation refers to performing correlation matching point by point between the received symbol-level complex baseband data sequence and the locally pre-stored 64-bit all-"1" carrier synchronization code. Let the received symbol-level complex baseband data sequence be r[n], and the local carrier synchronization code be c_sync[k]. The correlation magnitude is calculated at the candidate starting point τ: R(τ)=Σ r[τ+k]·c_sync*[k], k=0 to 63.

[0061] Where c_sync*[k] represents the conjugate value of the local carrier synchronization code. The system slides τ across the continuous data stream, calculating the correlation values ​​at different positions. When the correlation amplitude |R(τ)| at a certain position exceeds the dynamic threshold T, that position is determined as a coarse synchronization candidate position.

[0062] The dynamic threshold is constructed based on the current noise floor estimate. The noise variance can be estimated from the sampling window outside the no-signal interval, the correlated sidelobe region, or the synchronization peak. For example, in a sliding correlation process, the mean and variance of the correlation output in the non-peak region can be calculated and used as the noise floor estimate.

[0063] In some embodiments, the dynamic threshold can be expressed as: , where μ_noise is the noise-related output mean, is the noise-related output variance (this is acceptable), and α is a preset coefficient or a configurable coefficient. A coarse synchronization candidate position is considered to exist when |R(τ)|>T. Compared to a fixed threshold scheme, this dynamic threshold can adaptively adjust with changes in the noise floor, helping to reduce the probability of false alarms or missed detections when noise changes and interference are present.

[0064] Secondly, a 64-bit spreading code guide sequence is used for coarse correlation detection near the coarse synchronization candidate positions. Its excellent autocorrelation characteristics improve the fine positioning accuracy, and phase compensation is performed in conjunction with the coarse frequency offset estimation results. Finally, a 64-bit unique code is used to perform matching verification, further filtering the coarse synchronization candidate positions to obtain the final frame header position after fine synchronization, thereby reducing misjudgments caused by multipath and burst interference. Specifically, after determining the coarse synchronization candidate positions, the theoretical starting position of the spreading code guide sequence is determined based on the fixed positional relationship between the carrier synchronization code and the spreading code guide sequence in the frame header. A spreading code search window is set within a preset range before and after the theoretical starting position, and the received sequences at different offset positions within the spreading code search window are coarsely correlated with the locally pre-stored 64-bit spreading code guide sequence. The position corresponding to the maximum correlation peak that meets a preset threshold is determined as the spreading code fine synchronization position. If no position with the maximum correlation peak that meets the preset threshold exists, the current coarse synchronization candidate position is eliminated.

[0065] The coarse synchronization position is obtained by sliding correlation of the 64-bit carrier synchronization code and exceeding the dynamic threshold. The coarse correlation of the spreading code guide sequence refers to the correlation matching between the received sequence (i.e., the received symbol-level complex baseband data sequence) and the locally pre-stored 64-bit spreading code guide sequence within the spreading code search window. Based on the carrier synchronization code correlation results, the residual frequency offset and initial phase are estimated. The phase compensation amount for the corresponding time position of the spreading code guide sequence is calculated based on the residual frequency offset estimate and the initial phase, thereby further refining the frame header position.

[0066] Phase compensation can be used to compensate the received sequence within the spreading code search window. Specifically, before performing coherent correlation matching of the spreading code, phase compensation is calculated based on the residual frequency offset estimate and the initial phase estimate within the spreading code search window, and phase compensation is performed on the received sequence at different offset positions. The phase-compensated received sequence is then coherently correlated with the locally pre-stored 64-bit spreading code guide sequence, and the position corresponding to the maximum correlation peak that meets the preset threshold is determined as the spreading code fine synchronization position.

[0067] The unique code is a 64-bit fixed sequence preset in the protocol, which is pre-stored locally at the receiver. After completing coarse synchronization of the carrier synchronization code and fine synchronization of the Gold code (i.e., determining the fine synchronization position of the spreading code), the candidate position of the unique code is determined according to the fixed position relationship between the spreading code guide sequence and the unique code in the frame header. Starting from the candidate position of the unique code, a sequence of the same length as the locally predicted unique code is read from the symbol-level complex baseband data sequence, and correlation matching is performed with the unique code. When the correlation value meets a preset threshold, the coarse synchronization candidate position corresponding to the current fine synchronization position of the spreading code is confirmed to be valid, and the valid frame header position is determined according to the fixed position relationship between the carrier synchronization code, the spreading code guide sequence, and the unique code in the frame header. When the correlation value does not meet the preset threshold, the current coarse synchronization candidate position is eliminated.

[0068] In the frequency offset and phase correction stage, the frequency offset and phase correction unit in the baseband processing module is used to perform residual frequency offset compensation and phase correction on the complex baseband data stream after frame synchronization. The frequency offset and phase correction unit includes a residual frequency offset estimation unit, a phase error estimation unit, and a complex multiplier or phase rotator.

[0069] The NCO is set in the digital downconverter module. The frequency offset and phase correction unit does not set the NCO separately. Instead, it generates the NCO frequency control word correction amount based on the residual frequency offset estimate and the phase error estimate, and the on-chip control unit writes the correction amount into the NCO configuration register in the digital downconverter module.

[0070] Specifically, the residual frequency offset estimation unit obtains a residual frequency offset estimate based on the phase changes of the synchronization sequence and / or multiple consecutive input signals in the frame header; the phase error estimation unit obtains a phase deviation estimate based on the phase difference between the synchronization sequence and the input signal. The on-chip control unit updates the NCO frequency control word correction and phase compensation based on the residual frequency offset estimate and phase error estimate. The NCO frequency control word correction is used to update the configuration parameters of the NCO in the digital downconversion module, so that the NCO generates a corrected digital local oscillator signal in subsequent processing cycles. The complex multiplier or phase rotator uses the digital local oscillator signal and the phase compensation to perform point-by-point rotation compensation on the symbol-level complex baseband data sequence after frame synchronization, to obtain the symbol-level complex baseband data sequence after frequency offset and phase correction, and inputs it into the subsequent spread spectrum despreading unit.

[0071] In scenarios involving frequency offset and phase disturbances, the on-chip control unit can dynamically adjust at least one of the following: NCO frequency control word, phase compensation amount, loop bandwidth, loop filter coefficients, parameter update period, and lockout decision threshold, thereby improving carrier tracking capability. When the channel state is relatively stable, the parameter update frequency can be appropriately reduced or the loop bandwidth can be narrowed to reduce computational load and noise disturbance. The frequency offset and phase correction unit includes a residual frequency offset estimation unit, a phase error estimation unit, and a complex multiplier or phase rotator, and is connected to the numerically controlled oscillator (NCO) in the digital down-conversion module. The residual frequency offset estimation unit and the phase error estimation unit generate residual frequency offset estimates and phase error estimates; wherein, the residual frequency offset estimates and phase error estimates are used by the on-chip control unit to update the frequency control word and phase compensation amount of the NCO; the complex multiplier or phase rotator uses the digital local oscillator signal and the phase compensation amount to perform point-by-point rotation compensation on the frame-synchronized symbol-level complex baseband data sequence to obtain the frequency offset and phase-corrected symbol-level complex baseband data sequence, which is then input into the subsequent spread spectrum despreading unit.

[0072] The above data flow can be summarized as follows: complex baseband data flow after frame synchronization → residual frequency offset estimation and phase compensation estimation → updating NCO frequency control word and phase compensation → complex rotation compensation → complex baseband data flow after frequency offset and phase correction → spread spectrum despreading.

[0073] In the spread spectrum despreading stage, in some embodiments, a spreading sequence with a spreading ratio of approximately 1024 can be used for correlation despreading. Theoretically, this spreading process can bring a processing gain of approximately 30 dB, which is an important foundation for the system to achieve high-sensitivity reception. Unlike despreading strategies with a fixed integration length, this disclosure allows for adjustment of the correlation integration length according to the current channel scenario: in high signal-to-noise ratio scenarios, a shorter correlation integration time is sufficient to meet the detection requirements; in weak signal scenarios, a longer correlation integration time is used to improve the effective detection probability. It should be noted that the symbol-level complex baseband data sequence described in this disclosure corresponds to chip-level data before spread spectrum despreading, and after spread spectrum despreading, a symbol-level decision quantity or symbol sequence is obtained. The spread spectrum despreading unit performs correlation integration between the frame-synchronized symbol-level complex baseband data sequence and the locally predicted spreading code to obtain a despread symbol decision quantity. This accumulation process is the correlation integration. In the spread spectrum despreading stage, the receiver multiplies the received chip sequence corresponding to each spreading symbol with the locally pre-stored spreading code point by point and accumulates the results to obtain the despreading decision value corresponding to that spreading symbol. In one embodiment, the spreading ratio can be 1024, therefore, the basic correlation integral length corresponding to a single spreading symbol is 1024 chips. Based on this, the on-chip control unit can also adjust the outer accumulation integral length according to the channel scenario, that is, to accumulate multiple consecutive despreading decisions: in a high signal-to-noise ratio stable scenario, a shorter outer accumulation window is used; in a low signal-to-noise ratio weak signal scenario, a longer outer accumulation window is used to improve the equivalent output signal-to-noise ratio and decision reliability.

[0074] In weak signal scenarios, the number of accumulations of synchronization sequence correlation results can be increased or the correlation integration window of the synchronization detection stage can be extended to improve the equivalent output signal-to-noise ratio and synchronization detection probability. In scenarios with good channel conditions, the number of accumulations of synchronization sequence correlation results can be reduced to decrease computational load and processing latency. It should be noted that the basic correlation integration length for a single data symbol in the spread spectrum and despreading stage is determined by the spreading ratio. In one embodiment, the spreading ratio can be 1024 chips.

[0075] In some embodiments, the correlation integration length is selected by the adaptive scheduling logic in the on-chip control unit based on the current channel parameters. The system can preset multiple correlation integration length configurations, such as short integration, medium integration, and long integration, corresponding to different channel conditions. When a decrease in correlation peak, an increase in noise variance, or a decrease in LLR confidence is detected, the current scenario can be determined to be an extremely low SNR weak signal scenario. In this extremely low SNR weak signal scenario, the on-chip control unit writes a longer correlation integration length to the correlation operation unit. In this scenario, the useful signal approaches the receiver sensitivity limit, the correlation peak of the synchronization sequence decreases, the correlation peak sidelobe ratio deteriorates, the confidence of the demodulated soft decision information decreases, and the risk of decoding errors increases. In the extremely low SNR weak signal scenario, QPSK demodulation adopts a soft decision method, outputting the log-likelihood ratio (LLR) or equivalent soft information to provide the subsequent channel decoding unit with the decision result and confidence information corresponding to each bit to be decoded. When the signal is detected to be stable and the synchronization peak is obvious, the on-chip control unit restores a shorter correlation integration length to reduce the computational load.

[0076] In some embodiments, QPSK demodulation employs a soft-decision method, outputting a log-likelihood ratio (LLR) or equivalent soft information to provide more confidence information to subsequent decoders when the signal is weak. The QPSK demodulation unit outputs confidence-based decision information for each bit of the symbol-level complex baseband data sequence after spread and despreading by the spreading and despreading unit. This confidence-based decision information includes the LLR corresponding to each bit to be decoded; the LLR characterizes the value tendency and decision confidence of the corresponding bit and serves as input to the subsequent channel decoding unit.

[0077] Soft decision information refers to the confidence-based decision information output by the demodulator, rather than a simple hard decision of 0 or 1. For example, after QPSK demodulation, the system not only determines whether a bit is more likely to be 0 or 1, but also outputs its reliability, which is usually expressed as the log-likelihood ratio (LLR). The larger the absolute value of the LLR, the more reliable the decision for that bit; the smaller the absolute value of the LLR, the less uncertain the decision for that bit. The subsequent Viterbi decoder utilizes soft information to improve error correction performance under weak signals. The channel quality is evaluated by the channel feature extraction and scene recognition unit in the on-chip control unit. The channel feature extraction and scene recognition unit determines the quality based on at least one of the following: synchronization sequence correlation peak, peak-sidelobe ratio, noise floor estimate, residual frequency offset estimate, phase rotation speed, DFE equalization error, LLR statistics, and decoding state.

[0078] In some embodiments, the channel decoding stage may employ the Viterbi algorithm or an error correction decoding structure that matches the system code pattern, and adapt the path metric accuracy, decoding integral length, and related resource usage intensity according to the channel quality, thereby ensuring reliability while avoiding unnecessary energy consumption.

[0079] The on-chip control unit is further configured to adjust the decoding parameters of the channel decoding unit according to the current channel scenario. These decoding parameters include at least one of the following: soft information quantization precision, decoding backtracking integration length, and decoding resource configuration parameters. In high signal-to-noise ratio (SNR) stable scenarios, the on-chip control unit reduces the intensity of decoding resource usage to decrease computation and power consumption. In extremely low SNR weak signal scenarios, the on-chip control unit increases soft information quantization precision, extends the decoding backtracking integration length, and / or enables more decoding resources to improve error correction capabilities.

[0080] In multipath and reflection interference scenarios, relying solely on RF front-end filtering and synchronization is insufficient to completely suppress inter-symbol interference. Therefore, this disclosure introduces a decision feedback equalizer (DFE). In some embodiments, the baseband processing module further includes a decision feedback equalizer (DFE), which is positioned after the spread spectrum despreading unit and before the QPSK demodulation unit. The input of the decision feedback equalizer (DFE) is the symbol sequence output from the spread spectrum despreading unit, and the output is an equalized symbol sequence after multipath distortion compensation. The equalized symbol sequence is input to the QPSK demodulation unit. The decision feedback equalizer (DFE) includes a forward filter, a feedback filter, a symbol decision unit, and a coefficient update unit. The coefficient update unit updates the tap coefficients of the forward filter and the feedback filter based on the equalization error. The DFE includes a forward filter, a feedback filter, and a coefficient update unit, and the tap coefficients of the forward filter and the feedback filter are updated by the coefficient update unit based on the decision error. The decision feedback equalizer (DFE) includes a forward filter, a feedback filter, a symbol decision unit, an error calculation unit, and a coefficient update unit. During the initialization phase, the error calculation unit determines the decision error based on the difference between the known reference symbol and the equalization output. Upon entering the decision-guided update phase, the error calculation unit determines the decision error again based on the difference between the decision symbol output by the symbol decision controller and the equalization output. Based on the decision error, the coefficient update unit updates the tap coefficients of the feedforward and feedback filters using LMS, RLS, or their variants. These tap coefficients are updated using LMS (Least Mean Square), RLS (Recursive Least Squares), or their variants. Here, "filter adaptation" refers not only to real-time coefficient changes but also to the selection of the number of taps, the adjustment of the update step size, and the dynamic matching of the weights for the feedforward and feedback filters.

[0081] Therefore, the complete meaning of "filter adaptation" in this disclosure includes: adjustment of the center frequency and bandwidth of the analog front-end bandpass filter, adjustment of the cutoff frequency and order of the digital low-pass filter, adjustment of the interpolation filter coefficients, adjustment of the decimation anti-aliasing filter parameters, and adjustment of the decision feedback equalizer tap coefficients and step size. The coefficient update step size is used to control the single adjustment magnitude when updating the feedforward and feedback filter tap coefficients using the LMS algorithm or a variant thereof.

[0082] In some embodiments, the on-chip control unit is implemented by a programmable DSP or an on-chip control processor. The on-chip control unit is connected to the digital down-conversion module, the baseband processing module, and the on-chip memory unit or configuration register, respectively.

[0083] The on-chip control unit extracts channel characteristic parameters based on the processing status information output by the digital down-conversion module and / or the baseband processing module. The processing status information includes digital down-conversion processing status information and / or baseband processing status information. The channel status information includes at least one of the following: synchronization sequence correlation peak value, peak-sidelobe ratio, noise floor estimate, residual frequency offset estimate, phase compensation error estimate (or phase rotation), LLR statistics, DFE equalization error, and decoding status.

[0084] The on-chip control unit extracts channel feature parameters based on the aforementioned channel state information and matches these parameters with preset thresholds, rule tables, or parameter configuration tables to identify the current channel scenario. The channel scenario includes at least one of the following: a high signal-to-noise ratio stable scenario, an extremely low signal-to-noise ratio weak signal scenario, a frequency offset and phase disturbance scenario, a multipath and reflection interference scenario, and a sudden interference or adjacent-channel interference scenario.

[0085] In some embodiments, high SNR stable scenarios are characterized by higher synchronization sequence correlation peaks, higher peak-sidelobe ratios, lower noise floor estimates, smaller residual frequency offset estimates, and higher LLR confidence. Extremely low SNR weak signal scenarios are characterized by lower synchronization sequence correlation peaks, lower peak-sidelobe ratios, higher noise floor estimates, and lower LLR confidence. Frequency offset and phase disturbance scenarios are characterized by increased residual frequency offset estimates, continuous changes in phase error, increased carrier loop error signals, or increased NCO residual correction. Multipath and reflection interference scenarios are characterized by broadened correlation peaks, decreased peak-sidelobe ratios, and increased DFE equalization errors. Sudden interference or adjacent-channel interference scenarios are characterized by short-term increases in noise floor, abnormal synchronization correlation outputs, increased unique code check failure rates, or increased false synchronization probabilities. The preset thresholds, rule tables, or parameter configuration tables involved in different channel scenarios can be set according to actual needs and are not specifically limited here.

[0086] After determining the current channel scenario, the on-chip control unit reads the corresponding parameter configuration from the on-chip storage unit, or calculates the underlying processing parameters that need to be updated according to preset rules, and writes the updated underlying processing parameters into the configuration register or coefficient storage area of ​​the corresponding hardware unit. The underlying processing parameters include: (1) Frequency control word of NCO in digital downconversion module; (2) Parameters of digital low-pass filter LPF such as cutoff frequency, filter order and filter coefficient; (3) Interpolation coefficient of Farrow structure fractional delay interpolation filter; (4) Dynamic threshold of frame synchronization detection in baseband processing module; (5) Synchronization related parameters such as integration length and accumulation number; (6) Baseband synchronization and tracking parameters of carrier synchronization and tracking unit such as loop bandwidth, loop filter coefficient, parameter update period and phase compensation amount; (7) Parameters of decision feedback equalizer DFE such as forward filter tap coefficient, feedback filter tap coefficient, number of taps and coefficient update step size; (8) Soft information quantization accuracy, decoding parameters such as decoding backtracking integration length and decoding resource configuration parameters of channel decoding unit.

[0087] Parameter updates can take effect at frame boundaries, symbol boundaries, or preset processing window boundaries to avoid link jitter caused by changing parameters midway through current data processing. After the parameter update, the digital down-conversion module and baseband processing module process subsequent received signals according to the updated parameters. The on-chip control unit continues to monitor the channel status of the next frame or the next time window and cyclically executes the channel scene identification and parameter update process based on the monitoring results.

[0088] In some embodiments, the digital downconversion module further includes a decimation filter and a downsampling unit. The decimation filter is located after the Farrow fractional delay interpolation filter and before the downsampling unit, and is used to filter out high-frequency components that may alias into the target baseband bandwidth before reducing the sampling rate. The configurable parameters of the decimation filter include at least one of cutoff frequency, filter coefficients, and filter order; the configurable parameters of the downsampling unit include decimation factor.

[0089] The aforementioned filtering process includes both tunable or configurable filtering structures in hardware and updates to digital filter coefficients and parameters under software control, forming a full-link adaptive filtering system from analog to digital and from front-end to baseband.

[0090] The approximately -140dBm receiver sensitivity achieved in this disclosure is not due to a single technology, but rather to the synergy of multiple technologies.

[0091] First, a low-noise RF front-end is adopted, and by using a low-noise amplifier, reasonable gain allocation and high-selectivity filter, the equivalent input noise is reduced as much as possible and out-of-band interference is suppressed, thereby improving the observability of weak signals from the analog level.

[0092] Second, spread spectrum despreading is employed. With a spreading ratio of approximately 1024, a processing gain of about 30dB can be obtained after despreading, which is a key factor in improving the weak signal detection capability at the system level.

[0093] Third, a multi-level synchronization correlation mechanism is adopted. The three-level correlation and verification of carrier synchronization code, Gold code and unique code enable frame header detection in extremely low signal scenarios to not rely on a single threshold judgment, but improve detection reliability through multiple correlation enhancements and false judgment suppression.

[0094] Fourth, dynamic correlation integration and soft-decision decoding are employed. Under signal conditions approaching the sensitivity limit, appropriately extending the synchronization and despreading integration lengths and using soft-decision decoding to provide the decoder with more reliable information can significantly improve the final decoding success rate. The dynamic extension of the synchronization and despreading integration lengths is based on factors including the synchronization correlation peak amplitude, peak-sidelobe ratio, noise variance, LLR confidence, and pre-decoding error prediction. When the correlation peak amplitude decreases, the peak-sidelobe ratio deteriorates, or the soft-bit confidence decreases, it indicates poor signal quality. The system extends the integration window to allow more chips or more symbol energy to participate in the accumulation, thereby improving the equivalent output signal-to-noise ratio.

[0095] The basic principle is that correlation integration can enhance useful signal components that are consistent with local synchronization codes or spreading codes, while random noise, due to its random phase and amplitude, is partially canceled out during the accumulation process. Therefore, extending the integration can improve the detectability of weak signals.

[0096] Fifth, end-to-end adaptive filtering and equalization are employed. By narrowing the effective noise bandwidth, suppressing multipath distortion, and compensating for inter-symbol crosstalk according to the channel scenario, the quality of the effective signal entering demodulation and decoding is further improved. Channel scenario identification is performed by the on-chip control unit. Identification criteria include: synchronization sequence correlation peak value, peak-sidelobe ratio, noise variance, residual frequency offset estimate, phase rotation speed, DFE equalization error, LLR statistics, and pre-decoding error prediction.

[0097] The identification timing can include: the initial acquisition phase, the frame header synchronization phase, the periodic detection phase within a fixed time window, and the trigger detection phase when an abnormal bit error rate or synchronization status is detected. The on-chip control unit matches the above parameters with preset thresholds or rule tables to determine whether the current scenario is a high signal-to-noise ratio stable, extremely low signal-to-noise ratio, frequency offset disturbance, multipath interference, or sudden interference.

[0098] Sixth, it employs on-chip resource rapid adjustment. Because this disclosure completes parameter adjustment and process reconfiguration internally within the chip, it eliminates the need for slow control from external servers or boards. Therefore, it can rapidly enhance weak signal processing capabilities in the early stages of channel degradation, reducing synchronization loss and detection failures caused by processing lag. The hardware resources of this disclosure include existing chip platform components such as the RF front-end, ADC, NCO, digital mixer, digital filter, Farrow interpolation filter, decimation filter, decision feedback equalizer, correlation unit, decoding acceleration unit, on-chip control unit, and on-chip memory.

[0099] The software or firmware implementation includes channel scene identification rules, parameter selection logic, NCO control word calculation, filter coefficient selection, integral length selection, equalizer step size adjustment, decoding resource configuration, and state preservation strategy.

[0100] In other words, this disclosure does not involve adding new independent hardware, but rather controlling the operating parameters of existing on-chip hardware resources through software / firmware to adapt them to different channel scenarios.

[0101] Stable reception under dynamic channel conditions is not a problem that can be solved simply by increasing computing power; its core lies in implementing targeted real-time adjustments based on different types of channel changes. This disclosure achieves stable reception under dynamic channel conditions through a mechanism of "scenario determination—parameter adjustment—state maintenance—continuous tracking".

[0102] The dynamic channel stabilization reception process is as follows: 1: Receive satellite broadcast signals and generate symbol-level complex baseband data sequences; 2: Extract channel feature parameters based on synchronization correlation peak, noise variance, frequency offset estimate, equalization error, and LLR statistics; 3: The DSP identifies the current channel scenario based on channel characteristic parameters; 4. Determine the parameter adjustment strategy based on the identified channel scenario, such as selecting the target parameter from the preset parameter configuration table, or calculating the target parameter according to preset rules; 5: Write the target parameters into the configuration registers or coefficient storage areas corresponding to the NCO, digital low-pass filter, Farrow structure fractional delay interpolation filter, decimation filter, DFE equalizer and / or decoding unit; 6: The target parameters are made effective at symbol boundaries, frame boundaries, or preset processing window boundaries, and the continuity of carrier loop state, synchronization window position, DFE tap coefficients, and / or decoding state is maintained during parameter switching. 7: Continue monitoring the signal status of the next time window or the next frame, and repeat the above steps.

[0103] The on-chip control unit continuously monitors the processing status information of the next time window or the next frame signal, and extracts channel feature parameters based on the processing status information. When the channel feature parameters meet the preset scenario determination conditions, the current channel scenario is identified. Based on the identified current channel scenario, the on-chip control unit reads the corresponding target parameters from the preset parameter configuration table, or calculates the target parameters according to preset rules, and writes the target parameters into the configuration register or coefficient storage area of ​​the corresponding processing unit, so that subsequent received signals are processed according to the updated parameters.

[0104] For example, when the system detects an increase in frequency offset variation, it maintains carrier lock by updating the NCO frequency control word and adjusting the carrier loop parameters; the frequency offset variation is identified by the DSP or carrier synchronization control unit. The identification criteria include the phase change of adjacent synchronization correlation peaks, the phase rotation or phase error estimate in the Gold code coherent correlation results, the carrier loop error signal, and the NCO residual correction.

[0105] When the phase difference monotonically accumulates within multiple consecutive time windows, or when the carrier loop error exceeds a preset threshold, the system determines that there is an enhanced frequency offset change, and the DSP calculates a new NCO frequency control word and writes it into the NCO register to complete the frequency offset compensation.

[0106] When noise increase and correlation peak decrease are detected, synchronization robustness is improved by updating the dynamic threshold, appropriately increasing the correlation integral length, and narrowing the digital filter bandwidth. When equalization error increases and inter-symbol interference is enhanced, channel distortion is compensated by increasing equalizer taps, adjusting the step size, and updating filter coefficients. When sudden interference is detected, false alarms and missynchronization are reduced by enhancing multi-level verification and filtering strategies to suppress out-of-band noise. The NCO update method is as follows: the DSP calculates the frequency control word correction based on the residual frequency offset estimate and writes it to the NCO frequency control register.

[0107] The digital filter is updated as follows: the DSP selects the corresponding coefficients from the pre-stored filter coefficient table based on the noise variance, signal bandwidth and interference conditions, or calculates new filter coefficients and writes them into the filter configuration register.

[0108] The equalizer is updated as follows: the DFE coefficient update unit updates the tap coefficients of the forward filter and feedback filter using the LMS or RLS algorithm based on the current decision error; when the equalization error exceeds the threshold for a long time, the DSP can also adjust the number of taps and the update step size.

[0109] Furthermore, to avoid link oscillations caused by parameter changes themselves, this disclosure maintains the continuity of key state quantities within the chip, including DFE tap coefficients, carrier loop integration state, synchronization window position, and phase estimation results. This allows processing parameter adjustments to be made at symbol boundaries or at appropriate times, without having to re-complete the entire convergence process after each change. In other words, this disclosure does not "restart processing upon encountering a change," but rather performs gradual adjustments while maintaining link continuity, thereby improving reception stability in dynamic environments. Maintaining the continuity of key state quantities means that when adjusting parameters, the system does not clear or reset the original synchronization, carrier tracking, and equalization states, but rather smoothly updates the parameters based on the existing states. For example, when updating the NCO frequency control word, the carrier loop integrator state is retained; when adjusting the number or step size of DFE taps, existing tap coefficients are retained; when changing the synchronization integration length, the current synchronization window position and frame count state are retained.

[0110] In practice, the on-chip memory stores the carrier loop state, DFE tap coefficients, synchronization window position, phase estimation results, and decoding state. The DSP writes new parameters at symbol boundaries or frame boundaries to ensure a continuous link transition and avoid re-acquisition and re-convergence.

[0111] This disclosure does not rely on redefining a completely new dedicated ASIC chip, but rather on an existing commercial software-defined radio architecture satellite communication SoC chip platform. This chip platform already integrates modules such as RF front-end, ADC, digital processing resources, and DSP. Based on this, this disclosure introduces mechanisms such as channel scenario determination, adaptive filtering, adaptive synchronization, adaptive equalization, and adaptive decoding through software, firmware, and on-chip control logic reconstruction. In this way, the maturity and availability of the existing chip platform are preserved, while avoiding the development cycle, NRE costs, and tape-out failure risks associated with re-tape-out.

[0112] Among them, 1) Channel scenario determination mechanism: This mechanism is mainly implemented by the on-chip control unit through software or firmware, without the need for additional independent hardware modules.

[0113] The on-chip control unit receives status information output by the baseband processing module, including synchronization sequence correlation peak, peak-sidelobe ratio, noise floor estimate, residual frequency offset estimate, phase rotation speed, LLR statistics, DFE equalization error, and decoding status, and identifies the current channel scenario based on preset thresholds, rule tables, or parameter configuration tables.

[0114] 2) Adaptive filtering mechanism: This mechanism is implemented by a configurable hardware filtering unit and an on-chip control unit.

[0115] The corresponding hardware resources include: (1) Digital low-pass filter (LPF) in digital downconversion module; (2) Farrow structure fractional delay interpolation filter; (3) Decimation filter or anti-aliasing filter; (4) If supported by existing chip platform, tunable radio bandpass filter (RF BPF) in radio frequency front end may also be included.

[0116] The on-chip control unit selects or calculates filter parameters based on the channel scenario and writes the corresponding parameters into the filter configuration register or coefficient storage area. These parameters may include the cutoff frequency, filter order, and filter coefficients of a digital low-pass filter; the interpolation coefficients of a Farrow interpolation filter; and the cutoff frequency, filter order, and filter coefficients of a decimation filter, etc.

[0117] If the existing RF BPF in the RF front-end does not support dynamic configuration, then the RF bandpass filter will not be listed as a dynamic adjustment object of the DSP, and only the adaptive adjustment of the digital filtering part will be retained.

[0118] 3) Adaptive synchronization mechanism: This mechanism is jointly implemented by the frame synchronization unit in the baseband processing module and the on-chip control unit.

[0119] The corresponding hardware resources include: (1) Carrier synchronization code correlation operation unit; (2) Spreading code guide sequence correlation operation unit; (3) Unique code matching verification unit; (4) Noise-low statistics unit or related output statistics unit.

[0120] The on-chip control unit dynamically adjusts parameters such as the carrier synchronization code correlation decision threshold, the cumulative number of synchronization sequence correlations, the spread spectrum code search window range, the unique code correlation matching threshold, the maximum number of allowed bit errors, and the number of consecutive acknowledgments based on information such as the noise floor estimate, the peak value of the synchronization sequence correlation, and the peak-side lobe ratio.

[0121] If the aforementioned related operations are not configured with an independent hardware acceleration unit, the on-chip control unit can also perform the relevant calculations and parameter adjustments through software.

[0122] 4) Adaptive Equilibrium Mechanism This mechanism is jointly implemented by the decision feedback equalizer (DFE) in the baseband processing module and the on-chip control unit.

[0123] The corresponding hardware resources include: (1) DFE forward filter; (2) DFE feedback filter; (3) symbol decision unit; (4) error calculation unit; (5) coefficient update unit.

[0124] The on-chip control unit of the DSP can adjust the forward filter tap coefficients, feedback filter tap coefficients, number of taps, and coefficient update step size of the DFE according to the equalization error and the current channel scenario.

[0125] If the coefficient update unit in the existing chip supports LMS, RLS or their variants, the tap coefficient iterative update is performed by hardware; if the existing chip does not have independent coefficient update hardware, the on-chip control unit calculates the updated tap coefficients through software and writes them into the coefficient storage area of ​​the DFE.

[0126] 5) Adaptive decoding mechanism This mechanism is jointly implemented by the channel decoding unit and the on-chip control unit in the baseband processing module.

[0127] The corresponding hardware resources may include a Viterbi decoding acceleration unit or an error correction decoding unit that matches the system code pattern.

[0128] The on-chip control unit adjusts the soft information quantization accuracy, decoding backtracking integration length, and decoding resource configuration parameters based on channel conditions and LLR statistics. In high SNR stable scenarios, the intensity of decoding resource usage can be reduced to decrease computation and power consumption; in extremely low SNR weak signal scenarios, the soft information quantization accuracy can be increased, the decoding backtracking integration length can be extended, or more decoding resources can be enabled to improve error correction capabilities.

[0129] If the existing decoding unit does not support dynamic configuration of some of the above parameters, only the parameters that the chip can actually adjust will be retained.

[0130] 6) State maintenance and continuous tracking mechanism This mechanism is mainly implemented by the on-chip control unit and the on-chip storage unit through software or firmware collaboration.

[0131] The corresponding hardware resources include on-chip memory, configuration registers, and status registers. The on-chip memory is used to store carrier loop status, synchronization window position, DFE tap coefficients, filter coefficients, decoding status, and parameter configuration tables for different channel scenarios.

[0132] The on-chip control unit applies new parameters at symbol boundaries, frame boundaries, or preset processing window boundaries, while retaining existing state variables, thereby avoiding re-capture, re-convergence, or link interruption caused by parameter switching.

[0133] Among them, the RF front-end, ADC, NCO, digital filter, Farrow interpolation filter, decimation filter, DFE, correlation operation unit and decoding unit belong to the chip hardware resources; channel feature extraction, scene recognition, parameter selection, state maintenance and scheduling control are mainly implemented by the on-chip control unit executing software or firmware programs; on-chip memory is used to store parameter tables, filter coefficients, equalizer coefficients and state variables.

[0134] Unlike simple software upgrades, the upgrade target of this disclosure is the physical layer signal processing flow itself, that is, changing the working parameters and resource configuration of the underlying processing chain through software definition.

[0135] First, this disclosure extends the processing and control of satellite signals from the system level, board level, or application layer to the on-chip physical layer processing link, achieving real-time closed-loop control of synchronization, filtering, equalization, and decoding processes. Therefore, its innovation lies not merely in miniaturizing the system, but in constructing a real-time adaptive signal processing mechanism oriented towards the physical layer within the chip. The system directly acquires physical layer processing results within the chip, such as synchronization correlation peaks, noise variance, frequency offset estimation, equalization error, and LLR statistics, and adjusts physical layer processing parameters in real time based on these results, such as NCO control words, filter coefficients, synchronization integral length, DFE taps, and decoding parameters.

[0136] Therefore, the "closed loop" is reflected in the following: the physical layer processing result serves as the feedback input, the scheduling logic adjusts the subsequent physical layer processing parameters based on the feedback result, and the adjusted parameters continue to affect the physical layer processing result at the next moment.

[0137] Second, this disclosure abstracts the actual reception conditions of Fengyun-4 EWAIB into multiple typical channel scenarios and establishes parameter adjustment strategies for different scenarios. Compared with the traditional approach of handling all scenarios with a fixed process, this approach is more in line with the actual engineering application and can reduce resource consumption under stable channels and enhance processing capabilities under complex channels.

[0138] Third, this disclosure constructs a full-link adaptive filter system from analog front-end to digital baseband to equalizer, and implements it in detail at multiple levels such as hardware adjustable structure, digital filter parameters, interpolation extraction and equalization taps.

[0139] Fourth, this disclosure achieves a high receiving sensitivity of approximately -140dBm through the synergy of multiple technologies, including low-noise front-end, spread spectrum processing gain, multi-level correlation detection, dynamic integration, soft decision decoding, and adaptive equalization, which can meet the receiving requirements of weak signal and low-power terminals.

[0140] Fifth, this disclosure can maintain stable reception under dynamic channel conditions. Faced with scenarios such as frequency offset fluctuations, noise rise, multipath interference, and sudden interference, the system can achieve continuous tracking and stable demodulation through parameter adjustment and state maintenance mechanisms, reducing link interruptions and performance jitter.

[0141] Sixth, this disclosure is based on existing chip platforms and can be deployed without re-tape-out, significantly shortening the development cycle, reducing R&D costs and engineering risks, and has good productization and commercialization value. Unlike simple software upgrades, this disclosure targets the physical layer signal processing flow itself, that is, changing the operating parameters and resource configuration of the underlying processing chain through software definition. Therefore, this disclosure represents a structural technical improvement built on an existing chip platform, rather than a general functional update. This is also the innovative aspect of this disclosure compared to server solutions, board-based solutions, and traditional fixed-flow chip solutions.

[0142] Seventh, in addition to being used for receiving meteorological data and disaster early warning information, this disclosure can also be extended to support the reception of navigation enhancement information, and has good application extension capabilities.

[0143] Example 1: Unattended Meteorological Monitoring Terminal This disclosed chip is integrated into an automatic weather station terminal. The terminal receives broadcast signals from the Fengyun-4 satellite via an antenna. The chip internally performs RF reception, down-conversion, synchronization, despreading, demodulation, and decoding, and sends the acquired meteorological data and early warning information to a low-power MCU via an on-chip interface. The MCU fuses local sensor data with satellite regional forecast information to improve the terminal's predictive response capabilities to heavy rainfall, short-term strong winds, extreme temperatures, and other conditions.

[0144] In this scenario, the terminal typically operates in a stable environment for extended periods, but weather-related noise variations, local oscillator temperature drift, and partial signal blockage may still occur. Therefore, the system adjusts the filtering bandwidth, synchronization threshold, integration length, and equalization parameters based on the detected channel conditions. Under stable environmental conditions, the system maintains low resource consumption; when weak signals or increased noise occur, the system enhances weak signal detection and decoding capabilities. Since this disclosure can be implemented using existing chip platforms, there is no need to redesign dedicated chips, making it suitable for rapidly developing terminal products for unmanned stations.

[0145] Example 2: Communication Terminal for Low-Altitude Economic Unmanned Aerial Vehicles In UAV applications, antenna attitude changes, building obstructions, and ground reflections can more easily cause frequency offset fluctuations and multipath scene switching. This disclosed chip, embedded in the UAV communication module, can perceive changes in relevant peak, frequency offset, and equalization errors in real time. In this application, the UAV receives satellite broadcast signals from the Fengyun-4 satellite's EWAIB channel, which may include meteorological monitoring information, disaster warning information, and navigation enhancement information. The UAV terminal uses this signal to obtain regional meteorological, warning, or navigation assistance data to improve environmental awareness and navigation reliability during low-altitude flight. In the face of frequency offset and phase disturbance scenarios, the system dynamically corrects the NCO and carrier tracking parameters; in the face of multipath scenarios, the system enhances the equalizer compensation capability; in the face of short-term weak signal scenarios, the system extends the integration and enhances decoding processing. Since all these adjustments are performed on-chip, the response is faster, reducing interruption problems caused by scheduling lag in board or server solutions.

[0146] Example 3: Emergency Disaster Early Warning Receiving Terminal Emergency terminals are required to reliably receive critical broadcast information even in noisy and complex electromagnetic environments. This disclosure improves tolerance to sudden interference and low signal-to-noise ratio scenarios through dynamic thresholding, multi-level correlation verification, filter adaptation, and equalizer parameter reconfiguration. In emergency deployments, where terminals typically require rapid deployment in large numbers, the advantages of this disclosure based on existing chip platforms are even more pronounced, significantly reducing development and mass production barriers.

[0147] Example 4: Agricultural Internet of Things Terminal Agricultural IoT terminals are typically widely distributed, numerous, cost-sensitive, and reliant on battery or solar power. This disclosed chip enables agricultural nodes to receive satellite broadcast meteorological data and integrate it with local soil moisture, temperature, and humidity sensor data, supporting functions such as irrigation control, frost prevention, and disaster early warning. The terminal can receive meteorological monitoring information and can also be extended to receive navigation enhancement information to support agricultural machinery positioning and precision operations. Since this disclosure can be implemented on existing chip platforms without tape-out, it is more suitable for developing large-scale, low-cost agricultural IoT products.

[0148] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A satellite signal receiving chip system, wherein, include: RF front-end module, analog-to-digital conversion module, digital down-conversion module, baseband processing module, and on-chip control unit; The radio frequency front-end module is used to receive satellite radio frequency signals and perform front-end processing on the satellite radio frequency signals to output analog intermediate frequency signals; The analog-to-digital conversion module is used to perform analog-to-digital conversion on the analog intermediate frequency signal and output a digital intermediate frequency signal; The digital downconversion module is used to perform digital downconversion and decimation filtering on the digital intermediate frequency signal, and output a symbol-level complex baseband data sequence. The baseband processing module performs baseband processing on the symbol-level complex baseband data sequence and outputs the demodulated and decoded service data and baseband processing status information. The on-chip control unit identifies the current channel scenario based on the baseband processing status information output by the baseband processing module, and determines the parameter adjustment strategy based on the current channel scenario. The parameter adjustment strategy is used to adjust and store the underlying processing parameters for use by at least one of the RF front-end module, the digital down-conversion module, and the baseband processing module when processing subsequent input signals.

2. The system according to claim 1, wherein, The underlying processing parameters include at least one of the following: NCO frequency control word, digital low-pass filter parameters, Farrow interpolation coefficients, baseband synchronization and tracking parameters, synchronization correlation parameters, dynamic threshold, decision feedback equalizer parameters, and decoding parameters.

3. The system according to claim 1, wherein, The baseband processing module includes a frame synchronization unit, a spread spectrum despreading unit, a demodulation unit, and a channel decoding unit, which are used to sequentially perform synchronization, despreading, demodulation, and decoding on the symbol-level baseband complex data sequence, and recover the baseband processing of the service data.

4. The system according to claim 3, wherein, The frame synchronization unit adopts a three-level synchronization mechanism, namely: coarse synchronization detection based on carrier synchronization code, fine synchronization detection based on spreading code guide sequence, and frame header validity verification based on unique code.

5. The system according to claim 4, wherein, The frame synchronization unit employs a three-level synchronization mechanism, including: The received symbol-level complex baseband data sequence is correlated and matched point by point with the locally pre-stored carrier synchronization code to obtain coarse synchronization candidate positions; The spreading code search window is determined based on the coarse synchronization candidate positions; Within the spreading code search window, the received symbol-level complex baseband data sequence is correlated and matched with the locally pre-stored spreading code guide sequence to obtain the spreading code fine synchronization position; The unique code candidate position is determined based on the spread spectrum code fine synchronization position; Starting from the candidate unique code position, read a sequence of the same length as the locally predicted unique code from the symbol-level complex baseband data sequence, and perform correlation matching with the unique code to determine the effective frame header position.

6. The system according to any one of claims 3-5, wherein, The spread spectrum despreading unit performs correlation integration between the frame-synchronized symbol-level complex baseband data sequence and the locally predicted spreading code, wherein the on-chip control unit dynamically adjusts the integration length of the correlation integration according to the current channel scenario.

7. The system according to claim 6, wherein, The demodulation unit is used to output a decision information with confidence level for each bit of the symbol-level complex baseband data sequence after it has been spread and despread by the spreading and despreading unit.

8. The system according to any one of claims 1-5, 7, wherein, The digital downconversion module includes: a numerically controlled oscillator that generates a digital local oscillator signal based on the digital intermediate frequency signal; and an on-chip control unit that dynamically corrects the frequency control word of the numerically controlled oscillator based on the residual frequency offset estimate and phase compensation amount in the baseband processing status information.

9. The system according to claim 8, wherein, The frequency control word of the numerically controlled oscillator is dynamically corrected as follows: The baseband processing module estimates the residual frequency offset and the phase compensation amount; The on-chip control unit converts the residual frequency offset estimate into a correction value for the frequency control word and writes it into the configuration register of the numerically controlled oscillator; The numerically controlled oscillator generates a digital local oscillator signal in the next symbol period or the next processing window based on the frequency control word updated by the correction amount of the frequency control word. The digital mixer of the digital down-conversion module uses the digital local oscillator signal to perform complex mixing on the subsequent input signal to achieve carrier frequency offset compensation.

10. The system according to any one of claims 3-5, 7, wherein, The baseband processing module further includes a frequency offset and phase correction unit, which includes a residual frequency offset estimation unit, a phase error estimation unit, and a complex multiplier or a phase rotator. The residual frequency offset estimation unit obtains the residual frequency offset estimate based on the synchronization sequence in the frame header and / or the phase changes of multiple consecutive input signals; The phase error estimation unit obtains a phase deviation estimate based on the phase difference between the synchronization sequence and the input signal; wherein, the residual frequency offset estimate and the phase error estimate are used by the on-chip control unit to update the frequency control word and phase compensation amount of the numerically controlled oscillator; The complex multiplier or phase rotator uses the digital local oscillator signal and phase compensation amount to perform point-by-point rotation compensation on the symbol-level complex baseband data sequence after frame synchronization, so as to obtain the symbol-level complex baseband data sequence after frequency offset and phase correction, and input it into the subsequent spread spectrum despreading unit.

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