An ECL baseband switching device

Abstract

The application discloses an ECL baseband switching device, which comprises an input ECL level conversion unit, an ECL full cross-point chip, an output ECL level conversion unit and an MCU control unit; the ECL level conversion chip of each input channel converts external single-end ECL baseband signals into +PECL and -PECL differential signals and sends the signals into the ECL full cross-point chip in parallel; the internal signal channel of the ECL full cross-point chip is a straight-through structure, the signal is kept as a PECL differential analog signal in the whole process, and the signal is not sampled and digitized; the MCU control unit sends a register configuration word to the ECL full cross-point chip through a local configuration interface to complete path routing switching configuration. The signal channel is straight-through in the whole process, the jitter and phase offset introduced by digital switching are eliminated, the channel isolation degree is high, the time delay consistency is good, and the high-speed baseband interconnection requirement of a satellite ground station is met.

Description

Technical Field

[0001] This invention relates to the field of satellite ground station telemetry and control technology, specifically to an ECL baseband switching device. Background Technology

[0002] In integrated satellite communication, telemetry, tracking, and command (TT&C) and data transmission systems, the ECL baseband switching matrix undertakes core functions such as multi-channel baseband signal routing and scheduling, channel switching, and signal distribution. It can flexibly schedule baseband data streams from multiple terminals, significantly improving the integration of the baseband processing platform, the real-time performance of signal scheduling, and the flexibility of system expansion. ECL baseband signals are high-speed signals, and the switching process has strict requirements for signal integrity.

[0003] Currently, the industry's ECL baseband switching matrix mainly uses FPGA with level conversion chips to complete the switching: the ECL level conversion chip converts the ECL signal into a single-ended TTL signal, the TTL signal is sent to the FPGA to complete the switching function, and the FPGA outputs a TTL signal, which is then converted back into an ECL signal by the ECL level conversion chip for output. This solution offers flexible configuration and strong channel expansion capabilities.

[0004] However, the above scheme requires multi-level level conversion and digital domain processing of the signal, resulting in high signal delay, jitter, and poor channel isolation. The digital switching inside the FPGA also brings problems such as inconsistent channel delay and crosstalk between channels, which degrades the quality of high-speed ECL baseband signals. It is difficult to meet the application scenarios with strict signal integrity requirements, and it is also difficult to meet the use requirements of high-speed baseband interconnection of aerospace ground stations. Summary of the Invention

[0005] The technical problem to be solved by this invention is that in the existing ECL baseband switching matrix based on FPGA switching architecture, the signal needs to be converted at multiple levels and enter the digital domain to complete the switching, which easily introduces additional jitter and phase offset, and there are problems such as inconsistent channel delay and crosstalk between channels. Signal integrity is difficult to guarantee, and it is difficult to meet the stringent requirements of high-speed baseband interconnection of aerospace ground stations for signal quality.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: In a first aspect, an ECL baseband switching device is provided, comprising an input ECL level conversion unit, an ECL full crossover chip, an output ECL level conversion unit, and an MCU control unit. The input ECL level conversion unit includes multiple input channels, each configured with an ECL level conversion chip. Externally input ECL baseband signals are connected to the input terminal of the corresponding ECL level conversion chip. Each ECL level conversion chip converts the externally input ECL baseband signal into +PECL and -PECL differential signals for output. The PECL differential signals output from the multiple input channels are connected in parallel to the signal input port of the ECL full crossover chip. The ECL full crossover chip is a full crossover switch chip with a direct-through internal signal path. The signal remains a PECL differential analog signal throughout the entire process, without sampling or digitizing the signal. Internally, it implements multiple... The system comprises a full cross-connect matrix between input and multiple output channels. Based on configuration instructions, it routes the PECL differential signal from any input channel to one or more output ports. Channels selected for PECL differential signal routing without configuration instructions maintain high isolation. The output ECL level conversion unit includes multiple output channels, each configured with an ECL level conversion chip. Each output channel's ECL level conversion chip receives the PECL differential signal output from the corresponding output port of the ECL full cross-connect chip and converts it into a corresponding single-ended ECL signal for external output. The MCU control unit is connected to the configuration port of the ECL full cross-connect chip via a local configuration interface. The MCU control unit receives control commands, parses them, generates register configuration words, and sends them to the ECL full cross-connect chip via the local configuration interface, completing the channel routing switching configuration.

[0007] Specifically, the ECL full crosspoint chip integrates a receive equalization circuit, a transmit pre-emphasis circuit, and a 50Ω termination matching circuit.

[0008] Specifically, the signal bandwidth of the ECL full cross-point chip is DC to 4.25Gbps, and the inter-channel isolation is 35dB.

[0009] Specifically, the signal transmission links between the input ECL level conversion unit and the ECL full crosspoint chip, and between the ECL full crosspoint chip and the output ECL level conversion unit, are laid on a high-speed differential PCB. The high-speed differential PCB is equipped with differential impedance control and multi-stage power supply filtering circuits to suppress power supply noise.

[0010] Specifically, the MCU control unit also has an RJ45 Ethernet interface. The MCU control unit remotely receives control commands through the RJ45 Ethernet interface, which together with the local configuration interface constitutes two control methods: remote configuration and local configuration.

[0011] Specifically, the MCU control unit parses the control command to obtain channel routing configuration information, and generates the register configuration word based on the channel routing configuration information. The register configuration word represents the routing correspondence between input ports and output ports, with one input port corresponding to one or more output ports.

[0012] Specifically, before and after the channel routing switching configuration is completed, the signal path of the ECL full crosspoint chip maintains the straight-through architecture. Before and after the switching, the signal is transmitted in the form of PECL differential analog signal and does not enter the digital domain.

[0013] Specifically, the channel delay consistency of each signal channel shall not exceed ±15ps, and the single-channel delay jitter shall not exceed 22ps.

[0014] Specifically, the ECL baseband switching device provides a standard ECL differential interface to the outside world. The external interface is fully compatible with the ECL level. The ECL full crosspoint chip internally uses the PECL level to complete signal switching. The input ECL level conversion unit and the output ECL level conversion unit complete the level matching between the external ECL level and the internal PECL level.

[0015] Specifically, the number of input channels and the number of output channels can be 16, and the ECL full cross-point chip can be an ADN4604 chip.

[0016] The beneficial effects of this invention are: 1. Excellent signal integrity with minimal signal quality degradation. The signal path uses a direct-through architecture, eliminating digital domain sampling and reconstruction processing. It only undergoes one ECL-to-PECL and one PECL-to-ECL level conversion, eliminating additional jitter and digital noise introduced by digital logic and effectively reducing phase shift. Simultaneously, the full-crosspoint chip itself possesses high channel isolation, suppressing crosstalk between channels and ensuring good latency consistency across channels. This guarantees the high-speed ECL baseband signal transmission quality, meeting the stringent signal quality requirements of satellite ground stations. Since the signal never enters the digital domain, this solution avoids pipeline delay accumulation and synchronous switching noise caused by digital routing scheduling within the FPGA. This improves inter-channel latency consistency from ±80ps in traditional FPGA solutions to within ±15ps, and reduces single-channel latency jitter from ≤50ps to ≤22ps.

[0017] 2. Enables large-scale full cross-connect routing with strong interface compatibility. It adapts external ECL and internal PECL levels through input / output level conversion, providing a standard ECL differential interface for direct connection to external ECL baseband devices. It allows for full cross-connect switching from any input channel to any output channel, supporting one input to multiple outputs, meeting the flexible scheduling needs of multiple baseband signals.

[0018] 3. Reduces the difficulty of software and hardware development and debugging, and increases project feasibility. The core switching logic is implemented by the full cross-point chip hardware, eliminating the need to develop complex FPGA digital switching IPs, significantly reducing the workload of logic development and simulation debugging, shortening the development cycle, and making later troubleshooting and maintenance more convenient.

[0019] 4. Improved overall system stability. The reduced number of digital domain processing steps in the link avoids the timing anomaly risks caused by digital logic. Combined with high-speed differential PCB impedance control and multi-stage power supply filtering design, power supply noise interference is suppressed, improving the stability of the equipment in the complex electromagnetic environment of aerospace ground stations. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of an ECL baseband switching device provided in an embodiment of the present invention; The attached diagram shows: 1-Input ECL level conversion unit, 2-ECL full crosspoint chip, 3-Output ECL level conversion unit, and 4-MCU control unit. Detailed Implementation

[0021] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] like Figure 1 As shown, this embodiment provides an ECL baseband switching device, including an input ECL level conversion unit 1, an ECL full crosspoint chip 2, an output ECL level conversion unit 3, and an MCU control unit 4.

[0023] In this embodiment, the device has a total of 16 signal input channels, and each input channel is equipped with one ECL level conversion chip. That is, the input ECL level conversion unit 1 is composed of 16 ECL level conversion chips. The externally input single-ended ECL baseband signal is connected to the input terminal of the corresponding ECL level conversion chip; the ECL level conversion chip completes the level conversion, converting the externally input single-ended ECL baseband signal into a PECL differential signal, and outputs +PECL and -PECL differential pairs. All 16 PECL differential signals are sent in parallel to the signal input port of the ECL full crosspoint chip 2.

[0024] In this embodiment, the ECL full cross-point chip 2 uses the ADN4604 chip, which can complete 16×16 full switching. The signal bandwidth of the ECL full cross-point chip 2 is DC-4.25Gbps, the channel isolation is better than 35dB, the chip integrates receive equalization and transmit pre-emphasis functions, and integrates 50Ω termination matching on the chip. The ECL full cross-point chip 2 is the core switching device, and the internal signal path is a straight-through architecture. The signal is maintained as a PECL differential analog signal throughout the entire process, without sampling or digitization processing. The chip internally implements a 16-input × 16-output full cross-connect matrix, which can route any one input PECL differential signal to one or more output ports according to configuration instructions, realizing arbitrary cross-connection between input and output; unselected channels maintain a high isolation state to suppress channel crosstalk; the high isolation state of a channel indicates that the channel is disabled, the two ends are electrically isolated, and the two ends have high impedance to prevent bus collision or inter-domain interference.

[0025] The 16 output ports of the ECL full-crosspoint chip 2 output PECL differential signals. Each output port is connected to an output ECL level conversion chip, meaning that the output ECL level conversion unit 3 consists of 16 ECL level conversion chips. Each output ECL level conversion chip receives +PECL and -PECL differential signals, converts the PECL level back to a single-ended ECL signal, and outputs it to subsequent equipment.

[0026] The MCU control unit 4 has a local control interface and an RJ45 Ethernet interface. The MCU control unit 4 connects to the configuration port of the ECL full crosspoint chip 2 via the local configuration interface. The MCU control unit 4 receives control commands, parses them, generates register configuration words, and sends them to the ECL full crosspoint chip 2 via the local configuration interface to complete the channel routing switching configuration. Remote control can be achieved via the RJ45 Ethernet interface, forming two control methods—remote configuration and local configuration—to meet the integrated usage requirements of aerospace ground stations.

[0027] In this embodiment, the ECL baseband switching equipment adopts a symmetrical concentric circle layout: the ECL full crosspoint chip 2 is placed in the center of the PCB, and the 16 input ECL level conversion chips and 16 output ECL level conversion chips are evenly distributed in a ring around the outer circle of the PCB. The channel length constraint is implemented for all 16 input and 16 output high-speed differential signal traces to avoid the problem of large channel delay differences. The PCB periphery is the input and output physical interface, which adopts IPEX sockets. The IPEX sockets are placed as close as possible to the level conversion chips. High-speed differential signal lines are used from the level conversion chips to the switching chips to improve the isolation between channels and reduce crosstalk between channels.

[0028] The device features a direct signal path, preventing signals from entering the digital domain and avoiding the jitter and inconsistent channel delays introduced by the two-stage conversion in FPGA solutions. The external interface is fully compatible with ECL levels, while the chip internally uses PECL levels for switching, with level matching achieved through front and rear level conversion chips.

[0029] To verify the performance of this embodiment, a comparative test was conducted between the full cross-point chip solution and the FPGA solution. The test results are shown in the table below:

[0030] As can be seen from the table above, this embodiment outperforms the FPGA digital switching solution in terms of channel delay consistency, single-channel delay jitter, channel isolation, switching time, and signal bandwidth, and can meet the requirements of satellite ground stations for high-speed ECL baseband signal switching quality.

[0031] In addition, the PECL differential signal transmission link between the input ECL level conversion unit 1, the ECL full crosspoint chip 2, and the output ECL level conversion unit 3 is laid on a high-speed differential PCB for differential impedance control. It is also combined with multi-stage power supply filtering design to suppress power supply noise interference and improve the stability of the equipment in the complex electromagnetic environment of the aerospace ground station.

[0032] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An ECL baseband switching device, characterized in that, It includes an input ECL level conversion unit (1), an ECL full crosspoint chip (2), an output ECL level conversion unit (3), and an MCU control unit (4). The input ECL level conversion unit (1) includes multiple input channels. Each input channel is configured with an ECL level conversion chip. Externally input ECL baseband signals are connected to the input terminal of the corresponding ECL level conversion chip. Each ECL level conversion chip converts the externally input ECL baseband signals into +PECL and -PECL differential signals for output. The PECL differential signals output from the multiple input channels are connected in parallel to the signal input port of the ECL full crosspoint chip (2). The ECL full cross-point chip (2) is a full cross-switch chip with a direct-through internal signal path. The signal remains a PECL differential analog signal throughout the entire process, without sampling or digitization. It internally implements a full cross-matrix between multiple inputs and multiple outputs. According to the configuration command, it routes any input PECL differential signal to one or more output ports. The channel selected for PECL differential signal routing by non-configuration commands is kept in a high isolation state. The high isolation state of the channel indicates that the channel is disabled and has high impedance at both ends to prevent bus conflicts or inter-domain interference. The output ECL level conversion unit (3) includes multiple output channels. Each output channel is configured with an ECL level conversion chip. The ECL level conversion chip of each output channel is connected to the PECL differential signal output by the corresponding output port of the ECL full cross point chip (2) and converted into the corresponding single-ended ECL signal for external output. The MCU control unit (4) is connected to the configuration port of the ECL full cross-point chip (2) through the local configuration interface. The MCU control unit (4) receives the control command, parses it and generates a register configuration word, and sends it to the ECL full cross-point chip (2) through the local configuration interface to complete the channel routing switching configuration.

2. The ECL baseband switching device according to claim 1, characterized in that, The ECL full crosspoint chip (2) integrates a receive equalization circuit, a transmit pre-emphasis circuit, and a 50Ω terminal matching circuit.

3. An ECL baseband switching device according to claim 2, characterized in that, The signal bandwidth of the ECL full cross-point chip (2) is DC to 4.25Gbps, and the channel isolation is 35dB.

4. An ECL baseband switching device according to claim 1, characterized in that, The signal transmission links between the input ECL level conversion unit (1) and the ECL full cross-point chip (2), and between the ECL full cross-point chip (2) and the output ECL level conversion unit (3) are laid on a high-speed differential PCB. The high-speed differential PCB is equipped with differential impedance control and multi-stage power supply filtering circuits to suppress power supply noise.

5. An ECL baseband switching device according to claim 1, characterized in that, The MCU control unit (4) also has an RJ45 Ethernet interface. The MCU control unit (4) remotely receives control commands through the RJ45 Ethernet interface, which together with the local configuration interface constitute two control methods: remote configuration and local configuration.

6. An ECL baseband switching device according to claim 5, characterized in that, The MCU control unit (4) parses the control command to obtain channel routing configuration information, and generates the register configuration word according to the channel routing configuration information. The register configuration word represents the routing correspondence between the input port and the output port, and one input port corresponds to one or more output ports.

7. An ECL baseband switching device according to claim 1, characterized in that, Before and after the channel routing switching configuration is completed, the signal path of the ECL full crosspoint chip (2) maintains the straight-through architecture. Before and after the switching, the signal is transmitted in the form of PECL differential analog signal and does not enter the digital domain.

8. An ECL baseband switching device according to claim 1, characterized in that, The channel delay consistency of each signal channel shall not exceed ±15ps, and the single-channel delay jitter shall not exceed 22ps.

9. An ECL baseband switching device according to claim 1, characterized in that, The ECL baseband switching device also includes an external standard ECL differential interface. The external interface is fully compatible with ECL level. The ECL full crosspoint chip (2) uses PECL level to complete signal exchange. The input ECL level conversion unit (1) and the output ECL level conversion unit (3) complete the level matching between the external ECL level and the internal PECL level.

10. An ECL baseband switching device according to any one of claims 1 to 9, characterized in that, The number of input channels of the input ECL level conversion unit (1) and the number of output channels of the output ECL level conversion unit (3) are both 16.

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