An optical logic encoding method and system based on spatial position and topological charge, a terminal and a medium

Abstract

The application discloses an optical logic encoding method and system based on spatial position and topological charge, a terminal and a medium, and relates to the technical field of optical logic encoding. The method comprises the following steps: taking distinguishable spatial position states in an input light field as a first type of expandable information encoding freedom, taking distinguishable topological charge states of vortex light as a second type of expandable information encoding freedom, and combining the distinguishable spatial position states and the distinguishable topological charge states to form a multi-logic input state; inputting the input light field carrying the multi-logic input state to the same logic hologram to form a target light spot on an output detection surface; collecting the target light spot on the output detection surface, comparing integral light intensities of different judgment areas, and outputting corresponding binary logic operation results. Compared with a scheme that only relies on a single topological charge dimension or a fixed spatial position dimension, the application has the advantages of expandable position encoding capacity, high input variable distinguishability, strong logic function multiplexing capability, low crosstalk, high 0 / 1 judgment contrast, and stable logic output.

Description

Technical Field

[0001] This invention relates to the technical fields of optical computing, holographic optics, vortex light manipulation, multidimensional light field coding, and light field inverse design, and particularly to an optical logic coding method, system, terminal, and medium based on spatial position and topological charge. Background Technology

[0002] Optical logic operations utilize the propagation, interference, diffraction, holographic modulation, or nonlinear effects of light fields to implement Boolean logic functions. Compared with traditional electronic logic devices, optical logic operations have advantages such as fast propagation speed, high parallel processing potential, strong resistance to electromagnetic interference, and ease of integration with optical communication systems. Although existing optical logic systems can already implement some logic operations such as AND, OR, NOT, and XOR, most schemes are still designed for one or a few logic functions. When it is necessary to switch logic functions or increase the number of input variables, it is often necessary to replace the phase plate, change the hologram, adjust the optical path structure, or reconfigure the modulator. Therefore, the system's logic function reuse capability and scalability remain limited.

[0003] Vortex beams possess a helical phase structure due to their orbital angular momentum, and their topological charge number can serve as an important physical quantity for optical information encoding. Existing research has utilized the topological charge number of vortex beams in scenarios such as optical information transmission, pattern recognition, holographic multiplexing, and logical operations. In some vortex beam logic operation schemes, the logic input is typically represented by one or two vortex beams with different topological charges; that is, different input states are distinguished by different values ​​of the topological charge number, combinations of topological charges, or mode superposition relationships. This type of scheme demonstrates that the topological charge number can participate in optical logic encoding, but it essentially relies primarily on the same type of physical degree of freedom, namely orbital angular momentum or topological charge dimension, to represent multiple input variables. As the number of logic inputs or logic functions increases, relying solely on further expansion of the topological charge dimension leads to further increases in the difficulty of mode spacing, mode purity, energy balance, and output discrimination.

[0004] Spatial location can also serve as a degree of freedom for carrying optical information. Existing optical systems commonly employ methods such as spatial multiplexing, spot arrays, and multi-channel detection, which typically only assign different beams or outputs to different spatial locations. They do not systematically apply the idea that "the more spatial locations, the greater the encoding capacity" to encoding multi-input logical variables. In other words, while existing technologies can utilize spatial location for channel differentiation, they lack a universal encoding framework that maps multiple distinguishable spatial location states to one or more logical input variables and further combines them with topological charge states to construct multi-input logical states.

[0005] Furthermore, existing vortex optical logic operations are mostly designed with a single logic function or a small number of logic functions as the target, meaning that one optical operation usually corresponds to only one fixed logic rule. Even if certain logic functions can be switched by changing the incident light state or modulation parameters, the output structure is usually built around a single logic gate or a single output channel, making it difficult to simultaneously carry the input-output mapping relationship of multiple logic functions under the same holographic structure. For logic functions with three, four, or even more input variables, existing solutions are usually even more difficult to achieve stable multiplexing under the same input encoding rule and the same logic hologram.

[0006] Arrayed vortex optical fields can provide multiple independent or quasi-independent input positions in space, offering new possibilities for multi-channel optical logic operations. However, traditional vortex optical arrays are typically generated by analytical phase superposition, lens phase superposition, or spatial carrier methods. When the array size increases, or when different elements in the array need to maintain different topological charge states, analytical generation methods are prone to problems such as uneven sub-beam energy distribution, inaccurate topological charge maintenance, strong sidelobes, high crosstalk between adjacent channels, and dispersed peak energy. These problems directly affect the input quality of subsequent logic holograms, causing output spot diffusion, increased energy leakage in non-target areas, and consequently reducing the contrast of logic 0 / 1 judgments and increasing the risk of misjudgment.

[0007] Therefore, existing technologies still have the following shortcomings: First, existing vortex optical logic encoding mostly relies on topological charge number or similar mode parameters, lacking a general method to utilize spatial location multi-state encoding to carry one or more logical input variables; Second, existing spatial multiplexing methods mostly remain at the channel allocation level, failing to fully utilize the capacity relationship between the number of position states and the number of logical input states; Third, existing optical logic systems are mostly used to implement single or a few logic functions, lacking a scheme that can utilize spatial location scalable encoding combined with topological charge states to achieve multiplexing and parallel output of multiple input logic functions under the same holographic structure; Fourth, ordinary analytical vortex optical arrays are prone to energy unevenness and crosstalk under multi-position and multi-topological charge conditions, making it difficult to provide a stable and high-quality input light field for multifunctional logic holographic operations. Summary of the Invention

[0008] To address the aforementioned shortcomings of existing technologies, this invention provides an optical logic encoding method, system, terminal, and medium based on spatial location and topological charge number. This solves problems such as insufficient input variable discrimination, underutilization of position encoding capacity, limited number of logic input channels, difficulty in supporting multiple input logic functions within the same holographic structure, and susceptibility to crosstalk in multi-channel outputs in existing vortex optical logic operations. The technical solution adopted by this invention is as follows: In a first aspect, the present invention provides an optical logic encoding method based on spatial location and topological charge number, the method comprising: Within the logical input region, the distinguishable spatial position state in the input light field is used as the first type of scalable information encoding degree of freedom to encode the first set of binary logical input variables. The distinguishable topological charge state of the vortex light is used as the second type of scalable information encoding degree of freedom to encode the second set of binary logical input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form multiple logical input states. The input light field carrying the multiple logic input states is incident on the same logic hologram. After propagation by free space diffraction, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. Different logic input states are modulated by the same logic hologram and mapped to the corresponding determination regions in the output detection surface respectively. The system collects and outputs the target light spot in the corresponding judgment area of ​​the detection surface, and outputs the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

[0009] In one implementation, a single logical input region has K distinguishable spatial location states, and each spatial location corresponds to Q distinguishable topological load states. If binary logic encoding is performed solely based on distinguishable spatial location states, then the number of representable spatial location encoding input variables is: ,in, Indicates rounding down; If only binary logic encoding is performed using distinguishable topological load states, then the number of topological load encoding input variables that can be represented is: ; When spatial location encoding and topological load encoding are used for different input variables, the total number of binary logic input variables that the logic input region can represent is: .

[0010] In one implementation, the distinguishable spatial position states include any one or more of the following: left-right position, up-down position, two-dimensional grid position, ring distribution position, radial distribution position, angular sector position, and irregular addressable position; all spatial positions are addressable spatial regions that can be distinguished by the optical system. The distinguishable topological charge states include any one or more of the following: different positive integer topological charges, different negative integer topological charges, topological charges with opposite positive and negative values, topological charges with different absolute values, and other orbital angular momentum modes that can be distinguished by the optical system.

[0011] In one implementation, K = 2 distinguishable spatial location states and Q = 2 distinguishable topological load states are set, encoding a total of 2 binary logic input variables; wherein, the two distinguishable spatial location states correspond to the two logic states of the first input variable, and the two distinguishable topological load states correspond to the two logic states of the second input variable, and the two are combined to form 4 logic input states. K = 4 distinguishable spatial position states and Q = 2 distinguishable topological load states are set, encoding a total of 3 binary logic input variables. Among them, the four distinguishable spatial position states are arranged in a two-dimensional grid of upper left, upper right, lower left, and lower right. The horizontal position corresponds to the first input variable and the vertical position corresponds to the second input variable. The two distinguishable topological load states correspond to the third input variable. The two are combined to form 8 logic input states. K = 8 distinguishable spatial position states and Q = 2 distinguishable topological load states are set, encoding a total of 4 binary logic input variables. Among them, the eight distinguishable spatial position states are arranged in a 3×3 grid, with the central area set as an empty area, an isolation area, or a reference area. The eight distinguishable spatial position states correspond to 8 combination states of 3 binary input variables, and the distinguishable topological load states correspond to the fourth input variable. The two are combined to form 16 logic input states.

[0012] In one implementation, the mapping relationship of the logical hologram is preset according to the truth table of the target logical function, specifically including: The region in the output probe surface corresponding to the target logic function is divided into a first determination region and a second determination region, which correspond to logic output 0 and logic output 1, respectively. For any logical input state, if its corresponding logical output is 0, then after the input light field is modulated by the logical hologram, the light spot is mapped onto the first determination region. If the corresponding logic output is 1, then after the input light field is modulated by the logic hologram, the light spot is mapped to the second determination region.

[0013] In one implementation, the method further includes: Multiple independent logical input regions are set on the input surface. Each logical input region adopts a joint encoding method of spatial location and topological load. Different logical input regions correspond to different logical functions or different input channels of the same logical function. The input-output mapping relationship of all logical input regions is integrated into the same logical hologram to realize the arrayed parallel multiplexing operation of multiple logical functions. The input surface adopts a 6×6 vortex optical array space, which is divided into 16 logic input regions in a way that each pair of adjacent grid points is a group, corresponding to the 16 logic functions of standard two-input Boolean logic.

[0014] In one implementation, the input light field is a coherent light field, and the process of the input light field being incident on the same logical hologram and propagating through free space diffraction is modeled using the angular spectrum method, specifically including: The input light field is modulated by the phase modulation surface to form a complex amplitude light field. The output light field distribution after propagation distance is calculated by combining two-dimensional Fourier transform and inverse Fourier transform with the free space angular spectrum propagation transfer function. The modeling yields an optical field propagation model, which is used for the design of array-generated phase structures and the calculation of the optical field response of logic holograms to multiple logic input states. The phase structure generated by the array is produced using a reverse design, and the reverse design process includes: For each array position and each topological load state, a reference phase is constructed by superimposing the vortex phase, lens phase, and space carrier phase; Using the generated phase of the array to be optimized as a variable, the intensity matching error between the output light field and the target array, as well as the matching score between the output phase and the reference phase of each channel, are calculated based on the diffraction propagation model. The array generation phase is updated by iterative optimization algorithm so that the output array simultaneously meets the preset requirements in terms of spatial position accuracy, energy uniformity and topological charge retention accuracy, resulting in an optimized array generation phase plate.

[0015] Secondly, embodiments of the present invention also provide an optical logic encoding system based on spatial location and topological charge number, wherein the system is used to implement the steps of the optical logic encoding method based on spatial location and topological charge number as described in any of the above-mentioned schemes, and the system includes: The joint encoding module is used to encode the distinguishable spatial position state in the input light field as the first type of scalable information encoding degree of freedom within the logical input region, and to encode the first set of binary logic input variables. It also uses the distinguishable topological charge state of the vortex light as the second type of scalable information encoding degree of freedom, and to encode the second set of binary logic input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form multiple logical input states. The logic hologram modulation module is used to incident an input light field carrying the multiple logic input states onto the same logic hologram. After propagation through free space diffraction, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. After different logic input states are modulated by the same logic hologram, they are respectively mapped to the corresponding determination regions in the output detection surface. The logic operation result output module is used to collect the target light spot in the corresponding judgment area in the output detection surface, and output the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

[0016] Thirdly, embodiments of the present invention also provide a terminal, wherein the terminal includes a memory, a processor, and an optical logic encoding program based on spatial location and topological load number stored in the memory and executable on the processor. When the processor executes the optical logic encoding program based on spatial location and topological load number, it implements the steps of the optical logic encoding method based on spatial location and topological load number of any of the above schemes.

[0017] Fourthly, embodiments of the present invention also provide a computer-readable storage medium, wherein the computer-readable storage medium stores an optical logic encoding program based on spatial location and topological charge number, the optical logic encoding program based on spatial location and topological charge number implementing the steps of the optical logic encoding method based on spatial location and topological charge number as described in any of the above schemes on the computer-readable storage medium.

[0018] Beneficial Effects: Compared with existing technologies, this invention provides an optical logic encoding method based on spatial position and topological charge number. First, within the logic input region, the distinguishable spatial position states in the input light field are used as the first type of scalable information encoding degree of freedom to encode the first set of binary logic input variables. The distinguishable topological charge states of the vortex light are used as the second type of scalable information encoding degree of freedom to encode the second set of binary logic input variables. The distinguishable spatial position states and distinguishable topological charge states are combined to form multiple logic input states. Then, the input light field carrying the multiple logic input states is incident on the same logic hologram. After free-space diffraction propagation, a target light spot is formed in the corresponding decision region in the output detector surface. The logic hologram pre-stores the mapping relationship between all logic input states and decision regions. Different logic input states, after being modulated by the same logic hologram, are respectively mapped to the corresponding decision regions in the output detector surface. Finally, the target light spot in the corresponding decision region in the output detector surface is acquired. By comparing the integrated light intensity of different decision regions, the corresponding binary logic operation result is output.

[0019] This invention first elevates spatial position states to a scalable, expandable degree of freedom for information encoding, rather than simply treating spatial position as a beam channel or output location. Since two, four, eight, or more distinguishable spatial position states can be set within a single logical input region, the position state itself can carry multiple input states; as the number of spatial positions increases, the amount of information that can be encoded also increases. Based on this, topological charge states can be added as additional degrees of freedom to further expand the input dimension, enabling the same vortex beam input unit to represent the logical states of two, three, four, or even more input variables.

[0020] Compared to schemes that rely solely on topological charge number or similar pattern parameters to represent multiple input variables, this invention assigns logical input variables to degrees of freedom with different and independently controllable physical meanings, such as spatial location and topological charge. This improves the distinguishability between input states and reduces pattern confusion and recognition instability that may occur when multiple input variables are superimposed in the same dimension. Compared to schemes that only use fixed left and right positions for two-input encoding, this invention further reveals and protects the scalable encoding concept that "the more positions, the greater the position encoding capacity," allowing optical logic input to no longer be limited to a two-input structure.

[0021] Under this coding concept, a single logical input region can be mapped to different output detector surfaces through the same logical hologram, thereby completing the optical operation of a multi-input Boolean logic function. Further extending this basic unit to the array optical field space, multiple logical input states can correspond to different logic functions, realizing the reuse and parallel expansion of logic functions under the same logical hologram. Compared with traditional schemes that require frequent hologram switching or rebuilding of the optical path, this invention can switch between different logical input states simply by changing the position and topological charge states of the incident vortex light, exhibiting better reconfigurability, integration, and scalability. Attached Figure Description

[0022] Figure 1 This is a flowchart of a preferred embodiment of the optical logic encoding method based on spatial location and topological charge number according to an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram illustrating the overall concept of spatial position scalable coding and topological load joint coding in the optical logic coding method based on spatial position and topological load number according to an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of two-input, three-input, and four-input spatial position-topological load joint encoding embodiments in the optical logic encoding method based on spatial position and topological load number according to the present invention.

[0025] Figure 4 This is a flowchart illustrating the multi-logic input state and output determination process in the optical logic encoding method based on spatial location and topological charge number according to an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the spatial numbering and logical input area division of a 6×6 vortex optical array according to a preferred embodiment of the present invention.

[0027] Figure 6 This is a flowchart illustrating the preferred reverse design optimization process for generating the phase structure using an array in this invention.

[0028] Figure 7This is a flowchart illustrating the design process of implementing multiple inputs or multiple logic function operations using the same logic hologram in this invention.

[0029] Figure 8 This is an example diagram showing the output light intensity distribution corresponding to different logic input states AB=00, 01, 10, 11 in this invention.

[0030] Figure 9 This is a comparison diagram of the input and output of the optimized vortex optical array and the analytical vortex optical array in this invention.

[0031] Figure 10 This is a technical framework diagram of an optical logic coding system based on spatial location and topological charge number according to an embodiment of the present invention.

[0032] Figure 11 A schematic diagram of a terminal provided in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content, operations, or steps, nor does it require execution in the described order. For example, some operations or steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0035] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0036] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. For example, "first control information" and "second control information" are only used to distinguish different control information and do not limit their order.

[0037] Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or the order of execution, and that the words "first" and "second" do not necessarily imply that they are different.

[0038] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0039] The method in this embodiment can be applied to a terminal, which can be an intelligent electronic device such as a computer. Figure 1 As shown in the figure, the optical logic encoding method based on spatial location and topological charge number in this embodiment specifically includes the following steps: Step S100: Within the logic input region, the distinguishable spatial position state in the input light field is used as the first type of scalable information encoding degree of freedom to encode the first set of binary logic input variables. The distinguishable topological charge state of the vortex light is used as the second type of information encoding degree of freedom to encode the second set of binary logic input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form a multi-logic input state.

[0040] The core of this embodiment lies in using the distinguishable spatial position state in the input light field as the first type of scalable information encoding degree of freedom to encode the first set of binary logic input variables; simultaneously, using the distinguishable topological charge state of the vortex light as the second type of scalable information encoding degree of freedom to encode another set of binary logic input variables. These two are not simply mixed into a single input channel, but rather each undertakes the encoding function of different logic input variables. Finally, the combination of the spatial position state and the topological charge state forms a complete multi-logic input state, which is the joint encoded state of spatial position and topological charge, and is mapped to the corresponding output decision region by the same logic hologram.

[0041] Specifically, in combination Figure 2 As shown, suppose a logical input region has K distinguishable spatial position states, which can be denoted as:

[0042] in, Indicates the first An addressable spatial location = 1, 2, ..., K. The distinguishable spatial position states include any one or more of the following: left-right position, up-down position, two-dimensional grid position, ring distribution position, radial distribution position, angular sector position, and irregular addressable position (other addressable spatial regions that can be distinguished by the optical system); all spatial positions are addressable spatial regions that can be distinguished by the optical system. This invention does not limit the specific geometric arrangement of the spatial positions.

[0043] If binary logic encoding is performed solely based on distinguishable spatial location states, then the number of representable spatial location encoding input variables is: ,in, This represents the number of binary logic input variables that can be encoded by spatial location state. This indicates rounding down. Therefore, the larger the number of spatial location states K, the greater the amount of input information the location code itself can carry. For example: When K = 2, = 1, indicating that 2 positions can encode 1 binary input variable; When K = 4, = 2, indicating that 4 positions can encode 2 binary input variables; When K = 8, = 3 means that 8 positions can encode 3 binary input variables.

[0044] Furthermore, suppose that at each spatial location, there are also Q distinguishable topological load states to choose from, which can be denoted as:

[0045] in, Indicates the first A topological load state, = 1, 2, ..., Q. The distinguishable topological charge states are only required to be distinguishable from each other, including any one or more of different positive integer topological charges, different negative integer topological charges, topological charges with opposite signs, topological charges with different absolute values, and other orbital angular momentum modes that can be distinguished by the optical system. This invention does not limit them to being "high topological charge" or "low topological charge".

[0046] If only topological load states are used for binary logic encoding, then the maximum number of topological load encoding input variables that can be represented is:

[0047] in, This represents the number of binary logic input variables that can be encoded by the topological load state.

[0048] Therefore, when spatial location encoding and topological load encoding are used for different input variables, the maximum total number of binary logic input variables that this logic input region can represent is:

[0049] Right now:

[0050] in, This represents the total number of logical input variables jointly encoded by the spatial location state and the topological load state.

[0051] For any n-bit logic input vector, it can be split into a position-coded part and a topological load-coded part:

[0052] in, This represents a set of input variables encoded by spatial location state. This represents another set of input variables encoded by the topological load state.

[0053] Accordingly, two independent encoding mapping relationships can be established: Location encoding mapping:

[0054] Topological load encoding mapping:

[0055] Therefore, the complete optical input state can be represented as:

[0056] That is to say:

[0057] Therefore, each combination of logical input states can be represented by a combination of "spatial position state + topological load state". The key to this encoding method is that the spatial position state itself can expand the number of input channels as the number of positions increases, while the topological load state continues to increase the input dimension as an additional degree of freedom. Therefore, this invention does not limit the number of spatial position states to two, four, or eight, nor does it limit the spatial position arrangement to left-right, up-down, or nine-square grid; as long as multiple distinguishable spatial positions can independently encode a set of logical input variables and together with distinguishable topological load states to form a multi-input logical state, they all fall within the technical concept scope of this invention.

[0058] This invention does not limit the number of spatial position states, nor does it limit the geometric arrangement of the spatial position states. Spatial positions can be left-right positions, up-down positions, two-dimensional grid positions, circular distribution positions, radial distribution positions, angular sector positions, or irregular addressable positions; as long as different spatial positions can be distinguished by the optical system and pre-mapped to different logical input states, they all fall within the scope of spatial position encoding of this invention.

[0059] Combination Figure 3As shown, in the two-input implementation, two distinguishable spatial position states and two distinguishable topological load states can be set, i.e., K=2 distinguishable spatial position states and Q=2 distinguishable topological load states are set, encoding a total of 2 binary logic input variables. The two distinguishable spatial position states correspond to the two logic states of the first input variable (i.e., the first position state and the second position state), and the two distinguishable topological load states correspond to the two logic states of the second input variable (i.e., the first topological load state and the second topological load state). These two combinations form 4 logic input states. For example, this embodiment uses a logic input region as an example to illustrate the two-input implementation. This logic input region consists of two adjacent positions: the first position state represents A=0, and the second position state represents A=1; the first topological load state represents B=0, and the second topological load state represents B=1. Thus, the two position states and the two topological load states combine to form 4 logic input states, corresponding to AB=00, 01, 10, and 11, respectively. In subsequent steps, based on the truth table of the logic function to be implemented, the four input states are mapped to the first output decision area or the second output decision area respectively, thus realizing the optical operation of a two-input Boolean logic function.

[0060] In the three-input implementation, four distinguishable spatial position states and two distinguishable topological load states can be set. For example, the four spatial positions can be arranged as upper left, upper right, lower left, and lower right. That is, K=4 distinguishable spatial position states and Q=2 distinguishable topological load states are set, encoding a total of 3 binary logic input variables; wherein, the four distinguishable spatial position states are arranged in a two-dimensional grid of upper left, upper right, lower left, and lower right, the horizontal position corresponds to the first input variable, the vertical position corresponds to the second input variable, and the two distinguishable topological load states correspond to the third input variable, and the two combinations form 8 logic input states. For example, this embodiment sets four distinguishable spatial positions, such as upper left, upper right, lower left, and lower right. The horizontal position is used to represent the first input variable A, and the vertical position is used to represent the second input variable B; the first and second topological load states are used to represent the third logic input variable C. Thus, the four position states and the two topological load states combine to form 8 input states, corresponding to ABC=000 to 111 respectively. In subsequent steps, based on the truth table of the three-input logic function, typical logic operations such as three-input AND, three-input OR, three-input XOR, three-input majority voting function, or three-input conditional selection function can be implemented.

[0061] In the four-input implementation, eight distinguishable spatial position states and two distinguishable topological load states can be set. For example, the plane can be divided into a 3×3 grid area, with the central area designated as an empty area, an isolated area, or a reference area, and the eight outer positions used as valid spatial position states. That is, K=8 distinguishable spatial position states and Q=2 distinguishable topological load states are set, encoding a total of 4 binary logic input variables; among them, the eight distinguishable spatial position states are arranged in a 3×3 grid, with the central area set as an empty area, an isolated area, or a reference area, and the eight distinguishable spatial position states correspond to 8 combination states of 3 binary input variables, and the distinguishable topological load states correspond to the fourth input variable, and the two combine to form 16 logic input states. For example, in this embodiment, eight distinguishable spatial positions are set, and the eight valid positions correspond to eight combination states of three position encoded variables A, B, and C in a preset order; the first topological load state and the second topological load state are used to represent the fourth logic input variable D. Thus, the eight position states and the two topological load states combine to form 16 input states, corresponding to ABCD=0000 to 1111 respectively. The above two-input, three-input, and four-input encoding implementations are as follows: Figure 3 As shown. In subsequent steps, based on the truth table of the four-input logic function, typical logical operations such as four-input AND, four-input OR, four-input XOR, four-input parity check function, four-input threshold function, or four-input majority voting function can be implemented. It should be noted that the eight positions in this embodiment are not the only choice. This invention can also use sixteen positions, thirty-two positions, or other numbers of distinguishable spatial position states; when the number of position states is sufficient, more input variables can even be implemented mainly by spatial position encoding, with the topological load state serving as an optional additional degree of coding freedom.

[0062] It should be noted that four positions, eight positions, and a 3×3 grid are all preferred embodiments and do not constitute a limitation on the scope of protection of this invention. As the number of spatial positions increases, the position encoding capacity can be expanded, and the topological load, as an additional degree of freedom, further expands the input dimension. Those skilled in the art can set any number of distinguishable spatial position states based on the optical field modulator resolution, array size, number of output decision regions, and number of logic functions, and jointly encode them with any number of distinguishable topological load states.

[0063] Step S200: The input light field carrying the multiple logic input states is incident on the same logic hologram. After free space diffraction propagation, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. Different logic input states are modulated by the same logic hologram and mapped to the corresponding determination regions in the output detection surface, respectively.

[0064] For any n-input Boolean logic function F(X1,X2,…,Xn), the system first maps each input combination (i.e., multiple logic input states) to a spatial location-topological charge joint input state according to a preset mapping g. After passing through the same logic hologram, the input light field forms a target light spot on the output detector surface. The mapping relationship of the logic hologram in this embodiment is preset according to the truth table of the target logic function, specifically including: dividing the region corresponding to the target logic function in the output detector surface into a first determination region and a second determination region, corresponding to logic output 0 and logic output 1, respectively; for any logic input state, if its corresponding logic output is 0, the light spot is mapped to the first determination region after modulation by the logic hologram; if its corresponding logic output is 1, the light spot is mapped to the second determination region after modulation by the logic hologram.

[0065] For any input combination x = (x1, x2, ..., xn) of the logic function, if F(x) = 0, the target spot is set in the first decision region; if F(x) = 1, the target spot is set in the second decision region. In this way, the same logic hologram can map multiple logic input states to different decision regions according to the spatial position and topological charge state of the input light field, thus realizing the optical operation of the multi-input logic function.

[0066] In serial operation mode, the system activates only one logic input region and one spatial location-topological load input state at a time, thereby obtaining the logic output corresponding to that input combination. In parallel or multiplexed operation mode, the system can activate multiple logic input states simultaneously, allowing the same output probe surface to simultaneously provide the output results of multiple logic functions or multiple input channels. The multi-input logic holographic mapping and output determination process is as follows: Figure 4 As shown.

[0067] In a further array-based implementation, this embodiment can set multiple independent logical input regions on the input surface. Each logical input region adopts a joint encoding method of spatial location and topological load. Different logical input regions correspond to different logical functions, or to different input channels of the same logical function. The input-output mapping relationship of all logical input regions is integrated into the same logical hologram, realizing array-based parallel multiplexing of multiple logical functions. For the j-th logical input region, its corresponding logical function can be denoted as Fj(X1,X2,…,Xn). The system maps each input combination to the corresponding output decision region of the logical function according to the truth table of the logical function. In this way, multiple logical input states can be multiplexed under the same logical hologram; when multiple logical input states are activated simultaneously, the system can simultaneously provide the output results of multiple logical functions on the same output detection surface, thereby realizing array-based parallel multiplexing.

[0068] In a preferred embodiment, combined with Figure 5 As shown, Figure 5 Numbers 33, 34, 35, and 36 are reserved / vacant units and are not involved in logical grouping. The input surface adopts a 6×6 vortex optical array space, and starting from the upper left corner, it is divided into 16 logical input regions in groups of two adjacent grid points, corresponding to the 16 logic functions of standard two-input Boolean logic. However, this 6×6 array, 16 logical input regions, and specific numbering method are only one embodiment, and the present invention is not limited to this array size. Depending on the actual system size, spatial light modulator resolution, number of output detection regions, and number of logic functions, the present invention can also be extended to N×M arrays, non-uniform arrays, ring arrays, or other spatial arrangements.

[0069]

[0070] Where M represents the number of array columns; and They represent the first The row and column numbers of each array grid point. The above numbering method is only an example of row-priority numbering; column-priority numbering, circular numbering, partition numbering, or other addressable numbering methods can also be used.

[0071] In this embodiment, the input light field is a coherent light field. The input light field is incident on the same logical hologram, and its propagation process via free-space diffraction is modeled using the angular spectrum method. Specifically, the input light field is modulated by a phase modulation surface to form a complex amplitude light field. The output light field distribution after propagation distance is calculated by combining two-dimensional Fourier transform and inverse Fourier transform with the free-space angular spectrum propagation transfer function. In a preferred embodiment, the input light field can be confined by a circular aperture. Let the input plane coordinates be... If the aperture radius is R, then the input amplitude is... It can be represented as:

[0072] When the input light passes through the phase modulation surface, a complex amplitude optical field with a phase distribution is formed. If the phase loaded on the phase modulation surface is... The modulated light field is then:

[0073] The process of a light field propagating from a plane to a distance z can be described using the angular spectrum method, outputting the light field. It can be written as:

[0074]

[0075] in, and These represent the two-dimensional Fourier transform and the inverse Fourier transform, respectively. and The coordinates represent spatial frequency, where λ is the operating wavelength and k is the wave number. This is the free-space angular spectrum propagation transfer function, used to describe the diffraction evolution of the light field after propagation distance z. The resulting light field propagation model is used for the design of the phase structure generated by the array and for calculating the light field response of the logic hologram to multiple logic input states.

[0076] To improve the optical field quality of the aforementioned dual-dimensional encoded input, the array generation phase structure in this embodiment adopts a reverse design. The reverse design process includes: constructing a reference phase composed of the superposition of vortex phase, lens phase, and spatial carrier phase for each array position and each topological charge state; using the array generation phase to be optimized as a variable, calculating the intensity matching error between the output optical field and the target array, as well as the matching score between the output phase and the reference phase of each channel, based on the diffraction propagation model; updating the array generation phase through an iterative optimization algorithm, so that the output array simultaneously meets the preset requirements in terms of spatial position accuracy, energy uniformity, and topological charge retention accuracy, thereby obtaining the optimized array generation phase plate.

[0077] Specifically, in combination Figure 6 As shown, for the k-th array position and the s-th topological load state, the reference phase Can be determined by vortex phase Lens phase and space carrier phase composition:

[0078]

[0079]

[0080]

[0081] in, This represents the topological load number of the s-th topology. The angular phase function representing a regular vortex or a generalized vortex. Indicates the focal length of the lens. and Indicates the first The lateral spatial carrier parameters corresponding to each array position This represents the grating period. A conventional analytical array can be obtained by coherently superimposing the complex amplitudes of multiple channels and then taking the phase. However, as the array size increases and multiple topological charge channels are used, uneven intensity and channel crosstalk are easily generated. Therefore, this invention uses a reverse design framework based on a physical propagation model to optimize the array generation phase plate.

[0082] The phase to be optimized in the phase structure generated by the array is denoted as . Its output light field and predicted light intensity for:

[0083] in, {·} denotes the diffraction propagation operator with a propagation distance of z. Let represent the predicted light intensity at the target array surface. Assume the target array intensity is . and normalize its total energy to the input optical power. :

[0084] To make the output array closely approximate the target array in terms of spatial location and intensity distribution, a target region mask is defined. And a normalized intensity matching term is used:

[0085] Constraining only the output light intensity may ensure the correct spot position, but it cannot guarantee that each sub-beam maintains the desired topological charge structure. Therefore, this invention further introduces phase-correlation matching scores. .make Then the first The phase matching scores for each channel are:

[0086] The superscript * in the formula indicates complex conjugation. The closer the value is to 1, the better the current phase plate matches the corresponding position-topological load channel. To avoid some channels matching well while others match poorly, this invention introduces a low-score channel focusing weight:

[0087] in, For numerical stability parameters, This refers to the focus intensity coefficient for low-scoring channels. The above parameters can be preset or adjusted according to actual needs and are not limited to specific values. When a certain channel's... At lower levels, The weight of this channel is relatively large, therefore its weight in the phase optimization term is automatically increased, thus preventing low-match channels from being masked by the overall average objective function. The phase optimization objective can be written as:

[0088] in, The target phase matching score, Focus weights on low-scoring channels. Channel equalization weights are applied. Finally, the optimization objective function for generating the phase plate using the array is: in, and These are the weights for the intensity matching term and the phase matching term, respectively. Updated via gradient classes or other iterative optimizers. This allows the output array to simultaneously approach the target in terms of spatial location, energy distribution, and topological charge preservation. After optimization, an optimized array generating phase plate is obtained. This phase plate can be loaded into a spatial light modulator, or it can be further discretized to fabricate a pure phase diffraction optical element.

[0089]

[0090] when rise, Reduced, and each channel When the mean increases and the standard deviation decreases, it indicates that the array generates a phase structure that can simultaneously output a uniform, low-crosstalk, and topologically accurate vortex optical array.

[0091] It should be noted that this reverse design is a preferred implementation method, but not a necessary condition for the two-dimensional encoding logic of the present invention; the vortex optical array can also be generated by the analytical phase method, the spatial light modulator loading method, or the diffractive optical element preparation method.

[0092] In this embodiment, during the logic hologram design phase, the incident phase corresponding to different position-topological load encoding states is used as the input sample. For the m-th input sample, its incident phase is denoted as... The incident complex amplitude is:

[0093] The phase to be optimized in the logical hologram is denoted as... The input light field first propagates from the input phase plane to the logic hologram plane, then is modulated by the logic hologram, and finally propagates to the output detector plane. Its forward propagation process is as follows:

[0094]

[0095] For a single n-input logic function, construct 2 based on its truth table. n Group target output. Combined Figure 7As shown, in the implementation of multiple logic functions, different logic input regions and different input states together constitute training or design samples. For each input sample, a target output graph is constructed based on its corresponding logic function and the truth table result. and target mask If the truth table output is 0, the target spot is set in the first decision area of ​​the corresponding output group; if the truth table output is 1, the target spot is set in the second decision area.

[0096] The logical hologram in this embodiment can be obtained through conventional holographic design, iterative optimization, or reverse design based on a physical propagation model. In a preferred embodiment, the optimization objective of the logical hologram includes target graph matching terms. and background noise suppression term :

[0097] in, and These are preset weights for the target image matching term and the background noise suppression term, which can be set according to actual needs. After optimization, a single logical hologram is obtained. When operating serially, this hologram can perform selective operations on a multi-input logic function, and when operating in array multiplexing mode, it can simultaneously respond to multiple spatial location-topology load-encoded input states.

[0098] Step S300: Collect the target light spot in the corresponding judgment area in the output detection surface, and output the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

[0099] In this embodiment, the logical hologram is used to map different spatial location-topological charge input states to corresponding output detection regions. In a preferred embodiment, the system can also obtain an optimized array generation phase structure to generate a vortex light array with high uniformity and accurate topological charge preservation. During operation, the system starts from coherent light incidence, and proceeds through spatial location scalable encoding, optional topological charge joint encoding, logical holographic modulation, and output detection. Finally, the integrated light intensity of the output determination region is used as the criterion for determining whether the logical output is 0 or 1. Thus, the complete optical logic operation process from light field input to logical result output is completed.

[0100] Specifically, at the system output, the output detection surface is divided into several output decision groups. For the j-th output decision group, a first decision region Ωj,0 and a second decision region Ωj,1 are defined. Their integrated light intensities are respectively:

[0101] The logic output can be determined based on the magnitude of the integrated light intensity in the two decision regions:

[0102] To improve the stability of the judgment, a normalized discriminant coefficient can also be introduced:

[0103] when When the value is less than a preset negative threshold, it is determined to be 0. When the value is greater than the preset positive threshold, it is determined as 1; when When the light intensity is within the threshold range, peak intensity, centroid position, background energy, or signal-to-noise ratio can be used for auxiliary determination. Examples of input array and output light intensity distributions corresponding to different logic input states AB=00, 01, 10, and 11 are shown below. Figure 8 Show.

[0104] Furthermore, in practical applications, this embodiment can extend the single logic input region to the space of a vortex light array. The array size can be N×M, where N and M are integers greater than or equal to 2. Multiple logic input states can each employ the same or different numbers of spatial position states, and can correspond to different two-input, three-input, or four-input logic functions. After the design is completed, without changing the logic hologram, the switching of the corresponding logic function and input state can be achieved simply by changing the position state and topological charge state of the incident vortex light within the array region. When multiple logic input states are simultaneously incident on the same logic hologram, the output detection surface can simultaneously provide the output results of multiple logic functions.

[0105] To improve the array input quality, this embodiment further employs a reverse design framework based on a physical propagation model to optimize the phase structure generated by the vortex optical array. Coherent incident light is irradiated onto the phase structure to be optimized, and after free-space diffraction propagation, a vortex optical array is formed on the target plane. During optimization, the phase structure is treated as the variable to be optimized, and the target array light intensity, the target spatial position-topological charge reference phase structure, and channel equalization requirements are all incorporated into the optimization objective function. After optimization, an optimized array generation phase map is obtained, which can be used for loading spatial light modulators or fabricating diffractive optical elements.

[0106] Under the same logical hologram, the same input encoding method, and the same output determination method, reverse-engineered optimized vortex optical arrays and ordinary analytical vortex optical arrays were used as inputs, respectively. For example... Figure 9 As shown, Figure 9The top left of the image represents the optimized array input, the top right represents the optimized array output, the bottom left represents the analytical array input, and the bottom right represents the analytical array output. Comparison results show that the optimized vortex array results in a more concentrated output spot, higher light intensity in the target area, lower crosstalk in non-target areas, higher 0 / 1 contrast, and lower risk of logical misjudgment. Therefore, this embodiment demonstrates that the key to this invention lies not only in using a vortex array for logical operations, but also in establishing multi-input logical states through spatially scalable coding and topological charge joint coding, and in improving the stability of this coding system in holographic output by combining the optimized array method.

[0107] Compared with existing technologies, the advantages of this invention are as follows: Firstly, this invention elevates spatial position states to a scalable degree of freedom for information encoding, rather than simply treating spatial position as a beam channel or output location. Since two, four, eight, or more distinguishable spatial position states can be set within a single logical input region, the position state itself can carry multiple input states; as the number of spatial positions increases, the amount of information that can be encoded also increases. Based on this, topological charge states can be used as additional degrees of freedom to further expand the input dimension, enabling the same vortex beam input unit to represent the logical states of two, three, four, or even more input variables.

[0108] Compared to schemes that rely solely on topological charge number or similar pattern parameters to represent multiple input variables, this invention assigns logical input variables to degrees of freedom with different and independently controllable physical meanings, such as spatial location and topological charge. This improves the distinguishability between input states and reduces pattern confusion and recognition instability that may occur when multiple input variables are superimposed in the same dimension. Compared to schemes that only use fixed left and right positions for two-input encoding, this invention further reveals and protects the scalable encoding concept that "the more positions, the greater the position encoding capacity," allowing optical logic input to no longer be limited to a two-input structure.

[0109] Under this coding concept, a single logical input region can be mapped to different output detection regions through the same logical hologram, thereby completing the optical operation of a multi-input Boolean logic function. Further extending this basic unit to the array light field space, multiple logical input regions can correspond to different logic functions, realizing the reuse and parallel expansion of logic functions under the same logical hologram. Compared with traditional schemes that require frequent hologram switching or rebuilding of the optical path, this invention can switch between different logical input states simply by changing the position and topological charge states of the incident vortex light, exhibiting better reconfigurability, integration, and scalability.

[0110] Since spatial location scalable coding and topological charge joint coding simultaneously introduce composite optical fields with multiple spatial frequencies, spatial locations, and topological charge modes, ordinary analytical arrays or simple phase superposition methods are prone to energy unevenness, mode crosstalk, and energy leakage in non-target regions under multi-channel conditions. As a preferred embodiment, this invention can optimize the array generation phase structure and logic hologram through reverse design based on the physical propagation model, enabling the input vortex optical array to have higher energy uniformity, more accurate topological charge preservation capability, and lower channel crosstalk. This results in a more concentrated target output spot, a more obvious contrast between logic 0 and 1 light intensity, and more stable judgment results, thereby reducing the risk of logic misjudgment.

[0111] Based on the above embodiments, the present invention also provides an optical logic encoding system based on spatial location and topological charge number, the system being used to implement the steps in the above method embodiments. Specifically, as Figure 10 As shown, the system includes: a joint encoding module 10, a logic hologram modulation module 20, and a logic operation result output module 30. Specifically, the joint encoding module 10 is used to encode the distinguishable spatial position state in the input light field as a first type of scalable information encoding degree of freedom within the logic input region, and to encode a first set of binary logic input variables. It also uses the distinguishable topological charge state of the vortex light as a second type of scalable information encoding degree of freedom, and to encode a second set of binary logic input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form multiple logic input states. The logic hologram modulation module 20 is used to incident the input light field carrying the multiple logic input states onto the same logic hologram. After free-space diffraction propagation, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. Different logic input states, after being modulated by the same logic hologram, are respectively mapped to the corresponding determination regions in the output detection surface. The logic operation result output module 30 is used to collect the target light spot in the corresponding judgment area in the output detection surface, and output the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

[0112] The principles of each module in the optical logic coding system based on spatial location and topological charge number in this embodiment are the same as the implementation process of each step in the above method embodiment, and will not be elaborated further here.

[0113] Based on the above embodiments, the present invention also provides a terminal, the principle block diagram of which can be as follows: Figure 11 As shown. The terminal may include one or more processors 100 ( Figure 11(Only one is shown in the diagram), memory 101, and computer program 102 stored in memory 101 and executable on one or more processors 100. For example, an optical logic encoding program based on spatial location and topological load number. When one or more processors 100 execute computer program 102, they can implement the various steps in the embodiment of the optical logic encoding method based on spatial location and topological load number. Alternatively, when one or more processors 100 execute computer program 102, they can implement the functions of various modules / units in the embodiment of the optical logic encoding apparatus based on spatial location and topological load number, which is not limited here.

[0114] In one embodiment, the processor 100 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0115] In one embodiment, memory 101 can be an internal storage unit of the terminal, such as a hard disk or RAM. Memory 101 can also be an external storage terminal of the terminal, such as a plug-in hard disk, smart media card (SM), secure digital card (SD), flash card, etc., all equipped on the terminal. Furthermore, memory 101 can include both internal and external storage units. Memory 101 is used to store computer programs and other programs and data required by the terminal. Memory 101 can also be used to temporarily store data that has been output or will be output.

[0116] Those skilled in the art will understand that Figure 11 The block diagram shown is merely a partial structural diagram related to the present invention and does not constitute a limitation on the terminal to which the present invention is applied. A specific terminal may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0117] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct memory bus RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An optical logic encoding method based on spatial location and topological charge number, characterized in that, The method includes: Within the logical input region, the distinguishable spatial position state in the input light field is used as the first type of scalable information encoding degree of freedom to encode the first set of binary logical input variables. The distinguishable topological charge state of the vortex light is used as the second type of scalable information encoding degree of freedom to encode the second set of binary logical input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form multiple logical input states. The input light field carrying the multiple logic input states is incident on the same logic hologram. After propagation by free space diffraction, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. Different logic input states are modulated by the same logic hologram and mapped to the corresponding determination regions in the output detection surface respectively. The system collects and outputs the target light spot in the corresponding judgment area of ​​the detection surface, and outputs the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

2. The optical logic encoding method based on spatial location and topological charge number according to claim 1, characterized in that, A single logical input region has K distinguishable spatial location states, and each spatial location corresponds to Q distinguishable topological load states; If binary logic encoding is performed solely based on distinguishable spatial location states, then the number of representable spatial location encoding input variables is: ,in, Indicates rounding down; If only binary logic encoding is performed using distinguishable topological load states, then the number of topological load encoding input variables that can be represented is: ; When spatial location encoding and topological load encoding are used for different input variables, the total number of binary logic input variables that the logic input region can represent is: .

3. The optical logic encoding method based on spatial location and topological charge number according to claim 2, characterized in that, The distinguishable spatial position states include any one or more of the following: left-right position, up-down position, two-dimensional grid position, ring distribution position, radial distribution position, angular sector position, and irregular addressable position; all spatial positions are addressable spatial regions that can be distinguished by the optical system. The distinguishable topological charge states include any one or more of the following: different positive integer topological charges, different negative integer topological charges, topological charges with opposite positive and negative values, topological charges with different absolute values, and other orbital angular momentum modes that can be distinguished by the optical system.

4. The optical logic encoding method based on spatial location and topological charge number according to claim 3, characterized in that, K = 2 distinguishable spatial location states and Q = 2 distinguishable topological load states are set, encoding a total of 2 binary logic input variables; wherein, the two distinguishable spatial location states correspond to the two logic states of the first input variable, and the two distinguishable topological load states correspond to the two logic states of the second input variable, and the two are combined to form 4 logic input states. K = 4 distinguishable spatial position states and Q = 2 distinguishable topological load states are set, encoding a total of 3 binary logic input variables. Among them, the four distinguishable spatial position states are arranged in a two-dimensional grid of upper left, upper right, lower left, and lower right. The horizontal position corresponds to the first input variable and the vertical position corresponds to the second input variable. The two distinguishable topological load states correspond to the third input variable. The two are combined to form 8 logic input states. K = 8 distinguishable spatial position states and Q = 2 distinguishable topological load states are set, encoding a total of 4 binary logic input variables. Among them, the eight distinguishable spatial position states are arranged in a 3×3 grid, with the central area set as an empty area, an isolation area, or a reference area. The eight distinguishable spatial position states correspond to 8 combination states of 3 binary input variables, and the distinguishable topological load states correspond to the fourth input variable. The two are combined to form 16 logic input states.

5. The optical logic encoding method based on spatial location and topological charge number according to claim 1, characterized in that, The mapping relationship of the logical hologram is preset according to the truth table of the target logical function, specifically including: The region in the output probe surface corresponding to the target logic function is divided into a first determination region and a second determination region, which correspond to logic output 0 and logic output 1, respectively. For any logical input state, if its corresponding logical output is 0, then after the input light field is modulated by the logical hologram, the light spot is mapped onto the first determination region. If the corresponding logic output is 1, then after the input light field is modulated by the logic hologram, the light spot is mapped to the second determination region.

6. The optical logic encoding method based on spatial location and topological charge number according to claim 1, characterized in that, The method further includes: Multiple independent logical input regions are set on the input surface. Each logical input region adopts a joint encoding method of spatial location and topological load. Different logical input regions correspond to different logical functions or different input channels of the same logical function. The input-output mapping relationship of all logical input regions is integrated into the same logical hologram to realize the arrayed parallel multiplexing operation of multiple logical functions. The input surface adopts a 6×6 vortex optical array space, which is divided into 16 logic input regions in a way that each pair of adjacent grid points is a group, corresponding to the 16 logic functions of standard two-input Boolean logic.

7. The optical logic encoding method based on spatial location and topological charge number according to claim 1, characterized in that, The input light field is a coherent light field. The process of the input light field being incident on the same logical hologram and propagating through free space diffraction is modeled using the angular spectrum method, specifically including: The input light field is modulated by the phase modulation surface to form a complex amplitude light field. The output light field distribution after propagation distance is calculated by combining two-dimensional Fourier transform and inverse Fourier transform with the free space angular spectrum propagation transfer function. The modeling yields an optical field propagation model, which is used for the design of array-generated phase structures and the calculation of the optical field response of logic holograms to multiple logic input states. The phase structure generated by the array is produced using a reverse design, and the reverse design process includes: For each array position and each topological load state, a reference phase is constructed by superimposing the vortex phase, lens phase, and space carrier phase; Using the generated phase of the array to be optimized as a variable, the intensity matching error between the output light field and the target array, as well as the matching score between the output phase and the reference phase of each channel, are calculated based on the diffraction propagation model. The array generation phase is updated by iterative optimization algorithm so that the output array simultaneously meets the preset requirements in terms of spatial position accuracy, energy uniformity and topological charge retention accuracy, resulting in an optimized array generation phase plate.

8. An optical logic coding system based on spatial location and topological charge number, characterized in that, The system is used to implement the steps of the optical logic encoding method based on spatial location and topological charge number as described in any one of claims 1-7, and the system includes: The joint encoding module is used to encode the distinguishable spatial position state in the input light field as the first type of scalable information encoding degree of freedom within the logical input region, and to encode the first set of binary logic input variables. It also uses the distinguishable topological charge state of the vortex light as the second type of scalable information encoding degree of freedom, and to encode the second set of binary logic input variables. The distinguishable spatial position state and the distinguishable topological charge state are combined to form multiple logical input states. The logic hologram modulation module is used to incident an input light field carrying the multiple logic input states onto the same logic hologram. After propagation through free space diffraction, a target light spot is formed in the corresponding determination region in the output detection surface. The logic hologram pre-stores the mapping relationship between all logic input states and determination regions. After different logic input states are modulated by the same logic hologram, they are respectively mapped to the corresponding determination regions in the output detection surface. The logic operation result output module is used to collect the target light spot in the corresponding judgment area in the output detection surface, and output the corresponding binary logic operation result by comparing the integrated light intensity of different judgment areas.

9. A terminal, characterized in that, The terminal includes a memory, a processor, and an optical logic encoding program based on spatial location and topological load number stored in the memory and executable on the processor. When the processor executes the optical logic encoding program based on spatial location and topological load number, it implements the steps of the optical logic encoding method based on spatial location and topological load number as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an optical logic encoding program based on spatial location and topological charge number, the optical logic encoding program based on spatial location and topological charge number implementing the steps of the optical logic encoding method based on spatial location and topological charge number as described in any one of claims 1-7 on the computer-readable storage medium.

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