FPGA and DSP anti-interference transmission method based on SRIO doorbell interrupt

Abstract

The application belongs to the technical field of high-speed embedded heterogeneous system data transmission, and discloses an FPGA and DSP anti-interference transmission method based on an SRIO doorbell interrupt, wherein the doorbell interrupt of the SRIO protocol is used to replace the hardware pin interrupt, and the false interrupt caused by level jitter and electromagnetic interference is eliminated by means of the data packet encapsulation and frame check slave mechanism of the protocol layer, the count difference of the FPGA end doorbell counter and the DSP end interrupt counter is compared to realize real-time detection of the link frame loss abnormal state, the method has the characteristics of simple structure, strong anti-interference ability and high transmission reliability, and is suitable for the heterogeneous collaborative processing scene of the FPGA and the DSP in the complex electromagnetic environment such as industrial measurement and control and high-speed data acquisition.

Description

Technical Field

[0001] This invention belongs to the field of high-speed embedded heterogeneous system data transmission technology, and specifically relates to an anti-interference transmission method for FPGA and DSP based on SRIO doorbell interrupt. Background Technology

[0002] Traditional EMIF buses consume a large number of FPGA I / O pins and have low transmission rates. In contrast, SRIO (Serial RapidIO) is a highly reliable, high-performance, packet-switched next-generation high-speed interconnect technology for embedded systems, using high-speed differential serial signal transmission at its physical layer. The SRIO protocol supports scalable topologies and multi-point interconnects with fewer pins, making it suitable for high-speed data exchange between chips, boards, and between chips and boards. With its low power consumption, low pin footprint, high bandwidth, and high reliability, SRIO has been widely used in serial backplane interconnects, DSP interconnects, and data plane interconnects.

[0003] In embedded heterogeneous systems using DSPs and FPGAs, data interaction typically relies on hardware pin interrupts in conjunction with a high-speed serial bus. In actual circuits, signal level jitter can easily trigger false interrupts, leading to data reading errors. At the link layer, high-speed transmission lacks reliable synchronization verification methods; once a frame is lost, both the sender and receiver lose synchronization, affecting system reliability. The complex buffer architecture introduced in traditional designs to ensure transmission quality also complicates the software layer and reduces real-time response performance.

[0004] Therefore, there is an urgent need in the existing technology for an FPGA-DSP communication method that can effectively avoid false triggering of hardware interrupts, detect data frame loss in real time, and simplify the system architecture. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an anti-interference transmission method for FPGA and DSP based on SRIO doorbell interrupts. This method utilizes the doorbell interrupt of the SRIO protocol to replace traditional hardware pin interrupts, fundamentally eliminating the problem of false interrupt triggering caused by level jitter and electromagnetic interference. Simultaneously, by comparing the difference between the doorbell counter and the interrupt counter, it eliminates the need to send additional dedicated link detection data packets, achieving real-time monitoring and fault warning of SRIO link frame loss. This simplifies the implementation architecture while significantly improving the anti-interference capability and reliability of the transmission.

[0006] To achieve the above objectives, this invention employs an FPGA and DSP anti-interference transmission method based on SRIO doorbell interrupts, specifically including the following steps:

[0007] Step S1: The FPGA acquires the current doorbell counter value and encapsulates the count value and the user data to be transmitted into an SRIO data packet;

[0008] Step S2: The FPGA sends a doorbell transaction packet to the DSP via the SRIO protocol to notify the DSP that the data is ready, and after sending the SRIO doorbell transaction packet, the doorbell counter performs an auto-increment operation.

[0009] Step S3: The DSP responds to the received doorbell interrupt, causes the interrupt counter to increment, and reads the SRIO data packet containing the count value and user data stored on the FPGA through an SRIO read transaction.

[0010] Step S4: The DSP parses the received SRIO data packet, extracts the count value, and calculates the difference between the current value of the interrupt counter and the extracted count value;

[0011] Step S5: If the difference is equal to the preset value, the SRIO link transmission is determined to be normal, and subsequent data processing is performed; if the difference is not equal to the preset value, the SRIO link is determined to have a frame loss anomaly, the currently received data packet is discarded, and a link fault alarm signal is output.

[0012] Furthermore, the SRIO read transaction mentioned in step S3 specifically refers to the DSP reading the SRIO data packet from the FPGA through an NREAD transaction.

[0013] Furthermore, the initial value of the doorbell counter is 0. During each round of data transmission, the current value of the doorbell counter before its increment is read during packet assembly and written into the data packet. After packet assembly, the FPGA initiates the doorbell transaction, at which point the doorbell counter performs its increment operation. Therefore, the doorbell counter value read from the SRIO data packet by the DSP in this transmission actually corresponds to the counter state of the FPGA after the previous transmission, and differs from the current reception count recorded by the DSP's interrupt counter by 1. Based on this, by determining whether the difference between the DSP's interrupt counter and the received doorbell counter value is 1, it is possible to detect whether there is frame loss in this transmission.

[0014] The beneficial effects of this invention are as follows:

[0015] (1) The present invention replaces the traditional hardware interrupt that relies on the rising or falling edge transition of the external GPIO pin with a doorbell interrupt, avoiding false triggering caused by external signal jitter and improving the anti-interference capability and stability of the system.

[0016] (2) The present invention sets a doorbell counter and an interrupt counter at both ends of the FPGA and DSP respectively. By comparing the difference of the count values ​​in real time in the interrupt handling function, the link status monitoring and fault alarm can be realized, which can effectively detect the frame loss problem caused by link abnormality. Attached Figure Description

[0017] The accompanying drawings are used to provide a further understanding of the technical solutions of this application or the prior art, and constitute a part of the specification. The drawings illustrating embodiments of this application, together with the embodiments of this application, are used to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0018] Figure 1 This is a flowchart illustrating an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the doorbell transaction packet structure sent from the FPGA to the DSP according to an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the data flow interaction between the FPGA and DSP in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the NREAD response data packet structure returned by the FPGA to the DSP according to an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the NREAD response data packet structure received by the DSP in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the NWRITE transaction data packet structure written from the DSP to the FPGA according to an embodiment of the present invention. Detailed Implementation

[0024] The present invention will be further illustrated below with reference to specific embodiments.

[0025] Figure 1 This is a flowchart illustrating an embodiment of the present invention. In this embodiment, the data generator inside the FPGA increments the base N at a frequency of 10kHz and sends the generated 12 64-bit data words to the sending module. The first 11 words are test data with values ​​of N, N+1, ..., N+10 in sequence, and the 12th word is the doorbell counter value used to record the number of doorbell packet transmissions. Subsequently, the DSP receives the data and performs algorithm processing. This embodiment uses the example of the DSP writing data back to the FPGA via an NWRITE transaction for illustration, but the algorithms that the DSP can execute are not limited to this example.

[0026] Figure 2This is a schematic diagram of the doorbell transaction packet structure sent from the FPGA to the DSP in an embodiment of the present invention. The signal value sent by the FPGA SRIO IP core request interface (ireq) is hexadecimal 00a0200000000000, and the count value of the doorbell counter is decimal 1373524.

[0027] Figure 3 This is a schematic diagram of the data flow interaction between the FPGA and DSP in an embodiment of the present invention, illustrating the process of alternating execution of NREAD and NWRITE transactions during data interaction.

[0028] Figure 4 This is a schematic diagram of the NREAD response data packet structure returned by the FPGA to the DSP in an embodiment of the present invention. Taking N=2 as an example, the data value sent by the FPGA-side SRIO IP core response interface (resp) is an integer that increases sequentially from decimal 2 to 12, and the current count value of the doorbell counter is 1.

[0029] Figure 5 This is a schematic diagram of the NREAD response data packet structure received by the DSP in an embodiment of the present invention. The data value received by the DSP is consistent with the data sent by the FPGA, and the current value of the interrupt counter on the DSP minus the count value in the data packet equals 1, which is in line with the theoretical expectation.

[0030] Figure 6 This is a schematic diagram of the NWRITE transaction data packet structure written by the DSP to the FPGA in an embodiment of the present invention. The value sent by the DSP in the NWRITE transaction is the same as the value read by the DSP.

[0031] Although the present invention has been described in conjunction with specific embodiments, the present invention is not limited to the embodiments described above. Equivalent substitutions or modifications made by those skilled in the art without departing from the spirit of the present invention and the scope of protection of the appended claims should fall within the scope of protection of the present invention.

Claims

1. A method for anti-interference transmission between FPGA and DSP based on SRIO doorbell interrupts, characterized in that, Includes the following steps: Step S1: The FPGA acquires the current doorbell counter value and encapsulates the count value and the user data to be transmitted into an SRIO data packet; Step S2: The FPGA sends a doorbell transaction packet to the DSP via the SRIO protocol, and after sending, the doorbell counter is incremented. Step S3: The DSP responds to the doorbell interrupt and increments the interrupt counter, then reads the SRIO data packet stored on the FPGA through an SRIO read transaction; Step S4: The DSP parses the data packet to extract the count value and calculates the difference between the current value of the interrupt counter and the extracted count value; Step S5: Determine whether there is a frame loss anomaly in the link based on whether the difference is equal to a preset value.

2. The FPGA and DSP anti-interference transmission method based on SRIO doorbell interrupt according to claim 1, characterized in that, The SRIO read transaction mentioned in step S3 specifically refers to the DSP reading the SRIO data packet from the FPGA through an NREAD transaction.

3. The FPGA and DSP anti-interference transmission method based on SRIO doorbell interrupt according to claim 1, characterized in that, In step S5, the preset value is 1. If the difference is equal to 1, the link is determined to be normal; otherwise, the link is determined to have a frame loss anomaly, and an alarm signal is output.

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