A multi-domain self-test system and method for radio frequency SiP built-in calibration loopback

Abstract

The application provides a kind of radio frequency SiP built-in calibration loopback multi-domain self-test system and method, it is related to semiconductor integrated circuit test technical field, its system includes hardware configuration module, for configuring loopback switch matrix, reference passage and test interface in radio frequency SiP;Fault test module, for injecting excitation signal to the link to be measured by the matrix, response signal is collected and analyzed to generate fault result;Loopback test module, for when fault result is fault-free, loopback path is constructed and gain value is obtained;Calibration and decoupling module, for obtaining the gain value of reference passage, the gain value of calibration loopback path generates calibration data, then decoupling obtains link parameter;Result output module, for link parameter and fault result are packaged as report and are output through test interface, to realize the independent fault detection and performance evaluation of radio frequency SiP internal link, reduce the dependence on external test and test cost, improve test efficiency and fault location precision.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit testing technology, and in particular to a radio frequency SiP built-in calibration loopback multi-domain self-test system and method. Background Technology

[0002] With the rapid development of wireless communication technology, radio frequency system-in-package (SiP) technology integrates radio frequency chips, control chips, and passive components into a single package with high density, significantly improving overall performance while achieving system miniaturization. However, high-density integration also brings severe challenges to post-packaging testing and verification.

[0003] Currently, testing of RF SiPs primarily relies on external RF automated test equipment (ATE) for probe or peripheral pin testing. This specification-based, item-by-item testing method requires verifying all performance indicators promised in the datasheet on the ATE one by one, resulting in numerous test items and long testing times. Furthermore, as the operating frequency of RF SiPs continues to increase, the management difficulty of ATE in signal generation and acquisition is increasing. More importantly, ATE testing can only apply stimuli and collect responses through the chip's peripheral pins, and cannot directly access the RF signal nodes inside the package. After packaging, the internal RF physical nodes of the RF SiP become inaccessible. Once performance degradation or failure occurs in the internal links, external ATE testing cannot accurately locate faults and assess performance in critical internal RF paths.

[0004] Therefore, it is necessary to provide a radio frequency SiP built-in calibration loopback multi-domain self-test system and method to solve the above-mentioned technical problems. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a multi-domain self-test system and method for built-in calibration loopback in radio frequency SiP, which solves the problem that the internal radio frequency nodes are unreachable after the existing radio frequency SiP packaging, making it difficult for external testing to accurately locate internal link faults and resulting in high testing costs.

[0006] This invention provides a radio frequency SiP built-in calibration loopback multi-domain self-test system, the system comprising: The hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path and standard test interface for accessing the transmit and receive links in the RF SiP. The fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results. The loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault. The calibration and decoupling module is used to obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters. The result output module is used to encapsulate the link performance parameters and the fault test results into a standardized test report, and output the standardized test report through the standard test interface.

[0007] Preferably, the hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path, and standard test interface for accessing the transmit and receive links in the RF SiP, specifically including: A loopback matrix configuration unit is used to configure the multi-node loopback switch matrix within the radio frequency SiP. The loopback injection nodes of the multi-node loopback switch matrix are at least located at the power amplifier input terminal, the power amplifier output terminal, and the low-noise amplifier output terminal of the transmit link. A reference path configuration unit is used to configure the embedded reference path in parallel in the multi-node loopback switch matrix. The embedded reference path includes a fixed attenuator and a reference amplifier. An interface configuration unit is used to configure the standard test interface on the RF SiP surface. The standard test interface defines the BIST instruction set and structured data report format. The BIST instruction set includes mode selection instructions, path configuration instructions, test start instructions, and result reading instructions.

[0008] Preferably, the fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results, specifically including: The signal injection unit is used to control the multi-node loopback switch matrix to select the radio frequency transmission line under test, and to connect the preset step pulse generator to the starting point of the radio frequency transmission line under test to inject the test excitation signal into the radio frequency transmission line under test. The response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test through an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform. The fault analysis unit is used to calculate the fault location based on the arrival time of the reflected pulse in the digital reflected waveform, determine the fault type based on the amplitude and polarity of the reflected pulse, and generate the fault test result based on the fault location and the fault type.

[0009] Preferably, the response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test using an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform, specifically including: A clock generation unit is used to generate a reference clock signal from the phase-locked loop in the radio frequency SiP, wherein the reference clock signal is of the same origin as the trigger signal of the step pulse generator; A programmable delay unit is used to receive the reference clock signal and successively delay the reference clock signal according to a preset step delay value to generate a sampling trigger signal sequence. A sampling control unit is used to control the high-speed sample-and-hold circuit with the sampling trigger signal in the sampling trigger signal sequence after the step pulse generator outputs the test excitation signal, to perform a sampling operation near the injection point of the radio frequency transmission line under test, and to obtain the reflected signal. The conversion and reconstruction unit is used to perform analog-to-digital conversion on the reflected signal to generate digital reflection values; and to arrange the digital reflection values ​​in sequence according to the delay of the sampling trigger signal to reconstruct the digital reflection waveform.

[0010] Preferably, the fault test module further includes a loopback test trigger unit, used to control the loopback test module to start based on the fault test result, specifically including: When the fault test result is no fault, the loopback test triggering unit generates a loopback test start signal, and allows the loopback test module to start according to the loopback test start signal; When the fault test result indicates a fault, the loopback test triggering unit generates a fault isolation signal, prevents the loopback test module from starting based on the fault isolation signal, encapsulates the fault test result into the standardized test report, and outputs the standardized test report through the standard test interface.

[0011] Preferably, the loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault, specifically including: The path construction unit is used to control the multi-node loopback switch matrix to connect the loopback injection node of the transmit link and the loopback injection node of the receive link to construct the loopback path according to the preset loopback path configuration strategy when the fault test result is no fault. A gain measurement unit is configured to configure a power detection network, acquire the input power value and output power value of the loopback path based on the power detection network, and calculate the cascaded gain test value of the loopback path according to the ratio of the output power value to the input power value.

[0012] Preferably, the calibration and decoupling module is used to obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters, specifically including: The reference measurement unit is used to control the multi-node loopback switch matrix to switch the embedded reference path into the measurement path and obtain the cascaded gain test value of the embedded reference path. The calibration calculation unit is used to calculate the drift correction coefficient based on the deviation between the cascaded gain test value of the embedded reference path and the preset factory calibration value. The calibration execution unit is used to correct the cascade gain test value of the loop path based on the drift correction coefficient and generate the calibration test data; The decoupling calculation unit is used to perform decoupling operations on the calibration test data corresponding to different loopback paths by solving simultaneous equations to obtain the link performance parameters.

[0013] Preferably, the decoupling calculation unit is used to perform decoupling operations on the calibration test data based on the calibration test data corresponding to different loopback paths, through simultaneous equations, to obtain the link performance parameters, specifically including: A variable definition unit is used to define the gain values ​​of the link components in the transmit link and the receive link as unknown variables; wherein, the link components include at least a power amplifier of the transmit link, a low-noise amplifier of the receive link, and subsequent circuitry. The equation construction unit is used to set the calibration test data as a linear combination of the unknown variables corresponding to the link components traversed by the loop path, based on the calibration test data corresponding to different loop paths, and to establish a set of gain relationship equations. The solution unit is used to substitute the calibration test data into the gain relationship equations, solve the unknown variables simultaneously, obtain the gain value of the link component, and obtain the link performance parameters.

[0014] A method for self-testing multiple domains with built-in calibration loopback in radio frequency SiP, the method comprising: Configure a multi-node loopback switch matrix, embedded reference path, and standard test interface in the RF SiP to access the transmit and receive links; Test excitation signals are injected into the link under test through the multi-node loopback switch matrix, and the excitation response signals are collected and analyzed to generate fault test results. When the fault test result is no fault, a loopback path is constructed based on the multi-node loopback switch matrix, and the cascade gain test value of the loopback path is obtained. Obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters; The link performance parameters and the fault test results are encapsulated into a standardized test report, and the standardized test report is output through the standard test interface.

[0015] Compared with related technologies, the RF SiP built-in calibration loopback multi-domain self-test system and method provided by the present invention have the following advantages: This invention includes a hardware configuration module for configuring a multi-node loopback switch matrix, an embedded reference path, and a standard test interface for accessing the transmit and receive links in an RF SiP; a fault testing module for injecting test excitation signals into the link under test through the multi-node loopback switch matrix, collecting and analyzing the excitation response signals, and generating fault test results; a loopback testing module for constructing a loopback path based on the multi-node loopback switch matrix and obtaining the cascaded gain test value of the loopback path when the fault test result is fault-free; a calibration and decoupling module for obtaining the cascaded gain test value of the embedded reference path, calibrating the cascaded gain test value of the loopback path, generating calibration test data, and performing decoupling processing on the calibration test data to obtain link performance parameters; and a result output module for encapsulating the link performance parameters and fault test results into a standardized test report and outputting the standardized test report through a standard test interface. This achieves autonomous fault detection and performance evaluation of the internal links of the RF SiP, effectively reducing dependence on external testing and testing costs, and improving testing efficiency and fault location accuracy.

[0016] This invention configures a multi-node loopback switch matrix, embedded reference path, and standard test interface for the transmit and receive links within an RF SiP through a hardware configuration module. This enables controllable access to internal RF paths, fundamentally solving the problem of unreachable RF physical nodes after packaging, eliminating dependence on external automated test equipment, and significantly reducing testing costs. Furthermore, this invention utilizes a fault testing module to inject test excitation signals into the RF transmission line under test using a step pulse generator. It then acquires reflected signals through a high-speed sample-and-hold circuit combined with equivalent time sampling. After analog-to-digital conversion and waveform reconstruction, a digital reflected waveform is generated, enabling precise calculation of fault location and fault type determination. Fault screening of the internal RF interconnects within the package is completed within milliseconds, effectively avoiding invalid tests caused by structural link faults and improving testing efficiency. This invention utilizes the coordinated operation of a loopback testing module and a calibration and decoupling module. The loopback testing module constructs various loopback paths based on a multi-node loopback switch matrix to obtain cascaded gain test values. The calibration and decoupling module calculates drift correction coefficients through an embedded reference path and performs real-time calibration of the cascaded gain test values ​​of the loopback paths, eliminating the impact of temperature drift and process deviations on measurement accuracy. Furthermore, it performs simultaneous equation decoupling operations on the calibration test data corresponding to different loopback paths to deduce the gain values ​​of link components such as the power amplifier, low-noise amplifier, and subsequent circuits, achieving the separation and extraction of the independent performance of each transmit and receive link. This invention encapsulates link performance parameters and fault test results into a standardized test report through a result output module and outputs it through a standard test interface. External test equipment can obtain complete test results through this interface, significantly simplifying the testing process. Attached Figure Description

[0017] Figure 1 This is a system block diagram of a radio frequency SiP built-in calibration loopback multi-domain self-test system according to the present invention. Figure 2 This is a flowchart of a radio frequency SiP built-in calibration loopback multi-domain self-test method according to the present invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments. Example

[0019] like Figure 1 As shown, a radio frequency SiP built-in calibration loopback multi-domain self-test system includes: The hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path and standard test interface for accessing the transmit and receive links in the RF SiP. RF SiP is a system-level packaging technology that integrates RF chips, control chips, and passive components into a single package with high density. A multi-node loopback switch matrix is ​​a network of switches distributed across multiple preset nodes in the transmit and receive links. These nodes are located at the input, output, and low-noise amplifier outputs of power amplifiers, etc., to guide RF signals from any transmit node to any receive node, forming multiple loopback measurement paths. An embedded reference path is a calibration channel with known gain and attenuation characteristics connected in parallel within the multi-node loopback switch matrix, providing a reference value for each test. The standard test interface is a set of digital pads configured on the RF SiP surface, defining an instruction set and structured data report format for external devices to initiate tests and read results.

[0020] The RF SiP Built-in Calibration Loopback Multi-Domain Self-Test System is an autonomous test solution integrated within the RF system-in-package. Utilizing the hardware resources built into the package, this system performs fault detection and performance parameter measurement of the transmit and receive links within the package without relying on external test equipment. It also performs real-time calibration via an embedded reference path, enabling joint decoupling analysis of multi-node loopback paths and outputting standardized test reports.

[0021] Understandably, after RF SiP is packaged, the internal RF nodes are enclosed within the substrate and molding compound, preventing direct external contact. This makes it impossible for conventional ATE testing to perform in-situ measurements of the internal transmission lines and amplifier nodes. Therefore, a multi-node loopback switch matrix, controllable by internal logic, needs to be pre-installed inside the package. Several key nodes of the transmit and receive links are routed to this matrix, allowing arbitrary path selection during testing. Simultaneously, since process variations and temperature changes affect the insertion loss of switches and couplers, an embedded reference path with known characteristics is required as a measurement benchmark. Furthermore, to meet the needs of automated production line testing, a standardized digital interface needs to be reserved on the package surface to receive test commands and return structured data. The hardware configuration module is designed based on these considerations.

[0022] The fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results. The link under test (DUT) refers to the RF signal transmission path within the RF SiP (Radio Frequency Integrated Platform) that needs to be tested, either in the transmit or receive link. The test excitation signal is a fast-rising-edge pulse generated by a step pulse generator, propagating along the DUT transmission line and reflecting when it encounters an impedance discontinuity. The excitation response signal mainly refers to the reflected signal, which is acquired near the injection point by a high-speed sample-and-hold circuit. The fault test results include the fault location and fault type.

[0023] Understandably, if structural problems such as open circuits, short circuits, or impedance mismatches occur during the routing of RF transmission lines within the package substrate, the signal reflection coefficient at that location will change significantly. The fault test module utilizes this physical characteristic. By injecting a fast-rising-edge pulse into the link under test and capturing the reflected signal near the injection point, the physical location and type of fault can be deduced based on the return time and amplitude polarity of the reflected pulse. This test is independent of the active circuit state of the RF link, enabling rapid structural integrity screening before performance parameter measurements.

[0024] The loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault. The loopback path refers to the closed-loop signal channel formed by connecting any loopback injection node of the transmit link to any loopback injection node of the receive link using a multi-node loopback switch matrix. The cascaded gain test value of the loopback path refers to the ratio of the output power to the input power after the signal passes through each link component along the loopback path, reflecting the overall amplification capability of the entire loopback path.

[0025] Understandably, fault screening ensures that performance measurements are conducted on the premise of an intact link structure, avoiding data distortion caused by performing invalid tests on damaged links, while also saving testing time and improving overall testing efficiency. The loopback test module connects preset nodes of the transmit and receive links through a multi-node loopback switch matrix to form different signal loopback channels, and measures the cascaded gain test value of each channel to calculate the true gain of independent devices such as power amplifiers and low-noise amplifiers. Therefore, the loopback test module is the data acquisition link in the entire performance parameter measurement process.

[0026] The calibration and decoupling module is used to obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters. The cascaded gain test value of the embedded reference path refers to the gain value measured under current measurement conditions using the factory-calibrated reference path, serving as the calibration benchmark. The calibration test data is the calibration result after correcting the cascaded gain measurement value of the loopback path. Link performance parameters refer to the independent gain values ​​of link components such as the power amplifier, low-noise amplifier, and subsequent circuitry.

[0027] Understandably, the cascaded gain measurement value obtained by the loopback test module is the superposition result of the gains of multiple components in the transmit and receive links, and cannot directly reflect the true performance of the power amplifier or low-noise amplifier individually. The role of the calibration and decoupling module is to first use the deviation value measured by the embedded reference path to correct the drift of the cascaded gain measurement value of the loopback path, eliminating systematic errors introduced by temperature and process fluctuations; then, based on the different combinations of components traversed by multiple loopback paths, the gain of each link component is separated from the superposition value one by one through simultaneous equations, finally obtaining the gain parameter of each independent component.

[0028] The result output module is used to encapsulate the link performance parameters and the fault test results into a standardized test report, and output the standardized test report through the standard test interface.

[0029] Understandably, the preceding modules completed fault screening, loopback measurement, and decoupling operations, obtaining link performance parameters and fault detection results. However, this data was scattered across different processing stages, making it unusable directly by external testing equipment. The results output module integrates this data into a structured data packet, encapsulates it into a standardized test report according to the format defined by the standard test interface, and outputs it through the digital pads reserved on the package surface. This design allows any testing equipment conforming to the interface protocol to directly read the test results without parsing the internal data structure, facilitating automated testing and yield management on the production line.

[0030] The hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path, and standard test interface for accessing the transmit and receive links in the RF SiP, specifically including: A loopback matrix configuration unit is used to configure the multi-node loopback switch matrix within the radio frequency SiP. The loopback injection nodes of the multi-node loopback switch matrix are at least located at the power amplifier input terminal, the power amplifier output terminal, and the low-noise amplifier output terminal of the transmit link. A reference path configuration unit is used to configure the embedded reference path in parallel in the multi-node loopback switch matrix. The embedded reference path includes a fixed attenuator and a reference amplifier. An interface configuration unit is used to configure the standard test interface on the RF SiP surface. The standard test interface defines the BIST instruction set and structured data report format. The BIST instruction set includes mode selection instructions, path configuration instructions, test start instructions, and result reading instructions.

[0031] The loopback injection node is the connection point between the RF switch matrix and the transmission line, used for signal input or output. The power amplifier input refers to the RF transmission line node before the power amplifier, and the output refers to the RF transmission line node after the power amplifier. The low-noise amplifier output refers to the RF transmission line node after the low-noise amplifier stage. These nodes are used to construct different loopback paths. The fixed attenuator provides a known stable attenuation, and the reference amplifier provides a known gain; together, they form an embedded reference path as a calibration benchmark. The BIST (Built-In Self-Test) instruction set is a collection of test control commands, and the structured data report format defines the arrangement and encoding rules of the test results. The mode selection instruction is used to switch between TDR (Time-Domain Reflectometry) fault testing and loopback testing modules. The path configuration instruction is used to set the connectivity state of the multi-node loopback switch matrix. The start test instruction is used to trigger test execution. The read result instruction is used to obtain standardized test report data.

[0032] In practical applications, the loopback matrix configuration unit completes the layout of the multi-node loopback switch matrix during the internal substrate routing stage of the RF SiP, embeds the RF switch network between the transmit link and the receive link, and leads out loopback injection nodes at the power amplifier input, power amplifier output and low noise amplifier output respectively. Each node is connected to the corresponding port of the switch matrix through a short transmission line. The multi-node loopback switch matrix uses RF switch dies with low insertion loss.

[0033] The reference path configuration unit connects to an embedded reference path in parallel within the multi-node loopback switch matrix. One end of this path is connected to the common port of the multi-node loopback switch matrix, and the other end is connected to a matching load. A fixed attenuator and a reference amplifier are sequentially connected in series in the middle of the embedded reference path. Both are individually calibrated for gain and attenuation values ​​before leaving the factory, and the calibration results are written to the chip's internal non-volatile memory. The interface configuration unit sets a standard test interface on the surface-mount ball layer of the RF SiP. This interface is assigned a dedicated digital pad and is connected to the general-purpose input / output port of the digital control chip through traces within the substrate. The mapping relationship between the BIST instruction set encoding table and the structured data report format is defined in the firmware of the digital control chip.

[0034] The fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results, specifically including: The signal injection unit is used to control the multi-node loopback switch matrix to select the radio frequency transmission line under test, and to connect the preset step pulse generator to the starting point of the radio frequency transmission line under test to inject the test excitation signal into the radio frequency transmission line under test. The response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test through an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform. The fault analysis unit is used to calculate the fault location based on the arrival time of the reflected pulse in the digital reflected waveform, determine the fault type based on the amplitude and polarity of the reflected pulse, and generate the fault test result based on the fault location and the fault type.

[0035] The RF transmission line under test (DUT) refers to the microstrip line, stripline, or coplanar waveguide within the internal substrate or package structure of an RF SiP (System-in-Package) used to transmit RF signals. A step pulse generator is a circuit that generates a fast-rising-edge electrical pulse, whose output pulse propagates forward along the DUT. A high-speed sample-and-hold circuit is a sampling front-end circuit that captures and holds the instantaneous voltage of a signal for subsequent analog-to-digital conversion in a very short time. Equivalent-time sampling refers to successively changing the delay between the sampling time and the pulse emission time, acquiring one amplitude point on the reflected waveform each time, and combining multiple samples to form a complete waveform.

[0036] A reflected signal is a wave that propagates back after a pulse encounters an impedance discontinuity on a transmission line. Analog-to-digital conversion converts the analog voltage amplitude of the reflected signal into a digital value. Waveform reconstruction arranges the digital values ​​acquired from each sample according to the order of sampling time to generate a complete digital reflected waveform. The arrival time of the reflected pulse is the time difference between the pulse's emission and the return of the reflected wave to the injection point. The fault location is calculated based on the arrival time of the reflected pulse and the propagation speed of the reflected signal in the transmission line. The amplitude of the reflected pulse reflects the degree of impedance change, and its polarity reflects the direction of impedance change; both are used to distinguish between fault types such as open circuits, short circuits, or impedance mismatches.

[0037] In practical applications, the signal injection unit receives the gating command from the digital control chip and connects the RF transmission line under test (DUT) to the step pulse generator by configuring the register of the multi-node loopback switch matrix. After being activated by the trigger signal, the step pulse generator rapidly turns its internal high-speed logic gates on and off, working in conjunction with the charging / discharging network to generate a step voltage with a rising edge of less than 20 picoseconds at the output. This voltage serves as the starting point for the test excitation signal directly injected into the DUT, propagating forward along the DUT. Simultaneously with pulse injection, the response acquisition unit uses a programmable delay line circuit to successively generate a sampling trigger signal with increasing delay based on a preset step delay value.

[0038] The high-speed sample-and-hold circuit samples and holds the voltage near the injection point of the RF transmission line under test when each sampling trigger signal arrives. Each sampling point corresponds to an amplitude value on the reflected waveform. The analog-to-digital converter converts the held voltage of each sampling point into a digital reflection value. The digital reflection values ​​obtained from each sampling are arranged in order according to the delay of the sampling trigger signal and combined to reconstruct a digital reflection waveform. After receiving the digital reflection waveform, the fault analysis unit detects the arrival time difference between the reflected pulse and the injection pulse in the digital reflection waveform. The time difference is multiplied by the propagation speed of the reflected signal in the substrate medium and then divided by 2 to obtain the fault location. At the same time, the amplitude and polarity of the reflected pulse are read. When the reflected pulse is in the same direction as the incident pulse, it is determined to be an open circuit; when it is in the opposite direction, it is determined to be a short circuit; when the amplitude is between zero and the incident amplitude, it is determined to be an impedance mismatch. Based on this, the fault test result is generated.

[0039] The response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test using an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform, specifically including: A clock generation unit is used to generate a reference clock signal from the phase-locked loop in the radio frequency SiP, wherein the reference clock signal is of the same origin as the trigger signal of the step pulse generator; A programmable delay unit is used to receive the reference clock signal and successively delay the reference clock signal according to a preset step delay value to generate a sampling trigger signal sequence. A sampling control unit is used to control the high-speed sample-and-hold circuit with the sampling trigger signal in the sampling trigger signal sequence after the step pulse generator outputs the test excitation signal, to perform a sampling operation near the injection point of the radio frequency transmission line under test, and to obtain the reflected signal. The conversion and reconstruction unit is used to perform analog-to-digital conversion on the reflected signal to generate digital reflection values; and to arrange the digital reflection values ​​in sequence according to the delay of the sampling trigger signal to reconstruct the digital reflection waveform.

[0040] A phase-locked loop (PLL) is a closed-loop frequency control component that outputs a stable high-frequency clock signal synchronized with the input reference frequency. The reference clock signal is this stable clock output by the PLL. The reference clock signal and the trigger signal of the step pulse generator are from the same source, meaning they are generated by the same clock source, and the time relationship between the sampling time and the pulse emission time remains fixed and known. The preset step delay value is a fixed time increment pre-calculated during system design based on the required time resolution and number of sampling points, typically set to 5 picoseconds to 10 picoseconds. Successive increment delay means that the delay is increased by one step value after each sampling. The sampling trigger signal sequence is a set of trigger pulses generated using a successive increment delay method, with each pulse shifted one step value backward relative to the emission time. The digital reflection value is the digital quantity output by the analog-to-digital converter, corresponding to the amplitude of the reflected signal at that sampling point. The digital reflection waveform is a complete waveform diagram obtained by arranging multiple discrete sampling points in chronological order.

[0041] In practical applications, the clock generation unit receives the reference frequency output from the internal crystal oscillator of the RF SiP. The phase-locked loop multiplies this frequency and outputs a high-frequency reference clock signal. This reference clock signal is simultaneously allocated to the step pulse generator as its trigger source reference clock, achieving co-source between the reference clock signal and the trigger signal. The programmable delay unit contains a digitally controlled delay line. The digital control chip writes the preset step delay value into the control register of the programmable delay unit. Each time the digitally controlled delay line receives a reference clock cycle, it increments the delay by one step value, outputting a sequence of sampling trigger signals with progressively increasing delay values.

[0042] The sampling control unit starts counting at the same moment the step pulse generator outputs the test excitation signal, sequentially outputting each sampling trigger signal in the sampling trigger signal sequence to the trigger terminal of the high-speed sample-and-hold circuit. The high-speed sample-and-hold circuit samples the instantaneous voltage near the injection point of the RF transmission line under test when each sampling trigger signal arrives. After the sampling switch is turned on, the voltage value is stored by the holding capacitor. Subsequently, the analog-to-digital converter reads the voltage on the holding capacitor and converts it into a digital reflection value. The conversion and reconstruction unit receives the digital reflection value generated by each sampling, associates it with the delay amount of the corresponding sampling trigger signal, and stores it. After all sampling is completed, the digital reflection values ​​are read out in ascending order of delay amount and arranged sequentially to reconstruct a complete digital reflection waveform.

[0043] The fault testing module further includes a loopback test triggering unit, used to control the loopback test module to start based on the fault test results, specifically including: When the fault test result is no fault, the loopback test triggering unit generates a loopback test start signal, and allows the loopback test module to start according to the loopback test start signal; When the fault test result indicates a fault, the loopback test triggering unit generates a fault isolation signal, prevents the loopback test module from starting based on the fault isolation signal, encapsulates the fault test result into the standardized test report, and outputs the standardized test report through the standard test interface.

[0044] The loopback test start signal is an enable level or pulse generated by the loopback test trigger unit after receiving a fault-free result. This signal is sent to the control input of the loopback test module to unlock the start conditions of the loopback test module. The fault isolation signal is a control signal generated by the loopback test trigger unit after receiving a fault result. This signal directly shuts off the start path of the loopback test module.

[0045] In practical applications, after the fault analysis unit completes the fault determination, it writes the fault test result into the input register of the loopback test trigger unit in digital code form via the on-chip bus. The loopback test trigger unit contains a logic judgment circuit that reads the fault type field from the input register. When the fault type field is a code corresponding to no fault, the logic judgment circuit outputs a high-level enable signal to the power management unit of the loopback test module. The power management unit then turns on the power supply to the loopback test module and simultaneously disables the output of the clock buffer inside the loopback test module, putting the loopback test module into a ready-to-start state. When the fault type field is a code corresponding to a fault, the logic judgment circuit outputs a low-level latch signal to the control terminal of the loopback test module, keeping the loopback test module in a reset state. Simultaneously, the loopback test trigger unit transmits the fault test result, along with the current test timestamp and link identifier, to the buffer of the result output module. The result output module encapsulates this data packet into a data packet according to the protocol frame format defined by the standard test interface and drives the standard test interface to output the data packet.

[0046] In this manner, the loopback test trigger unit executes shunt control based on the fault test results, demonstrating the orderly switching between the time and frequency domains of testing. When there is no fault, frequency domain loopback measurement is enabled; when a fault occurs, it is blocked, and the time domain fault location result is directly output. This shunt control ensures that performance parameters are extracted when the structure is intact, achieving multi-domain testing capability coverage from time domain fault location to frequency domain performance evaluation.

[0047] The loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault. Specifically, it includes: The path construction unit is used to control the multi-node loopback switch matrix to connect the loopback injection node of the transmit link and the loopback injection node of the receive link to construct the loopback path according to the preset loopback path configuration strategy when the fault test result is no fault. A gain measurement unit is configured to configure a power detection network, acquire the input power value and output power value of the loopback path based on the power detection network, and calculate the cascaded gain test value of the loopback path according to the ratio of the output power value to the input power value.

[0048] The preset loopback path configuration strategy is a switch combination table pre-stored in the firmware. Each test corresponds to a set of loopback path node combinations. During testing, the switch combination table is queried according to the measurement sequence number to obtain the path parameters, which are then written to the shift register of the multi-node loopback switch matrix to complete the path construction. The power detection network consists of power detectors deployed at the input and output ends of the loopback path. The power detector at the input end is coupled after the loopback injection node of the transmit link to collect the input power, and the power detector at the output end is coupled before the loopback injection node of the receive link to collect the output power.

[0049] In practical applications, after receiving the loopback test start signal from the loopback test trigger unit, the path construction unit reads the switch control word corresponding to the current test sequence number from the preset loopback path configuration strategy table. This control word contains the on / off state codes of each RF switch in the multi-node loopback switch matrix. The path construction unit writes the switch control word into the shift register of the multi-node loopback switch matrix through the general-purpose input / output port of the digital control chip. After latching the switch control word, the RF switches are controlled to switch to the on or off state according to the on / off state codes, connecting the loopback injection node specified in the transmit link with the loopback injection node specified in the receive link to form a complete signal loopback path.

[0050] After the loopback path is constructed, the gain measurement unit sends an enable signal to the power detection network. The first power detector, located at the input of the loopback path, couples the input signal and outputs a voltage value proportional to the input power. The second power detector, located at the output of the loopback path, couples the amplified output signal from each link component of the loopback path and outputs a voltage value proportional to the output power. The output voltages of the two power detectors are converted into input and output power values ​​by an analog-to-digital converter, respectively. The gain measurement unit reads these two power values, performs a division operation to obtain the ratio of the output power value to the input power value, and then performs a logarithmic operation to convert it into a dB value, which is the cascaded gain test value of the loopback path.

[0051] The calibration and decoupling module is used to acquire the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters, specifically including: The reference measurement unit is used to control the multi-node loopback switch matrix to switch the embedded reference path into the measurement path and obtain the cascaded gain test value of the embedded reference path. The calibration calculation unit is used to calculate the drift correction coefficient based on the deviation between the cascaded gain test value of the embedded reference path and the preset factory calibration value. The calibration execution unit is used to correct the cascade gain test value of the loop path based on the drift correction coefficient and generate the calibration test data; The decoupling calculation unit is used to perform decoupling operations on the calibration test data corresponding to different loopback paths by solving simultaneous equations to obtain the link performance parameters.

[0052] The preset factory calibration value is obtained during the chip's factory testing phase: under standard environmental conditions, the gain of the embedded reference path is measured using external testing equipment, and this value is written into the chip's internal non-volatile memory. The deviation between the cascaded gain test value of the embedded reference path and the preset factory calibration value reflects the total system drift introduced by factors such as temperature, voltage, and device aging. The drift correction coefficient is used to compensate for the gain shift caused by changes in system temperature, voltage, etc., ensuring measurement accuracy.

[0053] In practical applications, when the reference measurement unit is operating, the digital control chip sends a path switching command to the multi-node loopback switch matrix, connecting the embedded reference path to the measurement path. A fixed attenuator and a reference amplifier are connected in series in this signal channel, and a power detection network measures the input power value of this path. With output power value The logarithm of the two values ​​is then used to obtain the cascaded gain test value of the embedded reference path. For example, the built-in reference path has a gain calibration value of 10dB under standard conditions when it leaves the factory, while the current cascaded gain test value is 10.3dB, indicating that the overall system gain has drifted upward by 0.3dB due to environmental factors such as temperature rise or voltage fluctuations.

[0054] The calibration calculation unit reads the factory calibration value of 10dB from the non-volatile memory and subtracts it from the current cascaded gain test value of 10.3dB, obtaining a deviation of 0.3dB. This deviation reflects the total system drift under the current environment. To compensate for this drift, the calibration calculation unit inverts the deviation, obtaining a drift correction factor of -0.3dB.

[0055] The calibration execution unit reads the cascade gain test values ​​of each loopback path from the temporary register of the loopback test module. For example, if the cascade gain test value of a certain loopback path is 8.2dB, the calibration execution unit adds a drift correction factor of -0.3dB to the cascade gain test value, resulting in a calibrated cascade gain test value of 7.9dB for that loopback path. All loopback path cascade gain test values ​​are calibrated in the same way, and the generated calibration test data is stored in the calibration data buffer.

[0056] The decoupling calculation unit is used to perform decoupling operations on the calibration test data corresponding to different loopback paths by solving simultaneous equations to obtain the link performance parameters, specifically including: A variable definition unit is used to define the gain values ​​of the link components in the transmit link and the receive link as unknown variables; wherein, the link components include at least a power amplifier of the transmit link, a low-noise amplifier of the receive link, and subsequent circuitry. The equation construction unit is used to set the calibration test data as a linear combination of the unknown variables corresponding to the link components traversed by the loop path, based on the calibration test data corresponding to different loop paths, and to establish a set of gain relationship equations. The solution unit is used to substitute the calibration test data into the gain relationship equations, solve the unknown variables simultaneously, obtain the gain value of the link component, and obtain the link performance parameters.

[0057] In this context, link components refer to active or passive devices that constitute the transmit and receive links. This scheme includes at least a power amplifier, a low-noise amplifier, and subsequent stage circuitry. The gain relationship equations are a set of linear equations formed by simultaneously solving the calibration test data of all loopback paths. Each equation corresponds to one loopback path, and the unknowns are the gain values ​​of each link component. The link performance parameters are the independent gain values ​​of each link component obtained after solving the simultaneous equations, such as the gain of the power amplifier, the gain of the low-noise amplifier, and the gain of the subsequent stage circuitry.

[0058] In practical applications, the decoupling calculation unit reads the calibration test data corresponding to all loopback paths from the calibration data buffer. The variable definition unit sets the gain values ​​of each link component in the transmit and receive links as unknown variables, such as the gain of the power amplifier. Gain of low-noise amplifier Gain of the subsequent circuit .

[0059] The equation-building unit establishes a set of gain relationship equations based on the combination of nodes traversed by each loop path. For example, when the loop path runs from the input of the power amplifier to the output of the low-noise amplifier, its calibration test data... Equal to the gain of the power amplifier With the gain of the low-noise amplifier The sum; the calibration test data when the loopback path runs from the output of the power amplifier to the output of the low-noise amplifier. Equal to the gain of the power amplifier Gain of low-noise amplifier Gain of the subsequent circuit The sum; when the output of the embedded reference path is connected in series with the input of the low-noise amplifier in the receiving link and inserted into the measurement path, its calibration test data. Equal to the cascaded gain test value of the embedded reference path With the gain of the low-noise amplifier The sum of these relationships. The above relationships constitute the following system of equations: .

[0060] For example, if , , , Substituting into the equation yields... , , .

[0061] The solution unit substitutes the calibration test data of each loop path into the above equation system, solves the unknown variables by elimination or matrix operations, obtains the independent gain value of each link component, and stores it as a link performance parameter in the result register for the result output module to read and encapsulate. Example

[0062] like Figure 2 As shown, a multi-domain self-test method for built-in calibration loopback in radio frequency SiP is provided, the method comprising: S1, configures a multi-node loopback switch matrix, embedded reference path and standard test interface in the RF SiP to access the transmit link and receive link; S2, inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results; S3, when the fault test result is no fault, construct a loopback path based on the multi-node loopback switch matrix, and obtain the cascade gain test value of the loopback path; S4, obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters; S5, encapsulate the link performance parameters and the fault test results into a standardized test report, and output the standardized test report through the standard test interface.

[0063] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0064] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0065] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

Claims

1. A radio frequency SiP built-in calibration loopback multi-domain self-test system, characterized in that, The system includes: The hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path and standard test interface for accessing the transmit and receive links in the RF SiP. The fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results. The loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault. The calibration and decoupling module is used to obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters. The result output module is used to encapsulate the link performance parameters and the fault test results into a standardized test report, and output the standardized test report through the standard test interface.

2. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 1, characterized in that, The hardware configuration module is used to configure the multi-node loopback switch matrix, embedded reference path, and standard test interface for accessing the transmit and receive links in the RF SiP, specifically including: A loopback matrix configuration unit is used to configure the multi-node loopback switch matrix within the radio frequency SiP. The loopback injection nodes of the multi-node loopback switch matrix are at least located at the power amplifier input terminal, the power amplifier output terminal, and the low-noise amplifier output terminal of the transmit link. A reference path configuration unit is used to configure the embedded reference path in parallel in the multi-node loopback switch matrix. The embedded reference path includes a fixed attenuator and a reference amplifier. An interface configuration unit is used to configure the standard test interface on the RF SiP surface. The standard test interface defines the BIST instruction set and structured data report format. The BIST instruction set includes mode selection instructions, path configuration instructions, test start instructions, and result reading instructions.

3. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 1, characterized in that, The fault testing module is used to inject test excitation signals into the link under test through the multi-node loopback switch matrix, collect and analyze the excitation response signals, and generate fault test results, specifically including: The signal injection unit is used to control the multi-node loopback switch matrix to select the radio frequency transmission line under test, and to connect the preset step pulse generator to the starting point of the radio frequency transmission line under test to inject the test excitation signal into the radio frequency transmission line under test. The response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test through an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform. The fault analysis unit is used to calculate the fault location based on the arrival time of the reflected pulse in the digital reflected waveform, determine the fault type based on the amplitude and polarity of the reflected pulse, and generate the fault test result based on the fault location and the fault type.

4. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 3, characterized in that, The response acquisition unit is used to control a preset high-speed sample-and-hold circuit to acquire the reflected signal on the radio frequency transmission line under test near the injection point of the line under test using an equivalent time sampling method, and to perform analog-to-digital conversion and waveform reconstruction on the reflected signal to generate a digital reflected waveform, specifically including: A clock generation unit is used to generate a reference clock signal from the phase-locked loop in the radio frequency SiP, wherein the reference clock signal is of the same origin as the trigger signal of the step pulse generator; A programmable delay unit is used to receive the reference clock signal and successively delay the reference clock signal according to a preset step delay value to generate a sampling trigger signal sequence. A sampling control unit is used to control the high-speed sample-and-hold circuit with the sampling trigger signal in the sampling trigger signal sequence after the step pulse generator outputs the test excitation signal, to perform a sampling operation near the injection point of the radio frequency transmission line under test, and to obtain the reflected signal. The conversion and reconstruction unit is used to perform analog-to-digital conversion on the reflected signal to generate digital reflection values; and to arrange the digital reflection values ​​in sequence according to the delay of the sampling trigger signal to reconstruct the digital reflection waveform.

5. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 1, characterized in that, The fault testing module further includes a loopback test triggering unit, used to control the loopback test module to start based on the fault test results, specifically including: When the fault test result is no fault, the loopback test triggering unit generates a loopback test start signal, and allows the loopback test module to start according to the loopback test start signal; When the fault test result indicates a fault, the loopback test triggering unit generates a fault isolation signal, prevents the loopback test module from starting based on the fault isolation signal, encapsulates the fault test result into the standardized test report, and outputs the standardized test report through the standard test interface.

6. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 1, characterized in that, The loopback test module is used to construct a loopback path based on the multi-node loopback switch matrix and obtain the cascade gain test value of the loopback path when the fault test result is no fault. Specifically, it includes: The path construction unit is used to control the multi-node loopback switch matrix to connect the loopback injection node of the transmit link and the loopback injection node of the receive link to construct the loopback path according to the preset loopback path configuration strategy when the fault test result is no fault. A gain measurement unit is configured to configure a power detection network, acquire the input power value and output power value of the loopback path based on the power detection network, and calculate the cascaded gain test value of the loopback path according to the ratio of the output power value to the input power value.

7. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 1, characterized in that, The calibration and decoupling module is used to acquire the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters, specifically including: The reference measurement unit is used to control the multi-node loopback switch matrix to switch the embedded reference path into the measurement path and obtain the cascaded gain test value of the embedded reference path. The calibration calculation unit is used to calculate the drift correction coefficient based on the deviation between the cascaded gain test value of the embedded reference path and the preset factory calibration value. The calibration execution unit is used to correct the cascade gain test value of the loop path based on the drift correction coefficient and generate the calibration test data; The decoupling calculation unit is used to perform decoupling operations on the calibration test data corresponding to different loopback paths by solving simultaneous equations to obtain the link performance parameters.

8. The RF SiP built-in calibration loopback multi-domain self-test system according to claim 7, characterized in that, The decoupling calculation unit is used to perform decoupling operations on the calibration test data corresponding to different loopback paths by solving simultaneous equations to obtain the link performance parameters, specifically including: A variable definition unit is used to define the gain values ​​of the link components in the transmit link and the receive link as unknown variables; wherein, the link components include at least a power amplifier of the transmit link, a low-noise amplifier of the receive link, and subsequent circuitry. The equation construction unit is used to set the calibration test data as a linear combination of the unknown variables corresponding to the link components traversed by the loop path, based on the calibration test data corresponding to different loop paths, and to establish a set of gain relationship equations. The solution unit is used to substitute the calibration test data into the gain relationship equations, solve the unknown variables simultaneously, obtain the gain value of the link component, and obtain the link performance parameters.

9. A method for multi-domain self-testing with built-in calibration loopback in radio frequency SiP, characterized in that, The method, applied to an RF SiP built-in calibration loopback multi-domain self-test system as described in any one of claims 1-8, comprises: Configure a multi-node loopback switch matrix, embedded reference path, and standard test interface in the RF SiP to access the transmit and receive links; Test excitation signals are injected into the link under test through the multi-node loopback switch matrix, and the excitation response signals are collected and analyzed to generate fault test results. When the fault test result is no fault, a loopback path is constructed based on the multi-node loopback switch matrix, and the cascade gain test value of the loopback path is obtained. Obtain the cascaded gain test value of the embedded reference path, calibrate the cascaded gain test value of the loopback path, generate calibration test data, and perform decoupling processing on the calibration test data to obtain link performance parameters; The link performance parameters and the fault test results are encapsulated into a standardized test report, and the standardized test report is output through the standard test interface.

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