Passive clock source device, board, network device and communication system

Abstract

The application provides a passive clock source device, a single board, a network device and a communication system, and belongs to the technical field of communication. The passive clock device provided by the application is used for providing a clock signal for a network device. Accordingly, the passive clock device comprises a clock generator and a pluggable interface. The clock generator is connected with the pluggable interface. The pluggable interface is used for connecting with the network device. The clock generator is used for obtaining a clock signal. The pluggable interface is used for outputting the clock signal to the network device in the case of connecting with the network device. When the network device needs to perform high-precision clock synchronization, the passive clock device can be inserted on the network device at any time. The clock generator in the passive clock device provides a clock signal for the network device, realizes separation of the high-precision clock generator from the network device, does not need to integrate the high-precision clock generator on a main control board, reduces the cost of the device and the cost of network deployment, and can also avoid resource waste.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a passive clock source device, a single board, a network device, and a communication system. Background Technology

[0002] With the development of communication technology, by propagating a reference clock signal among multiple network devices in a network, the network devices can adjust the clock signal generated by their local clock source based on the reference clock signal to achieve clock synchronization.

[0003] When the clock link between network devices is unavailable, the network devices cannot receive the reference clock signal. In order to ensure that the error between the clock signal generated by the local clock source of the network device and the reference clock signal is within a preset range before the link is restored, a high-precision clock source such as a high-performance crystal oscillator or a rubidium atomic clock is integrated on the main control board of the network device. This ensures that when the clock link is unavailable, the error between the clock signal generated by the local clock source and the reference clock signal is within a preset range.

[0004] Since some existing communication networks may not currently require high-precision clock synchronization from network devices for their current services, and integrating high-precision clock sources such as high-performance crystal oscillators or rubidium atomic clocks onto the main control board of network devices is costly, integrating high-precision clock sources onto the main control board of each network device would not only increase equipment and network deployment costs, but also potentially lead to resource waste, if we consider that communication networks may need high-precision time synchronization in the future. Summary of the Invention

[0005] This application provides a passive clock source device, a single board, a network device, and a communication system, which can reduce equipment costs and network deployment costs, and avoid resource waste. The technical solution is as follows.

[0006] Firstly, a passive clock device is provided for providing clock signals to network devices. This passive clock device includes a clock generator and a pluggable interface. The clock generator is connected to the pluggable interface, which is used to connect to the network device. The clock generator obtains the clock signal, and the pluggable interface outputs the clock signal to the network device when connected. When any network device requires high-precision clock synchronization, technicians can easily install the passive clock device, making it pluggable. This allows the clock generator within the passive clock device to provide a high-precision clock signal to the network device, thus separating the high-precision clock generator from the network device. This eliminates the need to integrate a high-precision local clock generator on the main control board of the network device during network establishment, reducing equipment and network deployment costs and avoiding resource waste.

[0007] Optionally, the passive clock device also includes a temperature sensor connected to both the pluggable interface and the clock generator. The temperature sensor detects the temperature of the clock generator and outputs this temperature to the network device via the pluggable interface. Since the clock signal obtained by the clock generator is significantly affected by its temperature, outputting this temperature to the network device allows the network device to compensate for the clock signal based on the temperature, thereby improving the accuracy of the clock signal and ultimately enhancing the accuracy of clock synchronization based on it.

[0008] Optionally, the clock generator includes a clock source connected to a pluggable interface. The clock source is used to generate a clock signal. The device generates a clock signal through the clock source and then outputs the clock signal to the network device through the pluggable interface. When the clock accuracy of the clock source is high, the device can provide a high-precision clock signal to the network device, thereby improving the accuracy of the clock maintained by the network device.

[0009] Optionally, the aforementioned clock generator includes a clock source and a clock conversion module, which are connected together. The clock conversion module is connected to a pluggable interface. The clock source generates a raw clock signal, and the clock conversion module converts the raw clock signal generated by the clock source based on a preset frequency to obtain a clock signal. This device performs frequency conversion on the raw clock signal generated by the clock source through the clock conversion module, enabling it to provide clock signals at different preset frequencies to network devices, thus providing different chips in the network device with the clock signals at the frequencies required by those chips.

[0010] Optionally, the aforementioned pluggable interface is also used to receive preset frequency information sent by the network device. The preset frequency information indicates a preset frequency, enabling the clock conversion module to perform frequency conversion on the original clock signal according to the preset frequency required by the network device, thereby providing the network device with a clock signal at the frequency required by the network device according to its needs.

[0011] Optionally, the pluggable interface includes multiple output pins, which are used to output multiple clock signals to the network device, thereby providing clock signals to different chips in the network device, enabling different chips to synchronize their clocks according to the clock signals they receive, and meeting the clock synchronization requirements of their own services.

[0012] Optionally, the clock generator is integrated as a component of the passive clock device onto the circuit board of the passive clock device, or the components of the clock generator are distributed and integrated onto the circuit board of the passive clock device to reduce the size of the passive clock device and improve its portability.

[0013] Secondly, a clock signal output method is provided. This method is applied to a passive clock device used to provide clock signals to network devices. The passive clock device includes a clock generator and a pluggable interface. The clock generator is connected to the pluggable interface, which is used to connect to the network device. The method includes: the clock generator obtaining a clock signal; and the pluggable interface outputting the clock signal to the network device when connected. When any network device requires high-precision clock synchronization, relevant technicians can easily insert the passive clock device into the network device, making the passive clock device pluggable to the network device. This allows the clock generator in the passive clock device to provide a high-precision clock signal to the network device, thus separating the high-precision clock generator from the network device. This eliminates the need to integrate a high-precision local clock generator on the main control board of the network device before establishing the communication network, reducing equipment and network deployment costs and avoiding resource waste.

[0014] Optionally, the passive clock device further includes a temperature sensor, which is connected to both the pluggable interface and the clock generator. The method further includes: the temperature sensor detecting the temperature of the clock generator and outputting the temperature to the network device via the pluggable interface. Since the clock signal obtained by the clock generator is significantly affected by its temperature, outputting the temperature to the network device allows the network device to compensate for the clock signal obtained by the clock generator based on the temperature, thereby improving the accuracy of the clock signal and ultimately enhancing the accuracy of clock synchronization based on the clock signal.

[0015] Optionally, the clock generator includes a clock source connected to a pluggable interface. The clock generator obtains a clock signal by: the clock source generating the clock signal. This method generates a clock signal through the clock source and then outputs the clock signal to the network device through the pluggable interface. When the clock source has high clock accuracy, this method can provide a high-precision clock signal to the network device, thereby improving the accuracy of the clock maintained by the network device.

[0016] Optionally, the clock generator includes a clock source and a clock conversion module, which are connected together. The clock conversion module is connected to a pluggable interface. The clock generator obtains a clock signal by: the clock source generating a raw clock signal; and the clock conversion module converting the raw clock signal generated by the clock source based on a preset frequency to obtain the clock signal. This method converts the frequency of the raw clock signal generated by the clock source through the clock conversion module, enabling the passive clock device to provide clock signals at different preset frequencies to network devices, thus providing different chips in the network device with clock signals at the frequencies required by those chips.

[0017] Optionally, the above method further includes: receiving preset frequency information sent by a network device through a pluggable interface, wherein the preset frequency information indicates a preset frequency, so that the clock conversion module can perform frequency conversion on the original clock signal according to the preset frequency required by the network device, thereby providing the network device with a clock signal at the frequency required by the network device according to the needs of the network device.

[0018] Optionally, the pluggable interface includes multiple output pins, and the above method further includes: the multiple output pins output multiple clock signals to the network device, thereby providing clock signals to different chips in the network device, so that different chips can synchronize clocks according to the clock signals they receive, and meet the clock synchronization requirements of their own services.

[0019] Optionally, the clock generator is integrated as a component of the passive clock device onto the circuit board of the passive clock device, or the components of the clock generator are distributed and integrated onto the circuit board of the passive clock device to reduce the size of the passive clock device and improve its portability.

[0020] Thirdly, a single-board unit is provided, comprising a connector, a clock generator, and a clock synchronization module. The connector and the clock generator are respectively connected to the clock synchronization module. The connector is used to receive a first clock signal, i.e., a clock signal output by a passive clock device. The clock generator is used to generate a second clock signal, i.e., the single-board's own clock signal. The clock synchronization module is used to obtain a local clock signal based on the first and second clock signals, and, upon receiving a reference clock signal, to perform clock synchronization based on the reference clock signal and the local clock signal. That is, the aforementioned single-board unit selects the clock signal output by the passive clock device and the clock signal generated by the clock generator for clock synchronization. The local clock signal is synchronized based on the selected local clock signal and the received reference clock signal when a reference clock signal is received. However, when no reference clock signal is received, compared with the clock signal generated by the local clock generator in related technologies, this board can output a clock signal with higher accuracy from the passive clock device than the clock signal generated by the local clock generator. This avoids affecting the communication between network devices and avoids integrating a high-precision clock generator on the board, reducing equipment and network deployment costs and avoiding resource waste.

[0021] Optionally, the aforementioned clock synchronization module is specifically used to select a local clock signal from the first clock signal and the second clock signal, so as to select a clock signal with higher clock accuracy from the first clock signal and the second clock signal for clock synchronization, thereby improving the accuracy of clock synchronization.

[0022] Optionally, the aforementioned clock synchronization module is used to detect the first clock signal and the second clock signal based on the reference clock signal, and select a local clock signal from the first clock signal and the second clock signal based on the detection result. By detecting the first clock signal and the second clock signal before selecting the local clock signal, it is possible to avoid mistakenly selecting the abnormal clock signal as the local clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0023] Optionally, the clock synchronization module is used to select the first clock signal as the local clock signal when the first clock signal is received. That is, the clock synchronization module defaults to the first clock signal having a higher priority or performance than the second clock signal. Once the first clock signal is received, the first clock signal is selected as the local clock signal to realize clock synchronization based on the clock signal with higher precision.

[0024] Optionally, the aforementioned clock synchronization module is specifically used to synchronize the second clock signal based on the first clock signal to obtain a local clock signal, so as to synchronize the clock signal generated by the local clock generator into a higher-precision clock signal output by the passive clock device, thereby improving the accuracy of clock synchronization based on the local clock signal.

[0025] Optionally, the aforementioned clock synchronization module is used to detect the first clock signal and the second clock signal based on the reference clock signal, and to synchronize the second clock signal based on the detection result and the first clock signal to obtain a local clock signal. By detecting the first clock signal and the second clock signal before obtaining the local clock signal, it is possible to avoid incorrectly obtaining the local clock signal based on the abnormal clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0026] Optionally, the aforementioned clock synchronization module is also used to perform clock synchronization based on the local clock signal when no reference clock signal is received. This enables the module to maintain a high-precision clock based on the local clock signal when no reference clock signal is received, thus avoiding any impact on communication services.

[0027] Optionally, the connector is connected to the service board of the network device. The connector is used to receive a first clock signal from the service board, so that even if there is no port on the board for connecting to the passive clock device, the board can receive the clock signal output by the passive clock device through the service board and then perform clock synchronization based on the clock signal.

[0028] Optionally, the connector is further configured to receive the temperature corresponding to the first clock signal, and the clock synchronization module is further configured to compensate the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, the accuracy of the first clock signal can be improved by compensating the first clock signal based on temperature, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0029] Fourthly, a clock synchronization method is provided, applied to a single-board unit. The single-board unit includes a connector, a clock generator, and a clock synchronization module. The connector and clock generator are respectively connected to the clock synchronization module. The method includes: the connector receiving a first clock signal, i.e., a clock signal output by a passive clock device; the clock generator generating a second clock signal, i.e., the single-board unit's own clock signal; the clock synchronization module acquiring a local clock signal based on the first and second clock signals; and, upon receiving a reference clock signal, performing clock synchronization based on the reference clock signal and the local clock signal. In other words, the above method selects the appropriate clock signal from the clock signal output by the passive clock device and the clock signal generated by the clock generator. For local clock signals used for clock synchronization, when a reference clock signal is received, clock synchronization is performed based on the selected local clock signal and the received reference clock signal. However, when no reference clock signal is received, compared to the clock signal generated by the local clock generator in related technologies, this method outputs a clock signal with higher accuracy from the passive clock device than the clock signal generated by the local clock generator. This avoids affecting communication between network devices and also avoids integrating a high-precision clock generator on a single board, reducing equipment and network deployment costs and preventing resource waste.

[0030] Optionally, the clock synchronization module obtains a local clock signal based on the first clock signal and the second clock signal by selecting a local clock signal from the first clock signal and the second clock signal, so as to select a clock signal with higher clock accuracy from the first clock signal and the second clock signal for clock synchronization, thereby improving the accuracy of clock synchronization.

[0031] Optionally, the clock synchronization module selects a local clock signal from the first clock signal and the second clock signal by: detecting the first clock signal and the second clock signal based on the reference clock signal, and selecting a local clock signal from the first clock signal and the second clock signal based on the detection result. By detecting the first clock signal and the second clock signal before selecting the local clock signal, it is possible to avoid mistakenly selecting an abnormal clock signal as the local clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0032] Optionally, the clock synchronization module selects the local clock signal from the first clock signal and the second clock signal by: when the clock synchronization module receives the first clock signal, it selects the first clock signal as the local clock signal. That is, the clock synchronization module defaults to the first clock signal having a higher priority or performance than the second clock signal. Once the first clock signal is received, the clock synchronization module selects the first clock signal as the local clock signal, thereby realizing clock synchronization based on the clock signal with higher precision.

[0033] Optionally, the clock synchronization module obtains a local clock signal based on the first clock signal and the second clock signal by: the clock synchronization module performs clock synchronization on the second clock signal based on the first clock signal to obtain a local clock signal, so as to synchronize the clock signal generated by the local clock generator into a higher-precision clock signal output by the passive clock device, thereby improving the accuracy of clock synchronization based on the local clock signal.

[0034] Optionally, the clock synchronization module above synchronizes the second clock signal with the first clock signal to obtain a local clock signal by: detecting the first clock signal and the second clock signal based on a reference clock signal, and synchronizing the second clock signal with the detection result and the first clock signal to obtain a local clock signal. By detecting the first clock signal and the second clock signal before obtaining the local clock signal, it is possible to avoid incorrectly obtaining the local clock signal based on the abnormal clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0035] Optionally, the above method further includes: when the clock synchronization module does not receive a reference clock signal, it performs clock synchronization based on the local clock signal, which can maintain a high-precision clock based on the local clock signal when no reference clock signal is received, thus avoiding the impact on communication services.

[0036] Optionally, the connector is connected to the service board of the network device, and the method further includes: the connector receiving a first clock signal from the service board, so that when there is no port on the board for connecting to the passive clock device, the board can receive the clock signal output by the passive clock device through the service board, and then perform clock synchronization according to the clock signal.

[0037] Optionally, the above method further includes: the connector receiving the temperature corresponding to the first clock signal, and the clock synchronization module compensating the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, the accuracy of the first clock signal can be improved by compensating the first clock signal based on temperature, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0038] Fifthly, a single-board unit is provided, comprising a connector, a clock generator, and a clock synchronization module. The connector and clock generator are respectively connected to the clock synchronization module. The connector receives a first clock signal, i.e., the clock signal output by a passive clock device. The clock generator generates a local clock signal. The clock synchronization module performs clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received, and performs clock synchronization based on the first clock signal and the local clock signal when no reference clock signal is received. Therefore, when no reference clock signal is received, compared to related technologies that output clock signals generated by local clock generators, this single-board unit, even when the accuracy of the clock signal provided by the passive clock device is higher than that generated by the local clock generator, can output a clock signal with higher synchronization accuracy from the passive clock device, avoiding interference with communication between network devices. It also avoids integrating a high-precision clock generator on the single-board unit, reducing equipment and network deployment costs and preventing resource waste.

[0039] Optionally, the connector is connected to the service board of the network device. The connector is used to receive a first clock signal from the service board, so that even if there is no port on the board for connecting to the passive clock device, the board can receive the clock signal output by the passive clock device through the service board and then perform clock synchronization based on the clock signal.

[0040] Optionally, the connector is also used to receive the temperature corresponding to the first clock signal, and the clock synchronization module is also used to compensate the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, the accuracy of the first clock signal can be improved by compensating the first clock signal based on the temperature, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0041] Sixthly, a clock synchronization method is provided. This method includes: a single board receiving a first clock signal, i.e., a clock signal output by a passive clock device, and the single board generating a local clock signal; when a reference clock signal is received, clock synchronization is performed based on the reference clock signal and the local clock signal; when no reference clock signal is received, clock synchronization is performed based on the first clock signal and the local clock signal. Based on this, when no reference clock signal is received, compared to the related art which outputs a clock signal generated by a local clock generator, this method, even when the accuracy of the clock signal provided by the passive clock device is higher than that generated by the local clock generator, can output a clock signal with higher synchronization accuracy provided by the passive clock device, avoiding impact on communication between network devices. It also avoids integrating a high-precision clock generator on the single board, reducing equipment and network deployment costs and preventing resource waste.

[0042] Optionally, the above-mentioned single board receiving the first clock signal includes: the single board receiving the first clock signal from the service board, so that when there is no port on the single board for connecting to the passive clock device, the single board can receive the clock signal output by the passive clock device through the service board, and then perform clock synchronization according to the clock signal.

[0043] Optionally, the above method further includes: the single board receiving the temperature corresponding to the first clock signal, and compensating the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, compensating the first clock signal based on temperature can improve the accuracy of the first clock signal, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0044] In a seventh aspect, a network device is provided, the network device comprising the single board provided in either the third or fifth aspect described above.

[0045] Eighthly, a communication system is provided, comprising the passive clock device provided in the first aspect and the network device provided in the seventh aspect, wherein the network device is connected to the passive clock device.

[0046] In a ninth aspect, a clock chip is provided, the clock chip including a clock synchronization module in a single board provided by either the third or fifth aspect, or the clock chip including a clock synchronization module and a connector in a single board provided by either the third or fifth aspect.

[0047] In a tenth aspect, a clock chip is provided, which includes the clock generator in the passive clock device provided in the first aspect.

[0048] Eleventhly, a computer-readable storage medium is provided, which stores at least one piece of program code that is read by a processor to cause a passive clock device to perform a clock signal output method as provided in the above two aspects or various alternative implementations of the second aspect.

[0049] In a twelfth aspect, a computer-readable storage medium is provided, which stores at least one piece of program code that is read by a processor to cause a network device to perform a clock synchronization method as provided in the above four aspects or various alternative implementations of the fourth aspect.

[0050] In a thirteenth aspect, a computer-readable storage medium is provided, which stores at least one piece of program code that is read by a processor to cause a network device to perform a clock synchronization method as provided in the above-described sixth aspect or various alternative implementations of the sixth aspect.

[0051] In a fourteenth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor of a passive clock device reading the program code from the computer-readable storage medium, the processor executing the program code, causing the passive clock device to perform a clock signal output method as provided in the above two aspects or various alternative implementations of the second aspect.

[0052] In a fifteenth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor of a network device reading the program code from the computer-readable storage medium, the processor executing the program code, causing the network device to perform a clock synchronization method as provided in the above four aspects or various alternative implementations of the fourth aspect.

[0053] In a sixteenth aspect, a computer program product or computer program is provided, the computer program product or computer program including program code stored in a computer-readable storage medium, a processor of a network device reading the program code from the computer-readable storage medium, the processor executing the program code, causing the network device to perform the clock synchronization method provided in the above six aspects or various alternative implementations of the sixth aspect.

[0054] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the structure of a communication network provided in an embodiment of this application;

[0056] Figure 2 This is a schematic diagram of another communication network structure provided in an embodiment of this application;

[0057] Figure 3 This is a schematic diagram of another communication network structure provided in an embodiment of this application;

[0058] Figure 4 This is a schematic diagram of another communication network structure provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the structure of a single board provided in an embodiment of this application;

[0060] Figure 6 This is a schematic diagram of the structure of a network device provided in an embodiment of this application;

[0061] Figure 7 This is a schematic diagram of another single-board structure provided in an embodiment of this application;

[0062] Figure 8 This is a schematic diagram of another single-board structure provided in an embodiment of this application;

[0063] Figure 9 This is a schematic diagram of the structure of a passive clock device provided in an embodiment of this application;

[0064] Figure 10 This is a schematic diagram of another passive clock device provided in an embodiment of this application. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0066] To facilitate understanding, the key terms and concepts involved in this application will be explained below.

[0067] Clock synchronization refers to the process of keeping the clocks of different devices, systems, or networks consistent. Clock synchronization ensures the normal operation of network communication, guarantees data consistency within the network, and optimizes task scheduling. For example, in communication networks, the timer functions in many network protocols (such as the Transmission Control Protocol / Internet Protocol (TCP / IP) suite) rely on accurate clocks. If the clocks of multiple devices in a communication network are not synchronized, it may lead to problems such as incorrect packet timeout judgments. For instance, after a device in a communication network sends a data packet, it sets a timeout retransmission timer based on its local clock. If the device does not receive an acknowledgment message from the receiving end within the preset time, it will retransmit the data packet. If the clocks of the sending and receiving ends are not synchronized, the receiving end may believe that the data packet has been correctly received (because the receiving end's clock shows that the acknowledgment message was sent within the preset time), but the sending end, due to the clock difference, may mistakenly believe that the data packet has been lost and perform unnecessary retransmission. For example, a computing cluster consists of multiple computing nodes that may operate on data simultaneously. Consistent clock speeds across these nodes ensure the accurate time sequence of operations performed on the data, facilitating data updates, backups, and recovery. Furthermore, in cloud computing or cluster computing scenarios, a task typically requires the collaborative execution of multiple computing nodes. Clock synchronization provides a unified time base for task scheduling, enabling tasks to start, execute, and terminate accurately on each computing node according to a pre-set schedule.

[0068] Clock source: This is the source that provides the clock signal, used to provide a clock (such as time or frequency) to the device. It can be a crystal oscillator, atomic clock, or ceramic resonator, etc. Network device clock sources are divided into local clock sources and external clock sources. The local clock source of a network device is integrated on the main control board and generates the clock signal using its internal components. The external clock source of a network device is located outside the device and is integrated into a dedicated device or system (such as a satellite) for providing clock signals. For example, the passive clock device described below is an example of an external clock source for network devices.

[0069] Time reference source: It is the source that provides a high-precision and high-stability time reference, and the time signal it generates is used as a basis for measuring whether other time signals are accurate.

[0070] The Precision Clock Synchronization Protocol Standard for Network Measurement and Control Systems (IEEE 1588) is a clock synchronization protocol, often simply referred to as the 1588 protocol. IEEE stands for Institute of Electrical and Electronics Engineers. The 1588 protocol achieves high-precision clock synchronization by transmitting precise timestamp information between network devices. Accordingly, the communication network includes a master clock device and slave clock devices. The master clock periodically sends synchronization messages (sync messages) to the slave clocks. This synchronization message is the core message of the 1588 protocol, carrying timestamp information. Based on this timestamp information and its local clock, the slave clock calculates the network delay and time offset, and adjusts its local clock accordingly to synchronize with the master clock.

[0071] A building integrated timing system (BITS) is a standalone system or device in a communication network that provides a precise clock. The BITS receives high-precision clock signals from satellites or atomic clocks and, based on these signals, provides a unified clock signal for devices within the communication network to synchronize.

[0072] 1588 Server: A device that achieves high-precision clock synchronization based on the 1588 protocol. The 1588 server is used to receive high-precision clock signals from satellites or atomic clocks, perform clock synchronization based on these high-precision clock signals, and send the synchronized clock to downstream devices (such as routers, switches, or base stations) through the 1588 protocol so that downstream devices can synchronize their clocks according to the clock from the 1588 server.

[0073] Reference clock signal: A high-precision and stable periodic signal used to provide a unified time reference or synchronization signal for network devices and base stations in a communication network. Reference clock signals can be implemented as clock signals output by BITS, clock signals output by 1588 servers in a communication network, or clock signals output by network devices in a communication network that integrate high-precision clock sources, etc.

[0074] The application scenarios of this application are described below.

[0075] This application can be applied to communication networks. Figure 1This is a schematic diagram of the structure of a communication network provided in an embodiment of this application. The communication network may be a fourth-generation mobile communication technology (4G) network or a 5G network, etc., and this embodiment of the application does not limit it.

[0076] like Figure 1 As shown, the communication network 10 includes multiple base stations and multiple network devices. Figure 1 The number of base stations and network devices shown is merely an example, and this application does not limit the scope of the embodiments. These multiple base stations and network devices are divided into an access layer, an aggregation layer, and a core layer, which are sequentially connected. The base station, as an edge device of the access layer, provides communication services to the user's terminal within a certain coverage area by transmitting and receiving radio waves. Accordingly, after receiving data from a terminal, the base station, through the network devices connected to it, sequentially transmits the data to the access layer, aggregation layer, and core layer. The network devices in the core layer then, according to the destination address of the data, sequentially transmit the data through the aggregation layer and access layer to the base station corresponding to the destination address, ensuring that different users can communicate with each other through the base stations. During the above communication process, to ensure the reliability of data transmission, the multiple base stations in the communication network need to maintain clock synchronization; that is, the multiple base stations operate at the same time, or the multiple base stations transmit data at the same frequency. Taking the clock frequency as an example, suppose base station A receives a service from a terminal (e.g., a voice call) and needs to send it to another user through communication network 10. However, during the service communication, the terminal may move from the area served by base station A to the area served by base station B (e.g., the terminal is on a fast-moving car or train). In order to ensure that the service is not interrupted, the clocks of base station A and base station B need to be synchronized with each other. Otherwise, the service will be interrupted during the terminal's movement.

[0077] To ensure clock synchronization among multiple base stations in a communication network, 1588 clock synchronization technology can be used. For example, ... Figure 1 As shown, the communication network 10 also includes a BITS. Figure 1The number of BITSs shown is merely an example; the number of BITSs in a communication network can be one or more, and this application embodiment does not limit this. BITSs are used to track the clocks of satellites or atomic clocks. Network devices and base stations in communication network 10 achieve clock synchronization by tracking the clocks of the BITSs. Accordingly, the BITS receives clock signals from satellites or atomic clocks, obtains a high-precision clock based on these signals, and transmits the clock layer by layer through the core layer, aggregation layer, and access layer of communication network 10, providing the clock to the terminal base station. The base station performs clock synchronization based on this clock. In the above process, if a network device in communication network 10 has clock synchronization capabilities, it performs clock synchronization based on the received clock and then forwards the synchronized clock to downstream devices. If a network device does not have clock synchronization capabilities, it forwards the received clock to downstream devices.

[0078] In some embodiments, each hop in the clock transmission process has clock synchronization capability (i.e., the ability to process the 1588 protocol), and can perform clock synchronization according to the received clock to achieve hop-by-hop synchronization. In other embodiments, some network devices in the communication network do not have clock synchronization capability and only forward the received clock. The following describes... Figures 2 to 4 The clock synchronization process under the two conditions described above will be explained respectively.

[0079] Figure 2 This is a schematic diagram of the structure of a communication network provided in an embodiment of this application, such as... Figure 2 As shown, the communication network includes a 1588 server, a base station, and multiple network devices, also known as network elements (NEs). These network devices are NE1 to NE3, and all NE1 to NE3 have clock synchronization capabilities. The 1588 server is connected to NE1, NE1 is connected to NE2, NE2 is connected to NE3, and NE3 is connected to the base station. It should be noted that... Figure 2 The number of 1588 servers, network devices, and base stations in the illustrated communication network is merely an example. The number of 1588 servers, network devices, and base stations in the communication network can be one or more, and this application does not limit this. Figure 2 The connection methods of the 1588 server, network devices and base stations are merely examples, and the embodiments of this application do not limit the connection methods of the 1588 server, network devices and base stations in the communication network.

[0080] exist Figure 2In the communication network shown, the 1588 server receives a clock from a satellite or other clock source, synchronizes its clock based on this clock, and then transmits the synchronized clock to NE1 via the 1588 protocol. NE1, after receiving the clock from the 1588 server via the 1588 protocol, synchronizes its clock based on this clock and then transmits the synchronized clock to the next hop, and so on, until the clock is transmitted to the base station. The base station then synchronizes its clock based on the received clock. Taking NE1 as an example, in the clock synchronization process... Figure 3 As shown, the main control board of NE1 integrates a local clock source and a clock synchronization module. The local clock source and the clock synchronization module are connected. The local clock source is used to generate a local clock signal. The clock synchronization module is used to synchronize the local clock according to the received clock and the local clock signal during the clock synchronization process. After that, the synchronized clock is passed to the next hop (i.e., NE2).

[0081] In the above Figure 2 In the communication network shown, if the link between network devices is broken, for example, the link between NE2 and NE3, NE3 cannot receive an external high-precision clock and can only rely on its local clock source to maintain its local clock and transmit it to the base station. If NE3's local clock source is a low-precision clock source such as a common crystal oscillator, the local clock precision maintained by NE3 will be low, which will affect the normal communication between NE3 and the base station. If NE3's local clock source is a high-precision clock source such as a high-performance crystal oscillator or a rubidium atomic clock, it can ensure that the base station can still communicate normally for a certain period of time. However, since NE3 itself integrates a high-precision clock source, the equipment cost and network deployment cost will be relatively high, and it may also lead to resource waste.

[0082] Figure 4 This is a schematic diagram of another communication network structure provided in an embodiment of this application, such as... Figure 4 As shown, the communication network includes a 1588 server, a base station, and multiple network devices, namely NE4 to NE6. NE4 and NE5 do not have 1588 clock synchronization capability, while NE6 does. The 1588 server is connected to NE4, NE4 is connected to NE5, NE5 is connected to NE6, and NE6 is connected to the base station. It should be noted that... Figure 4 The number of 1588 servers, network devices, and base stations in the illustrated communication network is merely an example. The number of 1588 servers, network devices, and base stations in the communication network can be one or more, and this application does not limit this. Figure 4 The connection methods of the 1588 server, network devices and base stations are merely examples, and the embodiments of this application do not limit the connection methods of the 1588 server, network devices and base stations in the communication network.

[0083] exist Figure 4 In the communication network shown, the 1588 server receives a clock from a satellite or other clock source, synchronizes its clock based on this clock, and then transmits the synchronized clock to NE4 via the 1588 protocol. NE4 forwards the clock to NE5, and NE5 then forwards the clock to NE6. NE6 synchronizes its clock based on the received clock and then transmits the synchronized clock to the base station. The base station synchronizes its clock based on the received clock. The clock synchronization process of NE6 is similar to that of NE1 described above, and will not be repeated here in this embodiment.

[0084] In the above Figure 4 In the communication network shown, the clock delays of NE4 and NE5 are not fixed, which can cause jitter in the clock received by NE6. To avoid reduced clock synchronization accuracy due to clock jitter, NE6 filters the received clock. During filtering, NE6 relies on its local clock source to briefly maintain its local clock and transmits this local clock to the base station. If the local clock source of NE6 is a low-precision clock source such as a common crystal oscillator, the local clock accuracy maintained by NE6 during this brief period will be low. This low-precision local clock will affect the accuracy of base station synchronization. When the base station synchronization accuracy cannot meet the clock requirements of base station services, it will affect the normal communication of base station services. If the local clock source of NE6 is a high-precision clock source such as a high-performance crystal oscillator or a rubidium atomic clock, it can guarantee the synchronization accuracy of the base station and the normal communication of base station services for a certain period of time. However, since a high-precision clock source is integrated into NE6, the equipment cost and network deployment cost will be relatively high, and it may also lead to resource waste.

[0085] To address the issues of high equipment and network deployment costs, as well as resource waste, this application provides a pluggable passive clock device. This passive clock device can serve as a portable external clock source, plugged into network devices to provide high-precision clock signals. This eliminates the need to integrate a high-precision clock source within the network device, reducing equipment and network deployment costs. Furthermore, this passive clock device can be flexibly installed on network devices requiring high-precision clock synchronization, further avoiding resource waste.

[0086] Based on this pluggable passive clock device, embodiments of this application provide an adaptable board, which can be implemented as a main control board in a network device, etc., and embodiments of this application do not limit this. One type of board receives a clock signal provided by the passive clock device, selects a local clock signal from the clock signal provided by the passive clock device and a clock signal generated by the board's local clock generator, and then performs clock synchronization based on the local clock signal and a reference clock signal in the communication network. The reference clock signal can be a high-precision clock signal from a 1588 server or other network devices in the communication network. Another type of board receives a clock signal provided by the passive clock device, synchronizes the clock signal generated by the board's local clock generator based on the clock signal provided by the passive clock device, thereby synchronizing the clock signal generated by the local clock generator with the clock signal provided by the passive clock device, using the synchronized clock signal as the local clock signal, and then performs clock synchronization based on the local clock signal and the reference clock signal. The two types of boards mentioned above acquire a local clock signal based on the clock signal provided by the passive clock device and the clock signal generated by the local clock generator on the board. Then, they synchronize the clock based on the local clock signal and the reference clock signal. There is also a type of board that receives the clock signal provided by the passive clock device. When the reference clock signal can be received, it synchronizes the clock based on the reference clock signal and the clock signal generated by the local clock generator on the board. When the reference clock signal is not received, it synchronizes the clock based on the clock signal provided by the passive clock device and the clock signal generated by the local clock generator on the board.

[0087] The structure of the various single boards mentioned above and the process of clock synchronization based on each single board are explained below.

[0088] Figure 5 This is a schematic diagram of the structure of a single board provided in an embodiment of this application. Figure 5The illustrated board selectively uses the clock signal provided by the passive clock device. Specifically, the board can not only receive the aforementioned reference clock signal and generate a clock signal via its onboard local clock generator, but also connect to the passive clock device provided in this embodiment to receive the clock signal from the passive clock device. It then selects a local clock signal from the clock signal provided by the passive clock device and the clock signal generated by the local clock generator. When the reference clock signal is received, the board performs clock synchronization based on the local clock signal and the reference clock signal. When the reference clock signal is not received, the board can select a clock signal with higher clock accuracy from the clock signal provided by the passive clock device and the clock signal generated by the local clock generator, using this clock signal as the local clock signal and outputting it, or outputting clock information obtained based on this local clock signal. Based on this, in the absence of a reference clock signal, compared with the clock signal generated by the local clock generator in related technologies, the single board provided in this application embodiment can output a higher precision clock signal provided by the passive clock device when the precision of the clock signal provided by the passive clock device is higher than that of the clock signal generated by the local clock generator. This avoids affecting the communication between network devices and also avoids integrating a high-precision clock generator on the single board, reducing equipment costs and network deployment costs, and avoiding resource waste.

[0089] like Figure 5 As shown, the single board 500 includes a connector 501, a clock generator 502, and a clock synchronization module 503. The connector 501 is directly or indirectly connected to a passive clock device and is used to receive the clock signal output by the passive clock device. The clock generator 502 serves as the local clock generator of the single board 500 and is used to generate the clock signal of the single board 500 itself. The connector 501 and the clock generator 502 are respectively connected to the clock synchronization module 503. Accordingly, the clock synchronization module 503 is used to select the local clock signal of the single board 500 from the clock signal received from the connector 501 and the clock signal generated by the clock generator 502, and, when a reference clock signal is received, performs clock synchronization based on the reference clock signal and the selected local clock signal. It should be noted that when connector 501 is directly connected to the passive clock device, it means that the passive clock device is directly inserted into connector 501, and connector 501 can directly receive the clock signal output by the passive clock device. When connector 501 is indirectly connected to the passive clock device, it means that connector 501 is connected to the service board of the network device, the passive clock device is inserted into the service board, and connector 501 receives the clock signal output by the passive clock device through the service board.

[0090] Next, the connector 501, clock generator 502 and clock synchronization module 503 will be described respectively.

[0091] (1) Connector 501 is used to receive a first clock signal. The first clock signal is the clock signal provided by the passive clock device described above. Connector 501 is implemented as a port or pin, such as a gigabit Ethernet (GE) port or a pin for connecting to other boards. When connector 501 is implemented as a port, it is directly and pluggably connected to the passive clock device to receive the first clock signal from it. When connector 501 is implemented as a pin, it is connected to other boards, indirectly connecting to the passive clock device through these other boards, and receiving the first clock signal from the passive clock device through these other boards. The cases where connector 501 is implemented as a port and a pin are described below.

[0092] In some embodiments, connector 501 is implemented as a port, such as a GE port or a 10GE port. Figure 5 As shown, the connector 501 is used for pluggable connection with a passive clock device, receiving a first clock signal output by the passive clock device, and transmitting the first clock signal to the clock synchronization module 503. Accordingly, the connector 501 includes a physical layer (PHY) chip. The connector 501 receives the signal output by the passive clock device through the PHY chip, extracts the first clock signal from the received signal, and transmits the extracted first clock signal to the clock synchronization module 503.

[0093] In some embodiments, connector 501 is implemented as a pin, which is used to connect with other boards and receive clock signals from other boards, such as service boards of network devices. These service boards perform services such as message sending and receiving, and can also receive clock signals (e.g., 1588 messages). After receiving the clock signal, they send it to the aforementioned board, which then synchronizes its clock based on the clock signal. The service board can also receive clock signals from the aforementioned board and adjust its own clock accordingly to ensure synchronization with the clock of the aforementioned board. Of course, the service board can also send clock signals to other network devices or base stations; this embodiment does not limit this. Accordingly, connector 501 is connected to the service board of the network device to receive a first clock signal from the service board. For example, as... Figure 6 As shown, the single board provided in this embodiment is implemented as the main control board 601 of a network device, and the other single boards mentioned above are implemented as multiple service boards 602 in the network device. The main control board 601 is connected to the multiple service boards 602 through pins located on it, and receives the clock signal output by the service boards 602 through these pins. It should be noted that... Figure 6The connections shown are merely examples and do not limit the connection relationships between the single boards provided in this application embodiment and other single boards. For example, the main control board of the network device can also be connected to a service board of the network device, or the service board of the network device is integrated on the main control board, etc. Figure 6 As shown, the service board 602 includes a port 6021, which is used to be pluggably connected to a passive clock device, receive a first clock signal output by the passive clock device, and output the first clock signal to the connector 501 through the lines on the service board 602.

[0094] The above description uses the example of the service board 602 directly outputting a first clock signal from a passive clock device to the connector 501. In some embodiments, the service board 602 further includes a clock generator 6022 and a clock synchronization module 6023. The clock generator 6022 is connected to the clock synchronization module 6023, which is connected in series between the port 6021 and the connector 501. The clock generator 6022 generates a local clock signal for the service board 602, and the clock synchronization module 6023 performs clock synchronization based on the first clock signal received at the port 6021 and the local clock signal generated by the clock generator 6022, and outputs the synchronized clock signal to the connector 501. Accordingly, in this embodiment, the first clock signal received by the connector 501 on the board 500 can be a clock signal output by a passive clock device, or it can be a clock signal synchronized by the other boards based on the clock signal output by the passive clock device.

[0095] In some embodiments, connector 501 is also used to receive the temperature corresponding to the first clock signal and transmit the temperature to clock synchronization module 503 through the line on board 500 connected to clock synchronization module 503.

[0096] (2) Clock generator 502 is used to generate a second clock signal. The second clock signal is the clock signal of the single board 500 itself, and the clock generator 502 is implemented as a clock source such as a crystal oscillator.

[0097] In this embodiment, the clock generator 502 generates a second clock signal and transmits the second clock signal to the clock synchronization module 503 through the line connected to the clock synchronization module 503 on the single board 500.

[0098] (3) Clock synchronization module 503 is used to select a local clock signal from the first clock signal and the second clock signal, and to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received.

[0099] The clock synchronization module 503 is implemented as hardware such as a clock chip, or as a component consisting of a selector and a clock chip. Accordingly, the clock synchronization module 503 includes a selector and a clock chip, which are connected. The selector is also connected to connector 501 and clock generator 502. Optionally, the clock chip is also connected to connector 501 and clock generator 502; this embodiment does not limit this. Correspondingly, the clock chip includes some or all of the components of the clock synchronization module 503; this embodiment does not limit this. The clock synchronization module 503 is integrated on a single board 500 and connected to connector 501 and clock generator 502 via lines on the single board 500. The reference clock signal is a high-precision clock signal from a BITS, 1588 server, or a network device integrated with a high-precision clock source, as described above. Figure 2 or Figure 4The reference clock signal is transmitted between multiple network elements in a communication network. This reference clock signal can be implemented as a square wave or sine wave, etc., and is used to indicate clock information. Alternatively, the reference clock signal can be implemented as a message carrying clock information, such as the message used in the 1588 protocol. This clock information is either time or frequency; this embodiment does not limit the specific implementation. In some embodiments, the board 500 includes a first connector, which is a connector other than the aforementioned connector 501. This first connector is implemented as a port, etc., and is connected to the clock synchronization module 503 via lines on the board 500. The first connector is used to connect to other network devices in the communication network, receive the reference clock signal transmitted through other network devices, and transmit the reference clock signal to the clock synchronization module 503. In some embodiments, the first connector is integrated into the clock synchronization module 503, in which case the clock synchronization module 503 receives the reference clock signal; this embodiment does not limit the specific implementation. In some embodiments, the board 500 includes a second connector, which is a connector other than the connector 501 described above. This second connector may be the same as or different from the first connector described above. The second connector is implemented as a port or pin and is connected to the clock synchronization module 503 via lines on the board 500. The second connector is used to connect to a service board in a network device. The service board is used to connect to other network devices in the communication network, receive a reference clock signal transmitted through other network devices, and then output a reference clock signal to the second connector. The second connector is used to receive the reference clock signal from the service board. This process is similar to the process by which the connector 501 receives the first clock signal from the service board 602, and will not be described again in this embodiment. In some embodiments, the second connector is integrated into the clock synchronization module 503, in which case the clock synchronization module 503 receives the reference clock signal. This embodiment does not limit this aspect. In some embodiments, the clock synchronization module 503 receives multiple candidate reference clock signals through multiple first connectors or multiple second connectors. Each candidate reference clock signal corresponds to a priority (such as a clock level). The clock synchronization module 503 determines the candidate reference clock signal with the highest priority among the multiple candidate reference clock signals as the reference clock signal.

[0100] In this embodiment, the clock synchronization module 503 receives the first clock signal and the second clock signal, selects one of the two clock signals as the local clock signal, and performs clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received. During the clock synchronization process, the clock synchronization module 503 obtains the error between the reference clock signal and the local clock signal based on the reference clock signal and the local clock signal, adjusts the local clock signal based on the error, and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. For example, when the reference clock signal and the local clock signal are implemented as square wave signals, the clock synchronization module obtains the phase difference between the reference clock signal and the local clock signal based on the reference clock signal and the local clock signal, adjusts the local clock signal based on the phase difference, and outputs the adjusted local clock signal.

[0101] In some embodiments, during the selection of a local clock signal from a first clock signal and a second clock signal, the clock synchronization module 503 selects the first clock signal as the local clock signal when it receives the first clock signal. That is, the clock synchronization module 503 assumes that the first clock signal has a higher priority or performance than the second clock signal. When the first clock signal is not received, the clock synchronization module 503 selects the second clock signal generated by the clock generator 502 as the local clock signal; conversely, once the first clock signal is received, the clock synchronization module 503 selects it as the local clock signal. Of course, the clock synchronization module 503 can also select the local clock signal based on the priority or performance of the first and second clock signals. For example, if the first and second clock signals each correspond to a priority, the clock synchronization module 503 selects the clock signal with the higher priority as the local clock signal. This embodiment does not limit this selection.

[0102] In some embodiments, during the process of selecting a local clock signal from the first clock signal and the second clock signal, the clock synchronization module 503 is used to detect the first clock signal and the second clock signal based on a reference clock signal, and select the local clock signal from the first clock signal and the second clock signal based on the detection result. Correspondingly, the clock synchronization module 503 performs frequency offset detection on the first clock signal and the second clock signal based on the reference clock signal; that is, the clock synchronization module 503 obtains a first error based on the reference clock signal and the first clock signal, which is the error between the reference clock signal and the first clock signal; obtains a second error based on the reference clock signal and the second clock signal, which is the error between the reference clock signal and the second clock signal; and obtains a third error based on the first clock signal and the second clock signal, which is the error between the first clock signal and the second clock signal. If the first error, the second error, and the third error are all less than a first threshold, the clock synchronization module 503 determines that neither the first clock signal nor the second clock signal is abnormal, and selects the first clock signal as the local clock signal; or, selects the clock signal with higher priority or performance from the first clock signal and the second clock signal as the local clock signal. If the first error is less than the first threshold, and the second and third errors are greater than or equal to the first threshold, then the clock synchronization module 503 determines that the second clock signal is abnormal and selects the first clock signal as the local clock signal from the first and second clock signals. If the first and third errors are greater than or equal to the first threshold, and the second error is less than the first threshold, then the clock synchronization module 503 determines that the first clock signal is abnormal and selects the second clock signal as the local clock signal from the first and second clock signals. By detecting the first and second clock signals before selecting the local clock signal, the clock synchronization module 503 can avoid mistakenly selecting the abnormal clock signal as the local clock signal when either the first or second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0103] In some embodiments, the clock synchronization module 503 can also detect the reference clock signal through the frequency offset detection process. Accordingly, if the first error and the second error are greater than or equal to the first threshold and the third error is less than the first threshold, the clock synchronization module 503 determines that the reference clock signal is abnormal, stops clock synchronization based on the reference clock signal, and instead performs clock synchronization based on the local clock signal, thereby avoiding clock synchronization based on the abnormal clock signal and improving the accuracy of clock synchronization.

[0104] In some embodiments, the clock synchronization module 503 is further configured to compensate the first clock signal based on the temperature corresponding to the first clock signal. For example, the clock synchronization module 503 records a fitting function that indicates the relationship between temperature and the frequency of the first clock signal. Based on the temperature of the first clock signal and the fitting function, the clock synchronization module 503 obtains the frequency deviation of the first clock signal, compensates the frequency of the first clock signal based on the frequency deviation, and performs subsequent selection of a local clock signal and clock synchronization based on the frequency-compensated first clock signal. The fitting function is obtained by fitting historical temperatures and historical frequencies of the first clock signal. The clock synchronization module 503, or other chips or devices, can perform this fitting process; this application embodiment does not limit this. For example, the clock synchronization module 503 records a compensation table, which includes the frequency deviation of the first clock signal at different temperatures. Based on the temperature corresponding to the first clock signal, the clock synchronization module 503 queries the compensation table to find the frequency deviation corresponding to that temperature. Based on this frequency deviation, it performs frequency compensation on the first clock signal. Then, based on the frequency-compensated first clock signal, it executes the subsequent process of selecting a local clock signal and performing clock synchronization based on the local clock signal. The compensation table is obtained based on historical temperatures and the frequencies of historical first clock signals. Since the frequency of the clock signal generated by the clock generator in the passive clock device is greatly affected by the temperature of the clock generator, the clock synchronization device 503 can improve the accuracy of the first clock signal by compensating for it based on temperature.

[0105] In some embodiments, the clock synchronization module 503 is used to perform clock synchronization based on a local clock signal when no reference clock signal is received. Accordingly, when no reference clock signal is received, the clock synchronization module 503 directly outputs the local clock signal, or directly outputs the clock information indicated by the local clock signal. Alternatively, the clock synchronization module 503 fits the error between the historical reference clock signal and the historical first clock signal based on the historical reference clock signal and the historical first clock signal to obtain a first fitting result, which indicates the change of the error between the historical reference clock signal and the historical first clock signal over time. The clock synchronization module 503 also fits the error between the historical reference clock signal and the historical second clock signal based on the historical reference clock signal and the historical second clock signal to obtain a second fitting result, which indicates the change of the error between the historical reference clock signal and the historical second clock signal over time. Both the first fitting result and the second fitting result can be implemented as a fitting curve, etc. After selecting the local clock signal from the first clock signal and the second clock signal, the clock synchronization module 503, in the absence of a reference clock signal, compensates and adjusts the local clock based on the local clock signal and its corresponding fitting result. Specifically, the clock synchronization module 503 predicts the error between the local clock signal and the reference clock signal based on the fitting result, adjusts the local clock signal according to the predicted error, and outputs the adjusted local clock signal, or the clock information indicated by the adjusted local clock signal. The fitting result corresponding to the local clock signal refers to: if the clock synchronization module 503 selects the first clock signal as the local clock signal, the fitting result is the first fitting result; if the clock synchronization module 503 selects the second clock signal as the local clock signal, the fitting result is the second fitting result. Furthermore, in the event of an abnormal reference clock signal, the clock synchronization module 503 can perform clock synchronization based on the local clock signal through the above process.

[0106] The above description is based on the example of the clock synchronization module 503 being implemented as a clock chip. In some embodiments, the connector 501 and the clock synchronization module 503 are implemented as clock chips. The clock chip is connected to the clock generator 502 through the lines on the single board 500. Accordingly, the clock chip includes the connector 501 and the clock synchronization module 503. This application does not limit this aspect.

[0107] The single-board provided in this application embodiment includes a connector, a clock generator, and a clock synchronization module. The connector is used to receive the clock signal output by the passive clock device, and the clock generator is used to generate the single-board's own clock signal. The connector and the clock generator are respectively connected to the clock synchronization module. The clock synchronization module is used to select the single-board's local clock signal from the clock signal received by the connector and the clock signal generated by the clock generator, and, when a reference clock signal is received, performs clock synchronization based on the reference clock signal and the selected local clock signal. Based on the above single-board, when the single-board does not receive a reference clock signal, compared with the clock signal generated by the local clock generator in related technologies, the single-board provided in this application embodiment can output a higher-precision clock signal provided by the passive clock device when the accuracy of the clock signal provided by the passive clock device is higher than that of the clock signal generated by the local clock generator. This avoids affecting the communication between network devices, and also avoids integrating a high-precision clock generator on the single-board, reducing equipment costs and network deployment costs, and avoiding resource waste.

[0108] The above content describes the hardware structure of the single board provided in the embodiments of this application. Next, in conjunction with... Figure 5 The structure of the clock synchronization module in this hardware architecture will be described.

[0109] like Figure 5 As shown, the clock synchronization module 503 includes a selector 5031, an error calculator 5032, and an adjuster 5033. The selector 5031 is connected to the connector 501, the clock generator 502, and the adjuster 5033. The error calculator 5032 is connected to the adjuster 5033. The selector 5031 selects a local clock signal from the first clock signal received from the connector 501 and the second clock signal generated by the clock generator 502. The error calculator 5032 and the adjuster 5033 perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received. This structure, by adding a selector to the clock synchronization module, allows the selector to select a local clock signal from the first and second clock signals for clock synchronization. This enables the output of a high-precision clock signal even when a reference clock signal is not received, avoiding interference with communication between network devices. It also avoids integrating a high-precision clock generator on a single board, reducing equipment and network deployment costs and preventing resource waste.

[0110] The selector 5031, error calculator 5032, and adjuster 5033 will be explained next.

[0111] Selector 5031 is used to receive a first clock signal from connector 501, receive a second clock signal generated by clock generator 502, select a local clock signal from the first clock signal and the second clock signal, and output the local clock signal to adjuster 5033. The process of the selector selecting the local clock signal is the same as the process of the clock synchronization module 503 selecting the local clock signal, and will not be described again in this embodiment.

[0112] Error calculator 5032 is used to receive a local clock signal from adjuster 5033. Upon receiving a reference clock signal, it obtains the error between the reference clock signal and the local clock signal based on the reference clock signal and the local clock signal, and outputs this error to adjuster 5033. The process of obtaining the error between the reference clock signal and the local clock signal is similar to the corresponding process performed by clock synchronization module 503 described above, and will not be repeated here. The error obtained by error calculator 5032 is either a time error or a frequency error; this embodiment does not limit the specific error to either.

[0113] Adjuster 5033 is used to receive the local clock signal from selector 5031 and the error from error calculator 5032. Based on the error, it adjusts the local clock signal and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. This process is similar to the corresponding process performed by clock synchronization module 503, and will not be described again in this embodiment. Furthermore, adjuster 5033 is also used to output the adjusted local clock signal to error calculator 5032 so that error calculator 5032 can calculate the error based on the adjusted local clock signal. Adjuster 5033 can be implemented as a frequency synthesizer or a time counter; this embodiment does not limit its implementation. When adjuster 5033 is implemented as a frequency synthesizer, error calculator 5032 is used to acquire and output the frequency error or phase error between the reference clock signal and the local clock signal. Adjuster 5033 adjusts the local clock signal based on the frequency error or phase error and outputs the adjusted local clock signal, or outputs the frequency information indicated by the adjusted local clock signal. When the adjuster 5033 is implemented as a time counter, the error calculator 5032 is used to acquire and output the time error between the reference clock signal and the local clock signal. The adjuster 5033 adjusts the local clock signal according to the time error and outputs the adjusted local clock signal, or outputs the time information indicated by the adjusted local clock signal.

[0114] In some embodiments, the adjuster 5033 is connected to the connector 501. The adjuster 5033 is also used to receive the temperature corresponding to the first clock signal or the frequency deviation related to the temperature corresponding to the first clock signal. When no reference clock signal is received and the first clock signal is selected as a local clock signal, the adjuster 5033 compensates the first clock signal based on the temperature corresponding to the first clock signal or the related frequency deviation, and outputs the compensated first clock signal, or outputs the clock information indicated by the compensated first clock signal. The temperature corresponding to the first clock signal is received by the adjuster 5033 from the connector 5031. The frequency deviation can be obtained by the frequency offset detection module 5034 based on the temperature received from the connector 501 and transmitted to the adjuster 5033. This embodiment does not limit this. Of course, when a reference clock signal is received and the first clock signal is selected as a local clock signal, the adjuster 5033 can also compensate the first clock signal based on the temperature corresponding to the first clock signal or the related frequency deviation, and then adjust the compensated first clock signal according to the error output by the error calculator 5032. This embodiment does not limit this.

[0115] In some embodiments, such as Figure 5 As shown, the clock synchronization module 503 also includes a frequency offset detection module 5034, which is connected to connector 501, clock generator 502, and selector 5031. The frequency offset detection module 5034 is also connected to a connector for receiving a reference clock signal. Figure 5 (Not shown in the diagram) Connection. The frequency offset detection module 5034 is used to detect the first clock signal and the second clock signal based on the reference clock signal when a reference clock signal is received, and output the detection result to the selector 5031 so that the selector 5031 can select the local clock signal from the first clock signal and the second clock signal according to the detection result. The frequency offset detection process performed by the frequency offset detection module 5034 is the same as the frequency offset detection process performed by the clock synchronization module 503, and will not be described again in this embodiment. In addition, the frequency offset detection module 5034 is also used to detect the reference clock signal through the above frequency offset detection process and output the detection result to the error calculator 5032. This detection process is the same as the corresponding process performed by the clock synchronization module 503, and will not be described again in this embodiment. If the detection result indicates that the reference clock signal is abnormal, the error calculator 5032 stops acquiring the error between the reference clock signal and the local clock signal, and the adjuster 5033 directly outputs the local clock signal or the clock information indicated by the local clock signal.

[0116] In some embodiments, the frequency offset detection module 5034 is also connected to the regulator 5033. The frequency offset detection module 5034 is also used to receive the temperature corresponding to the first clock signal from the connector 501, obtain the temperature-related frequency deviation of the first clock signal according to the temperature corresponding to the first clock signal, and output the frequency deviation to the regulator 5033 so that the regulator 5033 can perform frequency compensation on the first clock signal according to the frequency deviation.

[0117] In some embodiments, the frequency offset detection module 5034 is further configured to acquire the first fitting result and the second fitting result, and output the first fitting result and the second fitting result to the adjuster 5033 when no reference clock signal is received, so that the adjuster 5033 can predict the error of the local clock signal based on the fitting result corresponding to the local clock signal in the first fitting result and the second fitting result, and adjust the local clock signal according to the error. Alternatively, when no reference clock signal is received, the frequency offset detection module 5034 can determine the fitting result corresponding to the local clock signal based on the local clock signal selected by the selector 5031, and output the fitting result to the adjuster 5033. Or, when no reference clock signal is received, the frequency offset detection module 5034 can determine the fitting result corresponding to the local clock signal based on the local clock signal selected by the selector 5031, predict the error of the local clock signal based on the fitting result, and output the error to the adjuster 5033. This embodiment does not limit the scope of the embodiments.

[0118] It should be noted that the above Figure 5 The structure shown is illustrated using the clock selection module 503, which includes a selector 5031, an error calculator 5032, an adjuster 5033, and a frequency offset detection module 5034. It is also illustrated using the example of the selector, error calculator, adjuster, and frequency offset detection module being integrated onto a single clock chip. In some embodiments, the selector, error calculator, adjuster, and frequency offset detection module are distributed and integrated on a single board. Alternatively, one or more of these components can be integrated onto a single clock chip, with the remaining components distributed across the single board. For example, a single board may integrate a selector and a clock chip, with the clock chip including an error calculator, adjuster, and frequency offset detection module. This clock chip can perform the aforementioned process of compensating the first clock signal based on the temperature corresponding to the first clock signal. This embodiment of the application does not limit this specific implementation.

[0119] The above describes a scheme for clock synchronization by adding a selector to the single board, which selects the local clock signal from the clock signal output by the passive clock device and the clock signal generated by the local clock generator. The following section will combine... Figure 7This describes a scheme to add an error calculator and adjuster to the single board, and use these error calculator and adjuster to synchronize the clock signal generated by the local clock generator with the clock signal output by the passive clock device to obtain a local clock signal for clock synchronization.

[0120] Figure 7 This is a schematic diagram of the structure of a single board provided in an embodiment of this application. Figure 7 The illustrated board uses a passive clock device to track clock signals. Specifically, the board not only receives the reference clock signal and generates its own clock signal via a local clock generator, but also connects to the passive clock device provided in this embodiment. It receives the clock signal from the passive clock device and synchronizes it with the local clock generator's signal, resulting in a synchronized local clock signal. When a reference clock signal is received, the board synchronizes with both the local clock signal and the reference clock signal. When no reference clock signal is received, the board synchronizes the local clock signal with the passive clock device's signal, resulting in a more accurate local clock signal. This local clock signal is then used as the local clock signal, and either output as such or outputs clock information obtained based on it. Based on this, in the absence of a reference clock signal, compared with the clock signal generated by the local clock generator in related technologies, the single board provided in this application embodiment can output a high-precision clock signal that is synchronized with the clock signal provided by the passive clock device when the accuracy of the clock signal provided by the passive clock device is higher than that of the clock signal generated by the local clock generator. This avoids affecting the communication between network devices and also avoids integrating a high-precision clock generator on the single board, reducing equipment costs and network deployment costs, and avoiding resource waste.

[0121] like Figure 7As shown, the single board 700 includes a connector 701, a clock generator 702, and a clock synchronization module 703. The clock generator 702 serves as the local clock generator for the single board 700. The connector 701 and the clock generator 702 are respectively connected to the clock synchronization module 703. The connector 701 and the clock generator 702 are analogous to those of the connector 501 and the clock generator 502 described above, and will not be repeated here. The clock synchronization module 703 is used to synchronize the clock signal based on the clock signal received by the connector 701 and the clock signal generated by the clock generator 702. The synchronized clock signal is used as the local clock signal of the single board 700. Upon receiving a reference clock signal, clock synchronization is performed based on the reference clock signal and the local clock signal.

[0122] The following is about Figure 7 The clock synchronization module 703 in the single board shown will be described.

[0123] The clock synchronization module 703 is used to synchronize the second clock signal based on the first clock signal to obtain a local clock signal, and to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received.

[0124] The clock synchronization module 703 is implemented as a clock chip and other hardware. This module is integrated on a single-board 700 and connected to connector 701 and clock generator 702 via lines on the board 700. The reference clock signal is the same as described above. Figure 5 The reference clock signal received by the single board shown is similar.

[0125] In this embodiment, the clock synchronization module 703 receives the first clock signal and the second clock signal, obtains the error between the first clock signal and the second clock signal based on the first clock signal and the second clock signal, adjusts the second clock signal based on the error, thereby synchronizing the second clock signal with the first clock signal, and uses the adjusted second clock signal as the local clock signal. Subsequently, when the clock synchronization module 703 receives a reference clock signal, it obtains the error between the reference clock signal and the local clock signal based on the reference clock signal and the local clock signal, adjusts the local clock signal based on the error, and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. This process is similar to the clock synchronization process performed by the clock synchronization module 503 described above, and will not be repeated here.

[0126] In some embodiments, during the process of synchronizing a second clock signal based on a first clock signal to obtain a local clock signal, the clock synchronization module 703 is used to detect the first and second clock signals based on a reference clock signal, and to synchronize the second clock signal based on the detection result and the first clock signal to obtain the local clock signal. Correspondingly, the clock synchronization module 703 performs frequency offset detection on the first and second clock signals based on the reference clock signal and obtains a detection result. This frequency offset detection process is similar to the frequency offset detection process performed by the clock synchronization module 503 described above, and will not be repeated here. If the detection result indicates that neither the first nor the second clock signal is abnormal, the clock synchronization module 703 synchronizes the second clock signal based on the first clock signal. If the detection result indicates that the first clock signal is abnormal, the clock synchronization module 703 stops synchronizing the second clock signal based on the first clock signal and directly uses the second clock signal as the local clock signal. If the detection result indicates that the second clock signal is abnormal, the clock synchronization module 703 stops synchronizing the second clock signal based on the first clock signal and directly uses the first clock signal as the local clock signal. The clock synchronization module 703 detects the first clock signal and the second clock signal before acquiring the local clock signal. This avoids incorrectly acquiring the local clock signal based on the abnormal clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0127] In some embodiments, the clock synchronization module 703 can also detect the reference clock signal through the frequency offset detection process described above. This process is similar to the corresponding process performed by the clock synchronization module 503, and will not be described again in this embodiment. If the detection result indicates that the reference clock signal is abnormal, the clock synchronization module 703 stops clock synchronization based on the reference clock signal and instead performs clock synchronization based on the local clock signal, thereby avoiding clock synchronization based on abnormal clock signals and improving the accuracy of clock synchronization.

[0128] In some embodiments, the clock synchronization module 703 is further configured to compensate the first clock signal based on the temperature corresponding to the first clock signal. This process is similar to the corresponding process performed by the clock synchronization module 503 described above, and will not be repeated here in the embodiments of this application.

[0129] In some embodiments, the clock synchronization module 703 is used to perform clock synchronization based on the local clock signal when no reference clock signal is received. Accordingly, when no reference clock signal is received, the clock synchronization module 703 directly outputs the local clock signal, or directly outputs the clock information indicated by the local clock signal. Alternatively, the clock synchronization module 703 obtains a first fitting result and a second fitting result through a process similar to that of the clock synchronization module 503. When no reference clock signal is received, it compensates and adjusts the local clock based on the local clock signal and the fitting result corresponding to the local clock signal. This clock synchronization process is similar to the corresponding clock synchronization process performed by the clock synchronization module 503 described above, and will not be repeated here. The fitting result corresponding to the local clock signal refers to: if the local clock signal is a second clock signal synchronized with the first clock signal, then the fitting result corresponding to the local clock signal is the first fitting result; if the local clock signal is the first clock signal, then the fitting result corresponding to the local clock signal is the first fitting result; if the local clock signal is the second clock signal, then the fitting result corresponding to the local clock signal is the second fitting result. Furthermore, in the event of an abnormal reference clock signal, the clock synchronization module 703 can perform clock synchronization based on the local clock signal through the above process.

[0130] The above description is based on the example of the clock synchronization module 703 being implemented as a clock chip. In some embodiments, the connector 701 and the clock synchronization module 703 are implemented as clock chips. The clock chip is connected to the clock generator 702 through the lines on the single board 700. Accordingly, the clock chip includes the connector 701 and the clock synchronization module 703. This application does not limit this aspect.

[0131] The single-board provided in this application embodiment includes a connector, a clock generator, and a clock synchronization module. The connector is used to receive the clock signal output by the passive clock device, and the clock generator is used to generate the single-board's own clock signal. The connector and the clock generator are respectively connected to the clock synchronization module. The clock synchronization module is used to synchronize the clock based on the clock signal received by the connector and the clock signal generated by the clock generator, and uses the synchronized clock signal as the single-board's local clock signal. When a reference clock signal is received, clock synchronization is performed based on the reference clock signal and the selected local clock signal. Based on the above single-board, when the single-board does not receive a reference clock signal, compared with the clock signal generated by the local clock generator in related technologies, the single-board provided in this application embodiment can output a clock signal with higher accuracy synchronized with the clock signal provided by the passive clock device when the accuracy of the clock signal provided by the passive clock device is higher than that of the clock signal generated by the local clock generator. This avoids affecting the communication between network devices and avoids integrating a high-precision clock generator on the single-board, reducing equipment costs and network deployment costs, and avoiding resource waste.

[0132] The above content describes the hardware structure of the single board provided in the embodiments of this application. Next, in conjunction with... Figure 7 The structure of the clock synchronization module in this hardware architecture will be described.

[0133] like Figure 7 As shown, the clock synchronization module 703 includes a first error calculator 7031, a first adjuster 7032, a second error calculator 7033, and a second adjuster 7034. The first error calculator 7031 is connected to the connector 701 and the first adjuster 7032. The first adjuster 7032 is connected to the clock generator 702 and the second adjuster 7034. The second error calculator 7033 is connected to the second adjuster 7034. The first error calculator 7031 and the first adjuster 7032 are used to synchronize the clock based on a first clock signal received from the connector 701 and a second clock signal generated by the clock generator 702, using the synchronized clock signal as the local clock signal. The second error calculator 7033 and the second adjuster 7034 are used to synchronize the clock based on the reference clock signal and the local clock signal when a reference clock signal is received. The above structure adds an error calculator and adjuster to the clock synchronization module. The error calculator and adjuster synchronize the second clock signal with the first clock signal to obtain a local clock signal for clock synchronization. It can output a high-precision clock signal even when no reference clock signal is received, avoiding the impact on communication between network devices. It also avoids integrating a high-precision clock generator on a single board, reducing equipment and network deployment costs and avoiding resource waste.

[0134] The first error calculator 7031, the first adjuster 7032, the second error calculator 7033, and the second adjuster 7034 will be described next.

[0135] The first error calculator 7031 is used to receive a first clock signal from the connector 701 and a second clock signal from the first adjuster 7032, obtain the error between the first clock signal and the second clock signal based on the first clock signal and the second clock signal, and output the error to the first adjuster 7032. The process of obtaining the error between the first clock signal and the second clock signal is the same as the corresponding process performed by the clock synchronization module 703 described above, and will not be described again in this embodiment.

[0136] In some embodiments, the first error calculator 7031 is further configured to receive the temperature corresponding to the first clock signal or the frequency deviation related to the temperature corresponding to the first clock signal, compensate the first clock signal based on the temperature corresponding to the first clock signal or the related frequency deviation, and obtain the aforementioned error based on the compensated first clock signal and the second clock signal from the first adjuster 7032. The temperature corresponding to the first clock signal is received by the first error calculator 7031 from the connector 701, and the aforementioned frequency deviation can be obtained by the frequency offset detection module 7035 based on the temperature received from the connector 701 and transmitted to the first error calculator 7031; this embodiment does not limit this.

[0137] The first adjuster 7032, implemented as a frequency synthesizer, receives the second clock signal generated by the clock generator 702 and the error from the first error calculator 7031. Based on this error, it adjusts the second clock signal to obtain a local clock signal. This process is similar to the corresponding process performed by the clock synchronization module 703 described above, and will not be repeated here. Furthermore, the first adjuster 7032 also outputs the adjusted second clock signal to the first error calculator 7031 so that the first error calculator 7031 can calculate the error based on the adjusted second clock signal.

[0138] The aforementioned first error calculator 7031, first adjuster 7032, and clock generator 701 form a closed-loop clock phase-locked loop, enabling the clock signal output by the first adjuster 7032 to remain synchronized with the clock signal output by the passive clock device.

[0139] The second error calculator 7033 receives a local clock signal from the second adjuster 7034. Upon receiving a reference clock signal, it calculates the error between the reference clock signal and the local clock signal based on the reference clock signal and the local clock signal, and outputs this error to the second adjuster 7034. The process of calculating the error between the reference clock signal and the local clock signal is similar to the corresponding process performed by the clock synchronization module 703 described above, and will not be repeated here. The error calculated by the second error calculator 7033 is either a time error or a frequency error; this application does not limit the specific error.

[0140] The second adjuster 7034 is used to receive the local clock signal from the first adjuster 7032 and the error from the second error calculator 7033. Based on the error, it adjusts the local clock signal and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. This process is similar to the corresponding process performed by the clock synchronization module 703 described above, and will not be repeated here. Furthermore, the second adjuster 7034 is also used to output the adjusted local clock signal to the second error calculator 7033 so that the second error calculator 7033 can calculate the error based on the adjusted local clock signal. The second error calculator 7033 can be implemented as a frequency synthesizer or a time counter, and this application does not limit this implementation. When the second adjuster 7034 is implemented as a frequency synthesizer, the second error calculator 7033 is used to acquire and output the frequency error or phase error between the reference clock signal and the local clock signal. The second adjuster 7034 adjusts the local clock signal based on the frequency error or phase error and outputs the adjusted local clock signal, or outputs the frequency information indicated by the adjusted local clock signal. When the second adjuster 7034 is implemented as a time counter, the second error calculator 7033 is used to acquire and output the time error between the reference clock signal and the local clock signal. The second adjuster 7034 adjusts the local clock signal according to the time error and outputs the adjusted local clock signal, or outputs the time information indicated by the adjusted local clock signal.

[0141] In some embodiments, such as Figure 7 As shown, the clock synchronization module 703 also includes a frequency offset detection module 7035, which is connected to the connector 701, the clock generator 702, and the first error calculator 7031. The frequency offset detection module 7035 is also connected to a connector for receiving a reference clock signal. Figure 7(Not shown in the diagram) Connection. The frequency offset detection module 7035, upon receiving a reference clock signal, detects a first clock signal and a second clock signal based on the reference clock signal, and outputs the detection result to the first error calculator 7031. If the detection result indicates an abnormality in the first clock signal, the first error calculator 7031 stops acquiring the error between the first and second clock signals, and the first adjuster 7032 directly uses the second clock signal as its local clock signal. The frequency offset detection process performed by the frequency offset detection module 7035 is similar to that performed by the clock synchronization module 703, and will not be described again in this embodiment. Furthermore, the frequency offset detection module 7035 is also used to detect the reference clock signal through the above-described frequency offset detection process and output the detection result to the second error calculator 7033. This detection process is similar to the corresponding process performed by the clock synchronization module 703, and will not be described again in this embodiment. If the detection result indicates that the reference clock signal is abnormal, the second error calculator 7033 stops acquiring the error between the reference clock signal and the local clock signal, and the second adjuster 7034 directly outputs the local clock signal or the clock information indicated by the local clock signal.

[0142] In some embodiments, the frequency offset detection module 7035 is further configured to receive the temperature corresponding to the first clock signal from the connector 701, obtain the temperature-related frequency deviation of the first clock signal based on the temperature corresponding to the first clock signal, and output the frequency deviation to the first error calculator 7031 so that the first error calculator 7031 can perform frequency compensation on the first clock signal based on the frequency deviation.

[0143] In some embodiments, the frequency offset detection module 7035 is further configured to acquire the first fitting result and the second fitting result, and output the first fitting result and the second fitting result to the second adjuster 7034 when no reference clock signal is received, so that the second adjuster 7034 can predict the error of the local clock signal based on the fitting result corresponding to the local clock signal in the first fitting result and the second fitting result, and adjust the local clock signal according to the error. Alternatively, when no reference clock signal is received, the frequency offset detection module 7035 can determine the fitting result corresponding to the local clock signal based on the local clock signal acquired by the first adjuster 7032, and output the fitting result to the second adjuster 7034. Or, when no reference clock signal is received, the frequency offset detection module 7035 can determine the fitting result corresponding to the local clock signal based on the local clock signal acquired by the first adjuster 7032, predict the error of the local clock signal based on the fitting result, and output the error to the second adjuster 7034. This application embodiment does not limit this.

[0144] It should be noted that the above Figure 7 The structure shown is illustrated using a clock selection module 703 comprising a first error calculator 7031, a first adjuster 7032, a second error calculator 7033, a second adjuster 7034, and a frequency offset detection module 7035 as an example. Specifically, it is illustrated by integrating the first error calculator, first adjuster, second error calculator, second adjuster, and frequency offset detection module onto a single clock chip. In some embodiments, the first error calculator, first adjuster, second error calculator, second adjuster, and frequency offset detection module are distributed and integrated on a single board. Alternatively, one or more of these components may be integrated onto a single clock chip, while the remaining components may be distributed and integrated onto a single board or onto one or more other clock chips on the same board. This application does not limit this approach. For example, the first error calculator and first adjuster may be integrated onto a single clock chip on a single board, capable of performing the aforementioned process of compensating the first clock signal based on the temperature corresponding to the first clock signal. The second error calculator and second adjuster may be integrated onto another clock chip on the same single board.

[0145] To complement the aforementioned circuit board, this application also provides a clock synchronization method. This method is applied to the circuit board, which includes a connector, a clock generator, and a clock synchronization module. The connector and clock generator are respectively connected to the clock synchronization module. The method includes: the connector receiving a first clock signal, i.e., a clock signal output by a passive clock device; the clock generator generating a second clock signal, i.e., the circuit board's own clock signal; the clock synchronization module acquiring a local clock signal based on the first and second clock signals; and, upon receiving a reference clock signal, performing clock synchronization based on the reference clock signal and the local clock signal. In other words, the above method synchronizes the clock signal output by the passive clock device and the clock signal generated by the clock generator. The system selects a local clock signal for clock synchronization. When a reference clock signal is received, clock synchronization is performed based on the selected local clock signal and the received reference clock signal. When no reference clock signal is received, the system outputs a clock signal with higher accuracy from the passive clock device compared to the clock signal generated by the local clock generator in related technologies. This avoids affecting communication between network devices and also avoids integrating a high-precision clock generator on a single board, reducing equipment and network deployment costs and preventing resource waste.

[0146] In some embodiments, the clock synchronization module obtains a local clock signal based on a first clock signal and a second clock signal, including: the clock synchronization module selects a local clock signal from the first clock signal and the second clock signal, so as to select a clock signal with higher clock accuracy from the first clock signal and the second clock signal for clock synchronization, thereby improving the accuracy of clock synchronization.

[0147] In some embodiments, the clock synchronization module selects a local clock signal from the first clock signal and the second clock signal by: detecting the first clock signal and the second clock signal based on a reference clock signal, and selecting a local clock signal from the first clock signal and the second clock signal based on the detection result. By detecting the first clock signal and the second clock signal before selecting the local clock signal, it is possible to avoid erroneously selecting an abnormal clock signal as the local clock signal in the event of an abnormality in the first clock signal or the second clock signal, thereby improving the accuracy of clock synchronization.

[0148] In some embodiments, the clock synchronization module selects a local clock signal from the first clock signal and the second clock signal by: when the clock synchronization module receives the first clock signal, it selects the first clock signal as the local clock signal. That is, the clock synchronization module defaults to the first clock signal having a higher priority or performance than the second clock signal. Once the first clock signal is received, the clock synchronization module selects the first clock signal as the local clock signal, thereby realizing clock synchronization based on the clock signal with higher precision.

[0149] In some embodiments, the clock synchronization module obtains a local clock signal based on a first clock signal and a second clock signal by: the clock synchronization module performs clock synchronization on the second clock signal based on the first clock signal to obtain a local clock signal, so as to synchronize the clock signal generated by the local clock generator into a higher-precision clock signal output by the passive clock device, thereby improving the accuracy of clock synchronization based on the local clock signal.

[0150] In some embodiments, the clock synchronization module synchronizes the second clock signal with the first clock signal to obtain a local clock signal by means of: the clock synchronization module detects the first clock signal and the second clock signal based on a reference clock signal, and synchronizes the second clock signal with the detection result and the first clock signal to obtain a local clock signal. By detecting the first clock signal and the second clock signal before obtaining the local clock signal, it is possible to avoid incorrectly obtaining the local clock signal based on the abnormal clock signal when the first clock signal or the second clock signal is abnormal, thereby improving the accuracy of clock synchronization.

[0151] In some embodiments, the above method further includes: the clock synchronization module performs clock synchronization based on the local clock signal when no reference clock signal is received, which can maintain a high-precision clock based on the local clock signal when no reference clock signal is received, thereby avoiding the impact on communication services.

[0152] In some embodiments, the connector is connected to the service board of the network device, and the method further includes: the connector receiving a first clock signal from the service board, so that when there is no port on the board for connecting to the passive clock device, the board can receive the clock signal output by the passive clock device through the service board, and then perform clock synchronization according to the clock signal.

[0153] In some embodiments, the method further includes: the connector receiving the temperature corresponding to the first clock signal, and the clock synchronization module compensating the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, the accuracy of the first clock signal can be improved by compensating the first clock signal based on temperature, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0154] The above content combined Figures 5 to 7 The paper describes two types of boards that acquire a local clock signal based on a first clock signal and a second clock signal, and then perform clock synchronization based on the local clock signal. Next, the paper describes the scheme of selecting a clock signal for clock synchronization from a reference clock signal and a clock signal output by a passive clock device through a selector on a multiplexed board.

[0155] Figure 8 This is a schematic diagram of the structure of a single board provided in an embodiment of this application. Figure 8 The illustrated board uses the clock signal provided by the passive clock device in an alternative manner. Specifically, the board can receive both the reference clock signal and the clock signal provided by the passive clock device. When the reference clock signal is received, clock synchronization is performed based on the reference clock signal and the clock signal generated by the board's local clock generator. When the reference clock signal is not received, clock synchronization is performed based on the clock signal provided by the passive clock device and the clock signal generated by the board's local clock generator. Therefore, when no reference clock signal is received, compared to the related art which outputs a clock signal generated by a local clock generator, the board provided in this embodiment can output a clock signal with higher synchronization accuracy from the passive clock device, even when the accuracy of the clock signal provided by the passive clock device is higher than that generated by the local clock generator. This avoids affecting communication between network devices and avoids integrating a high-precision clock generator on the board, reducing equipment and network deployment costs and preventing resource waste.

[0156] like Figure 8As shown, the single board 800 includes a connector 801, a clock generator 802, and a clock synchronization module 803. Connector 801 and clock generator 802 are respectively connected to clock synchronization module 803. Connector 801 and clock generator 802 are analogous to connector 501 and clock generator 502 described above, and will not be repeated here. In this embodiment, the clock signal generated by clock generator 802 is referred to as the local clock signal. Clock synchronization module 803 is used to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received, and to perform clock synchronization based on the clock signal received by connector 801 and the local clock signal when no reference clock signal is received.

[0157] The following is about Figure 8 The clock synchronization module 803 in the single board shown will be described.

[0158] The clock synchronization module 803 is used to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received. The clock synchronization module is also used to perform clock synchronization based on the first clock signal and the local clock signal when no reference clock signal is received.

[0159] The clock synchronization module 803 is implemented as hardware such as a clock chip, or as a component consisting of a selector and a clock chip. Accordingly, the clock synchronization module 803 includes a selector and a clock chip, which are connected. The selector is also connected to a connector 801. Optionally, the clock chip is connected to the connector 801 and a clock generator 802; this embodiment does not limit this. Correspondingly, the clock chip includes some or all of the components of the clock synchronization module 803; this embodiment does not limit this. The clock synchronization module 803 is integrated on a single board 800 and connected to the connector 801 and the clock generator 802 via lines on the single board 800. The reference clock signal is the same as described above. Figure 5 The reference clock signal received by the single board shown is similar.

[0160] In this embodiment, when the clock synchronization module 803 receives a reference clock signal, it acquires the error between the reference clock signal and the local clock signal generated by the clock generator 802. Based on this error, it adjusts the local clock signal and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. This process is the same as the clock synchronization process performed by the clock synchronization module 503 described above, and will not be described again in this embodiment. When the clock synchronization module 803 does not receive a reference clock signal, it acquires the error between the first clock signal and the local clock signal generated by the clock generator 802. Based on this error, it adjusts the local clock signal and outputs the adjusted local clock signal, or outputs the clock information indicated by the adjusted local clock signal. This process is the same as the clock synchronization process performed by the clock synchronization module 503 described above, and will not be described again in this embodiment.

[0161] In some embodiments, the clock synchronization module 803 is further configured to perform frequency offset detection on the reference clock signal, the first clock signal, and the local clock signal upon receiving a reference clock signal. This frequency offset detection process is analogous to the corresponding process performed by the clock synchronization module 503 described above, and will not be repeated here. If the detection result indicates that the reference clock signal is abnormal, the clock synchronization module 803 performs clock synchronization based on the first clock signal and the local clock signal.

[0162] In some embodiments, the clock synchronization module 803 is further configured to compensate the first clock signal based on the temperature corresponding to the first clock signal. This process is similar to the corresponding process performed by the clock synchronization module 503 described above, and will not be repeated here in the embodiments of this application.

[0163] In some embodiments, the clock synchronization module 803 is used to perform clock synchronization based on a local clock when no reference clock signal or a first clock signal is received. Accordingly, when no reference clock signal or a first clock signal is received, the clock synchronization module 803 directly outputs the local clock signal, or directly outputs the clock information indicated by the local clock signal. Alternatively, the clock synchronization module 803, through a process similar to that of the clock synchronization module 503, fits the error (real-time frequency offset) between the historical reference clock signal and the historical first clock signal based on the historical reference clock signal and the historical first clock signal, obtaining a fitting result indicating how the error between the historical reference clock signal and the historical first clock signal changes over time. When no reference clock signal is received, based on this fitting result, the error of the first clock signal is predicted, the first clock signal is adjusted according to the error, and clock synchronization is then performed based on the adjusted first clock signal. This addresses the problems of initial frequency offset and aging rate (referring to changes in frequency offset) in passive clock devices, further improving the accuracy of clock synchronization.

[0164] The single-board provided in this application embodiment includes a connector, a clock generator, and a clock synchronization module. The connector is used to receive the clock signal output by the passive clock device, and the clock generator is used to generate the local clock signal of the single-board. The connector and the clock generator are respectively connected to the clock synchronization module. The clock synchronization module is used to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received. The clock synchronization module is also used to perform clock synchronization based on a first clock signal and the local clock signal when no reference clock signal is received. Based on the above single-board, when the single-board does not receive a reference clock signal, compared with the clock signal generated by the local clock generator in related technologies, the single-board provided in this application embodiment can output a clock signal with higher synchronization accuracy of the clock signal provided by the passive clock device when the accuracy of the clock signal provided by the passive clock device is higher than that of the clock signal generated by the local clock generator. This avoids affecting the communication between network devices and avoids integrating a high-precision clock generator on the single-board, reducing equipment costs and network deployment costs, and avoiding resource waste.

[0165] The above content describes the hardware structure of the single board provided in the embodiments of this application. Next, in conjunction with... Figure 8 The structure of the clock synchronization module in this hardware architecture will be described.

[0166] like Figure 8 As shown, the clock synchronization module 803 includes a selector 8031, an error calculator 8032, and an adjuster 8033. The selector 8031 ​​is connected to the connector 801 and the error calculator 8032; the error calculator 8032 is connected to the adjuster 8033; and the adjuster 8033 is connected to the clock generator 802. Specifically, the selector 8031 ​​performs clock synchronization based on the reference clock signal and the local clock signal generated by the clock generator 802 when a reference clock signal is received. When no reference clock signal is received, it performs clock synchronization based on the first clock signal received by the connector 801 and the local clock signal generated by the clock generator 802. This structure reuses the selector on the single-board unit, allowing the selector to select the clock signal for synchronization from the reference clock signal and the clock signal output by the passive clock device. This enables the output of a high-precision clock signal even when no reference clock signal is received, avoiding interference with communication between network devices. It also avoids integrating a high-precision clock generator on the single-board unit, reducing equipment and network deployment costs and preventing resource waste.

[0167] The selector 8031, error calculator 8032, and adjuster 8033 will be described next.

[0168] Selector 8031 ​​is used to use the reference clock signal as the target clock signal (i.e., the signal used for clock synchronization) when a reference clock signal is received, and output the reference clock signal to error calculator 8032. When no reference clock signal is received, selects the first clock signal as the target clock signal and outputs the first clock signal to error calculator.

[0169] Error calculator 8032 is used to receive the target clock signal from selector 8031, receive the local clock signal from adjuster 8033, obtain the error between the target clock signal and the local clock signal, smooth and filter the difference, and then output the error to adjuster 8033. The process of obtaining the error is the same as the corresponding process performed by the clock synchronization module 803 described above, and will not be described again in this embodiment.

[0170] In some embodiments, the error calculator 8032 is also connected to the connector 801. The error calculator 8032 is further configured to receive the temperature corresponding to the first clock signal or receive the frequency deviation related to the temperature corresponding to the first clock signal. When the target clock signal is the first clock signal, it compensates the first clock signal based on the temperature corresponding to the first clock signal or the related frequency deviation. Based on the compensated first clock signal, it obtains the error between the compensated first clock signal and the local clock signal. The temperature corresponding to the first clock signal is received by the error calculator 8032 from the connector 801. The frequency deviation can be obtained by the frequency offset detection module 8034 based on the temperature received from the connector 801 and transmitted to the adjuster 8033. This embodiment does not limit this aspect.

[0171] Adjuster 8033 receives the local clock signal generated by clock generator 802, adjusts the local clock signal based on the error from error calculator 8032, and outputs the adjusted local clock signal, or the clock signal indicated by the adjusted local clock signal. This process is similar to the corresponding process performed by clock synchronization module 503 described above, and will not be repeated here. Adjuster 8033 is also used to output the adjusted local clock signal to error calculator 8032 so that error calculator 8032 can obtain the error based on the local clock signal.

[0172] In some embodiments, such as Figure 8As shown, the clock synchronization module 803 also includes a frequency offset detection module 8034, which is connected to the connector 801, the clock generator 802, and the selector 8031. The frequency offset detection module 8034 performs frequency offset detection on the reference clock signal, the first clock signal, and the local clock signal, and outputs the detection result to the selector 8031. This detection process is similar to the corresponding process performed by the clock synchronization module 503 described above, and will not be repeated here. If the detection result indicates that the reference clock signal is abnormal, the frequency offset detection module 8034 outputs the detection result to the selector 8031, and the selector 8031 ​​uses the first clock signal as the target clock signal based on the detection result.

[0173] In some embodiments, the frequency offset detection module 8034 and the error calculator 8032 are connected. The frequency offset detection module 8034 fits the error (real-time frequency offset) between the historical reference clock signal and the historical first clock signal based on the historical reference clock signal and the historical first clock signal, and obtains a fitting result. The fitting result indicates how the error between the historical reference clock signal and the historical first clock signal changes over time. When no reference clock signal is received, the fitting result is output to the error calculator 8032 so that the error calculator 8032 can predict the error of the first clock signal based on the fitting result, adjust the first clock signal according to the error, and then perform clock synchronization based on the adjusted first clock signal. This solves the problems of initial frequency offset and aging rate (referring to the change in frequency offset) in passive clock devices, and further improves the accuracy of clock synchronization.

[0174] In some embodiments, the frequency offset detection module 8034 is further configured to receive the temperature corresponding to the first clock signal from the connector 801, obtain the temperature-related frequency deviation of the first clock signal based on the temperature corresponding to the first clock signal, and output the frequency deviation to the error calculator 8032 so that the error calculator 8032 can perform frequency compensation on the first clock signal based on the frequency deviation.

[0175] It should be noted that the above Figure 8The structure shown is illustrated using a clock selection module 803, which includes a selector, an error calculator, an adjuster, and a frequency offset detection module. It is also illustrated using an example where the selector, error calculator, adjuster, and frequency offset detection module are integrated onto a single clock chip. In some embodiments, the selector, error calculator, adjuster, and frequency offset detection module are distributed and integrated on a single board. Alternatively, one or more components of the selector, error calculator, adjuster, and frequency offset detection module are integrated onto a single clock chip, while the remaining components are distributed and integrated on a single board. For example, a single board integrates a selector and a clock chip, and the clock chip includes an error calculator, an adjuster, and a frequency offset detection module. This clock chip is capable of performing the aforementioned process of compensating the first clock signal based on the temperature corresponding to the first clock signal. This embodiment of the application does not limit this specific approach.

[0176] To cooperate with the above Figure 8 The illustrated board also provides a clock synchronization method in this application embodiment. This method, which can be executed by the board, includes: the board receiving a first clock signal; the board generating a local clock signal; and the board performing clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received, and performing clock synchronization based on the first clock signal and the local clock signal when no reference clock signal is received. Therefore, when no reference clock signal is received, compared to the related art which outputs a clock signal generated by a local clock generator, this method, even when the accuracy of the clock signal provided by the passive clock device is higher than that generated by the local clock generator, can output a clock signal with higher synchronization accuracy from the passive clock device, avoiding impact on communication between network devices. It also avoids integrating a high-precision clock generator on the board, reducing equipment and network deployment costs and preventing resource waste.

[0177] In some embodiments, the above-mentioned single board receiving the first clock signal includes: the single board receiving the first clock signal from the service board, so that when there is no port on the single board for connecting to the passive clock device, the single board can receive the clock signal output by the passive clock device through the service board, and then perform clock synchronization according to the clock signal.

[0178] In some embodiments, the method further includes: the board receiving the temperature corresponding to the first clock signal, and compensating the first clock signal based on the temperature. Since the accuracy of the clock signal is greatly affected by temperature, compensating the first clock signal based on temperature can improve the accuracy of the first clock signal, thereby improving the accuracy of clock synchronization based on the first clock signal.

[0179] Next, the passive clock device provided in this application embodiment will be described. This passive clock device integrates a high-precision clock generator and a pluggable interface. When any network device requires high-precision clock synchronization, relevant technicians can easily install this passive clock device on the network device, making it pluggable to the network device. The clock generator in the passive clock device provides a high-precision clock signal to the network device, solving the problem of insufficient clock accuracy of the network device's local clock generator. This also separates the high-precision clock generator from the network device, eliminating the need to pre-integrate a high-precision local clock generator on the network device's main control board when establishing the communication network, reducing equipment and network deployment costs, and avoiding resource waste. This passive clock device can be implemented as a small form-factor pluggable (SFP), an SFP+, or a 10-Gigabit Ethernet interface small form-factor pluggable transceiver (XFP), etc., and is compatible with the corresponding interface. This application embodiment does not limit this.

[0180] This application provides various passive clock devices. One passive clock device includes a clock source that directly outputs the clock signal generated by the clock source. Another passive clock device includes a clock source and a clock conversion module that can convert the clock signal generated by the clock source into a clock signal at a preset frequency through the clock conversion module, so as to output the clock signal at the preset frequency.

[0181] The following is combined with Figure 9 The passive clock device that directly outputs the clock signal generated by the clock source will be described.

[0182] Figure 9 This is a schematic diagram of a passive clock device provided in an embodiment of this application. The passive clock device is used to provide clock signals to network devices, such as... Figure 9 As shown, the passive clock device 900 includes a clock generator 901 and a pluggable interface 902. The clock generator 901 and the pluggable interface 902 are connected, and the pluggable interface 902 is used to connect to a network device. The clock generator 901 is used to obtain a clock signal, such as... Figure 9 As shown, the clock generator 901 includes a clock source 9011, which is connected to a pluggable interface for generating a clock signal. The pluggable interface is used to output the clock signal to the network device when connected to the network device, thereby providing the network device with a high-precision clock signal.

[0183] The clock generator 901 and the pluggable interface 902 will be described below.

[0184] (1) Clock generator 901, used to obtain clock signal. The clock generator 901 includes clock source 9011, which is a high-performance crystal oscillator or rubidium atomic clock, etc., which is not limited in this application embodiment.

[0185] In this embodiment of the application, after the clock source 9011 in the clock generator 901 is connected to the power supply, the clock source 9011 generates a clock signal at the frequency corresponding to the clock source 9011. For example, if the clock source 9011 is a high-performance crystal oscillator used to generate a 10 MHz clock signal, then after the clock source 9011 is connected to the power supply, it generates a 10 MHz clock square wave signal.

[0186] In some embodiments, the clock generator 901 is integrated as a component of the passive clock device 900 on the circuit board of the passive clock device, or the components of the clock generator 901 are distributed and integrated on the circuit board of the passive clock device 900. For example, the crystal and driving circuit of the clock source 9011 in the clock generator 901 are distributed and integrated on the circuit board of the passive clock device 900. This application embodiment does not limit this.

[0187] (2) A pluggable interface 902 is used to output a clock signal to a network device when the network device is connected.

[0188] In this embodiment, when the pluggable interface 902 is connected to a network device, it outputs a clock signal obtained by the clock generator 901 to the network device. Accordingly, the pluggable interface 902 includes multiple pins, including power pins and output pins. The power pins are used to connect the power supply, providing an electrical signal to the passive clock device 900, and the output pins are used to output the clock signal to the network device. For example, as... Figure 9 As shown, the pluggable interface 902 includes 20 pins, namely P1 to P20. P15 is a power pin, which is used to receive electrical signals from the network device when connected to the network device. The passive clock device provides this electrical signal. P8 is an output pin, which is connected to the clock generator 901 and is used to output the clock signal obtained by the clock generator 901 to the network device when connected to the network device.

[0189] In some embodiments, the pluggable interface 902 includes multiple output pins for outputting multiple clock signals to a network device. Accordingly, each output pin is connected to a chip in the network device to output a clock signal obtained by a clock generator 901 to that chip. For example, the pluggable interface 902 includes pins P2 and P8, which are respectively used to output clock signals obtained by the clock generator 901 to different chips in the network device. It should be noted that this embodiment is described using an SFP as an example of a passive clock device. In the SFP, pins P2 and P8 have the function of outputting signals to the network device. For example, when the SFP is used as an optical module, the SFP receives electrical signals output by the network device, converts the electrical signals into optical fiber signals, transmits the optical fiber signals onto an optical fiber, and the SFP also receives optical fiber signals, converts the optical fiber signals into electrical signals, and outputs the electrical signals to the network device to which the SFP is connected. In this scenario, when the SFP cannot transmit fiber optic signals to the fiber optic cable, it outputs a transmission failure signal to the network device via its P2 pin. When the SFP cannot receive fiber optic signals, it outputs a loss signal to the network device via its P8 pin. In other words, the P2 and P8 pins have the function of outputting signals to the network device. The passive clock device provided in this embodiment reuses the output functions of the P2 and P8 pins, outputting clock signals to the network device via these pins. Of course, if the passive clock device is implemented as other types of devices, it can also output clock signals via other pins with signal output functions; this embodiment does not limit this.

[0190] In some embodiments, such as Figure 9 As shown, the passive clock device 900 also includes a temperature sensor 903, which is connected to the clock generator 901 and the pluggable interface 902. The temperature sensor 903 detects the temperature of the clock generator 901, specifically the temperature of the clock source 9011 within the clock generator 901, and outputs this temperature to the network device through the pluggable interface 902. This temperature affects the accuracy of the clock signal generated by the clock source 901 in the clock generator 901. The network device can compensate for the clock signal from the clock generator 901 based on the temperature from the temperature sensor 903 to improve the accuracy of the clock signal, thereby improving the accuracy of clock synchronization performed by the network device based on this clock signal.

[0191] In some embodiments, the pluggable interface 902 further includes an information output pin for outputting data to the network device. Accordingly, the pluggable interface 902 outputs the temperature to the network device through this information output pin. For example, as... Figure 9As shown, the pluggable interface 902 includes an information output pin P4, which is connected to the temperature sensor 903. The information output pin P4 outputs the temperature detected by the temperature sensor 903 to the network device in real time.

[0192] The passive clock device provided in this application integrates a clock generator onto a pluggable passive clock device, separating the high-precision clock generator from the network device. Whenever any network device requires high-precision clock synchronization, relevant technicians can easily plug the passive clock device into the network device via its pluggable interface. This pluggable interface connects to the clock generator, providing a high-precision clock to the network device while it is connected, eliminating the need to pre-integrate a high-precision local clock generator on the network device's main control board during network establishment. This reduces equipment and network deployment costs, avoids resource waste, and facilitates network device upgrades and updates.

[0193] Next, the passive clock device including a clock source and a clock conversion module provided in the embodiments of this application will be described. The passive clock device includes a clock generator and a pluggable interface. The clock generator includes a clock source and a clock conversion module. The clock conversion module can convert the clock signal generated by the clock source into clock signals at different frequencies, and then output the clock signals at different frequencies to the network device through the pluggable interface to meet the clock signal requirements of different chips in the network device.

[0194] The following is combined with Figure 10 The passive clock device provided in the embodiments of this application will be described.

[0195] Figure 10 This is a schematic diagram of another passive clock device provided in an embodiment of this application. The passive clock device is used to provide clock signals to network devices, such as... Figure 10As shown, the passive clock device 1000 includes a clock generator 1001 and a pluggable interface 1002, which are connected. The clock generator 1001 is used to obtain a clock signal. Accordingly, the clock generator 1001 includes a clock source 10011 and a clock conversion module 10012. The clock source 10011 and the clock conversion module 10012 are connected, and the clock conversion module 10012 is connected to the pluggable interface 1002. The clock source 10011 generates the original clock signal, and the clock conversion module 10012 converts the original clock signal generated by the clock source based on a preset frequency point to obtain a clock signal. The pluggable interface 1002 is used to connect to a network device. When connected to a network device, it outputs the converted clock signal to the network device, thereby enabling the output of clock signals at different frequency points to the network device to meet the clock signal requirements of different chips in the network device.

[0196] The clock generator 1001 and the pluggable interface 1002 will be described below.

[0197] (1) A clock generator 1001 is used to obtain a clock signal. The clock generator 1001 includes a clock source 10011 and a clock conversion module 10012. The clock source 10011 and the clock conversion module 10012 are connected. The clock conversion module 10012 is connected to a pluggable interface 1002. The clock source 10011 is used to generate a raw clock signal. The clock conversion module 10012 is used to convert the raw clock signal generated by the clock source based on a preset frequency point to obtain a clock signal. The clock source 10011 is similar to the clock source 9011 described above, and will not be described again in this embodiment.

[0198] The clock conversion module 10012, such as a frequency synthesizer, is used to convert the clock signal generated by the clock source 10011 into a clock signal at a preset frequency. The pluggable interface 1002 then outputs this clock signal at the preset frequency to the network device. This preset frequency can be a frequency configured within the clock conversion module 10012 itself, or a frequency indicated by the network device that is pluggably connected to the passive clock device 1000. This embodiment does not limit the frequency. For example, the preset frequency is 38.88MHz. Figure 10 As shown, clock source 10011 generates a 10MHz clock signal, clock conversion module 10012 converts the 10MHz clock signal generated by clock source 10011 into a 38.88MHz clock signal, and pluggable interface 1002 then outputs the 38.88MHz clock signal to the network device through output pin P8.

[0199] (2) A pluggable interface 1002 is used to output a clock signal to a network device when the device is connected to the network device. The pluggable interface 1002 is similar to the pluggable interface 902, and will not be described again in this embodiment.

[0200] In some embodiments, the preset frequency point is the frequency point indicated by a network device that is pluggably connected to the passive clock device 1000. The pluggable interface 1002 is also used to receive preset frequency point information sent by the network device, which indicates the preset frequency point. Accordingly, the pluggable interface 1002 also includes an information receiving pin, which may be an inter-integrated circuit (I2C) communication data line pin, such as a pin connected to the serial data line (SDA) in the I2C bus (SDA pin), etc., used to receive the preset frequency point information from the network device so that the passive clock device 1000 can configure its parameters according to the preset frequency point information, such as the preset frequency point of the clock conversion module 10012, etc. Accordingly, the information receiving pin is used to receive preset frequency information from the network device and forward the preset frequency information to the clock conversion module 10012. This preset frequency information is used to enable the clock conversion module 10012 to convert the clock signal generated by the clock source 10011 into a clock signal at the preset frequency. For example, as... Figure 10 As shown, pin P4 is the information receiving pin. P4 is connected to the clock conversion module 10012 and can receive preset frequency information from the network device and forward the preset frequency information to the clock conversion module 10012.

[0201] In some embodiments, the pluggable interface 1002 further includes a frequency receiving pin, which may be an I2C communication data line pin, such as a pin connected to the serial clock line (SCL) in the I2C bus (SCL pin), etc., for receiving a clock signal through the clock line in the I2C bus. The clock signal transmitted by the clock line indicates the frequency at which the pluggable interface 1002 receives data from the network device and the frequency at which the pluggable interface 1002 outputs data to the network device, for controlling the passive clock device 1000 to transmit data with the network device. For example, as... Figure 10As shown, the pluggable interface includes a frequency receiving pin P5, which is connected to the clock conversion module 10012. This frequency receiving pin P5, through the SCL in the I2C bus, controls the aforementioned information receiving pin P4 in the pluggable interface 1002 to receive preset frequency information from the network device according to the frequency indicated by the clock signal transmitted on the clock line, via the SDA in the I2C bus. Data transmission between the pluggable interface 1002 and the network device is based on the clock signal in the clock line, ensuring timing consistency during data transmission, avoiding data transmission errors, and improving the reliability of data transmission.

[0202] In some embodiments, the pluggable interface 1002 includes multiple output pins for outputting multiple clock signals to a network device. Each output pin outputs a clock signal at a preset frequency to the network device. The preset frequencies corresponding to different pins may be the same or different, and this embodiment does not limit this. For example, the clock conversion module 10012 performs different conversions on the clock signal generated by the clock source 10011 according to different preset frequencies, outputting clock signals at different preset frequencies to the pluggable interface 1002. Multiple output pins in the pluggable interface 1002 simultaneously output clock signals at different preset frequencies to the network device, with each output pin outputting one clock signal at a preset frequency. Accordingly, as... Figure 10 As shown, the pluggable interface 1002 includes output pins P2 and P8. A clock conversion module 10012 is connected to P2 and P8, with preset frequencies of 80MHz and 38.88MHz. The clock conversion module 10012 converts the 10MHz clock signal generated by the clock source 10011 into an 80MHz clock signal and a 38.88MHz clock signal. It outputs the 80MHz clock signal to the network device through output pin P2 and the 38.88MHz clock signal to the network device through output pin P8. Accordingly, the board provided in this embodiment performs clock synchronization processing on the clock signals output through different output pins.

[0203] The above process is illustrated by taking the clock conversion module 10012 as an example of converting the clock signal generated by the clock source 10011. In some embodiments, the clock conversion module 10012 may also not perform the conversion operation on the clock signal generated by the clock source 10011, but directly output the clock signal generated by the clock source 10011 to the pluggable interface 1002, and the pluggable interface 1002 then outputs the clock signal generated by the clock source 10011 to the network device. This application embodiment does not limit this.

[0204] In some embodiments, such as Figure 10As shown, the passive clock device 1000 also includes a temperature sensor 1003, which is similar to the temperature sensor 903 described above. The embodiments of this application will not be described in detail here.

[0205] In some embodiments, the pluggable interface 1002 further includes an information output pin for outputting data to the network device. Accordingly, the pluggable interface 1002 outputs data to the network device through this information output pin. For example, as... Figure 10 As shown, the pluggable interface 1002 includes an information output pin P4, which is connected to the temperature sensor 1003. This information output pin P4 outputs the temperature detected by the temperature sensor 1003 to the network device in real time based on the communication clock received from P5. It should be noted that... Figure 10 In the passive clock device 1000 shown, the information receiving pin and the information output pin are the same pin, that is, pin P4 in the pluggable interface 1002 is a bidirectional pin. Pin P4 can be used as an information output pin to transmit data to the network device, and it can also be used as an information receiving pin to receive data from the network device. However, in some embodiments, the information receiving pin and the information output pin are different pins. This application embodiment does not limit this.

[0206] The passive clock device provided in this application integrates a clock generator onto a pluggable passive clock device, separating the high-precision clock generator from the network device. Whenever any network device requires high-precision clock synchronization, relevant technicians can easily plug the passive clock device into that network device via its pluggable interface. This pluggable interface connects to the clock generator, enabling the provision of a high-precision clock to the network device while it is connected, without needing to pre-integrate a high-precision local clock generator on the network device's main control board during network establishment. This reduces equipment and network deployment costs and avoids resource waste.

[0207] To complement the aforementioned passive clock device, this application also provides a clock signal output method. This method is applied to the passive clock device, which provides a clock signal to network devices. The passive clock device includes a clock generator and a pluggable interface. The clock generator is connected to the pluggable interface, which is used to connect to the network device. The method includes: the clock generator obtaining a clock signal; and the pluggable interface outputting the clock signal to the network device when connected. When any network device requires high-precision clock synchronization, relevant technicians can readily install the passive clock device on the network device, making the passive clock device pluggable to the network device. This allows the clock generator in the passive clock device to provide a high-precision clock signal to the network device, thus separating the high-precision clock generator from the network device. This eliminates the need to integrate a high-precision local clock generator on the main control board of the network device before establishing the communication network, reducing equipment and network deployment costs and avoiding resource waste.

[0208] In some embodiments, the passive clock device further includes a temperature sensor connected to both a pluggable interface and a clock generator. The method further includes: the temperature sensor detecting the temperature of the clock generator and outputting the temperature to a network device via the pluggable interface. Since the clock signal obtained by the clock generator is significantly affected by its temperature, outputting the temperature to the network device enables the network device to compensate for the clock signal obtained by the clock generator based on the temperature, thereby improving the accuracy of the clock signal and consequently improving the accuracy of clock synchronization based on the clock signal.

[0209] In some embodiments, the clock generator includes a clock source connected to a pluggable interface, and the clock generator obtains a clock signal by the clock source generating a clock signal. This method generates a clock signal through the clock source and then outputs the clock signal to the network device through the pluggable interface. When the clock source has high clock accuracy, this method can provide a high-precision clock signal to the network device, thereby improving the accuracy of the clock maintained by the network device.

[0210] In some embodiments, the clock generator includes a clock source and a clock conversion module, which are connected together. The clock conversion module is connected to a pluggable interface. The clock generator obtains a clock signal by: the clock source generating a raw clock signal; and the clock conversion module converting the raw clock signal generated by the clock source based on a preset frequency point to obtain a clock signal. This method converts the frequency point of the raw clock signal generated by the clock source through the clock conversion module, enabling the passive clock device to provide clock signals at different preset frequency points to network devices, thereby providing clock signals at the frequency points required by different chips in the network device.

[0211] In some embodiments, the above method further includes: receiving preset frequency information sent by a network device through a pluggable interface, the preset frequency information indicating a preset frequency, so that the clock conversion module can perform frequency conversion on the original clock signal according to the preset frequency required by the network device, thereby providing the network device with a clock signal at the frequency required by the network device according to the needs of the network device.

[0212] In some embodiments, the pluggable interface includes multiple output pins, and the method further includes: the multiple output pins output multiple clock signals to the network device, thereby providing clock signals to different chips in the network device, enabling different chips to synchronize clocks according to the clock signals they receive, and meeting the clock synchronization requirements of their own services.

[0213] In some embodiments, the clock generator is integrated as a component of the passive clock device onto the circuit board of the passive clock device, or the components of the clock generator are distributed and integrated onto the circuit board of the passive clock device to reduce the size of the passive clock device and improve its portability.

[0214] In an exemplary embodiment, a clock chip is also provided, which includes the clock synchronization module in the above embodiments, or the clock chip includes the clock synchronization module and connector in the above embodiments.

[0215] In an exemplary embodiment, a clock chip is also provided, which includes the clock generator described in the above embodiments.

[0216] In an exemplary embodiment, a network device is also provided, which includes any of the single boards provided in the embodiments of this application, for executing the clock synchronization method of the corresponding single board. The network device may be a router, a packet transport network (PTN) device, an optical transport network (OTN) device, or a base station, etc., and the embodiments of this application do not limit this to any particular type.

[0217] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in a passive clock device to perform the clock signal output method in the above embodiments. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0218] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in a network device to perform a clock synchronization method as described above. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0219] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including program code that can be executed by a processor in a network device to perform another clock synchronization method in the above embodiments. For example, the computer-readable storage medium is a non-transitory computer-readable storage medium, such as read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0220] This application also provides a computer program product or computer program, which includes program code. The computer instructions are stored in a computer-readable storage medium. The processor in the passive clock device reads the program code from the computer-readable storage medium and executes the program code, causing the passive clock device to perform the above-described clock signal output method.

[0221] This application also provides a computer program product or computer program, which includes program code. The computer instructions are stored in a computer-readable storage medium. A processor in a network device reads the program code from the computer-readable storage medium and executes the program code, causing the network device to perform a clock synchronization method as described in the above embodiments.

[0222] This application also provides a computer program product or computer program, which includes program code. The computer instructions are stored in a computer-readable storage medium. A processor in a network device reads the program code from the computer-readable storage medium and executes the program code, causing the network device to perform another clock synchronization method in the above embodiments.

[0223] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute a clock signal output method of one of the above method embodiments.

[0224] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute another clock synchronization method in the above-described method embodiments.

[0225] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the clock synchronization method in the above method embodiments.

[0226] In this embodiment, the apparatus, device, computer-readable storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding methods provided above, and will not be repeated here.

[0227] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the single-board embodiment or passive clock device embodiment provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the device embodiment, which will not be repeated here.

[0228] In the several embodiments provided in this application, it should be understood that the disclosed devices, boards, and methods can be implemented in other ways. For example, the board embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0229] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0230] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0231] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0232] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0233] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0234] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the sensitive words involved in this application were obtained with full authorization.

[0235] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this disclosure, and will not be described in detail here.

[0236] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A passive clock device, characterized in that, The passive clock device is used to provide clock signals to network devices. The passive clock device includes a clock generator and a pluggable interface. The clock generator and the pluggable interface are connected. The pluggable interface is used to connect to the network device. The clock generator is used to obtain the clock signal; The pluggable interface is used to output the clock signal to the network device when connected to the network device.

2. The passive clock device according to claim 1, characterized in that, The passive clock device also includes a temperature sensor, which is connected to the pluggable interface and the clock generator respectively. The temperature sensor is used to detect the temperature of the clock generator and outputs the temperature to the network device through the pluggable interface.

3. The passive clock device according to claim 1 or 2, characterized in that, The clock generator includes a clock source, which is connected to the pluggable interface. The clock source is used to generate the clock signal.

4. The passive clock device according to claim 1 or 2, characterized in that, The clock generator includes a clock source and a clock conversion module, the clock source and the clock conversion module are connected, and the clock conversion module is connected to the pluggable interface; The clock source is used to generate the original clock signal; The clock conversion module is used to convert the original clock signal generated by the clock source based on a preset frequency point to obtain the clock signal.

5. The passive clock device according to any one of claims 1-4, characterized in that, The pluggable interface is also used to receive preset frequency information sent by the network device, wherein the preset frequency information indicates a preset frequency.

6. The passive clock device according to any one of claims 1-5, characterized in that, The pluggable interface includes multiple output pins, which are used to output multiple clock signals to the network device.

7. The passive clock device according to any one of claims 1-6, characterized in that, The clock generator is integrated as a component of the passive clock device on the circuit board of the passive clock device, or the components of the clock generator are distributed and integrated on the circuit board of the passive clock device.

8. A single-board unit, characterized in that, The single board includes a connector, a clock generator, and a clock synchronization module, and the connector and the clock generator are respectively connected to the clock synchronization module; The connector is used to receive a first clock signal; The clock generator is used to generate a second clock signal; The clock synchronization module is used to obtain a local clock signal based on the first clock signal and the second clock signal, and to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received.

9. The single board according to claim 8, characterized in that, The clock synchronization module is specifically used to select the local clock signal from the first clock signal and the second clock signal.

10. The single board according to claim 9, characterized in that, The clock synchronization module is used to detect the first clock signal and the second clock signal based on the reference clock signal, and select the local clock signal from the first clock signal and the second clock signal based on the detection result.

11. The single board according to claim 9, characterized in that, The clock synchronization module is used to select the first clock signal as the local clock signal when it receives the first clock signal.

12. The single board according to claim 8, characterized in that, The clock synchronization module is specifically used to synchronize the second clock signal with the first clock signal to obtain the local clock signal.

13. The single board according to claim 12, characterized in that, The clock synchronization module is used to detect the first clock signal and the second clock signal based on the reference clock signal, and to synchronize the second clock signal based on the detection result and the first clock signal to obtain the local clock signal.

14. The single board according to any one of claims 8-13, characterized in that, The clock synchronization module is also used to perform clock synchronization based on the local clock signal when the reference clock signal is not received.

15. The single board according to any one of claims 8-13, characterized in that, The connector is connected to the service board of the network device; The connector is used to receive the first clock signal from the service board.

16. The single board according to any one of claims 8-15, characterized in that, The connector is also used to receive the temperature corresponding to the first clock signal; The clock synchronization module is also used to compensate the first clock signal based on the temperature.

17. A single-board, characterized in that, The single board includes a connector, a clock generator, and a clock synchronization module, and the connector and the clock generator are respectively connected to the clock synchronization module; The connector is used to receive a first clock signal; The clock generator is used to generate a local clock signal; The clock synchronization module is used to perform clock synchronization based on the reference clock signal and the local clock signal when a reference clock signal is received. The clock synchronization module is also used to perform clock synchronization based on the first clock signal and the local clock signal when the reference clock signal is not received.

18. The single board according to claim 17, characterized in that, The connector is connected to the service board of the network device; The connector is used to receive the first clock signal from the service board.

19. The single board according to claim 17 or 18, characterized in that, The connector is also used to receive the temperature corresponding to the first clock signal; The clock synchronization module is also used to compensate the first clock signal based on the temperature.

20. A network device, characterized in that, The network device includes the single board described in any one of claims 8-19.

21. A communication system, characterized in that, The communication system includes the passive clock device according to any one of claims 1-7 and the network device according to claim 20, wherein the network device is connected to the passive clock device.

22. A clock chip, characterized in that, The clock chip includes the clock synchronization module as described in any one of claims 8-19, or the clock chip includes the clock synchronization module and connector as described in any one of claims 8-19.

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