Interface synchronization method and apparatus, electronic device, storage medium, and product
Patent Information
- Application Number
- CN202611141472.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-30
- Publication Date
- 2026-10-30
AI Technical Summary
在最复杂的情况下（例如正确格式是16列256行），则需要依次尝试所有的格式，每次尝试都需要找特定同步码、验证帧格式、连续校验等，耗时非常长，导致设备从开机到能播放声音的延迟很高；此外，此过程也容易受到数据流中偶然出现的、与同步码相似的“假信号”干扰
[0010]第五方面，本申请实施例还提供了一种计算机程序产品，包括计算机程序和/或指令，所述计算机程序和/或指令被处理器执行时实现如上述任意实施例所述的接口同步方法。
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Figure CN123019938A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to an interface synchronization method, apparatus, electronic device, storage medium, and product. Background Technology
[0002] In the MIPI SoundWire interface protocol, synchronization logic includes static synchronization, physical layer (PHY) synchronization, and dynamic synchronization. Interface synchronization is the foundation and prerequisite for establishing a connection and initiating data transmission on the SoundWire interface. To achieve efficient interface synchronization, it is necessary to achieve real-time transmission as much as possible and reduce synchronization search latency, while also avoiding excessive resource consumption. Currently, the interface synchronization process in the protocol includes: after reset and cancellation, firstly, searching for the static synchronization word 8'hB1. After finding it twice consecutively, calibrating whether the current frame format (determined by row and column parameters) is valid and whether the frame format of subsequent frames is consistent with the current frame format. If both are consistent and the PHY synchronization word is correct, then jumping to the verification process of whether the dynamic synchronization word of 15 consecutive frames is correct. During this process, the value of the dynamic synchronization word changes sequentially according to the Linear Feedback Shift Register (LFSR) algorithm every 15 frames, and the dynamic synchronization word repeats every 15 frames.
[0003] However, the distribution of synchronization words is related to the data frame format. The location and distribution of synchronization word data within the data frame and data stream may differ under different frame formats. When multiple frame formats are available, it is necessary to find the correct one from among the various possible data frame formats. Based on the interface synchronization process described above, the traditional approach is to try each frame format one by one. For example, try the simplest format (e.g., 2 columns), and if it fails to synchronize correctly, try more complex formats (e.g., 4 columns and 6 columns). In the most complex case (e.g., the correct format is 16 columns and 256 rows), all formats need to be tried sequentially. Each attempt requires finding a specific synchronization code, verifying the frame format, and continuous verification, which is very time-consuming and results in a high delay from device power-on to sound playback. Furthermore, this process is easily interfered with by occasional "false signals" in the data stream that resemble the synchronization code.
[0004] In summary, for various frame formats, traditional interface synchronization processes suffer from high latency, complex control logic (state machines), and low efficiency. Designing an efficient interface synchronization method that simplifies control logic, reduces latency, quickly determines the correct frame format, and completes interface synchronization is a pressing issue. Summary of the Invention
[0005] This application provides an interface synchronization method, apparatus, electronic device, storage medium, and product to achieve rapid determination of data frame format and efficient completion of interface synchronization.
[0006] In a first aspect, embodiments of this application provide an interface synchronization method, including: Input steps: Input the received data stream into the shift register; Parallel comparison step: Based on the shift register, the static synchronization word is compared in parallel according to each column parameter in the parameter set to generate a matching signal corresponding to each column parameter; Synchronization word parsing verification steps: In response to a valid matching signal corresponding to any of the column parameters, perform the following operations in an independent path: The current path is searched for frame structure based on the column parameters to obtain candidate frame formats, and the PHY synchronization word and dynamic synchronization word are parsed based on the column parameters and the candidate frame formats. If the consecutive static synchronization word, PHY synchronization word, and dynamic synchronization word all pass verification, the format of the current communication frame is determined according to the column parameters and the corresponding candidate frame format, the interface synchronization is completed, and the synchronization word parsing and verification step ends. The synchronization word verification of the current path continues to be executed.
[0007] Secondly, embodiments of this application also provide an interface synchronization device, including: The input module is used to input the received data stream into the shift register; A parallel comparison module is used to compare the shift register with the static synchronization word in parallel according to each column parameter in the parameter set to generate a matching signal corresponding to each column parameter. The verification module, in response to a valid matching signal corresponding to any of the column parameters, performs the following operations in an independent path: The current path is searched for frame structure based on the column parameters to obtain candidate frame formats, and the PHY synchronization word and dynamic synchronization word are parsed based on the column parameters and the candidate frame formats. If the consecutive static synchronization word, PHY synchronization word, and dynamic synchronization word all pass verification, the format of the current communication frame is determined according to the column parameters and the corresponding candidate frame format, the interface synchronization is completed, and the synchronization word parsing and verification step ends. The synchronization word verification of the current path continues to be executed.
[0008] Thirdly, embodiments of this application provide an electronic device, including: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the interface synchronization method as described in the first aspect.
[0009] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the interface synchronization method as described in the first aspect.
[0010] Fifthly, embodiments of this application also provide a computer program product, including a computer program and / or instructions, wherein when the computer program and / or instructions are executed by a processor, they implement the interface synchronization method as described in any of the above embodiments.
[0011] This application provides an interface synchronization method, apparatus, electronic device, storage medium, and product. The interface synchronization method includes: inputting a received data stream into a shift register; comparing a static synchronization word in parallel with each column parameter in a parameter set based on the shift register to generate a matching signal corresponding to each column parameter; in response to a valid matching signal corresponding to any column parameter, performing the following operations in an independent path: performing a frame structure search on the current path based on the column parameters to obtain candidate frame formats, and parsing the PHY synchronization word and dynamic synchronization word based on the column parameters and the candidate frame formats; if consecutive static synchronization words, PHY synchronization words, and dynamic synchronization words all pass verification, determining the format of the current communication frame according to the column parameters and the corresponding candidate frame formats, completing interface synchronization, and ending the synchronization word parsing and verification step, while the synchronization word verification of the current path continues to execute. The above technical solution can obtain the matching results of each column parameter simultaneously by comparing it with the static synchronization word in parallel according to different column parameters, quickly lock the possible correct candidate frame format, and then verify multiple synchronization words based on the corresponding candidate frame format in parallel and independent paths, and finally determine the correct frame format, which simplifies the control logic, reduces latency, and improves the interface synchronization efficiency. Attached Figure Description
[0012] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0013] Figure 1 This is a schematic diagram illustrating the distribution of synchronization words in a data stream, as provided in one embodiment. Figure 2 A flowchart illustrating an interface synchronization method provided in an embodiment of this application; Figure 3This is a schematic diagram illustrating a parallel comparison of various column parameters with static synchronization words, provided as an embodiment. Figure 4 This is a schematic diagram illustrating an attempt to synchronize parameters in each column via independent paths, as provided in one embodiment. Figure 5 A schematic diagram illustrating one embodiment of the fastest synchronization period; Figure 6 This is a schematic diagram of the structure of an interface synchronization device provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0014] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present application are shown in the drawings, not all structures. Moreover, unless otherwise specified, the embodiments and features described in the present application can be combined with each other.
[0015] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. The process can be terminated when its operation is complete, but may also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subroutine, etc.
[0016] It should be noted that the concepts of "first" and "second" mentioned in the embodiments of this application are only used to distinguish different devices, modules, units or other objects, and are not used to limit the order of functions performed by these devices, modules, units or other objects or their interdependencies.
[0017] In the embodiments of this application, "multiple" refers to at least two unless otherwise specified.
[0018] In the embodiments of this application, "A / B" refers to A and / or B when there is no conflict, and can refer to A or B when there is a conflict.
[0019] The acquisition, storage, use, and processing of data in this application all comply with the relevant provisions of national laws and regulations.
[0020] In the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the relevant content of the solution.
[0021] For multiple frame formats, the traditional interface synchronization process is as follows: A. First, assume a column parameter (e.g., 2), in... Figure 1 In the data stream shown, the most significant bit (MSB) of the static synchronization word 8'hB1 is searched for as '1'. Then, after a 1-bit interval, it is checked whether it is the second bit '0' of 8'hB1. If it is 0, it is checked again after a 1-bit interval to see if it is the third bit '1'. Otherwise, the MSB bit '1' is searched again. B. If, according to 'A', a static synchronization word 8'hB1 is found within 512 time slots, it is marked as the first static synchronization word matching point. The search for static synchronization words will start again from this point, and a line counter will be triggered to record the line number when the second static synchronization word is found, which will be used as the line parameter determined for the first time.
[0022] C. If the second static synchronization word is found within 512 time slots, it is marked as the second static synchronization word matching point. At the same time, the row and column counter values at this time are temporarily stored, including the row parameter (ROW_1) and column parameter (COL_1). Based on this static synchronization point, PHY synchronization words and dynamic synchronization words are received and compared to see if they are correct (Note: This dynamic synchronization word comparison is the first of 15 consecutive dynamic synchronization word comparisons). It can be understood that the synchronization period in this embodiment is: after the first static synchronization word is detected, there are 14 frame periods, that is, after 15 static synchronizations, plus 22 rows; the comparison of the 15th dynamic synchronization word is the fastest synchronization detection time). D. Following the methods described in 'A', 'B', and 'C' above, continue searching for the third static synchronization word within 512 time slots and obtain the matching point of the third static synchronization word. At the same time, obtain the row and column parameters (ROW_2) and column parameters (COL_2) at this time. Compare whether ROW_1 and ROW_2, and COL_1 and COL_2 are equal to further eliminate abnormal matching of static synchronization words. If they are equal, continue searching. If they are not equal, exit the synchronization search process of the current column parameter and switch to the synchronization search of the next column parameter (such as 4). For the next column parameter, still search according to the methods described in 'A', 'B', 'C', and 'D' above. E. Based on the row and column parameters (ROW_2, COL_2) obtained from item 'D', check whether the PHY synchronization word and dynamic synchronization word parsed in each frame are consistent with the protocol requirements. If they are consistent, verify the synchronization again after 14 consecutive frame cycles. Then, determine that the synchronization of this channel is complete, the row and column parameters (ROW_2, COL_2) are the correct frame format parameters, and update them in the FrameCtrl register. F. In items 'A', 'B', 'C', 'D', and 'E' above, any error indicates that the synchronization of the current column parameter has failed, the synchronization process of the current column parameter ends, and the synchronization search process for the next column parameter begins.
[0023] Following the steps described above, the synchronization process is executed with column parameters 4, 6, 8, 10, 12, 14, and 16 until the correct frame format is determined, at which point the search for the remaining column parameters is stopped.
[0024] Based on the above search process and the maximum values of row and column parameters (16 and 256), the fastest scenario is: row parameter 48, column parameter 2. Synchronization can be completed by searching only column parameter 2, corresponding to 16 frames and 96 time slots, with a complexity of 16 × 96 = 1536. The slowest scenario is: both row and column parameters are at their maximum values, requiring a search for all column parameters (e.g., 2, 4, 6, 8, 10, 12, 14), corresponding to 16 frames, with a complexity of 16 × (256). ×16)+(256*2+256*4+256*6+256*8+256*10+256*12+256*14)=79872 time slots; In addition, for the extreme static + dynamic matching case, a maximum of 16 frames need to be searched, corresponding to 16×(256*2+256*4+256*6+256*8+256*10+256*12+256*14+256*16)=294912 time slots.
[0025] As can be seen, the traditional interface synchronization process attempts to synchronize serially for different frame formats (column parameters), resulting in high latency, highly complex control logic (state machine), and low efficiency. This application aims to design an efficient interface synchronization method that simplifies control logic, reduces latency, quickly determines the correct frame format, and completes interface synchronization.
[0026] Figure 2This is a flowchart illustrating an interface synchronization method provided in an embodiment of this application. This embodiment is applicable to interface synchronization scenarios. Specifically, the interface synchronization method can be executed by an interface synchronization device, which can be implemented through software and / or hardware and integrated into an electronic device. The electronic device includes, but is not limited to, devices with data processing capabilities such as computers, smartphones, or servers, and can also be a central processing unit (CPU), a system-on-chip (SoC), a field-programmable gate array (FPGA), or a microcontroller unit (MCU), etc.
[0027] like Figure 2 As shown, the method specifically includes the following steps: S110. Input the received data stream into the shift register.
[0028] For example, the shift register can be a 111-bit shifter.
[0029] S120: Based on the shift register, the static synchronization word is compared in parallel according to each column parameter in the parameter set to generate a matching signal corresponding to each column parameter.
[0030] In this embodiment, synchronization is attempted in parallel for different frame formats (column parameters). For example, there are 8 column parameters (such as 2, 4, 6, 8, 10, 12, 14, 16). Static synchronization word matching can be performed on each column parameter in multiple parallel paths, branches, or processes. For any column parameter, if a static synchronization word 8'hB1 (refer to 'A' above) is found by comparing with the static synchronization word, a valid matching signal (match_i, i=1,2,……8) is generated for that column parameter, and the found static synchronization word is marked as the first static synchronization word matching point.
[0031] Understandably, if there are 8 column parameters, comparing them with the static synchronization word can generate a minimum of 1 and a maximum of 8 matching signals. For each matching signal, subsequent synchronization word parsing and verification can be performed through the corresponding path. The relationship between matching signals and paths can be one-to-one or many-to-one. That is, if there are x matching signals, the total number of paths can be a positive integer less than or equal to x, meaning each path can be used to perform synchronization word parsing and verification for at least one column parameter. Different paths are parallel and independent. If synchronization word parsing and verification for at least two column parameters is required within a single path, it can be performed serially.
[0032] S130. In response to the valid matching signal corresponding to any of the column parameters, a synchronization word parsing verification is performed in an independent path.
[0033] In this embodiment, if a static synchronization word for a column parameter is successfully matched (generating a valid matching signal), then the column parameter may be a column parameter of the current frame format. The subsequent synchronization word parsing and verification process can be performed based on the column parameter in an independent path, including verification of static synchronization words for multiple consecutive frames as well as parsing and verification of PHY synchronization words and dynamic synchronization words. If the verification of static synchronization words, PHY synchronization words, and dynamic synchronization words for multiple consecutive frames in the path is correct, then the column parameter corresponding to the path can be determined to be the correct frame format, and synchronization can be completed without considering and trying other column parameters.
[0034] Furthermore, the synchronization word parsing verification steps include: S140. Based on the column parameters, perform a frame structure search on the current path to determine the candidate frame format, and parse the PHY synchronization word and dynamic synchronization word based on the candidate frame format.
[0035] In this embodiment, if the matching signal corresponding to a column parameter is valid, then in an independent path, a frame structure search is performed according to the column parameter to determine the row parameter. The row parameter and the column parameter together determine the candidate frame format. Then, based on this candidate frame format, the PHY synchronization word and dynamic synchronization word can be parsed, and various types of synchronization words in multiple consecutive frames can be verified.
[0036] For example, for a valid match signal, if a static synchronization word 8'hB1 is found within 512 time slots in the corresponding path, it is marked as the first static synchronization word match point, the match signal is valid, and from that point or that moment, the search for static synchronization words begins again, and the line counter is triggered to count. When the second static synchronization word is found, it is marked as the second static synchronization word match point. At this time, the line count value (ROW_1) of the line counter can be used as the line parameter. This line parameter and the column parameter (COL_1) of the current path determine the candidate frame format.
[0037] Furthermore, using the second static synchronization word matching point as a reference, the reception of PHY synchronization words and dynamic synchronization words begins. If a third static synchronization word is found within 512 time slots, it is marked as the third static synchronization word matching point. Simultaneously, the row parameter (ROW_2, which can be determined based on the difference in row count values between the two static synchronization word matching points, indicating how many rows have passed since the next static synchronization word was found) and column parameter (COL_2) are obtained. It is then determined whether ROW_1 and ROW_2 are equal, and whether COL_1 and COL_2 are equal. If both are equal, it indicates that the candidate frame format is conformed to, further confirming the correctness of the candidate frame format. Based on this, abnormal matching and interference of static synchronization words can be further eliminated. This process can be repeated to verify the correctness of static synchronization words in multiple consecutive frames based on multiple static synchronization word matching points.
[0038] S150. Verify the static synchronization word, PHY synchronization word, and dynamic synchronization word with continuously set frame numbers.
[0039] S160. If the consecutive static synchronization word, PHY synchronization word, and dynamic synchronization word all pass the verification, then execute S180; otherwise, if any one of the synchronization words fails the verification, then execute S170.
[0040] For example, by searching for static synchronization words, multiple consecutive frames can be obtained. Based on the row and column parameters (ROW_2, COL_2), the PHY synchronization words and dynamic synchronization words obtained from parsing each frame are judged to determine whether they are consistent with the protocol requirements. If they are consistent, synchronization can be determined to be completed after setting the frame period (e.g., 14 frame period) as quickly as possible. The candidate frame format is the correct format of the current communication frame.
[0041] S170, Exclude the candidate frame formats.
[0042] S180. Determine that the format of the current communication frame is the candidate frame format, complete the interface synchronization and stop the synchronization word parsing and verification steps of all other channels, and continue to execute the synchronization word verification of the current channel.
[0043] It should be noted that synchronization word parsing and verification are performed separately for different potentially correct column parameters in multiple independent paths. Once the synchronization word parsing and verification in any one path (first) is completed, the correct format of the current communication frame can be determined, and interface synchronization can be completed. In this case, the synchronization word parsing and verification steps of other paths can be stopped unconditionally, while the synchronization word verification of the current path can continue to be executed. If any subsequent synchronization word is incorrect, it means that the current path does not correspond to the correct candidate frame format. In this case, the synchronization word parsing and verification for all valid matching signals (i.e., for all paths) can be restarted.
[0044] This application provides an interface synchronization method that, by comparing static synchronization words with different column parameters in parallel, can simultaneously obtain the matching results of each column parameter, quickly identifying potentially correct candidate frame formats. Then, in parallel and independent paths, multiple synchronization words are verified based on the candidate frame formats to ultimately determine the correct frame format. This simplifies control logic, reduces latency, and improves interface synchronization efficiency. Furthermore, by combining a limited number of column parameter types, even for the largest candidate frame format, its latency is better than the minimum 16 frames described in the protocol, corresponding to a fastest latency of 1536 and a slowest of 65536 cycles. By adding a small amount of resources, the search control logic and optimal search latency can be effectively simplified, balancing resource availability and timeliness.
[0045] In one embodiment, a frame structure search is performed on the current path based on column parameters to determine the candidate frame format, including: Starting from the moment when the matching signal corresponding to the column parameter becomes valid, the input data rows are counted using a row counter; When the matching signal corresponding to the column parameter is valid in the next instance, if the count value of the row counter meets the frame format requirements, the candidate frame format is determined based on the count value and the column parameter.
[0046] In this embodiment, for a column parameter, the moment its corresponding matching signal is valid (i.e., the moment the first static synchronization word matching point is found) is when the input data row is counted using a row counter. When the matching signal becomes valid again (i.e., the moment the second static synchronization word matching point is found), if the row counter's count value meets the frame format requirements, it can be used as a row parameter to determine the candidate frame format. The frame format requirements mainly refer to the row counter's count value being within a reasonable range—neither too small nor too large. If the count value does not meet the frame format requirements, i.e., exceeds the reasonable range (e.g., too large or too small), the corresponding column parameter can be excluded. Based on this, potentially correct candidate frame formats can be quickly identified.
[0047] In one embodiment, the frame format requires that the line counter's count value is not less than a lower limit and does not exceed an upper limit.
[0048] For example, if the number of rows between two static synchronization word matching points is less than the lower limit (e.g., 48), it is considered an anomaly; if it exceeds the upper limit (e.g., 256), meaning no valid matching signal has been generated within the valid time, it is considered a timeout. In both cases, the corresponding column parameter can be excluded, terminating the attempt for that column parameter, without needing to perform subsequent synchronization word parsing and verification. However, the frame structure search for other column parameters in other paths continues unaffected. Based on this, erroneous frame formats can be quickly eliminated, avoiding unnecessary processing.
[0049] In one embodiment, the synchronization word parsing verification step further includes: if the row counter's count value does not meet the frame format requirements or the dynamic synchronization word is incorrect when the matching signal corresponding to the column parameter is valid in the next instance, then the next matching signal is searched again.
[0050] In this embodiment, if the line counter value does not meet the frame format requirements or the dynamic synchronization word is incorrect when the next matching signal is valid, it may be an abnormal match or interference. In this case, this matching signal can be disregarded as the matching point for the static synchronization word and treated as an invalid matching signal. The next matching signal can be searched again until the static synchronization word and dynamic synchronization word for a set number of consecutive frames are correct, and the PHY synchronization word of the last frame is also correct. Then, the synchronization word parsing and verification of this path is completed. Based on this, interference can be effectively eliminated, and the reliability of interface synchronization can be improved.
[0051] In one embodiment, the verification of static synchronization words, PHY synchronization words, and dynamic synchronization words for a continuously set number of frames includes: Based on the valid matching signal, after the first synchronization is completed, continuously verify whether the static synchronization word is correct; Using the first dynamic synchronization word obtained from parsing as a benchmark, verify whether the dynamic synchronization word is correct for a continuously set number of frames. Then, continuously verify whether the dynamic synchronization word is correct and repeat according to the continuously set number of frames. If the dynamic synchronization word of the last frame passes verification, verify whether the PHY synchronization word of the last frame is correct, and then continue to verify whether the PHY synchronization word of each frame is correct.
[0052] In this embodiment, the process of verifying various types of synchronization words includes: By searching for static sync word matching points, and based on the number of rows between each search and the next static sync word, it is possible to continuously verify whether the static sync words for a set number of consecutive frames (e.g., 15 frames) are correct. Using the dynamic synchronization word obtained by parsing the second static synchronization word matching point as the reference, the first dynamic synchronization word can be used to verify whether the dynamic synchronization word is correct for a continuously set number of frames (e.g., 15 frames). After that, the dynamic synchronization word can be continuously verified to see if it appears correctly in a loop according to the continuously set number of frames. If the dynamic synchronization words for the consecutive frame numbers are all correct, and the PHY synchronization word for the last frame is also correct, then synchronization is complete and verification is passed. After that, the PHY synchronization word for each frame can be continuously verified to ensure it is correct.
[0053] Based on this, the correctness of the determined frame format can be guaranteed by the above-mentioned synchronization word parsing verification, thereby improving the reliability of interface synchronization.
[0054] In one embodiment, the number of paths in the synchronization word parsing verification step is greater than 1 and less than or equal to the total number of column parameters in the parameter set.
[0055] In this embodiment, if there are x matching signals, the total number of paths can be a positive integer less than or equal to x, meaning each path can be used to perform synchronization word parsing verification on at least one column parameter. The total number of paths can be flexibly set according to actual needs. For example, with sufficient resources, eight paths can be used, each path attempting synchronization on a corresponding column parameter; conversely, with insufficient resources, fewer paths, such as four paths, can be used, each path attempting synchronization on one or more corresponding column parameters sequentially. If the synchronization word parsing verification of any column parameter in any path is completed, the correct frame format has been found and interface synchronization is complete. Based on this, resource allocation and latency control during the interface synchronization process can be considered, improving overall efficiency.
[0056] Figure 3 This is a schematic diagram illustrating a parallel comparison of various column parameters with a static synchronization word, as provided in one embodiment. As shown in Figure 3, the input data bits are sampled once per clock cycle and stored in the Shift_111 shift register. The corresponding bits for each of the eight column parameters (2, 4, 6, 8, 10, 12, 14, 16) are retrieved and compared with the static synchronization word 8'hB1 using a comparator (CMP). The matching result is then recorded in the corresponding bit of the 8-bit match_fg flag register. For example, if the matching result for column parameter Col2 is match_2, the match_2 pulse is triggered.
[0057] Figure 4 This is a schematic diagram illustrating an embodiment of an attempt to synchronize eight column parameters through eight independent paths. For example... Figure 4As shown, when match_i is 1, the row counter cn_row_cnt corresponding to that column parameter starts counting, and the dynamic synchronization word and PHY synchronization word are parsed according to the column parameter. When match_i is 1 again and the row counter is less than 256, the row count value is latched together with the column parameter as the frame row and column parameters for this path, and subsequent frame data is parsed. At the same time, the parsed dynamic synchronization word is used as the first value of 15 dynamic synchronization words, and subsequent values are used as the basis to determine whether the dynamic synchronization word is correct, until the 15 dynamic synchronization words are correct. The system continues parsing subsequent data using the parameters described above. If a `match_i` is valid but the row parameters differ from previous ones or the dynamic synchronization word is incorrect, the synchronization judgment for this `match_i` ends, and a new `match_i` judgment begins. This continues until 15 consecutive frames of static and dynamic synchronization words are correct, and the PHY synchronization word in the 15th frame is also correct. At this point, the synchronization for this path is complete, `match_fgn` goes high, and the row and column parameters of this path become the row and column parameters of the frame structure. The entire synchronization process ends, meaning the synchronization of other paths immediately and unconditionally ends. For subsequent data, the synchronization word verification for this path can continue. If any synchronization word is incorrect, the synchronization word parsing and verification for all paths can be restarted. Furthermore, in the check and judgment logic of each `match_i` path, if the number of rows between two `match_n` pairs is less than 48, it is considered an anomaly; if it exceeds 256, it is considered a timeout, and the synchronization logic for this path immediately restarts.
[0058] It should be noted that, Figure 4 The system is described using 8 columns of parameters in a fully parallel manner, which minimizes the synchronization time. In actual use, it can be flexibly modified to 4-channel, 2-channel, etc., depending on the requirements for delay and resource balance. If it is changed to 1-channel, it is a fully serial mode.
[0059] Figure 5 This is a schematic diagram illustrating one embodiment of the fastest synchronization period. (As shown...) Figure 5 As shown, the synchronization process within a single path, from detecting the first static synchronization word match point to completing the synchronization detection, takes at least 14 frames + 22 lines.
[0060] The method in this application, combining a limited number of column parameter types, introduces a shift register to compare the static synchronization words of all column parameters in real time, simultaneously obtaining matching results for multiple column parameters. This results in extremely fast synchronization speed and significantly reduced latency. For abnormal matches and interference without static synchronization words, synchronization can be completed within a fixed 15 frames. For cases with Y abnormal interference matches, synchronization can be completed within a maximum of 15+Y frames. This method can quickly complete the search with low latency, achieving synchronization in as little as 15 frames and as long as 15+Y frames. The synchronization process has clear logic and simple control; each column parameter is independently judged and controlled, without priority, loop, or other switching controls. Multiple numerical comparisons and a multi-channel parallel structure are incorporated into the synchronization process, allowing for rapid elimination of heavy interference matches. The mechanism of "preliminary matching to lock the frame format + precise verification of multiple types of synchronization words" effectively filters out occasional interference signals (false synchronization) resembling synchronization codes in the data stream, resulting in high efficiency and high reliability in the interface synchronization process.
[0061] Figure 6 This is a schematic diagram of an interface synchronization device provided in an embodiment of this application. Figure 6 As shown, the interface synchronization device provided in this embodiment includes: Input module 210 is used to input the received data stream into the shift register; The parallel comparison module 220 is used to compare the static synchronization word in parallel according to each column parameter in the parameter set based on the shift register, so as to generate a matching signal corresponding to each column parameter. Synchronization word parsing verification module 230 is configured to perform the following operations in an independent path in response to a valid matching signal corresponding to any of the column parameters: The current path is searched for frame structure based on the column parameters to determine the candidate frame format, and the PHY synchronization word and dynamic synchronization word are parsed based on the candidate frame format. The static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames are verified. If the static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames all pass the verification, the format of the current communication frame is determined to be the candidate frame format. The interface synchronization is completed and the synchronization word parsing and verification steps of all other channels are stopped. The synchronization word verification of the current channel continues to be executed.
[0062] This device can obtain the matching results of each column parameter simultaneously by comparing it with the static synchronization word in parallel according to different column parameters, quickly lock the possible correct candidate frame format, and then verify multiple synchronization words based on the corresponding candidate frame format in parallel and independent paths, and finally determine the correct frame format. This simplifies the control logic, reduces latency, and improves the interface synchronization efficiency.
[0063] Based on any of the above embodiments, a frame structure search is performed on the current path based on the column parameters to determine the candidate frame format, including: Starting from the moment when the matching signal corresponding to the column parameter becomes valid, the input data rows are counted using a row counter; When the matching signal corresponding to the column parameter is valid in the next instance, if the count value of the row counter meets the frame format requirements, the candidate frame format is determined based on the count value and the column parameter.
[0064] Based on any of the above embodiments, the synchronization word parsing verification module 230 is further configured to: when the matching signal corresponding to the column parameter is valid in the next time, if the count value of the row counter does not meet the frame format requirements, the interface synchronization based on the column parameter fails, and the candidate frame format is excluded.
[0065] Based on any of the above embodiments, the synchronization word parsing and verification module 230 is further configured to: if the count value of the row counter does not meet the frame format requirements or the dynamic synchronization word is incorrect when the matching signal corresponding to the column parameter is valid in the next instance, then search for the next one again.
[0066] Based on any of the above embodiments, the verification of the static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames includes: Based on the valid matching signal, after the first synchronization is completed, continuously verify whether the static synchronization word is correct; Using the first dynamic synchronization word obtained from parsing as a benchmark, verify whether the dynamic synchronization word is correct for a continuously set number of frames. Then, continue to verify whether the dynamic synchronization word is correct and appear in a loop according to the continuously set number of frames. If the dynamic synchronization word of the last frame passes verification, verify whether the PHY synchronization word of the last frame is correct, and then continue to verify whether the PHY synchronization word of each frame is correct.
[0067] Based on any of the above embodiments, the number of paths in the synchronization word parsing and verification step is greater than 1 and less than or equal to the total number of column parameters in the parameter set.
[0068] The interface synchronization device provided in this application embodiment can be used to execute the interface synchronization method provided in any of the above embodiments, and has corresponding functions and beneficial effects.
[0069] Figure 7A schematic diagram of an electronic device 10, which can be used to implement embodiments of this application, is shown. The electronic device 10 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 10 may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, user equipment, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.
[0070] like Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.
[0071] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks and wireless networks.
[0072] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above.
[0073] In some embodiments, the methods described above can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the methods of any of the embodiments described above by any other suitable means (e.g., by means of firmware).
[0074] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0075] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0076] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0077] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device 10, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device 10. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0078] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.
[0079] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.
[0080] This application also provides a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the interface synchronization method as described in any of the above embodiments.
[0081] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0082] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. An interface synchronization method, characterized in that, include: Input steps: Input the received data stream into the shift register; Parallel comparison step: Based on the shift register, the static synchronization word is compared in parallel according to each column parameter in the parameter set to generate a matching signal corresponding to each column parameter; Synchronization word parsing verification steps: In response to a valid matching signal corresponding to any of the column parameters, perform the following operations in an independent path: The current path is searched for frame structure based on the column parameters to determine the candidate frame format, and the PHY synchronization word and dynamic synchronization word are parsed based on the candidate frame format. The static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames are verified. If the static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames all pass the verification, the format of the current communication frame is determined to be the candidate frame format. The interface synchronization is completed and the synchronization word parsing and verification steps of all other channels are stopped. The synchronization word verification of the current channel continues to be executed.
2. The method according to claim 1, characterized in that, Based on the column parameters, a frame structure search is performed on the current path to determine the candidate frame format, including: Starting from the moment when the matching signal corresponding to the column parameter becomes valid, the input data rows are counted using a row counter; When the matching signal corresponding to the column parameter is valid in the next instance, if the count value of the row counter meets the frame format requirements, the candidate frame format is determined based on the count value and the column parameter.
3. The method according to claim 2, characterized in that, The frame format requirements include: The count value of the row counter is not less than the lower limit and does not exceed the upper limit.
4. The method according to claim 2, characterized in that, The synchronization word parsing and verification step also includes: If the row counter does not meet the frame format requirements or the dynamic synchronization word is incorrect when the matching signal corresponding to the column parameter is valid in the next time, the next matching signal will be searched again.
5. The method according to any one of claims 1-4, characterized in that, The verification of static synchronization words, PHY synchronization words, and dynamic synchronization words for a continuously set number of frames includes: Based on the valid matching signal, after the first synchronization is completed, continuously verify whether the static synchronization word is correct; Using the first dynamic synchronization word obtained from parsing as a benchmark, verify whether the dynamic synchronization word is correct for a continuously set number of frames. Then, continuously verify whether the dynamic synchronization word is correct and repeat according to the continuously set number of frames. If the dynamic synchronization word of the last frame passes verification, verify whether the PHY synchronization word of the last frame is correct, and then continue to verify whether the PHY synchronization word of each frame is correct.
6. The method according to any one of claims 1-4, characterized in that, The number of paths in the synchronization word parsing and verification step is greater than 1 and less than or equal to the total number of column parameters in the parameter set.
7. An interface synchronization device, characterized in that, include: The input module is used to input the received data stream into the shift register; A parallel comparison module is used to compare the shift register with the static synchronization word in parallel according to each column parameter in the parameter set to generate a matching signal corresponding to each column parameter. The synchronization word parsing and verification module, in response to a valid matching signal corresponding to any of the column parameters, performs the following operations in an independent path: The current path is searched for frame structure based on the column parameters to determine the candidate frame format, and the PHY synchronization word and dynamic synchronization word are parsed based on the candidate frame format. The static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames are verified. If the static synchronization word, PHY synchronization word, and dynamic synchronization word for a continuously set number of frames all pass the verification, the format of the current communication frame is determined to be the candidate frame format. The interface synchronization is completed and the synchronization word parsing and verification steps of all other channels are stopped. The synchronization word verification of the current channel continues to be executed.
8. An electronic device, characterized in that, include: At least one processor; A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the interface synchronization method as described in any one of claims 1-6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the interface synchronization method as described in any one of claims 1-6.
10. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the interface synchronization method as described in any one of claims 1-6.