FPGA hardware time stamping hierarchical servo master-slave pps synchronization method and system

Abstract

The application discloses a layered servo master-slave PPS synchronization method and system based on FPGA hardware time stamp, and belongs to the technical field of time synchronization, digital communication and FPGA hardware time sequence control. The method is characterized in that: asynchronous FIFO is used to convert Ethernet recovery clock domain message data into a system clock domain, candidate time stamps are latched at the edges of message transmission and reception, and hardware time stamps are output after PTP effective frames are identified; time stamps are obtained through message interaction, link average time delay and master-slave clock deviation are calculated, calculation precision is improved by combining half-second normalization processing, and abnormal time stamp samples are filtered and removed. The layered servo master-slave PPS synchronization method and system based on FPGA hardware time stamp are used to realize nanosecond-level master-slave PPS synchronization, and the internal clock index and external PPS observation are decoupled and controllable, so that the method and system are suitable for Ethernet high-precision time synchronization scenes of FPGA measurement and control platforms and distributed data acquisition platforms.

Description

Technical Field

[0001] This invention belongs to the fields of time synchronization and digital communication, and FPGA hardware timing control technology, specifically involving a hierarchical servo master-slave PPS synchronization method and system based on FPGA hardware timestamps. Background Technology

[0002] In FPGA measurement and control platforms, distributed data acquisition, industrial Ethernet distributed nodes, and networked instrumentation scenarios, each master and slave node needs to establish a unified high-precision time reference to ensure the timing consistency of multi-node data acquisition, timing control, and collaborative work. The edge characteristics of the second pulse (PPS) are clear and can be directly observed with an oscilloscope, making it a core measure of the time synchronization effect of distributed nodes. In engineering applications, the goal is to leverage a general-purpose FPGA Ethernet architecture to achieve low-cost, rapidly deployable nanosecond-level master-slave PPS synchronization without requiring dedicated timing chips or high-precision clock chips.

[0003] Existing FPGA+PTP time synchronization solutions have significant shortcomings when implemented: the Ethernet physical layer recovery clock directly participates in the synchronization logic, resulting in poor stability and susceptibility to PPS edge jitter; PTP sensitive packets share the transmission link with ARP, ICMP, and UDP service packets, lacking priority scheduling and easily blocked by long packets, leading to significant uncertainty in packet transmission timing; packet parsing, real-time clock, and servo control belong to different clock domains, and cross-domain interaction can easily cause hardware timestamp mismatch, degrading synchronization accuracy; the inherent fixed phase deviation of PPS is directly integrated into the correction closed loop, causing discrepancies between internal clock performance and external oscilloscope observations, making debugging and calibration difficult; traditional single PID or fixed-step servo algorithms converge slowly and are prone to phase oscillation after locking; there is a lack of timestamp validity verification and delay anomaly sample removal mechanisms, making it easy for network disturbances to cause clock transition loss of synchronization; at the same time, most high-precision solutions rely on dedicated timing chips, resulting in high hardware costs and making it difficult to adapt to the low-cost application requirements of general-purpose FPGA projects.

[0004] Therefore, in view of the above-mentioned defects in the existing technology, the present invention proposes a master-slave PPS synchronization scheme based on FPGA hardware timestamp and hierarchical servo correction. Summary of the Invention

[0005] The purpose of this invention is to provide a hierarchical servo master-slave PPS synchronization method and system based on FPGA hardware timestamps. This method achieves nanosecond-level master-slave PPS synchronization, and the internal clock index is decoupled and controllable from the external PPS observation. It is suitable for Ethernet high-precision time synchronization scenarios of FPGA measurement and control platforms and distributed data acquisition platforms.

[0006] To achieve the above objectives, this invention provides a hierarchical servo master-slave PPS synchronization method and system based on FPGA hardware timestamps, comprising the following steps: S1. Construct a unified system clock domain for master and slave nodes based on onboard crystal oscillator and FPGA phase-locked loop; S2. Based on the system clock domain provided by S1, the cross-clock domain data migration is completed at the receiving end. The received data from the Ethernet physical layer recovery clock domain is transferred to the system clock domain. Candidate timestamps are latched at the message transmission and reception edges. Valid timestamps are generated only for PTP protocol messages. The preprocessed valid timing data is output to S3. S3. Based on the valid timing data output by S2, the master node and the slave node complete the closed-loop timing interaction through four types of PTP messages. Relying on the hardware timestamp unit TSU, four sets of reference timestamps are collected respectively: master node sending time T1, slave node receiving time T2, slave node sending time T3, and master node receiving time T4. The PTP message is configured with the highest sending arbitration priority, and four sets of reference timestamps are output. S4. Based on the four sets of reference timestamps output by S3, the master-slave clock deviation and average link delay are calculated from the node, and the servo control error is generated. At the same time, distorted and abnormal timestamp samples are removed, and the servo control error is output. S5. Based on the servo control error output by S4, the slave node adopts a hierarchical servo control algorithm, and corrects the slave real-time clock RTC by superimposing phase stepping and frequency fine-tuning dual components, and outputs the RTC clock count value. S6. Based on the RTC clock count value output by S5, without changing the internal real-time clock and synchronous closed-loop logic, the system is divided into a physically isolated real protocol closed loop and an output-side compensation path. Only the nanosecond register value inside the real-time clock is read and compared with the configurable phase calibration threshold to generate a PPS pulse. Fixed phase deviation independent calibration compensation is completed on the PPS output link. The calibration process does not enter the synchronous closed loop and outputs the calibrated PPS second pulse signal. S7. Based on the calibrated PPS second pulse signal output by S6, output the PPS second pulse signals of the master node and the slave node. Observe the phase difference between the two PPS signals with an oscilloscope to complete the synchronization effect verification.

[0007] Preferably, S1 specifically includes: A 50MHz onboard passive crystal oscillator is used in conjunction with an FPGA phase-locked loop to generate a 125MHz system master clock and a 200MHz physical layer auxiliary clock. This ensures that the real-time clock counting unit, PTP message transmission and parsing module, hardware timestamp unit, hierarchical servo control module, and second pulse output calibration module are all constrained to operate synchronously within the 125MHz system clock domain.

[0008] Preferably, S2 specifically includes: Cross-clock domain data buffer migration is accomplished through asynchronous FIFO; candidate timestamps are generated by latching on the rising edge of the message transmission enable signal and the rising edge of the received data valid signal; the candidate timestamp is determined to be valid only when the Ethernet frame Ethernet type field is a PTP exclusive identifier, and the timestamps corresponding to other frame types are directly discarded.

[0009] Preferably, the four types of PTP messages in S3 include Sync, Follow_Up, Delay_Req, and Delay_Resp. The specific interaction process includes the following sub-steps: S301. When the master node TSU latches the Sync message, it generates T1, encapsulates T1 into a Follow_Up message, and sends the Sync message and Follow_Up message with high priority. S302, T2 is generated when the TSU latches the Sync message and receives it. After parsing the Follow_Up message, T3 is generated when the Delay_Req message is latched and sent. Then, the Delay_Req message is sent to the master node. S303: The master node TSU latches the Delay_Req message and generates T4 at the moment of receiving the message. The T4 is then encapsulated into a Delay_Resp message and sent back to the slave node. Among them, PTP messages have a higher priority than ARP, ICMP, and UDP ordinary service messages, and the cycle of a single round of complete message interaction is fixed at 1 second.

[0010] Preferably, S4 specifically includes: The time difference between T2-T1 and T4-T3 is subject to a 500ms half-second normalization constraint to eliminate the second boundary counting jump error; the average link delay and master-slave clock deviation are calculated through a 64-bit signed number arithmetic path, and the negative value of the clock deviation is used as the servo control error; distorted samples that exceed the 200ns hard anomaly threshold and the 100ns path delay anomaly threshold are removed. The formulas for calculating master-slave clock skew and average link delay are as follows: ; ； ; In the formula, This represents the average transmission delay of the link. The inherent clock bias between master and slave nodes; This is the input error for layered servo control.

[0011] Preferably, in S5, the slave node adopts a hierarchical servo control algorithm as follows: The system is divided into four control modes by setting three error thresholds: 50ns for coarse adjustment, 15ns for fine adjustment, and 3ns for dead zone. For errors greater than 50ns, a coarse adjustment step of 5ns / step is used; for errors between 15ns and 50ns, a medium adjustment step of 2ns / step is used; for errors between 3ns and 15ns, a fine adjustment step of 0.5ns / step is used; and when the error is less than 3ns, phase stepping is stopped and only frequency correction is retained. Correct the real-time clock using the formula: ; In the formula, To correct the clock count value before calibration, For the corrected clock count value, This is the phase step adjustment amount. This is the frequency fine-tuning correction amount; the limiting range for all correction amounts is [-20ns, +20ns].

[0012] This invention also provides an FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization system, comprising: The master node and the slave node exchange four types of PTP packets via an Ethernet link; The master node is the time reference side, including a local crystal oscillator / phase-locked loop, a main RTC, a main TSU, a main PTP module, a transmit arbitration module, a main PPS output module, and a PHY interface, used to generate a reference clock, latch transmit timestamps, encapsulate transmit synchronization messages, and output a reference PPS signal; The slave node is the time synchronization side, including a local crystal oscillator / phase-locked loop, slave RTC, slave TSU, slave PTP parsing module, hierarchical servo module, CDC cross-clock domain module, slave PPS output calibration module and PHY interface, used to complete cross-clock domain processing, timestamp acquisition, clock deviation correction and output side phase calibration; The arbitration sending module configures PTP messages to have the highest transmission priority, blocking ARP, ICMP, and UDP long packets from interfering with the synchronization messages. The CDC cross-clock domain module uses asynchronous FIFO to realize the data migration from the recovery clock domain to the system clock domain, eliminating cross-domain timing jitter and timestamp misalignment problems. The layered servo module has built-in four levels of control logic: coarse adjustment, medium adjustment, fine adjustment, and dead zone, which enables the slave clock to converge quickly and lock in a steady state without oscillation. The phase calibration logic of the PPS output calibration module is independently configured and physically isolated from the internal synchronization closed loop, and does not provide feedback to correct the RTC clock count value and hardware timestamp.

[0013] The present invention also provides a master-slave PPS synchronization device, comprising: The device is based on an FPGA programmable logic device, and its peripheral components include an onboard oscillator, phase-locked loop resources, an Ethernet PHY interface, a PPS output interface, a debug interface, and a configuration storage medium. The FPGA integrates an RTC real-time clock module, a TSU timestamp module, a PTP message interaction module, a CDC cross-clock domain module, a hierarchical servo correction module, and a PPS output calibration module, thus solidifying the synchronization method into a hardware pipeline processing link. When using an FPGA SoC architecture, parameter configuration, status monitoring, and data display auxiliary functions are implemented through the PS processor side; The measured master-slave PPS synchronization error of the device is stable at 7ns~20ns, and the remaining synchronization error of the internal clock is stable at 8ns~40ns, achieving nanosecond-level high-precision time synchronization.

[0014] Therefore, the present invention employs the above-mentioned FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method and system. Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) A unified 125MHz system clock domain is adopted across the entire domain, and the Ethernet PHY recovery clock is abandoned to participate in the synchronization logic. The clock domain of all synchronization modules is uniformly constrained. This solves the problems of multiple clock domains, timing jitter, and timestamp misalignment in traditional solutions. It ensures the accuracy of timestamp acquisition from the hardware level and improves the stability of the synchronization system. (2) A four-level layered servo combined with phase and frequency dual-component superposition correction algorithm is adopted, along with abnormal timestamp filtering and correction amount limiting mechanism; overcoming the defects of traditional single PID algorithm such as slow convergence, easy overshoot, and phase oscillation after locking; achieving fast convergence of large errors and high-precision steady-state locking of small errors, with synchronization error stabilized to the nanosecond level; (3) The PPS output side is independently phase calibrated and the internal and external links are physically isolated. The calibration amount does not participate in the synchronous closed loop iteration. This solves the industry pain points of PPS output fixed phase deviation polluting the synchronous closed loop and inconsistent internal and external observation accuracy. It takes into account both the internal clock synchronization accuracy and the external observation effect, and reduces the difficulty of engineering calibration and debugging.

[0015] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a flowchart of an embodiment of the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method of the present invention; Figure 2 This is a system architecture diagram of Embodiment 2 of the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method of the present invention; Figure 3This is a schematic diagram of the PTP message interaction timing of the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method and its first embodiment of the present invention. Figure 4 This is a schematic diagram of the control logic for phase calibration and synchronization closed-loop isolation on the PPS output side in the first embodiment of the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method and system of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used in the present invention should have the ordinary meaning understood by those skilled in the art.

[0018] Example 1 like Figure 1 As shown, this embodiment provides a hierarchical servo master-slave PPS synchronization method and system based on FPGA hardware timestamps. It should be understood that the specific parameters, models and protocols mentioned in this embodiment are only examples to help those skilled in the art understand the present invention, and are not intended to limit the present invention.

[0019] The present invention relates to an FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method and system, comprising the following steps: S1. By combining onboard crystal oscillator with phase-locked loop frequency multiplication and division, a dedicated unified system clock domain for master and slave nodes is constructed. The generated 125MHz system master clock and 200MHz physical layer auxiliary clock are directly and synchronously supplied to the hardware logic modules of S2 cross-clock domain buffer, S3 PTP message interaction, S4 time deviation calculation, S5 layered servo correction, and S6 PPS phase calibration.

[0020] In this step, the unstable recovery clock of the Ethernet physical layer is excluded from the core synchronization logic. Instead, an onboard crystal oscillator is used in conjunction with an FPGA phase-locked loop to generate a dedicated system clock domain through clock frequency multiplication. This ensures that real-time clock counting, PTP message processing, hardware timestamp generation, servo control, and second pulse output all operate within the same clock domain, isolating interference from the Ethernet physical layer recovery clock domain. This avoids timing jitter and timestamp misalignment issues caused by cross-domain interaction across multiple clock domains from the hardware level.

[0021] The system clock drives the real-time clock unit, PTP transceiver parsing, timestamp unit, PPS output unit, and servo control module, without reusing the PHY to restore the clock. After the FPGA powers on and resets, the system clock signal is continuously and constantly output, driving the operation of each hardware functional logic module in real time without interruption.

[0022] In this embodiment, the onboard reference crystal oscillator has a fixed frequency of 50MHz; the PLL phase-locked loop frequency multiplication generation system has a main clock of 125MHz; and the physical interface has a dedicated auxiliary clock of 200MHz.

[0023] S2. Asynchronous FIFO is used to realize cross-clock domain data synchronization. Candidate timestamps are hardware latched at the message transmission and reception edges and valid timestamps are generated. Two sets of timing data, valid transmission timestamp and valid reception timestamp, are output and directly used as raw sampled data to be input into the S3 master-slave PTP message interaction step.

[0024] In this step, the packet byte data and valid signals under the recovery clock domain of the Ethernet physical layer are first written into an asynchronous FIFO for cross-clock domain buffering; then the data is read out in the 125MHz system clock domain to achieve unified timing of all parsing logic.

[0025] At the rising edge of the message transmission enable signal and the rising edge of the receive data valid signal, the second count value and nanosecond count value of the real-time clock are instantaneously latched to generate candidate timestamps; further, the Ethernet frame Ethernet type field is parsed, and only when the field is a PTP exclusive identifier is the candidate timestamp marked as a valid timestamp, and the timestamp data of non-PTP frames is directly discarded.

[0026] When an Ethernet packet frame arrives at the physical interface, cross-domain buffering and timestamp latching are triggered in real time. Frame parsing is executed continuously without delay and is triggered uninterruptedly with the network packet flow.

[0027] S3. The master and slave ends interact in a closed loop through four types of Layer 2 PTP messages to collect four sets of reference timestamps (T1, T2, T3, and T4) required for the synchronization link. The four sets of timestamp samples collected are then completely transmitted to the S4 slave end deviation calculation step.

[0028] In this step, a simplified IEEE 1588 Layer 2 PTP communication mechanism is adopted, limiting the interaction to four message types: Sync, Follow_Up, Delay_Req, and Delay_Resp, to complete one round of closed-loop interaction. Specifically: S301. The master node's master timestamp unit (master TSU) latches the transmission time on the rising edge of the Sync message and generates a hardware timestamp T1. The master PTP module encapsulates T1 into a Follow_Up message and sends the Sync message and the Follow_Up message carrying T1 with the highest priority through the sending arbitration module to avoid being blocked by ARP, ICMP or UDP long packets. S302. The slave time stamp unit (slave TSU) of the slave node latches the reception time on the rising edge of the received Sync message and generates a hardware timestamp T2. After the PTP parsing module parses the Follow_Up message, the slave TSU latches the transmission time on the rising edge of the sent Delay_Req message and generates a hardware timestamp T3. The slave node sends the Delay_Req message to the master node. S303. The master timestamp unit (master TSU) of the master node latches the reception time on the rising edge of the received Delay_Req message and generates a hardware timestamp T4. The master PTP module encapsulates T4 into the Delay_Resp message and sends the Delay_Resp message carrying T4 back to the slave node through the sending arbitration module.

[0029] like Figure 3 As shown, T1 is the time when the master node sends the Sync message, T2 is the time when the slave node receives the Sync message, T3 is the time when the slave node sends the Delay_Req message, and T4 is the time when the master node receives the Delay_Req message. A complete time information exchange is completed through this interaction. A complete four-message exchange is completed with a fixed period of 1 second, and the four sets of timestamp samples (T1, T2, T3, and T4) are periodically refreshed.

[0030] S4. The slave end calculates the master-slave clock offset and the average link delay based on four sets of timestamps, and generates the servo error; the obtained average link delay, master-slave clock offset and servo control error are input to S5.

[0031] In this step, the time differences between T2-T1 and T4-T3 are first constrained by half a second to eliminate the calculation error caused by the second boundary count jump; the network transmission delay and the intrinsic deviation of the node clock are solved separately based on the symmetric Ethernet link model, and the calculation formula is as follows: ; ； ; In the formula, This represents the average transmission delay of the link. The inherent clock bias between master and slave nodes; This is the input error for layered servo control.

[0032] The entire computational data path is constructed using 64-bit signed numbers to avoid high-bit data overflow issues. At the same time, dual validity checks are performed, retaining only valid timestamp combinations of same-round interactions and eliminating distorted samples that exceed the hard anomaly threshold and path delay threshold. Finally, the negative clock deviation value is defined as the servo error and used as the standard input for hierarchical servo.

[0033] S5. Based on the servo error, the slave end uses a hierarchical servo control algorithm to adjust the real-time clock (RTC) to achieve smooth clock convergence. The phase step adjustment and frequency fine-tuning correction output by the slave end directly affect the counting correction logic of the slave end's real-time clock (RTC).

[0034] In this step, a three-level error threshold is set at the end to divide the control into four levels: coarse adjustment, medium adjustment, fine adjustment, and dead zone. When the error exceeds the first threshold, a large-step phase coarse adjustment is used to quickly reduce the clock deviation; when the error is between the first and second thresholds, a medium-step equalization adjustment is used; when the error is less than the second threshold but greater than the dead zone threshold, a small-step fine adjustment is used and the frequency correction is updated synchronously; when the error falls into the dead zone range, phase stepping is stopped and only steady-state frequency correction is maintained; at the same time, upper and lower limits are uniformly set for the phase step value, integral term, and frequency correction, and directional splitting and absolute value limiting are performed before output to suppress clock jumps and phase oscillations after locking.

[0035] The real-time clock calibration formula is: ; In the formula, To correct the clock count value before calibration, For the corrected clock count value, This is the phase step adjustment amount. This is the frequency fine-tuning correction amount.

[0036] In this embodiment, the first threshold coarse adjustment threshold is 50ns, the second threshold fine adjustment threshold is 15ns, and the dead zone threshold is 3ns; the coarse adjustment step is 5ns / step, the medium adjustment step is 2ns / step, and the fine adjustment step is 0.5ns / step; all correction values ​​are uniformly limited to the range of [-20ns, +20ns].

[0037] S6. Without altering the internal real-time clock and synchronization closed-loop logic, independent calibration compensation for fixed phase deviation is performed only on the PPS output link, and the calibration process does not enter the offset synchronization closed loop; the standard master-slave PPS second pulse signal generated after calibration is sent to S7.

[0038] like Figure 4 As shown, in this step, the system is divided into two physically isolated paths: the upper path is the real protocol closed loop that is not affected by the PPS output deviation, and the lower path is an independent output-side compensation path. The two paths are physically isolated and have no data interaction.

[0039] The real-time clock (RTC) is adjusted sequentially after offset calculation and hierarchical servo correction using the T1 / T2 / T3 / T4 timestamps as input. This closed loop strictly prohibits feedback from fixed PPS deviations to ensure that the synchronization control is not contaminated by output-side deviations. The output-side compensation path takes the rtc_ns register value inside the RTC as input and compares it in real time with the configurable phase calibration threshold through a threshold comparison module. When the rtc_ns register value is greater than or equal to the calibration threshold, the PPS output is controlled to be high; when the rtc_ns register value is less than the calibration threshold, the PPS output is controlled to be low, thereby generating a standard second pulse edge to achieve independent compensation for fixed phase deviations.

[0040] For the fixed phase deviation of PPS introduced by hardware link and pin delay, compensation and calibration are performed separately on the output side. The fixed phase deviation is not included in the offset synchronization closed-loop calculation. The real-time clock second and nanosecond count value is not modified, and the original hardware timestamp is not changed, thus achieving physical decoupling between the internal synchronization closed loop and the external PPS observation results.

[0041] In this embodiment, the PPS pulse has a fixed high-level width of 100ms; the minimum adjustment step of the phase calibration threshold is 1ns; and all calibration compensation values ​​on the output side do not participate in the servo closed-loop iterative calculation.

[0042] S7. Output PPS second pulse signals to the master and slave ends, and verify the synchronization effect by observing with an oscilloscope.

[0043] In this step, the standard PPS second pulse signals generated by the master and slave ends are output to an external oscilloscope through the FPGA pins; the phase difference of the rising edges of the two PPS signals is acquired synchronously to intuitively evaluate the time synchronization accuracy of the master and slave nodes; the observation process does not change any parameters of the synchronization closed loop and is only used for external verification of the synchronization effect and engineering calibration.

[0044] In this embodiment, the PPS signal output frequency is 1Hz; the oscilloscope sampling rate is not less than 1GSa / s; and the observation time is not less than 10 seconds, which is used to evaluate the long-term stability of synchronization.

[0045] Example 2 Based on the same inventive concept of the aforementioned method embodiment one, this application also provides an FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization system for implementing the master-slave PPS synchronization method of the aforementioned embodiment one.

[0046] like Figure 2 As shown, the system includes a master node and slave nodes, which communicate with each other via an Ethernet link.

[0047] The master node is the side that provides reference time and sends critical synchronization messages. Its internal functional modules include: The system comprises a local crystal oscillator / phase-locked loop, a master real-time clock (master RTC), a master timestamp unit (master TSU), a master PTP module, a transmit arbitration module, a master PPS output module, and a PHY interface. The local crystal oscillator / phase-locked loop provides a unified clock reference for the system. The master RTC generates time counts based on this reference. The master TSU latches hardware timestamps at the edges of message transmission and reception. The master PTP module encapsulates and transmits synchronization messages. The transmit arbitration module provides transmission priority guarantees for PTP messages. The master PPS output module generates and outputs the master-side second pulse signal. All modules work together to provide a standard time reference.

[0048] The slave node is the side that receives the reference time and completes clock calibration. Its internal functional modules include: local crystal oscillator / phase-locked loop, slave real-time clock (slave RTC), slave timestamp unit (slave TSU), slave PTP parsing module, hierarchical servo module, cross-clock domain processing module (CDC module), slave PPS output calibration module, and PHY interface. Among them, the local crystal oscillator / phase-locked loop provides the clock reference for the slave node, the slave TSU latches the hardware timestamp of the received message, the slave PTP parsing module parses the synchronization message sent by the master node, the hierarchical servo module performs hierarchical calibration of the slave RTC based on the timestamp data, the CDC module realizes cross-clock domain data synchronization, and the slave PPS output calibration module performs independent phase compensation for the second pulse signal. All modules work together to achieve synchronization between the slave node clock and the master node clock.

[0049] The master node and slave node exchange four types of PTP messages, namely Sync, Follow_Up, Delay_Req, and Delay_Resp, via an Ethernet link. Finally, the master node and slave node output the master PPS signal and slave PPS signal, respectively, which can be connected to an oscilloscope to observe and verify the synchronization effect.

[0050] Example 3 Based on the same inventive concept, this application also provides a master-slave PPS synchronization device. The device uses an FPGA programmable logic device as the core hardware carrier and is equipped with an onboard oscillator, phase-locked loop resources, an Ethernet PHY interface, a PPS signal output interface, a debugging interface, and a configuration storage medium. In the implementation using an FPGA SoC architecture, the processor system (PS side) can complete auxiliary functions such as parameter configuration, status monitoring, and data display, further improving the debuggability and versatility of the device.

[0051] The real-time clock (RTC), timestamp unit (TSU), PTP message interaction module, cross-clock domain CDC module, hierarchical servo correction module, and PPS output calibration module involved in the method of this invention can all be integrated and configured in the internal logic resources of the FPGA. This solidifies the timing synchronization method of this invention into a hardware-executable pipeline processing link, realizing a fully hardware-based, low-latency, and high-precision master-slave time synchronization function, and has good engineering feasibility and portability.

[0052] Therefore, the present invention adopts the above-mentioned FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method and system. This method achieves nanosecond-level master-slave PPS synchronization, and the internal clock index is decoupled and controllable from the external PPS observation. It is suitable for Ethernet high-precision time synchronization scenarios of FPGA measurement and control platforms and distributed data acquisition platforms.

[0053] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A hierarchical servo master-slave PPS synchronization method based on FPGA hardware timestamps, characterized in that, Includes the following steps: S1. Construct a unified system clock domain for master and slave nodes based on onboard crystal oscillator and FPGA phase-locked loop; S2. Based on the system clock domain provided by S1, the cross-clock domain data migration is completed at the receiving end. The received data from the Ethernet physical layer recovery clock domain is transferred to the system clock domain. Candidate timestamps are latched at the message transmission and reception edges. Valid timestamps are generated only for PTP protocol messages. The preprocessed valid timing data is output to S3. S3. Based on the valid timing data output by S2, the master node and the slave node complete the closed-loop timing interaction through four types of PTP messages. Relying on the hardware timestamp unit TSU, four sets of reference timestamps are collected respectively: master node sending time T1, slave node receiving time T2, slave node sending time T3, and master node receiving time T4. The PTP message is configured with the highest sending arbitration priority, and four sets of reference timestamps are output. S4. Based on the four sets of reference timestamps output by S3, the master-slave clock deviation and average link delay are calculated from the node, and the servo control error is generated. At the same time, distorted and abnormal timestamp samples are removed, and the servo control error is output. S5. Based on the servo control error output by S4, the slave node adopts a hierarchical servo control algorithm, and corrects the slave real-time clock RTC by superimposing phase stepping and frequency fine-tuning dual components, and outputs the RTC clock count value. S6. Based on the RTC clock count value output by S5, without changing the internal real-time clock and synchronous closed-loop logic, the system is divided into a physically isolated real protocol closed loop and an output-side compensation path. Only the nanosecond register value inside the real-time clock is read and compared with the configurable phase calibration threshold to generate a PPS pulse. Fixed phase deviation independent calibration compensation is completed on the PPS output link. The calibration process does not enter the synchronous closed loop and outputs the calibrated PPS second pulse signal. S7. Based on the calibrated PPS second pulse signal output by S6, output the PPS second pulse signals of the master node and the slave node. Observe the phase difference between the two PPS signals with an oscilloscope to complete the synchronization effect verification.

2. The FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to claim 1, characterized in that, S1 specifically includes: A 50MHz onboard passive crystal oscillator is used in conjunction with an FPGA phase-locked loop to generate a 125MHz system master clock and a 200MHz physical layer auxiliary clock. This ensures that the real-time clock counting unit, PTP message transmission and parsing module, hardware timestamp unit, hierarchical servo control module, and second pulse output calibration module are all constrained to operate synchronously within the 125MHz system clock domain.

3. The FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to claim 2, characterized in that, S2 specifically includes: Cross-clock domain data buffer migration is accomplished through asynchronous FIFO; candidate timestamps are generated by latching on the rising edge of the message transmission enable signal and the rising edge of the received data valid signal; the candidate timestamp is determined to be valid only when the Ethernet frame Ethernet type field is a PTP exclusive identifier, and the timestamps corresponding to other frame types are directly discarded.

4. The FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to claim 3, characterized in that, The four types of PTP messages in S3 include Sync, Follow_Up, Delay_Req, and Delay_Resp. The specific interaction process includes the following sub-steps: S301. When the master node TSU latches the Sync message, it generates T1, encapsulates T1 into a Follow_Up message, and sends the Sync message and Follow_Up message with high priority. S302, T2 is generated when the TSU latches the Sync message and receives it. After parsing the Follow_Up message, T3 is generated when the Delay_Req message is latched and sent. Then, the Delay_Req message is sent to the master node. S303: The master node TSU latches the Delay_Req message and generates T4 at the moment of receiving the message. The T4 is then encapsulated into a Delay_Resp message and sent back to the slave node. Among them, PTP messages have a higher priority than ARP, ICMP, and UDP ordinary service messages, and the cycle of a single round of complete message interaction is fixed at 1 second.

5. The FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to claim 4, characterized in that, S4 specifically includes: The time difference between T2-T1 and T4-T3 is subject to a 500ms half-second normalization constraint to eliminate the second boundary counting jump error; the average link delay and master-slave clock deviation are calculated through a 64-bit signed number arithmetic path, and the negative value of the clock deviation is used as the servo control error; distorted samples that exceed the 200ns hard anomaly threshold and the 100ns path delay anomaly threshold are removed. The formulas for calculating master-slave clock skew and average link delay are as follows: ； ； ； In the formula, This represents the average transmission delay of the link. The inherent clock bias between master and slave nodes; This is the input error for layered servo control.

6. The FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to claim 5, characterized in that, In S5, the hierarchical servo control algorithm used by the slave node is as follows: The system is divided into four control modes by setting three error thresholds: 50ns for coarse adjustment, 15ns for fine adjustment, and 3ns for dead zone. For errors greater than 50ns, a coarse adjustment step of 5ns / step is used; for errors between 15ns and 50ns, a medium adjustment step of 2ns / step is used; for errors between 3ns and 15ns, a fine adjustment step of 0.5ns / step is used; and when the error is less than 3ns, phase stepping is stopped and only frequency correction is retained. Correct the real-time clock using the formula: ； In the formula, To correct the clock count value before calibration, For the corrected clock count value, This is the phase step adjustment amount. This is the frequency fine-tuning correction amount; the limiting range for all correction amounts is [-20ns, +20ns].

7. A FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization system, applied to the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to any one of claims 1-6, characterized in that, include: The master node and the slave node exchange four types of PTP packets via an Ethernet link; The master node is the time reference side, including a local crystal oscillator / phase-locked loop, a main RTC, a main TSU, a main PTP module, a transmit arbitration module, a main PPS output module, and a PHY interface, used to generate a reference clock, latch transmit timestamps, encapsulate transmit synchronization messages, and output a reference PPS signal; The slave node is the time synchronization side, including a local crystal oscillator / phase-locked loop, slave RTC, slave TSU, slave PTP parsing module, hierarchical servo module, CDC cross-clock domain module, slave PPS output calibration module and PHY interface, used to complete cross-clock domain processing, timestamp acquisition, clock deviation correction and output side phase calibration; The arbitration sending module configures PTP messages to have the highest transmission priority, blocking ARP, ICMP, and UDP long packets from interfering with the synchronization messages. The CDC cross-clock domain module uses asynchronous FIFO to realize the data migration from the recovery clock domain to the system clock domain, eliminating cross-domain timing jitter and timestamp misalignment problems. The layered servo module has built-in four levels of control logic: coarse adjustment, medium adjustment, fine adjustment, and dead zone, which enables the slave clock to converge quickly and lock in a steady state without oscillation. The phase calibration logic of the PPS output calibration module is independently configured and physically isolated from the internal synchronization closed loop, and does not provide feedback to correct the RTC clock count value and hardware timestamp.

8. A master-slave PPS synchronization device, applied to the FPGA hardware timestamp-based hierarchical servo master-slave PPS synchronization method according to any one of claims 1-6, characterized in that, The device is based on an FPGA programmable logic device, and its peripheral components include an onboard oscillator, phase-locked loop resources, an Ethernet PHY interface, a PPS output interface, a debug interface, and a configuration storage medium. The FPGA integrates an RTC real-time clock module, a TSU timestamp module, a PTP message interaction module, a CDC cross-clock domain module, a hierarchical servo correction module, and a PPS output calibration module, thus solidifying the synchronization method into a hardware pipeline processing link. The PS processor side enables auxiliary functions such as parameter configuration, status monitoring, and data display. The measured master-slave PPS synchronization error of the device is stable at 7ns~20ns, and the remaining synchronization error of the internal clock is stable at 8ns~40ns, achieving nanosecond-level high-precision time synchronization.

9. A computer device, characterized in that, include: A processor configured to be coupled to memory, read and execute instructions and / or program code in the memory to perform the method as described in any one of claims 1-6.

10. A computer-readable medium, characterized in that, The computer-readable medium stores computer program code that, when executed on a computer, causes the computer to perform the method as described in any one of claims 1-6.

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