Time synchronization method and apparatus for distributed devices

Abstract

The application provides a time synchronization method and device for distributed equipment, the method comprising: receiving a first differential signal from a synchronization host; performing restoration processing on the first differential signal to obtain a first time service data packet and recording a first standard time stamp output by a standard time stamp counter corresponding to a first synchronization slave; performing verification processing on the first time service data packet to obtain a first verification result; when the first verification result is a verification success, extracting a first host time stamp from the first time service data packet; determining a first increment factor according to the first host time stamp and the first standard time stamp; and updating an output value of a slave time stamp counter corresponding to the first synchronization slave according to the first increment factor to obtain a synchronization time reference. Through differential link hardware time service and increment factor monotone smooth calibration, high-precision and high-deterministic time synchronization of the distributed equipment can be realized.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology, and in particular to a time synchronization method and apparatus for distributed devices. Background Technology

[0002] Currently, distributed devices need a unified time base for collaborative operation, but the local clocks of each distributed device exhibit frequency offset and drift. Existing synchronization methods based on network time protocols or software timestamps suffer from low accuracy and large jitter, and are affected by operating system scheduling and network conditions, making it difficult to meet the sub-millisecond level high deterministic synchronization requirements. In addition, while using external high-precision clock sources or dedicated clock distribution networks offers high accuracy, they are costly, bulky, and complex to deploy, and are unavailable in indoor or shielded environments. Traditional bus synchronization, on the other hand, has short transmission distances and poor scalability.

[0003] Therefore, how to achieve high-precision and highly deterministic time synchronization of distributed devices is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a time synchronization method and apparatus for distributed devices. By broadcasting time synchronization data packets through a synchronous communication link, the slave hardware verifies and extracts the host timestamp, and the local counter is calibrated with an incremental factor using monotonically smooth calibration, thereby achieving high-precision and high-determinism time synchronization for distributed devices.

[0005] In a first aspect, embodiments of this application provide a time synchronization method for distributed devices, applied to a first synchronization slave in a time synchronization system, the time synchronization system including a synchronization master, a synchronization slaves, and a synchronization communication links; a is a positive integer; the first synchronization slave is any one of the a synchronization slaves, the method comprising: Receive a first differential signal from the synchronization host; the first differential signal is the differential signal corresponding to the first timing data packet among a plurality of timing data packets sent by the synchronization host to the first synchronization slave through the first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links; The first differential signal is restored to obtain the first timing data packet, and the first standard timestamp is recorded by the standard timestamp counter corresponding to the first synchronization slave. The standard timestamp counter continuously increments with the local clock cycle and is not affected by the increment factor. The first time synchronization data packet is verified to obtain a first verification result; When the first verification result is successful, the first host timestamp is extracted from the first time synchronization data packet; the first host timestamp is obtained by the host timestamp counter corresponding to the synchronization host. A first increment factor is determined based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, or a third value; The output value of the slave timestamp counter corresponding to the first synchronization slave is updated according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

[0006] Secondly, embodiments of this application provide a time synchronization device for a distributed device, applied to a first synchronization slave in a time synchronization system. The time synchronization system includes a synchronization master, *a* synchronization slaves, and *a* synchronization communication links; *a* is a positive integer; the first synchronization slave is any one of the *a* synchronization slaves. The device includes: The receiving module is configured to receive a first differential signal from the synchronization host; the first differential signal is the differential signal corresponding to the first timing data packet among a plurality of timing data packets sent by the synchronization host to the first synchronization slave through a first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links; The restoration module is used to restore the first differential signal to obtain the first timing data packet, and record the first standard timestamp output by the standard timestamp counter corresponding to the first synchronization slave. The verification module is used to verify the first time synchronization data packet and obtain the first verification result; The extraction module is used to parse and extract the first host timestamp from the first time synchronization data packet when the first verification result is successful; the first host timestamp is obtained by the output of the host timestamp counter corresponding to the synchronization host; The determining module is configured to determine a first increment factor based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, and a third value; The update module is used to update the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

[0007] Thirdly, embodiments of this application provide an electronic device, including a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing steps in any method of the first aspect of this application.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps described in any method of the first aspect of this application.

[0009] Fifthly, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in any method of the first aspect of this application. The computer program product may be a software installation package.

[0010] As can be seen, by broadcasting a time synchronization data packet carrying the master's timestamp to each synchronization slave via the synchronization communication link, the synchronization slave performs hardware restoration and verification of the differential signal and extracts the master's timestamp. It then determines the increment factor by combining it with a standard timestamp counter that is not affected by the increment factor, and uses this increment factor to update the slave timestamp counter, thereby obtaining a synchronization time reference aligned with the synchronization master's time system. This achieves high-precision and high-determinism time synchronization of distributed devices. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a system architecture diagram of a time synchronization system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a synchronization host provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a first synchronous slave device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 5This is a flowchart illustrating a time synchronization method for distributed devices provided in an embodiment of this application. Figure 6 This is a schematic diagram of a time synchronization data packet verification process provided in an embodiment of this application; Figure 7 This is a schematic diagram of a process for determining a first increment factor provided in an embodiment of this application; Figure 8 This is a block diagram of the functional modules of a time synchronization device for distributed devices provided in an embodiment of this application. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0014] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0015] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, "multiple" refers to two or more.

[0016] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.

[0017] In this application, the term "connection" refers to various connection methods, such as direct connection or indirect connection, to achieve communication between devices. This application does not impose any limitations on this.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Currently, distributed devices need a unified time base for collaborative operation, but the local clocks of each distributed device exhibit frequency offset and drift. Existing synchronization methods based on network time protocols or software timestamps suffer from low accuracy and large jitter, and are affected by operating system scheduling and network conditions, making it difficult to meet the sub-millisecond level high deterministic synchronization requirements. In addition, while using external high-precision clock sources or dedicated clock distribution networks offers high accuracy, they are costly, bulky, and complex to deploy, and are unavailable in indoor or shielded environments. Traditional bus synchronization, on the other hand, has short transmission distances and poor scalability.

[0020] Therefore, how to achieve high-precision and highly deterministic time synchronization of distributed devices is an urgent problem to be solved.

[0021] To address the aforementioned problems, this application provides a time synchronization method and apparatus for distributed devices, applied to a first synchronization slave in a time synchronization system. The time synchronization system includes a synchronization master, *a* synchronization slaves, and *a* synchronization communication links; *a* is a positive integer; the first synchronization slave is any one of the *a* synchronization slaves. First, a first differential signal is received from the synchronization master; the first differential signal is the differential signal corresponding to the first timing data packet among multiple timing data packets sent by the synchronization master to the first synchronization slave via the first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the *a* synchronization communication links. Then, the first differential signal is restored to obtain the first timing data packet, and a first standard timestamp is output by a standard timestamp counter corresponding to the first synchronization slave; the standard timestamp counter continuously increments with the local clock cycle and is unaffected by the increment factor. Finally, the first timing data packet is verified to obtain a first... Verification result; when the first verification result is successful, the first host timestamp is extracted from the first time synchronization data packet; the first host timestamp is obtained by the output of the host timestamp counter corresponding to the synchronization host; then, a first increment factor is determined according to the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, and a third value; finally, the output value of the slave timestamp counter corresponding to the first synchronization slave is updated according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization host.

[0022] As can be seen, by broadcasting time synchronization data packets through the synchronous communication link, the slave hardware verifies and extracts the master timestamp, and the local counter is calibrated with incremental factor monotonically and smoothly, high-precision and high-deterministic time synchronization of distributed devices is achieved.

[0023] For easier understanding, please refer to Figure 1 , Figure 1This is a system architecture diagram of a time synchronization system provided in this application embodiment. The time synchronization system includes a synchronization host, *a* synchronization slaves, *a* synchronization communication links, a gateway, and a host computer. The synchronization host communicates with the host computer through the gateway, and establishes communication connections with each synchronization slave via corresponding synchronization communication links. Specifically, the synchronization host is connected to the first synchronization slave via a first synchronization communication link, the synchronization host is connected to the second synchronization slave via a second synchronization communication link, and the synchronization host is connected to the *a*th synchronization slave via the *a*th synchronization communication link; the remaining synchronization slaves are connected in the same manner. The host computer is used to issue global control commands and receive business data reported by each synchronization slave; the gateway is used to realize data forwarding and protocol conversion between the host computer and the synchronization host; the synchronization host, as the time reference source of the entire time synchronization system, can send differential signals carrying host timestamps to the corresponding synchronization slaves through each synchronization communication link according to a preset timing period (e.g., 1ms); each synchronization communication link uniquely corresponds to one synchronization slave. Each slave device receives the differential signal sent by the master device, executes the corresponding high-precision time synchronization method, iteratively maintains the local slave timestamp counter, establishes a monotonically increasing synchronization time reference aligned with the master device, and completes local signal acquisition, event triggering and other business operations based on this synchronization time reference.

[0024] As can be seen, by broadcasting a differential signal carrying the host timestamp to each synchronization slave via a dedicated synchronization communication link, each synchronization slave iteratively maintains its local timestamp counter, thereby establishing a high-precision synchronization time reference that is aligned with the synchronization host and monotonically increasing among the distributed devices (i.e., synchronization slaves), ensuring the determinism and coordination of local data acquisition and event triggering.

[0025] For easier understanding, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a synchronization host provided in an embodiment of this application. The synchronization host includes a host timestamp counter and host communication logic, which includes a framer, an encoder, a parallel-to-serial converter, and a physical layer driver.

[0026] The system comprises the following components: a host timestamp counter driven by a stable crystal oscillator, which outputs the current host timestamp of the synchronization host as the time reference source for the entire time synchronization system; a frame assembler connected to the host timestamp counter, which reads the current value of the host timestamp counter according to a preset time synchronization period and assembles the current value, along with the start control character, check byte, and end control character, into a time synchronization data packet according to a preset frame format; an encoder connected to the frame assembler, which performs line encoding on the data in the time synchronization data packet, such as 8b / 10b encoding, mapping each 8-bit data byte to a 10-bit symbol to ensure DC balance and sufficient level transitions in the serial bit stream; a parallel-to-serial converter connected to the encoder, which converts the encoded parallel symbol stream into a high-speed serial bit stream; and a physical layer driver connected to the parallel-to-serial converter, which converts the high-speed serial bit stream into a differential signal and sends it to the first synchronization slave through the first synchronization communication link.

[0027] It should be noted that the master communication logic of the synchronization host can be implemented using a Field-Programmable Gate Array (FPGA). The master timestamp counter, framer, encoder, parallel-to-serial converter, and physical layer driver are all integrated into the same FPGA logic or corresponding physical interface circuit. After the synchronization host is powered on, it can first continuously send idle control character sequences, such as K28.5, through the physical layer driver to complete link training. After the link is established, the framer triggers the generation of a timing data packet at a fixed timing period, such as 1ms. In each timing period, the framer reads the current value of the master timestamp counter, adds the start character K28.1, timestamp payload, check byte, and end character K28.7 to form the first timing data packet; the encoder performs 8b / 10b encoding on the first timing data packet; the parallel-to-serial converter converts the encoded parallel symbol stream into a serial bit stream; the physical layer driver converts the serial bit stream into a first differential signal and sends it to the first synchronization slave through the first synchronization communication link. Thus, the synchronization master can periodically broadcast a differential time signal carrying the master's timestamp to each synchronization slave, providing a time reference for the slave side to perform verification, timestamp extraction and incremental factor correction.

[0028] It is evident that by broadcasting time data packets with verification to each synchronous slave device at a fixed time synchronization period, a highly deterministic, low-jitter, and long-term stable time reference source is provided, laying the foundation for synchronous slave devices to achieve high-precision time synchronization and incremental factor correction.

[0029] For easier understanding, please refer to Figure 3 , Figure 3This is a schematic diagram of the structure of a first synchronous slave device provided in an embodiment of this application. The first synchronous slave device includes a slave timestamp counter and slave communication logic. The slave communication logic includes a physical layer receiver, a clock data recovery unit, a decoder, a timing packet detector and parser, a verification unit, smoothing correction logic, and a timestamp distribution interface.

[0030] The physical layer receiver receives a first differential signal from the synchronization host via a first synchronization communication link and converts the first differential signal into a first serial bit stream. A clock data recovery unit, connected to the physical layer receiver, recovers the sampling clock and data from the first serial bit stream, for example, by oversampling the first serial bit stream using a local multiphase clock to obtain a first sampled sample. A decoder, connected to the clock data recovery unit, performs voting filtering, edge detection, center sampling point decision, and line decoding on the first sampled sample to obtain the target data stream. A timing packet detector and parser, connected to the decoder, monitors the target data stream in real time, identifies the first control character (i.e., start character K28.1) as a frame start marker, and performs pre-defined timing packet detection and parsing. The frame format is used to extract the timestamp payload and checksum byte to obtain the first timing data packet. The checksum unit is connected to the timing packet detector and parser to perform checksum processing on the first timing data packet and obtain the first checksum result. Subsequent modules are allowed to use the first host timestamp extracted from the first timing data packet only when the first checksum result is successful. The slave timestamp counter is used to maintain the local timestamp sequence. Its output value is updated by the smoothing correction logic according to the increment factor to obtain a synchronization time reference aligned with the synchronization host's time system. The timestamp distribution interface is connected to the slave timestamp counter to provide the synchronization time reference to other functional modules inside the first synchronization slave, such as EEG acquisition control logic and stimulation waveform generator.

[0031] The smoothing correction logic includes a standard timestamp counter, which continuously increments with the local clock cycle and is unaffected by the increment factor. It is used to output a first standard timestamp when the first differential signal is received, and to output a second standard timestamp in the subsequent first clock cycle. This provides a stable, monotonic time reference for the smoothing correction logic to calculate the target dynamic timestamp and the first deviation, unaffected by the correction operation. The standard timestamp counter is independent of the slave timestamp counter. The slave timestamp counter is updated by the first increment factor to output a synchronous time reference, while the standard timestamp counter always increments by one with the local clock cycle, thereby ensuring that the calculation reference of the target dynamic timestamp does not jump or back due to the correction.

[0032] It should be noted that the first synchronous slave can be implemented by a Complex Programmable Logic Device (CPLD) or an FPGA. The physical layer receiver, clock data recovery unit, decoder, timing packet detector and parser, verification unit, slave timestamp counter, smoothing correction logic and timestamp distribution interface are all implemented by hardware logic (i.e. slave communication logic), thereby avoiding random delays caused by operating system scheduling, interrupt response and software marking.

[0033] As can be seen, by performing differential reception, clock data recovery, decoding, time packet parsing and verification, and smooth correction based on a standard timestamp counter within the first synchronization slave, random software delays are avoided, and a high-precision synchronous time reference that is aligned with the host time system, monotonically increasing, and without jumps or backoffs is established, providing a definite and real-time time reference for local acquisition, event triggering, and other services.

[0034] The following is combined with Figure 4 The electronic devices in the embodiments of this application will be described. Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 4 As shown, the electronic device includes one or more processors, a memory, a communication interface, and one or more programs. The processor is connected to the memory and the communication interface via an internal communication bus.

[0035] The processor can be used for: Receive a first differential signal from the synchronization master; the first differential signal is the differential signal corresponding to the first timing data packet among multiple timing data packets sent by the synchronization master to the first synchronization slave through the first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among a synchronization communication links; The first differential signal is restored to obtain the first timing data packet, and the first standard timestamp is recorded by the standard timestamp counter corresponding to the first synchronization slave. The standard timestamp counter continuously increments with the local clock cycle and is not affected by the increment factor. The first time synchronization data packet is verified to obtain the first verification result; When the first verification result is successful, the first host timestamp is extracted from the first time synchronization data packet; the first host timestamp is obtained from the output of the host timestamp counter corresponding to the synchronization host. The first increment factor is determined based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, or a third value; The output value of the slave timestamp counter corresponding to the first synchronization slave is updated according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

[0036] The one or more programs are stored in the aforementioned memory and configured to be executed by the aforementioned processor, and the one or more programs include instructions for performing any step in the above method embodiments.

[0037] The processor can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, cells, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. The communication unit can be a communication interface, transceiver, transceiver circuit, etc., and the storage unit can be a memory.

[0038] The memory can be volatile or non-volatile, or a combination of both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0039] It is understood that the electronic device may include more or fewer structural elements than those shown in the block diagram above, such as a power module, physical buttons, a Wi-Fi module, a speaker, a Bluetooth module, sensors, a display module, etc., without limitation. It is understood that the electronic device may be as follows: Figure 3 The first synchronous slave device.

[0040] After understanding the software and hardware architecture of this application, the following will be combined with... Figure 5 This application describes a time synchronization method for distributed devices in an embodiment. Figure 5 This is a flowchart illustrating a time synchronization method for distributed devices provided in an embodiment of this application. The method is applied to the first synchronization slave in a time synchronization system, which includes a synchronization master, *a* synchronization slaves, and *a* synchronization communication links; where *a* is a positive integer; and the first synchronization slave is any one of the *a* synchronization slaves. The method specifically includes the following steps: Step S501: Receive the first differential signal from the synchronization host.

[0041] Wherein, the first differential signal is the differential signal corresponding to the first timing data packet among the multiple timing data packets sent by the synchronization host to the first synchronization slave through the first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links.

[0042] Specifically, the first synchronization slave receives the first differential signal sent by the synchronization master from the first synchronization communication link through a physical layer receiver. The first synchronization communication link is a SerDes differential link dedicated to time synchronization, independent of the service network for transmitting service data between devices, such as Ethernet, PCIe and other upper-layer data links, thereby avoiding the impact of network protocol stack, operating system scheduling and service traffic on the determinism of synchronization signaling.

[0043] Prior to receiving the first differential signal from the synchronization host, the method further includes the following steps: S11. Receive the second differential signal continuously transmitted by the synchronization host through the first synchronization communication link; S12. The second differential signal is restored to obtain the idle control character sequence; S13. When the idle control character sequence is detected to be in a valid state, it is determined that the first synchronization communication link meets the time synchronization condition, and the step of receiving the first differential signal from the synchronization host is executed.

[0044] In a specific embodiment, before the formal broadcast of the timing data packet, the synchronization host first enters the link training phase, whereby the physical layer driver continuously transmits a second differential signal through the first synchronization communication link. This second differential signal is represented at the physical layer as a high-speed serial differential signal, carrying a sequence of idle control characters, such as continuously transmitted K28.5 control characters. The synchronization host can repeatedly transmit this idle control character sequence according to a fixed code pattern, enabling the first synchronization slave to complete bit-level and word-level alignment. The first synchronization slave can receive the second differential signal through a physical layer receiver and perform reconstruction processing on the second differential signal to obtain the idle control character sequence.

[0045] Then, it is determined whether the idle control character sequence is in a valid state. The determination criteria may include at least one of the following: a preset number of idle control characters are detected consecutively, such as 8, 16, or 32 consecutive K28.5 characters; the interval between adjacent idle control characters meets a preset period; no frame error, decoding error, or check error occurs; the word alignment is stable; and the oversampled phase remains locked for a preset time. When the determination criteria are met, the idle control character sequence is determined to be in a valid state, thereby determining that the first synchronous communication link has completed link training, meets the time synchronization conditions, and can receive the first differential signal from the synchronization host to trigger the timestamp correction process. When the determination criteria are not met, the idle control character sequence is determined to be in a invalid state, for example, due to continuous detection failure, decoding error rate exceeding a threshold, or oversampled phase loss of lock. The first synchronous slave can maintain or return to the training state, continue to receive and parse the second differential signal, and not trigger the timing packet reception and timestamp correction process.

[0046] As can be seen, by receiving and restoring the idle control character sequence and detecting its valid status to confirm that the first synchronous communication link meets the time synchronization conditions, the first differential signal is received only after the link completes bit and word alignment, thus avoiding missynchronization and improving the reliability and determinism of time synchronization.

[0047] Step S502: Perform restoration processing on the first differential signal to obtain the first timing data packet, and record the first standard timestamp output by the standard timestamp counter corresponding to the first synchronization slave.

[0048] The standard timestamp counter continuously increments with the local clock cycle and is unaffected by the increment factor. Upon detecting the first control character or completing the reception of the first timing data packet, the current output value of the standard timestamp counter is latched as the first standard timestamp, providing a time reference for subsequent verification, host timestamp extraction, and increment factor determination. Since the first synchronous communication link corresponds to the first synchronous slave, multiple synchronous slaves can receive the timing data packets synchronously broadcast by the synchronous host in parallel through their respective links, thereby ensuring the consistency and determinism of the reception reference for each slave.

[0049] The specific steps for restoring the first differential signal to obtain the first timing data packet include: S21. Determine the first serial bit stream corresponding to the first differential signal; S22. Oversample the first serial bit stream to obtain the first sampled sample; S23. Perform voting filtering on the first sample to obtain the second sample; S24. Perform edge detection on the second sample to obtain the center sampling point; S25. Based on the central sampling point, perform a sampling decision on the second sample to obtain data bits; S26. Perform line decoding on the data bits to obtain the target data stream; S27. When the first control character in the target data stream is identified, the timestamp payload and check byte are extracted according to the preset frame format to obtain the first timing data packet; the first control character is the control character in the first timing data packet used to identify the start of the frame.

[0050] In a specific embodiment, firstly, the physical layer receiver of the first synchronous slave receives a first differential signal from the first synchronous communication link. The physical layer receiver can convert the first differential signal into an internal single-ended serial bit stream, i.e., the first serial bit stream. This first serial bit stream is a high-speed serial data stream encoded with 8b / 10b. The physical layer receiver may also be equipped with an equalization circuit or pre-emphasis compensation to counteract high-frequency attenuation in the cable.

[0051] Then, the clock data recovery unit uses a local phase-locked loop (PLL) to generate a multi-phase clock. For example, the local PLL generates a four-phase 125MHz clock based on a 50MHz reference clock, with phases of 0°, 45°, 90°, and 135°, effectively creating a 500MHz sampling capability. This is used to oversample the first serial bit stream by 8 times, meaning 8 sampling points are collected per data bit period, resulting in the first sample. This first sample is a bit sequence arranged in chronological order; for example, 0 and 1 represent the level value of each sampling point. To suppress glitches caused by cable transmission, electromagnetic interference, and sampling metastability, the first sample can be digitally voted to obtain the second sample. For example, a majority vote is performed on three or five consecutive sampling points: if the majority is 1, the output is 1; if the majority is 0, the output is 0.

[0052] Next, the level changes of adjacent sampling points in the second sample can be monitored in real time. When a transition from 0 to 1 or from 1 to 0 is detected, the transition position is recorded as the bit boundary. Based on the bit boundary and the known oversampling factor, the center position of each data bit period is calculated. For example, under 8x oversampling, if the edge is located between the 2nd and 3rd sampling points, the bit center can be determined to be near the 6th sampling point. The center sampling point is the most stable sampling position within each data bit period. Edge detection can also be combined with a digital phase-locked loop or phase interpolator to dynamically adjust the sampling phase, ensuring that the center sampling point always tracks the optimal sampling time of the input bit stream.

[0053] Then, at the center sampling point of each data bit cycle, a sampling decision is made on the second sample. If the level of the center sampling point is greater than or equal to a preset decision threshold, it is judged as logic 1; if it is less than the preset decision threshold, it is judged as logic 0. Alternatively, multiple sampling points near the center sampling point can be used for majority voting to improve the reliability of the decision. The data bits are then line-decoded (i.e., 8b / 10b decoding) to obtain the target data stream. The unique 10-bit pattern of control characters in 8b / 10b encoding, such as the codeword of K28.5, can be used to determine the 10-bit symbol boundaries. After word alignment is established, the data bits are divided into symbols in groups of 10 bits. Then, a preset 8b / 10b decoding table is consulted to decode each 10-bit symbol into an 8-bit data byte or control character.

[0054] Finally, the decoded target data stream can be continuously monitored. If the first control character, such as K28.1, is detected, it indicates the start of the first timing data packet frame. The first control character is the control character in the first timing data packet used to identify the start of the frame and can be used to define the frame boundary. Subsequent bytes are then extracted sequentially according to a preset frame format, which can be: start character K28.1, timestamp bytes 1 to 6, checksum byte, and end character K28.7. After extraction, the timestamp payload and checksum byte can be combined to form the first timing data packet, and a valid packet indication signal is output. If the end character K28.7 is not detected within a preset time, or an invalid control character is captured, the current data can be discarded directly.

[0055] As can be seen, by oversampling, voting filtering, edge detection and center sampling point decision to restore the differential signal step by step, and by using control characters to identify the frame start to accurately extract the timestamp payload and check bytes, the first timing data packet can be obtained with high reliability and low jitter at the hardware level, providing a deterministic data foundation for subsequent verification and high-precision time synchronization.

[0056] Step S503: Perform verification processing on the first time synchronization data packet to obtain the first verification result.

[0057] For easier understanding, please refer to Figure 6 , Figure 6 This is a flowchart illustrating a time synchronization data packet verification process provided in an embodiment of this application. The specific steps for verifying the first time synchronization data packet to obtain a first verification result include: S31. The timestamp payload in the first time synchronization data packet is summed to obtain a local check value; S32. Compare the local verification value with the verification byte in the first time synchronization data packet; S33. When the local verification value is consistent with the verification byte, the first verification result is determined to be successful. S34. When the local check value is inconsistent with the check byte, the first check result is determined to be a check failure.

[0058] In a specific embodiment, after the timing packet detector and parser completes the capture of the first timing data packet, it sends the timestamp payload and check bytes to the verification unit. The verification unit first extracts all bytes of the timestamp payload from the first timing data packet, for example, six timestamp bytes, denoted as B0, B1, B2, B3, B4, and B5. Then, it performs an accumulation summation operation on each byte according to a preset order. This preset order can be consistent with the order used when framing the synchronous host, for example, from low byte to high byte, or from high byte to low byte. The accumulation summation operation can use modulo 256, meaning that only the lower 8 bits are retained after each addition, and the carry is discarded. For example, the local checksum SUM can be calculated as follows: SUM = (B0 + B1 + B2 + B3 + B4 + B5) mod 256.

[0059] The verification unit can input the local verification value and the extracted verification byte into a hardware comparator (such as an 8-bit equality comparator). If the local verification value and the verification byte are identical bit by bit, the hardware comparator outputs a high level or a verification success flag, determining that the first verification result is successful. If they are not identical, the hardware comparator outputs a low level or a verification failure flag, determining that the first verification result is a verification failure. It should be noted that when the first verification result is a verification failure, the first timing data packet can be directly discarded, and the slave timestamp counter of the synchronization slave will continue to operate under the current update strategy, waiting for the next timing data packet to arrive.

[0060] It is evident that by verifying the time synchronization data packets and allowing the use of the host timestamp only when the verification is successful, transmission errors can be effectively filtered out, timestamp reliability can be guaranteed, and the reliability and robustness of time synchronization can be improved.

[0061] Step S504: When the first verification result is successful, the first host timestamp is extracted from the first time synchronization data packet.

[0062] The first host timestamp is obtained from the host timestamp counter corresponding to the synchronization host. Specifically, the timestamp payload in the first timing data packet can be obtained first. This timestamp payload can be 6 bytes, such as B0 to B5, corresponding to the lower 8 bits to the higher 8 bits, or the higher 8 bits to the lower 8 bits, of the host timestamp, respectively. Then, according to the byte order consistent with that used when framing the synchronization host, multiple timestamp bytes are concatenated into a parallel timestamp value, such as a 48-bit first host timestamp.

[0063] Step S505: Determine the first increment factor based on the first host timestamp and the first standard timestamp.

[0064] The first incremental factor includes any one of the following: a first value, a second value, and a third value. It should be noted that the first, second, and third values ​​are all non-negative values, and satisfy the condition that the first value is greater than the second value, and the second value is greater than the third value. For example, the first value is 2, the second value is 1, and the third value is 0. The first value corresponds to the accelerated catching-up state, the second value corresponds to the synchronized maintenance state, and the third value corresponds to the paused waiting state.

[0065] The specific steps of determining the first increment factor based on the first host timestamp and the first standard timestamp include: S41. Obtain the second standard timestamp output by the standard timestamp counter in a preset first clock cycle; S42. Obtain the first slave timestamp output by the slave timestamp counter in the first clock cycle; S43. Determine the target dynamic timestamp based on the first host timestamp, the first standard timestamp, and the second standard timestamp; S44. Calculate the deviation between the target dynamic timestamp and the first slave timestamp to obtain the first deviation; S45. Determine the first increment factor based on the first deviation.

[0066] In a specific embodiment, the standard timestamp counter is located inside the first synchronous slave device, driven by the local clock, and continuously increments with the local clock cycle, unaffected by any increment factor. The first clock cycle is the local clock cycle in which the smoothing correction logic performs the current deviation calculation; it can be a fixed delay period after successful verification, such as the Nth clock cycle after the successful verification pulse. During this first clock cycle, the smoothing correction logic outputs a latch enable signal to the standard timestamp counter, which latches the current output value into the standard timestamp register, obtaining the second standard timestamp. The difference between the second and first standard timestamps represents the number of local standard clock cycles elapsed from receiving the first timing data packet to the current calculation time. Because the standard timestamp counter is not controlled by an increment factor, this difference accurately and monotonically reflects the passage of time, without any jumps or rollbacks caused by the correction operation.

[0067] The slave timestamp counter, located within the first synchronous slave, is also driven by the local clock, but its output value is updated according to an increment factor to maintain a synchronous time base aligned with the master time system. During the first clock cycle, the smoothing correction logic outputs a latch enable signal to the slave timestamp counter, which then latches its current output value into the slave timestamp register, obtaining the first slave timestamp. The first slave timestamp and the second standard timestamp can be latched on the same clock edge, ensuring they correspond to the same local time. If the slave timestamp counter is updating, the latching operation can be performed before or after the update according to a fixed rule; for example, latching before updating on the rising edge of the clock to avoid race conditions and uncertainties.

[0068] The target dynamic timestamp can be calculated based on the first master timestamp, the first standard timestamp, and the second standard timestamp. For example, the target dynamic timestamp = first master timestamp + (second standard timestamp - first standard timestamp). Then, the deviation between the target dynamic timestamp and the first slave timestamp is calculated to obtain the first deviation. A positive first deviation indicates that the slave timestamp counter output value lags behind the target dynamic timestamp, meaning the first synchronous slave is slower than the synchronous master; a negative first deviation indicates that the slave timestamp counter output value leads the target dynamic timestamp, meaning the first synchronous slave is faster than the synchronous master; a first deviation of zero or close to zero indicates that the first synchronous slave and the synchronous master are basically synchronized. Finally, the corresponding first increment factor is determined based on the first deviation.

[0069] As can be seen, by providing a stable and monotonic time reference through a standard timestamp counter, the deviation between the target dynamic timestamp and the slave timestamp can be accurately calculated, thereby providing an accurate and deterministic basis for determining the increment factor and achieving smooth and high-precision alignment between slave time and master time.

[0070] For easier understanding, please refer to Figure 7 , Figure 7 This is a flowchart illustrating the determination of a first increment factor according to an embodiment of this application. The specific steps of determining the first increment factor based on the first deviation include: S51. When the first deviation is greater than a preset first deviation threshold, the first value is determined as the first increment factor; the first deviation threshold is a positive value. S52. When the absolute value of the first deviation is less than or equal to the first deviation threshold, the second value is determined as the first increment factor. S53. When the first deviation is less than the second deviation threshold, the third value is determined as the first increment factor; the second deviation threshold is the opposite of the first deviation threshold.

[0071] In a specific embodiment, the first deviation threshold can be pre-configured as a positive value (e.g., D). Its value can be set according to the local clock frequency, timing period, and synchronization accuracy requirements. For example, when the local clock is 125MHz, the first deviation threshold can be 16 local clock cycles, i.e., D=128ns. The second deviation threshold is the opposite of the first deviation threshold, i.e., -D.

[0072] When the first deviation exceeds the first deviation threshold, it indicates that the output value of the slave timestamp counter lags behind the target dynamic timestamp, meaning the slave's local time is significantly slower than the master's time, requiring acceleration to catch up. The first value (e.g., 2) can be determined as the first increment factor, causing the slave timestamp counter to increment by 2 in each local clock cycle, i.e., increasing at a rate greater than the normal step size (e.g., 1), thereby gradually reducing the deviation from the target dynamic timestamp.

[0073] When the absolute value of the first deviation is less than or equal to the first deviation threshold, it indicates that the deviation between the slave timestamp counter output value and the target dynamic timestamp is within the allowable range. That is, the slave local time is basically synchronized with the master time, and there is no need to accelerate to catch up or pause and wait. The second value (such as 1) can be determined as the first increment factor, so that the slave timestamp counter increments by 1 in each local clock cycle, that is, it increments in normal steps, thereby maintaining the current synchronization state.

[0074] When the first deviation is less than the second deviation threshold, it indicates that the slave timestamp counter output value is ahead of the target dynamic timestamp, meaning the slave's local time is significantly faster than the master's time, requiring a pause and waiting. The second deviation threshold is the opposite of the first deviation threshold. A third value (such as 0) can be determined as the first increment factor, causing the slave timestamp counter to increment by 0 in each local clock cycle, thus pausing the increment and waiting for the target dynamic timestamp to gradually catch up.

[0075] As can be seen, by comparing the first deviation with the deviation threshold, the system smoothly switches between three incremental factors: accelerated catching up, synchronization maintenance, and pause waiting. This ensures that the slave timestamp is strictly monotonous and does not roll back, while also achieving high-precision and stable alignment with the master time.

[0076] Step S506: Update the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time reference.

[0077] The synchronization time base is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization host.

[0078] The step of updating the output value of the slave timestamp counter corresponding to the first synchronization slave based on the first increment factor to obtain the synchronization time base includes the following specific steps: S61. In each clock cycle of the slave timestamp counter, the output value of the slave timestamp counter is added to the first increment factor to obtain an updated value; S62. Update the first increment factor according to the update value to obtain the second increment factor, and use the update value as the output value of the slave timestamp counter in the next clock cycle; S63. When the second increment factor is not equal to the second value, continue to update the second increment factor; S64. When the second increment factor is equal to the second value, it is determined that the update has reached the synchronization maintenance state, and the output value of the slave timestamp counter is determined as the synchronization time reference.

[0079] In a specific embodiment, the slave timestamp counter is driven by a local clock, such as a 125MHz clock. An increment factor register can be set in the smoothing correction logic to store the currently effective first increment factor δ. At each rising edge of the local clock, the current output value T_local of the slave timestamp counter is added to the first increment factor δ in the increment factor register to obtain the updated value T_update, i.e., T_update = T_local + δ. Then, the updated value T_update is written back to the slave timestamp counter as the output value for the next clock cycle. Simultaneously, the smoothing correction logic can recalculate the deviation ΔT_new based on the updated value T_update and update the increment factor accordingly to obtain the second increment factor. For example, if ΔT_new is greater than the first deviation threshold D, the second increment factor remains the first value, i.e., 2; if |ΔT_new|≤D, the second increment factor is the second value, i.e., 1; if ΔT_new is less than the second deviation threshold -D, the second increment factor is the third value, i.e., 0.

[0080] If the second increment factor is not equal to the second value, it indicates that the slave timestamp counter is still in an accelerated catch-up state or a paused waiting state, and has not yet entered the synchronization holding area. For example, if the second increment factor is the first value, it means that the slave's local time is still significantly slower than the target dynamic timestamp, and it needs to continue accelerating to catch up; if the second increment factor is the third value, it means that the slave's local time is still significantly faster than the target dynamic timestamp, and it needs to continue pausing and waiting. In this case, the increment factor update operation continues to be performed in each local clock cycle until the newly calculated increment factor equals the second value. It should be noted that the entire process is controlled by the hardware state machine of the first synchronization slave, with a fixed cyclic delay, and does not depend on software.

[0081] If the second increment factor equals the second value, it indicates that the deviation between the slave timestamp counter's output value and the target dynamic timestamp is within the synchronization maintenance range of [-D, +D], meaning the slave's local time is basically synchronized with the master time. The slave timestamp counter can continue to increment normally according to the second value, and its output value can be used as a synchronization time reference. The timestamp distribution interface can provide this synchronization time reference to other functional modules within the first synchronization slave, such as EEG acquisition control logic and stimulation waveform generator. If the deviation subsequently exceeds the synchronization maintenance range again due to crystal oscillator drift or link jitter, the smoothing correction logic can switch the increment factor back to the first or third value, re-enter the acceleration catch-up or pause waiting state, and re-determine synchronization maintenance after the deviation returns to the synchronization maintenance range.

[0082] As can be seen, by accumulating the increment factor and dynamically updating it in each clock cycle of the slave timestamp counter, the counting output is made to increase strictly monotonically, and when the increment factor equals the second value, it is determined to enter the synchronization hold state, thereby outputting a synchronization time reference that is stably aligned with the master time system and has no backslide.

[0083] In one possible embodiment, before the next timing data packet (such as the second timing data packet) is successfully verified, the smoothing correction logic can keep the first increment factor unchanged, and the slave timestamp counter is continuously updated by accumulating the fixed first increment factor every local clock cycle. Then, when the next timing data packet arrives and the deviation is recalculated, a new increment factor is determined based on the new deviation. The slave timestamp counter then continues to update cycle by cycle according to the new increment factor until the next timing data packet (such as the third timing data packet) is successfully verified, at which point it is recalculated. If subsequent timing data packets fail to be verified, the timing data packet is discarded, the master timestamp is not extracted, the deviation is not recalculated, the increment factor register continues to hold the original increment factor (such as the first increment factor), and the slave timestamp counter continues to update according to the original increment factor. If the number of consecutive verification failures reaches a preset maximum, a link anomaly alarm can be output to notify the host computer or synchronization host to re-initiate link training.

[0084] It is evident that by keeping the incremental factor unchanged and updating it periodically within the timing period, and only recalculating the deviation after the timing packet verification is successful, the continuity and determinism of slave time synchronization are guaranteed.

[0085] In one possible embodiment, during system operation, the master synchronization unit continuously and periodically broadcasts timing packets, and each slave synchronization unit continuously receives and fine-tunes its local time to counteract minor drifts caused by crystal oscillator temperature drift and frequency offset. In the first slave synchronization unit (such as an EEG acquisition slave), when the ADC conversion is completed, the hardware latches the synchronized local timestamp in the next clock cycle and writes it into the data packet header, realizing a software-independent deterministic acquisition time marker. In the second slave synchronization unit (such as a transcranial electrical stimulation slave), after receiving an instruction specifying a future execution time, the hardware compares the local timestamp with the execution time. Once the local timestamp reaches or exceeds the execution time, the action output is triggered, so that the accuracy of the execution time depends only on the accuracy of the local synchronization clock, thereby ensuring high-precision coordination of acquisition, processing, and stimulation events on a unified time axis in closed-loop neuromodulation.

[0086] In one possible embodiment, after the system is powered on, the power supply of the host, EEG amplifier and electrostimulator is connected. The host FPGA starts to continuously send K28.5 idle sequence. After a preset time, the CPLD logic of the two slave devices completes bit alignment and word alignment by detecting continuous K28.5 and lights up the link synchronization indicator. Then the host computer sends a "start timing" command to the host FPGA through the gateway. The host FPGA inserts timing packets at 1ms intervals and broadcasts them to each slave device.

[0087] The slave CPLD quickly calculates and adjusts the deviation after receiving the first few timing packets. Typically, within tens of milliseconds, the deviation between the local timestamps of the two slave devices and the master timestamp stabilizes within a threshold range of ±128ns. In the labeling function verification, after the EEG amplifier starts analog signal acquisition, each data packet header carries a timestamp accurate to a 125MHz clock cycle, or 8ns, and the timestamp difference between consecutive packets equals the sampling interval, proving that the hardware labeling function is normal.

[0088] In the verification of the collaborative triggering function, the host computer sends a command to the electrostimulator, requiring it to output a rising edge pulse at a precise time of 100.000ms in the future. At the same time, the EEG amplifier also outputs a rising edge pulse from the digital I / O port when the internal timestamp reaches 200.000ms. The two I / O ports are monitored in dual channels using a high-speed oscilloscope with a sampling rate of over 1GHz. The experiment is repeated 1000 times and the time difference between the two rising edges is statistically analyzed. The expected average value is very close to the set 100ms, and the jitter standard deviation is much less than 1ms. Similar experiments have measured jitter of less than 0.6ms, thus directly proving that the system has high-precision time synchronization capability.

[0089] In one possible implementation, once the time synchronization system is verified to be error-free, it can be integrated into the complete closed-loop process: the EEG amplifier can use a synchronization timestamp to mark the acquisition time T_acq for each frame of data. The host computer can calculate the stimulation execution time T_stim corresponding to a future predicted EEG phase based on T_acq and a fixed processing delay, and send the {T_stim, stimulation parameters} instruction to the electrostimulator. The CPLD of the electrostimulator precisely adjusts the output current when the local synchronization timestamp reaches T_stim. Therefore, through this mechanism, even if there are random delays in host computer processing and data transmission, as long as the instruction arrives at the electrostimulator before T_stim, the final stimulation output time is determined, thus achieving truly high-precision phase-locked loop.

[0090] The above primarily describes the solutions of the embodiments of this application from the perspective of the method execution process. It is understood that, in order to achieve the above functions, the electronic device includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments provided herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0091] This application embodiment can divide the electronic device into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0092] When dividing each function into modules according to its corresponding function. Figure 8 This is a functional block diagram of a time synchronization device for a distributed device provided in an embodiment of this application. The time synchronization device 800 for a distributed device is applied to a first synchronization slave in a time synchronization system. The time synchronization system includes a synchronization master, a synchronization slaves, and a synchronization communication links; a is a positive integer; the first synchronization slave is any one of the a synchronization slaves. The time synchronization device 800 for a distributed device includes: The receiving module 810 is configured to receive a first differential signal from the synchronization host; the first differential signal is the differential signal corresponding to the first timing data packet among a plurality of timing data packets sent by the synchronization host to the first synchronization slave through a first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links. The restoration module 820 is used to restore the first differential signal to obtain the first timing data packet and record the first standard timestamp output by the standard timestamp counter corresponding to the first synchronization slave. The verification module 830 is used to verify the first time synchronization data packet and obtain the first verification result; The extraction module 840 is used to extract the first host timestamp from the first time synchronization data packet when the first verification result is successful; the first host timestamp is obtained by the output of the host timestamp counter corresponding to the synchronization host. The determining module 850 is configured to determine a first increment factor based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, and a third value. The update module 860 is used to update the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

[0093] Optionally, in the process of restoring the first differential signal to obtain the first timing data packet, the restoration module 820 is specifically used for: Determine the first serial bit stream corresponding to the first differential signal; The first serial bit stream is oversampled to obtain the first sampled sample; The first sampled sample is subjected to voting filtering to obtain the second sampled sample; Edge detection is performed on the second sample to obtain the center sampling point; Based on the central sampling point, the second sampled sample is sampled and decided to obtain data bits; The data bits are decoded to obtain the target data stream; When the first control character in the target data stream is detected, the timestamp payload and check byte are extracted according to the preset frame format to obtain the first timing data packet; the first control character is the control character in the first timing data packet used to identify the start of the frame.

[0094] Optionally, in the process of verifying the first timing data packet to obtain a first verification result, the verification module 830 is specifically used for: The local check value is obtained by summing and calculating each byte of the timestamp payload in the first time synchronization data packet; The local checksum is compared with the checksum byte in the first timing data packet; When the local check value matches the check byte, the first check result is determined to be a successful check. When the local check value is inconsistent with the check byte, the first check result is determined to be a check failure.

[0095] Optionally, in determining the first increment factor based on the first host timestamp and the first standard timestamp, the determining module 850 is specifically configured to: Obtain the second standard timestamp output by the standard timestamp counter in a preset first clock cycle; Obtain the first slave timestamp output by the slave timestamp counter in the first clock cycle; The target dynamic timestamp is determined based on the first host timestamp, the first standard timestamp, and the second standard timestamp; Calculate the deviation between the target dynamic timestamp and the first slave timestamp to obtain the first deviation; The first increment factor is determined based on the first deviation.

[0096] Optionally, in determining the first increment factor based on the first deviation, the determining module 850 is further specifically configured to: When the first deviation is greater than a preset first deviation threshold, the first value is determined as the first increment factor; the first deviation threshold is a positive value. When the absolute value of the first deviation is less than or equal to the first deviation threshold, the second value is determined as the first increment factor; When the first deviation is less than the second deviation threshold, the third value is determined as the first increment factor; the second deviation threshold is the opposite of the first deviation threshold.

[0097] Optionally, in updating the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time base, the update module 860 is specifically used for: In each clock cycle of the slave timestamp counter, the output value of the slave timestamp counter is added to the first increment factor to obtain the updated value; The first increment factor is updated according to the updated value to obtain the second increment factor, and the updated value is used as the output value of the slave timestamp counter in the next clock cycle. When the second increment factor is not equal to the second value, continue to update the second increment factor; When the second increment factor equals the second value, it is determined that the update has reached the synchronization maintenance state, and the output value of the slave timestamp counter is determined as the synchronization time reference.

[0098] Optionally, before receiving the first differential signal from the synchronization host, the receiving module 810 is specifically configured to: Receive the second differential signal continuously transmitted by the synchronization host through the first synchronization communication link; The second differential signal is restored to obtain the idle control character sequence; When the idle control character sequence is detected to be in a valid state, it is determined that the first synchronization communication link meets the time synchronization condition, and the step of receiving the first differential signal from the synchronization host is executed.

[0099] It should be noted that the specific implementation of each operation can be described in the corresponding description of the method embodiments shown above. The time synchronization device 800 for distributed devices can be used to execute the method embodiments of this application, and will not be described again here.

[0100] This application also provides a computer-readable storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments, wherein the computer includes an electronic device.

[0101] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer may include an electronic device.

[0102] It should be noted that, for the sake of simplicity, the above embodiments are all described as a series of actions. Those skilled in the art should understand that this application is not limited to the described order of actions, as some steps in the embodiments of this application can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions, steps, modules, or units involved are not necessarily essential to the embodiments of this application.

[0103] In the above embodiments, the descriptions of each embodiment in this application have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0104] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0105] The steps of the methods or algorithms described in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in RAM, flash memory, ROM, EPROM, electrically erasable programmable read-only memory (EEPROM), registers, hard disk, portable hard disk, read-only optical disk (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Furthermore, the ASIC can reside in a terminal device or management device. Alternatively, the processor and storage medium can exist as discrete components in the terminal device or management device.

[0106] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0107] The modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both. For example, for devices and products applied to or integrated into a chip, all modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits. For devices and products applied to or integrated into a chip module, all modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The implementation is achieved through a software program that runs on the processor integrated within the chip module. The remaining modules / units (if any) can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into terminal equipment, each of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal equipment. Alternatively, at least some modules / units can be implemented through a software program that runs on the processor integrated within the terminal equipment, while the remaining modules / units (if any) can be implemented using hardware methods such as circuits.

[0108] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above descriptions are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A time synchronization method for distributed devices, characterized in that, A first synchronization slave device applied to a time synchronization system, wherein the time synchronization system includes a synchronization master, a synchronization slave devices, and a synchronization communication links; where a is a positive integer. The first synchronous slave is any one of the a synchronous slaves, and the method includes: Receive a first differential signal from the synchronization host; the first differential signal is the differential signal corresponding to the first timing data packet among a plurality of timing data packets sent by the synchronization host to the first synchronization slave through the first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links; The first differential signal is restored to obtain the first timing data packet, and the first standard timestamp is recorded by the standard timestamp counter corresponding to the first synchronization slave. The standard timestamp counter continuously increments with the local clock cycle and is not affected by the increment factor. The first time synchronization data packet is verified to obtain a first verification result; When the first verification result is successful, the first host timestamp is extracted from the first time synchronization data packet; the first host timestamp is obtained by the host timestamp counter corresponding to the synchronization host. A first increment factor is determined based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, or a third value; The output value of the slave timestamp counter corresponding to the first synchronization slave is updated according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

2. The method as described in claim 1, characterized in that, The process of restoring the first differential signal to obtain the first timing data packet includes: Determine the first serial bit stream corresponding to the first differential signal; The first serial bit stream is oversampled to obtain the first sampled sample; The first sampled sample is subjected to voting filtering to obtain the second sampled sample; Edge detection is performed on the second sample to obtain the center sampling point; Based on the central sampling point, the second sampled sample is sampled and decided to obtain data bits; The data bits are decoded to obtain the target data stream; When the first control character in the target data stream is detected, the timestamp payload and check byte are extracted according to the preset frame format to obtain the first timing data packet; the first control character is the control character in the first timing data packet used to identify the start of the frame.

3. The method as described in claim 2, characterized in that, The step of verifying the first time synchronization data packet to obtain a first verification result includes: The local check value is obtained by summing and calculating each byte of the timestamp payload in the first time synchronization data packet; The local checksum is compared with the checksum byte in the first timing data packet; When the local check value matches the check byte, the first check result is determined to be a successful check. When the local check value is inconsistent with the check byte, the first check result is determined to be a check failure.

4. The method as described in claim 1, characterized in that, The step of determining the first increment factor based on the first host timestamp and the first standard timestamp includes: Obtain the second standard timestamp output by the standard timestamp counter in a preset first clock cycle; Obtain the first slave timestamp output by the slave timestamp counter in the first clock cycle; The target dynamic timestamp is determined based on the first host timestamp, the first standard timestamp, and the second standard timestamp; Calculate the deviation between the target dynamic timestamp and the first slave timestamp to obtain the first deviation; The first increment factor is determined based on the first deviation.

5. The method as described in claim 4, characterized in that, Determining the first increment factor based on the first deviation includes: When the first deviation is greater than a preset first deviation threshold, the first value is determined as the first increment factor; the first deviation threshold is a positive value. When the absolute value of the first deviation is less than or equal to the first deviation threshold, the second value is determined as the first increment factor; When the first deviation is less than the second deviation threshold, the third value is determined as the first increment factor; the second deviation threshold is the opposite of the first deviation threshold.

6. The method as described in claim 1, characterized in that, The step of updating the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time base includes: In each clock cycle of the slave timestamp counter, the output value of the slave timestamp counter is added to the first increment factor to obtain the updated value; The first increment factor is updated according to the updated value to obtain the second increment factor, and the updated value is used as the output value of the slave timestamp counter in the next clock cycle; When the second increment factor is not equal to the second value, continue to update the second increment factor; When the second increment factor equals the second value, it is determined that the update has reached the synchronization maintenance state, and the output value of the slave timestamp counter is determined as the synchronization time reference.

7. The method according to any one of claims 1-6, characterized in that, Before receiving the first differential signal from the synchronization host, the method further includes: Receive the second differential signal continuously transmitted by the synchronization host through the first synchronization communication link; The second differential signal is restored to obtain the idle control character sequence; When the idle control character sequence is detected to be in a valid state, it is determined that the first synchronization communication link meets the time synchronization condition, and the step of receiving the first differential signal from the synchronization host is executed.

8. A time synchronization device for distributed devices, characterized in that, A first synchronization slave device applied to a time synchronization system, wherein the time synchronization system includes a synchronization master, a synchronization slave devices, and a synchronization communication links; where a is a positive integer. The first synchronous slave is any one of the a synchronous slaves, and the device includes: The receiving module is configured to receive a first differential signal from the synchronization host; the first differential signal is the differential signal corresponding to the first timing data packet among a plurality of timing data packets sent by the synchronization host to the first synchronization slave through a first synchronization communication link; the first synchronization communication link is the synchronization communication link corresponding to the first synchronization slave among the a synchronization communication links; The restoration module is used to restore the first differential signal to obtain the first timing data packet, and record the first standard timestamp output by the standard timestamp counter corresponding to the first synchronization slave. The verification module is used to verify the first time synchronization data packet and obtain the first verification result; The extraction module is used to parse and extract the first host timestamp from the first time synchronization data packet when the first verification result is successful; the first host timestamp is obtained by the output of the host timestamp counter corresponding to the synchronization host; The determining module is configured to determine a first increment factor based on the first host timestamp and the first standard timestamp; the first increment factor includes any one of the following: a first value, a second value, and a third value; The update module is used to update the output value of the slave timestamp counter corresponding to the first synchronization slave according to the first increment factor to obtain the synchronization time reference; the synchronization time reference is a local timestamp sequence maintained by the slave timestamp counter and aligned with the time system of the synchronization master.

9. An electronic device, characterized in that, include: Processor, memory, communication interface, and one or more programs; The one or more programs are stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 1-7.

Images