A dual-band jamming signal generation method

Abstract

The application discloses a kind of dual-band interference signal generation methods, S1, receives interference task, calculates shared base carrier frequency, sets baseband sampling rate;S2, generates shared base carrier, and is inputted DDS module by power divider two-way, adjusts offset to generate dual-band carrier;S3, generates dual-band baseband signal according to interference mode, adjusts gain to satisfy power density threshold, peak value detection avoids clipping;S4, baseband signal and corresponding carrier mixing generates radio frequency signal, digital combiner loads amplitude-phase calibration coefficient and synthesizes signal, after amplification and band-pass filtering by power amplifier, output;S5, spectrum analyzer real-time monitoring target signal's frequency offset, power variation, bandwidth variation, feedback to FPGA adjustment DDS offset, PGA gain, subband quantity, repeat S2-S4 and realize closed-loop control.The application has the characteristics of hardware simplification, high synchronism, wide bandwidth coverage and flexible interference mode.

Description

Technical Field

[0001] This invention relates to the field of electronic countermeasures technology, and in particular to a method for generating dual-band jamming signals. Background Technology

[0002] Existing dual-band interference signal generation schemes mainly fall into two categories: one type uses two independent signal generation modules (such as an RF module based on AD9361) to generate single-band interference signals respectively, and then combines them into an output through a microstrip combiner. This scheme requires ≥200 hardware components (approximately 100 per module) and has a volume ≥500cm². 3 One type has a power consumption of ≥30W, and the clock signals of the two modules are synchronized through an external crystal oscillator (synchronization accuracy ≤100ns), resulting in a timing deviation of ≥50ns for the dual-band signals and an interference targeting accuracy of ≤80%. The other type uses a single programmable signal generator (such as Keysight N5183B) to achieve dual-band output through frequency band switching. The switching delay is ≥2ms, which cannot meet the real-time synchronization interference requirements. In addition, the maximum bandwidth of the signal generator is ≤160MHz, which cannot cover wide-band target systems such as 5G NR n78 band.

[0003] Meanwhile, the existing interference modes are fixed, supporting only single suppression (noise interference) or deception (fixed frame structure forgery) interference. They cannot dynamically adjust the strategy according to the power spectral density (PSD) and modulation method of the target signal. They have poor adaptability in complex electromagnetic environments (such as multiple signal superposition and frequency agility), and the interference success rate is ≤70%. Summary of the Invention

[0004] The purpose of this invention is to provide a dual-band interference signal generation method, which aims to solve the technical problems of complex hardware structure, poor dual-band synchronization, narrow bandwidth coverage, and fixed interference mode in existing dual-band interference signal generation methods.

[0005] To achieve the above objectives, the present invention provides a method for generating dual-band interference signals, comprising the following steps: S1. Receive the interference task sent by the host computer, initialize the hardware module, calculate the shared base carrier frequency, and set the baseband sampling rate; S2. Start the phase-locked loop (PLL), input a 10MHz OCXO reference clock to generate a shared base carrier, split it into two paths through a power divider and input it into the DDS module, adjust the offset to generate a dual-band carrier, and ensure a spurious rejection ratio of ≥60dBc through LC low-pass filtering. S3, FPGA generates dual-band baseband signals according to interference mode through dual independent baseband processing cores, controls the delay difference between the two baseband processing channels to be ≤5ns, adjusts the gain through PGA to meet the power density threshold, and avoids clipping by peak detection; S4. The baseband signal is mixed with the corresponding carrier to generate an RF signal. The digital combiner loads the amplitude and phase calibration coefficients to synthesize the signal, which is then amplified by a power amplifier and bandpass filtered before being output. S5. The spectrum analyzer monitors the frequency offset, power change, and bandwidth change of the target signal in real time, and feeds them back to the FPGA to adjust the DDS offset, PGA gain, and number of sub-bands. Repeating S2~S4 achieves closed-loop control to ensure that the interference suppression ratio is ≥15dB.

[0006] Preferably, in S1, the received interference task sent by the host computer includes: Target frequency band parameters: Target center frequency of frequency band 1 Target bandwidth Target center frequency of band 2 Target bandwidth ; Interference mode parameters: suppression, spoofing, frequency sweeping, and power density threshold; Synchronization accuracy requirements: Timing deviation of dual-band signals ≤ 10ns, carrier frequency stability ≤ 1×10 -12 / day.

[0007] Preferably, the shared base carrier is calculated. The frequency method is: prioritize and The greatest common divisor (GCD) is used; if the GCD is not within the PLL's operating range, a custom GCD is used. GHz, ensure , ,in, yes Compared to The offset, yes Compared to The offset, and , The absolute values ​​are all ≤2GHz; Set the baseband signal sampling rate .

[0008] Preferably, S2 specifically includes the following steps: S21. Start the PLL: Configure the PLL charge pump current and loop filter parameters by outputting the SPI control signal from the FPGA, input a 10MHz OCXO reference clock, and generate a shared base carrier. Frequency stability is ensured to be ≤1×10⁻⁶ by monitoring with a spectrum analyzer. -12 / day, phase noise ≤-110dBc / Hz@1kHz; S22. Generate dual-band carriers: Share the basic carrier. The signal is split into two paths by a power divider and input to the DDS module to generate the actual carrier wave for frequency band 1. and band 2 actual carrier ; S23. Carrier filtering: LC low-pass filter is used. After filtering, the signal is tested using a spectrum analyzer to ensure that the spurious rejection ratio is ≥60dBc and the harmonic rejection ratio is ≥50dBc.

[0009] Preferably, in S22, specifically: DDS Module 1: Adjusts the offset by writing frequency control words through the FPGA. Generate actual carrier of frequency band 1 Output power 0dBm±0.5dB; DDS Module 2: Adjust Offset Generate actual carrier in frequency band 2 Output power 0dBm±0.5dB.

[0010] Preferably, step S3 specifically includes the following steps: S31. Generate baseband signal in frequency band 1 according to the interference mode and scenario; S32. The same interference mode logic as band 1 is used to generate the baseband signal of band 2. The FPGA processes the signal in parallel through two independent baseband processing cores, and the cores are synchronized through the AXI4 bus to ensure that the processing delay difference between the two baseband signals is ≤5ns. The baseband signal bit width is uniformly 16bit and is output through the FPGA's DAC interface with an output impedance of 50Ω. S33: The FPGA adjusts the baseband signal amplitude through the PGA to ensure that the power of the subsequent modulated RF signal meets the requirements; after the gain is adjusted, the peak value of the signal is monitored by the peak detector of the FPGA to avoid clipping distortion.

[0011] Preferably, in S31, specifically: Suppression interference mode: The FPGA generates a Gaussian white noise sequence using its built-in noise generation IP core; the noise is divided into subband bandwidths of 50MHz. Each sub-band generates its own noise signal, which is then transmitted to the DDR4 cache via the FPGA's DMA controller. After the sub-band signals are spliced ​​together, they are input to an FIR low-pass filter to suppress out-of-band radiation, and the peak-to-average power ratio of the output baseband signal is ≤6dB. Deceptive jamming mode: The directional coupler extracts the target signal, and the spectrum analyzer analyzes the characteristics of the target signal: the modulation method is QPSK, the code rate is 10Mbps, and the frame structure is preamble + synchronization word + data segment; the FPGA generates fake data, modulates it through the QPSK modulator, and outputs the baseband signal. Frequency sweeping interference mode: The FPGA generates a linear frequency sweep control word to control the baseband signal frequency range. The initial sweep rate is set to 500MHz / s. The target bandwidth is monitored in real time by a spectrum analyzer. If the target bandwidth expands from 150MHz to 200MHz, the FPGA adjusts the control word to increase the sweep rate to 667MHz / s.

[0012] Preferably, step S4 specifically includes the following steps: S41, Frequency Band 1: The baseband signal is input to AD9371 quadrature modulator 1, and interacts with the signal generated by S2. Carrier mixing, mixer local oscillator power 0dBm, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc; Band 2: Baseband signal input to AD9371 quadrature modulator 2, and... Carrier mixing, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc; S42. Two RF signals are input to the digital combiner. The FPGA loads a preset amplitude and phase calibration coefficient through the combiner's control interface to compensate for the amplitude difference of the two signals ≤0.5dB and the phase difference ≤5°. After synthesis, a dual-band composite interference signal is output with an insertion loss ≤0.5dB. S43. The synthesized signal is input to the power amplifier and amplified to 32dBm±1dB, with an output power flatness ≤0.5dB. The amplified signal is then passed through a bandpass filter to remove out-of-band noise.

[0013] Preferably, step S5 specifically includes the following steps: S51. The directional coupler extracts the target system's output signal and inputs it to a spectrum analyzer to analyze the target signal parameters: frequency offset. Power change Bandwidth variation Analysis cycle 100μs; S52. Adjust the frequency, power, and bandwidth according to the feedback adjustment logic; S53. Repeat S2~S4 to form a closed loop of monitoring-analysis-adjustment-output with a closed loop period of 100μs to ensure the effectiveness of the interference.

[0014] Preferably, in S52, specifically: Frequency adjustment: If For frequencies >5MHz, the FPGA adjusts the frequency control word of the corresponding DDS module via the SPI interface, changing the DDS1 offset from 2.5GHz to 2.508GHz. Adjust the response time to ≤10μs; Power adjustment: If >3dB, the FPGA adjusts the PGA gain to increase the baseband signal gain of band 2 from -8dBFS to -5dBFS, ensuring that the interference power density is stable at -30dBm / Hz, with an adjustment accuracy of 0.1dB; Bandwidth adjustment: If For frequencies >10MHz, the FPGA reconfigures the number of sub-bands, extending the interference bandwidth to 215MHz, with a configuration time ≤50μs.

[0015] Therefore, the beneficial effects of the above-mentioned dual-band interference signal generation method of the present invention are as follows: (1) The present invention replaces the traditional dual independent modules with a shared carrier architecture, which greatly reduces the number and size of hardware components, thereby significantly reducing power consumption; the timing deviation of dual-band signals is ≤10ns, and the interference targeting accuracy is significantly improved.

[0016] (2) Based on subband splicing technology and high sampling rate FPGA, the present invention has a maximum interference bandwidth of 200MHz per frequency band, covering mainstream target frequency bands such as 5G NR n78, WiFi 6E, and X-band radar, and the bandwidth is improved compared with traditional solutions.

[0017] (3) The present invention supports real-time switching of three modes: suppression / spoofing / frequency sweeping (switching delay ≤ 1μs), and can dynamically adjust parameters (such as frequency sweeping rate and sub-band power) according to the characteristics of the target signal, thereby improving the interference success rate in multi-signal superposition scenarios.

[0018] (4) The closed-loop control cycle of the present invention is 100μs. When the target signal frequency shifts by ±50MHz, the power changes by ±10dB, and the bandwidth changes by ±50MHz, the system completes the adaptation within 50μs, and the interference suppression ratio remains ≥15dB, which improves the stability under complex electromagnetic environments.

[0019] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating an embodiment of a dual-band interference signal generation method according to the present invention. Detailed Implementation

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] Example 1: like Figure 1 As shown, the present invention provides a method for generating dual-band interference signals, comprising the following steps: S1. Receive the interference task sent by the host computer, initialize the hardware module, calculate the shared base carrier frequency, and set the baseband sampling rate.

[0024] The interference tasks received from the host computer (industrial control computer, model Advantech IPC-610) include: Target frequency band parameters: Target center frequency of frequency band 1 (Value range: 1GHz~18GHz, precision: 1kHz), target bandwidth (Value range 10MHz~200MHz, step size 1MHz); Target center frequency of frequency band 2 (Value range: 1GHz~18GHz, and the difference between f2 and f1 ≥ 500MHz), target bandwidth (Value range: 10MHz~200MHz, step size: 1MHz).

[0025] Interference mode parameters: Suppression (noise type: Gaussian white noise / impulse noise), Spoofing (modulation method: PSK / QAM / FM, code rate 1kbps~100Mbps), Sweep (sweep type: linear / nonlinear, sweep rate 10MHz / s~1GHz / s, step size 1MHz / s) and power density threshold (-40dBm / Hz~-20dBm / Hz, step size 0.1dBm / Hz).

[0026] Synchronization accuracy requirements: Timing deviation of dual-band signals ≤ 10ns, carrier frequency stability ≤ 1×10 -12 / day.

[0027] Initialize the hardware module; the specific configuration is as follows: Shared carrier generation unit: Phase-locked loop (PLL, model ADF4351, operating frequency 35MHz~4.4GHz, frequency resolution 0.01Hz), external reference clock (OCXO, model ABRACON ASV80, 10MHz output, frequency stability 5×10⁻⁶). -14 / day); Dual-band baseband signal generation unit: FPGA chip (model Xilinx Zynq UltraScale+ZU9EG, logic resources 275k LUTs, built-in 2 DDR4 controllers); Frequency conversion modulation unit: Quadrature modulator (model ADI AD9371, operating frequency 70MHz~6GHz, local oscillator rejection ratio ≥40dB); Signal combining unit: digital combiner (model Mini-Circuits ZN2PD2-63-S+, operating frequency 1MHz~6GHz, insertion loss ≤0.5dB); Target signal monitoring feedback unit: spectrum analyzer (model Rohde & Schwarz FSV30, frequency range 9kHz~30GHz, resolution bandwidth 1Hz~1MHz), directional coupler (coupling degree 20dB, insertion loss ≤0.3dB).

[0028] Calculate shared base carrier The frequency method is: prioritize and The greatest common divisor (GCD) should be used. If the GCD is not within the PLL's operating range (35MHz~4.4GHz), then a custom value should be used. GHz, ensure , ,in, yes Compared to The offset, yes Compared to The offset, and , The absolute values ​​are all ≤2GHz.

[0029] Set the baseband signal sampling rate (Redundancy of 20% to avoid aliasing, such as...) =150MHz, =330MHz).

[0030] S2. Start the phase-locked loop (PLL), input a 10MHz OCXO reference clock to generate a shared base carrier, split it into two inputs to the DDS module via a power divider, adjust the offset to generate a dual-band carrier, and ensure a spurious rejection ratio ≥60dBc after LC low-pass filtering. The specific steps include: S21. Start the PLL: Configure the PLL charge pump current (2.5mA~10mA, step size 0.5mA) and loop filter parameters (resistor 1kΩ~100kΩ, capacitor 10pF~1μF) by outputting the SPI control signal from the FPGA, input a 10MHz OCXO reference clock, and generate a shared base carrier. Frequency stability is ensured to be ≤1×10⁻⁶ by monitoring with a spectrum analyzer. -12 / day, phase noise ≤-110dBc / Hz@1kHz.

[0031] S22. Generate dual-band carriers: Share the basic carrier. The signal is split into two paths by a power divider (Mini-Circuits ZFSC-2-10-S+, frequency divider, insertion loss ≤0.3dB), and then input to the DDS module (integrated into the AD9910 chip, two independent channels) to generate the actual carrier of frequency band 1. and band 2 actual carrier Specifically: DDS Module 1: Adjusts the offset by writing frequency control words through the FPGA. Generate actual carrier of frequency band 1 Output power 0dBm±0.5dB; DDS Module 2: Adjust Offset Generate actual carrier in frequency band 2 Output power 0dBm±0.5dB.

[0032] S23. Carrier filtering: LC low-pass filter (topology: π type, inductor model Coilcraft 0805CS-100XJ, capacitor model Murata GRM188R61C104KA01D). After filtering, the signal is tested using a spectrum analyzer to ensure a spurious rejection ratio of ≥60dBc (test bandwidth 1kHz~10GHz) and a harmonic rejection ratio of ≥50dBc.

[0033] S3, the FPGA generates dual-band baseband signals according to interference mode through dual independent baseband processing cores, controls the delay difference between the two baseband processing paths to be ≤5ns, adjusts the gain through PGA to meet the power density threshold, and avoids clipping by peak detection. The specific steps include: S31. Generate baseband signals for frequency band 1 according to the interference mode and scenario, specifically: Suppression interference mode: The FPGA generates a Gaussian white noise sequence (16-bit width, sampling rate) through its built-in noise generation IP core. =330MHz); divided according to subband bandwidth of 50MHz. Individual band ( =150MHz, =3), each sub-band independently generates a noise signal, which is transmitted to the DDR4 cache (capacity 4GB, read / write rate 2133Mbps) through the FPGA's DMA controller; after the sub-band signals are spliced, they are input to the FIR low-pass filter (tap number 128, roll-off factor 0.25, passband ripple ≤0.1dB, stopband attenuation ≥60dB) to suppress out-of-band radiation, and the peak-to-average power ratio of the output baseband signal is ≤6dB; Deceptive jamming mode: The directional coupler extracts the target signal (coupling degree 20dB), and the spectrum analyzer analyzes the target signal characteristics: modulation method QPSK, code rate 10Mbps, frame structure preamble (8 bits) + synchronization word (16 bits) + data segment (256 bits); FPGA generates fake data (data segment replaced with fake instructions), and modulates it through a QPSK modulator (symbol rate 10Mbps, modulation error rate ≤1×10). -5 ), output baseband signal; Frequency sweeping interference mode: The FPGA generates a linear frequency sweep control word (32-bit width) to control the baseband signal frequency range. The initial sweep rate is set to 500MHz / s. The target bandwidth is monitored in real time by a spectrum analyzer. If the target bandwidth expands from 150MHz to 200MHz, the FPGA adjusts the control word to increase the sweep rate to 667MHz / s.

[0034] S32. The same interference mode logic as band 1 is used to generate the baseband signal of band 2. The FPGA processes the signal in parallel through two independent baseband processing cores (core 1 processes band 1 and core 2 processes band 2). The cores are synchronized through the AXI4 bus (synchronization clock 100MHz, synchronization delay ≤2ns) to ensure that the processing delay difference between the two baseband signals is ≤5ns. The baseband signal bit width is uniformly 16bit and is output through the FPGA's DAC interface (rate 500MSPS, resolution 14bit) with an output impedance of 50Ω.

[0035] S33. The FPGA adjusts the baseband signal amplitude via a programmable gain amplifier (PGA, model ADI AD8370, gain range -12dB to +24dB, step size 0.1dB). For example, when the power density threshold is -30dBm / Hz, the gain is adjusted to -10dBFS (0dBm full-scale output power at 16-bit width) to ensure that the subsequent modulated RF signal power meets the requirements (30dBm~40dBm). After gain adjustment, the peak detector (sampling rate) of the FPGA is used to... The detection threshold is 0dBFS-3dB to monitor the peak value of the signal and avoid clipping distortion (distortion degree ≤1%).

[0036] S4. The baseband signal is mixed with the corresponding carrier to generate an RF signal. The digital combiner applies amplitude and phase calibration coefficients to synthesize the signal, which is then amplified by a power amplifier and bandpass filtered before being output. This process includes the following steps: S41, Band 1: Baseband signal (16-bit, 330 MSPS) is input to AD9371 quadrature modulator 1, and mixed with the signal generated by S2. Carrier mixing, mixer local oscillator power 0dBm, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc; Band 2: Baseband signal input to AD9371 quadrature modulator 2, and... Carrier mixing, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc.

[0037] S42. Two RF signals are input to the digital combiner. The FPGA loads the preset amplitude and phase calibration coefficients (obtained through previous calibration tests, with an amplitude calibration accuracy of 0.1dB and a phase calibration accuracy of 1°) through the combiner's control interface to compensate for the amplitude difference of the two signals ≤0.5dB and the phase difference ≤5°. After synthesis, a dual-band composite interference signal is output with an insertion loss ≤0.5dB.

[0038] S43. The synthesized signal is input to a power amplifier (model Cree CMPA91000, operating frequency 1~10GHz, gain 25dB, linearity IP3=52dBm), amplified to 32dBm±1dB, and the output power flatness is ≤0.5dB; the amplified signal is then passed through a bandpass filter (model K&L Microwave 13325, passband 3.2~7.2GHz, out-of-band rejection ≥40dB@2GHz / 8GHz) to filter out out-of-band noise (noise power ≤-30dBm).

[0039] S5. The spectrum analyzer monitors the frequency offset, power change, and bandwidth change of the target signal in real time, and feeds this information back to the FPGA to adjust the DDS offset, PGA gain, and sub-band count. S2~S4 are repeated to achieve closed-loop control, ensuring an interference suppression ratio ≥15dB. This includes the following steps: S51. The directional coupler extracts the target system output signal (extraction ratio 10%~20%), inputs it to the spectrum analyzer, and analyzes the target signal parameters: frequency offset. (Resolution 1kHz), power change (Resolution 0.1dB), bandwidth change (Resolution 1MHz), analysis period 100μs.

[0040] S52. Adjust the frequency, power, and bandwidth according to the feedback adjustment logic, specifically as follows: Frequency adjustment: If >5MHz (e.g., 5G NR signal shifts from 3.55GHz to 3.558GHz) =8MHz), the FPGA adjusts the frequency control word of the corresponding DDS module through the SPI interface, adjusting the DDS1 offset from 2.5GHz to 2.508GHz, correcting... Adjust the response time to ≤10μs; Power adjustment: If >3dB (e.g., WiFi 6E signal power increased from -75dBm to -72dBm) =3dB), the FPGA adjusts the PGA gain to increase the baseband signal gain of band 2 from -8dBFS to -5dBFS, ensuring that the interference power density is stable at -30dBm / Hz, with an adjustment accuracy of 0.1dB; Bandwidth adjustment: If >10MHz (e.g., if the target bandwidth is extended from 200MHz to 215MHz, =15MHz), FPGA reconfiguration of subband quantity ( (Adjusted from 4 to 5), extending the interference bandwidth to 215MHz, with a configuration time ≤50μs.

[0041] S53. Repeat S2~S4 to form a closed loop of monitoring-analysis-adjustment-output with a closed loop period of 100μs to ensure the effectiveness of the interference (interference suppression ratio ≥15dB, obtained by testing the power ratio of the interference signal to the target signal using a spectrum analyzer).

[0042] Therefore, the present invention employs the above-mentioned dual-band interference signal generation method, which features simplified hardware, high synchronization, wide bandwidth coverage, and flexible interference modes, thereby improving the interference aiming accuracy and stability in complex electromagnetic environments.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for generating dual-band interference signals, characterized in that, Includes the following steps: S1. Receive the interference task sent by the host computer, initialize the hardware module, calculate the shared base carrier frequency, and set the baseband sampling rate; S2. Start the phase-locked loop (PLL), input a 10MHz OCXO reference clock to generate a shared base carrier, split it into two paths through a power divider and input it into the DDS module, adjust the offset to generate a dual-band carrier, and ensure a spurious rejection ratio of ≥60dBc through LC low-pass filtering. S3, FPGA generates dual-band baseband signals according to interference mode through dual independent baseband processing cores, controls the delay difference between the two baseband processing channels to be ≤5ns, adjusts the gain through PGA to meet the power density threshold, and avoids clipping by peak detection; S4. The baseband signal is mixed with the corresponding carrier to generate an RF signal. The digital combiner loads the amplitude and phase calibration coefficients to synthesize the signal, which is then amplified by a power amplifier and bandpass filtered before being output. S5. The spectrum analyzer monitors the frequency offset, power change, and bandwidth change of the target signal in real time, and feeds them back to the FPGA to adjust the DDS offset, PGA gain, and number of sub-bands. Repeating S2~S4 achieves closed-loop control to ensure that the interference suppression ratio is ≥15dB.

2. The method for generating a dual-band interference signal according to claim 1, characterized in that: In S1, the received interference tasks from the host computer include: Target frequency band parameters: Target center frequency of frequency band 1 Target bandwidth Target center frequency of band 2 Target bandwidth ; Interference mode parameters: suppression, spoofing, frequency sweeping, and power density threshold; Synchronization accuracy requirements: Dual-band signal timing deviation ≤ 10ns, carrier frequency stability ≤ 1×10 -12 / day.

3. The method for generating a dual-band interference signal according to claim 2, characterized in that: Calculate shared base carrier The frequency method is: prioritize and The greatest common divisor (GCD) is used; if the GCD is not within the PLL's operating range, a custom GCD is used. GHz, ensure , ,in, yes Compared to The offset, yes Compared to The offset, and , The absolute values ​​are all ≤2GHz; Set the baseband signal sampling rate .

4. The method for generating a dual-band interference signal according to claim 3, characterized in that: S2 specifically includes the following steps: S21. Start the PLL: Configure the PLL charge pump current and loop filter parameters by outputting the SPI control signal from the FPGA, input a 10MHz OCXO reference clock, and generate a shared base carrier. Frequency stability is ensured to be ≤1×10⁻⁶ by monitoring with a spectrum analyzer. -12 / day, phase noise ≤-110dBc / Hz@1kHz; S22. Generate dual-band carriers: Share the basic carrier. The signal is split into two paths by a power divider and input to the DDS module to generate the actual carrier wave for frequency band 1. and band 2 actual carrier ; S23. Carrier filtering: LC low-pass filter is used. After filtering, the signal is tested using a spectrum analyzer to ensure that the spurious rejection ratio is ≥60dBc and the harmonic rejection ratio is ≥50dBc.

5. The dual-band interference signal generation method according to claim 4, characterized in that: In S22, specifically: DDS Module 1: Adjusts the offset by writing frequency control words through the FPGA. Generate actual carrier of frequency band 1 Output power 0dBm±0.5dB; DDS Module 2: Adjust Offset Generate actual carrier in frequency band 2 Output power 0dBm±0.5dB.

6. The dual-band interference signal generation method according to claim 4, characterized in that: S3 specifically includes the following steps: S31. Generate baseband signal in frequency band 1 according to the interference mode and scenario; S32. The same interference mode logic as band 1 is used to generate the baseband signal of band 2. The FPGA processes the signal in parallel through two independent baseband processing cores, and the cores are synchronized through the AXI4 bus to ensure that the processing delay difference between the two baseband signals is ≤5ns. The baseband signal bit width is uniformly 16bit and is output through the FPGA's DAC interface with an output impedance of 50Ω. S33: The FPGA adjusts the baseband signal amplitude through the PGA to ensure that the power of the subsequent modulated RF signal meets the requirements; after the gain is adjusted, the peak value of the signal is monitored by the peak detector of the FPGA to avoid clipping distortion.

7. The dual-band interference signal generation method according to claim 6, characterized in that: In S31, specifically: Suppression interference mode: The FPGA generates a Gaussian white noise sequence using its built-in noise generation IP core; the noise is divided into subband bandwidths of 50MHz. Each sub-band generates its own noise signal, which is then transmitted to the DDR4 cache via the FPGA's DMA controller. After the sub-band signals are spliced ​​together, they are input to an FIR low-pass filter to suppress out-of-band radiation, and the peak-to-average power ratio of the output baseband signal is ≤6dB. Deceptive jamming mode: The directional coupler extracts the target signal, and the spectrum analyzer analyzes the characteristics of the target signal: the modulation method is QPSK, the code rate is 10Mbps, and the frame structure is preamble + synchronization word + data segment; the FPGA generates fake data, modulates it through the QPSK modulator, and outputs the baseband signal. Frequency sweeping interference mode: The FPGA generates a linear frequency sweep control word to control the baseband signal frequency range. The initial sweep rate is set to 500MHz / s. The target bandwidth is monitored in real time by a spectrum analyzer. If the target bandwidth expands from 150MHz to 200MHz, the FPGA adjusts the control word to increase the sweep rate to 667MHz / s.

8. A method for generating a dual-band interference signal according to claim 6, characterized in that: S4 specifically includes the following steps: S41, Frequency Band 1: The baseband signal is input to AD9371 quadrature modulator 1, and interacts with the signal generated by S2. Carrier mixing, mixer local oscillator power 0dBm, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc; Band 2: Baseband signal input to AD9371 quadrature modulator 2, and... Carrier mixing, output RF signal frequency, power -10dBm±0.5dB, modulation distortion ≤-35dBc; S42. Two RF signals are input to the digital combiner. The FPGA loads a preset amplitude and phase calibration coefficient through the combiner's control interface to compensate for the amplitude difference of the two signals ≤0.5dB and the phase difference ≤5°. After synthesis, a dual-band composite interference signal is output with an insertion loss ≤0.5dB. S43. The synthesized signal is input to the power amplifier and amplified to 32dBm±1dB, with an output power flatness ≤0.5dB. The amplified signal is then passed through a bandpass filter to remove out-of-band noise.

9. A method for generating a dual-band interference signal according to claim 8, characterized in that: S5 specifically includes the following steps: S51. The directional coupler extracts the target system's output signal and inputs it to a spectrum analyzer to analyze the target signal parameters: frequency offset. Power change Bandwidth variation Analysis cycle 100μs; S52. Adjust the frequency, power, and bandwidth according to the feedback adjustment logic respectively; S53. Repeat S2~S4 to form a closed loop of monitoring-analysis-adjustment-output with a closed loop period of 100μs to ensure the effectiveness of the interference.

10. A method for generating a dual-band interference signal according to claim 9, characterized in that: In S52, specifically: Frequency adjustment: If For frequencies >5MHz, the FPGA adjusts the frequency control word of the corresponding DDS module via the SPI interface, changing the DDS1 offset from 2.5GHz to 2.508GHz. Adjust the response time to ≤10μs; Power adjustment: If >3dB, the FPGA adjusts the PGA gain to increase the baseband signal gain of band 2 from -8dBFS to -5dBFS, ensuring that the interference power density is stable at -30dBm / Hz, with an adjustment accuracy of 0.1dB; Bandwidth adjustment: If For frequencies >10MHz, the FPGA reconfigures the number of sub-bands, extending the interference bandwidth to 215MHz, with a configuration time ≤50μs.

Images