Communication method and apparatus

Abstract

The application provides a communication method and device, which are suitable for the field of communication, and the method comprises the following steps: obtaining a first bit sequence, the first bit sequence comprising a bit with index a and a bit with index b, a and b belonging to a same coset of a subspace, the dimension of the subspace being t; performing interleaving on the first bit sequence to obtain a second bit sequence, the second bit sequence comprising a bit with index x and a bit with index x+Z, the bit with index a in the first bit sequence corresponding to the bit with index x in the second bit sequence, the bit with index b in the first bit sequence corresponding to the bit with index x+Z in the second bit sequence, Z belonging to {1, …, 2 t -1} or Z belonging to {‑1,‑2, …, 1‑2 t} or Z=nQ, Q indicating a modulation order; and modulating the second bit sequence to obtain a modulation symbol. By adjusting the order of the bits in the first bit sequence, the system performance is improved.

Description

Technical Field

[0001] This application relates to the field of communications, and particularly to communication methods and apparatus in the field of communications. Background Technology

[0002] Channel coding is an important technique in communication technology, which can improve the reliability of signal transmission and enhance the transmission quality of communication systems. Reed-Muller (RM) codes are error-correcting codes with a relatively simple structure. For example, when the number of bits for control channel information is greater than or equal to 3 and less than or equal to 11, RM codes can be used to encode the control information.

[0003] Currently, in wireless communication, the transmitting end encodes the control information and then directly maps the channel-encoded codewords onto constellation points (also known as constellation symbols) in the constellation diagram. This process is also called modulation, which is then used for subsequent channel transmission. In this way, the overall performance of the system is relatively poor. Summary of the Invention

[0004] This application provides a communication method and apparatus in order to improve system performance.

[0005] In a first aspect, this application provides a communication method that can be executed by a first communication device. For example, it can be executed by the first communication device itself, or by a component (such as a processor, chip, chip system, etc.) configured in the first communication device, or by a logic module or software capable of implementing all or part of the functions of the first communication device. This application does not limit the scope of the method.

[0006] The first communication device may be, for example, a terminal or a radio access network (RAN) device (hereinafter referred to as access network device). This application does not limit the type of the first communication device.

[0007] For example, the method includes: obtaining a first bit sequence, which includes a bit with index a and a bit with index b, where a and b belong to the same coset of a subspace, the subspace having dimension t, t≥1, and t being an integer; interleaving the first bit sequence to obtain a second bit sequence, which includes a bit with index x and a bit with index x+Z, wherein the bit with index a in the first bit sequence corresponds to the bit with index x in the second bit sequence, and the bit with index b in the first bit sequence corresponds to the bit with index x+Z in the second bit sequence, where x is an integer greater than or equal to 0, and Z belongs to {1,…,2}. t-1}, or, Z belongs to {-1,-2,…,1-2}. t}, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the second bit sequence mentioned above; the second bit sequence is modulated to obtain the modulation symbol.

[0008] The index of a bit in a bit sequence is used to indicate the position of the bit in the bit sequence. This index can also be called a position index, number, or sequence number, etc. This application does not limit its name.

[0009] The above a and b belong to the same coset of a subspace with dimension t. This can also be simply referred to as a and b belonging to the same t-dimensional subspace coset.

[0010] The first bit sequence contains the same bits as the second bit sequence, but the order of the bits is different, or in other words, the position indices of at least two bits are different.

[0011] The bit with index 'a' in the first bit sequence corresponds to the bit with index 'x' in the second bit sequence. This can be understood as the same bit, where the bit with index 'a' in the first bit sequence and the bit with index 'x' in the second bit sequence are simply different bits. The bit has index 'a' in the first bit sequence and index 'x' in the second bit sequence.

[0012] Similarly, the bit with index b in the first bit sequence corresponds to the bit with index x+Z in the second bit sequence. This can be understood as the bit with index b in the first bit sequence and the bit with index x+Z in the second bit sequence being the same bit, except that the index of this bit in the first bit sequence is b and the index of this bit in the second bit sequence is x+Z.

[0013] The aforementioned t-dimensional subspace satisfies the condition that the sum of any two elements in the t-dimensional subspace belongs to the t-dimensional subspace. For example, the aforementioned t-dimensional subspace can be a t-dimensional subspace over a binary field.

[0014] A coset of the aforementioned t-dimensional subspace can be defined as the set obtained by adding any element v in the full space V to any element in the t-dimensional subspace S.

[0015] Optionally, the first bit sequence is an encoded bit sequence or an encoded bit sequence after self-isomorphic permutation.

[0016] In the above scheme, by adjusting the order of bits in the first bit sequence, the bits can be mapped to different constellation bits, thereby changing the degree of protection for the bits and improving the overall performance of the system.

[0017] As mentioned earlier, one possible case is that Z belongs to {1,…,2}. t -1} or Z belongs to {-1,-2,…,1-2} t In other words, the difference between the indices of the bits corresponding to indices a and b (hereinafter referred to as the first bit) belonging to the same subspace coset in the first bit sequence in the second bit sequence will not exceed 2. t -1, and the aforementioned subspace is t-dimensional, therefore the coset of the aforementioned subspace contains 2 elements. t Therefore, no bits corresponding to the indices of other subspace cosets are added between the first bits. In this way, when mapping the bits in the second bit sequence to constellation points, the first bit can be mapped to constellation bits of different reliability. Thus, after soft value merging during decoding, the decoder obtains mostly soft values ​​with smaller absolute values, thereby improving the overall system performance in some scenarios. For example, the above implementation can be applied to precision-constrained scenarios, such as when the terminal is in power-saving mode. In precision-constrained scenarios, if the absolute values ​​of the soft values ​​vary greatly, the numerical range is large. Due to precision constraints, soft values ​​may not be fully represented, potentially causing performance loss. The above implementation ensures that the soft value merging results in soft values ​​with smaller absolute values, thereby improving the overall system performance.

[0018] Another possible scenario is Z = nQ, where n can be a positive or negative integer. That is, the bits corresponding to indices a and b (hereinafter referred to as the first bit) belonging to the same subspace coset in the first bit sequence are spaced nQ-1 apart in the second bit sequence. Thus, when mapping the bits in the second bit sequence to constellation points, the first bit can, for example, be mapped to constellation bits of the same reliability. Consequently, the absolute values ​​of the soft values ​​obtained after soft value merging during decoding at the decoding end vary, allowing the soft value with the larger absolute value to be retained, thereby improving decoding reliability and performance. This implementation can be applied, for example, to scenarios where precision is not limited, such as terminals not in power-saving mode.

[0019] It is understandable that when the decoding end performs soft value merging during the decoding process, the soft values ​​of the bits corresponding to the indices of the first bit sequence that belong to the same subspace coset can be merged.

[0020] In conjunction with the first aspect, in some possible implementations of the first aspect, the indices of any two bits in the first bit sequence are a and b.

[0021] In other words, the bits corresponding to the index of any coset belonging to the above subspace satisfy the above characteristics. Thus, in precision-constrained scenarios, the soft values ​​obtained by the decoder after soft value merging during decoding are all soft values ​​with smaller absolute values, thereby improving the overall system performance; in precision-unconstrained scenarios, the absolute values ​​of the soft values ​​obtained by the decoder after soft value merging during decoding vary, allowing the retention of soft values ​​with larger absolute values, thereby improving decoding reliability and ultimately decoding performance.

[0022] In conjunction with the first aspect, in some possible implementations of the first aspect, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the subspace in the first bit sequence.

[0023] Optionally, the above-mentioned interleaving of the first bit sequence to obtain the second bit sequence can be implemented in one possible way: based on the interleaving sequence, the first bit sequence is interleaved to obtain the second bit sequence. The interleaving sequence is used to indicate the correspondence between index x in the second bit sequence and index a in the first bit sequence, as well as the correspondence between index x+Z in the second bit sequence and index b in the first bit sequence.

[0024] The first bit sequence is interleaved using the above interleaving sequence. The interleaving method is relatively simple and helps to reduce the complexity of interleaving.

[0025] Another possible implementation is to perform a first interleaving operation on the first bit sequence when Z = nQ to obtain a third bit sequence. This third bit sequence includes a bit at index y and a bit at index y+M. The bit at index y in the third bit sequence corresponds to the bit at index a in the first bit sequence, and the bit at index y+M in the third bit sequence corresponds to the bit at index b in the first bit sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t}; Perform a second interleaving operation on the third bit sequence to obtain the second bit sequence.

[0026] Through the first interleaving operation, the bits corresponding to the indices of the same t-dimensional subspace coset in the first bit sequence can be arranged in order. Then, through the second interleaving operation, the bits corresponding to the indices of the same t-dimensional subspace coset are spaced nQ-1 apart. In this way, when the bits in the second bit sequence are mapped to constellation points, the bits corresponding to the indices of the same t-dimensional subspace coset can be mapped to constellation bits with the same reliability, thereby improving the decoding reliability.

[0027] When Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2}t When interleaving the first bit sequence to obtain the second bit sequence, the above includes: performing a first interleaving operation on the first bit sequence to obtain the second bit sequence.

[0028] The first interleaving operation arranges the bits corresponding to the indices of the same t-dimensional subspace coset in the first bit sequence in a sequential order. This sequential arrangement means that bits corresponding to the indices of the same t-dimensional subspace coset do not include bits corresponding to the indices of other subspace cosets. Therefore, when mapping the bits in the second bit sequence to constellation points, the bits corresponding to the indices of the same t-dimensional subspace coset in the first bit sequence can be mapped to constellation bits of different reliability levels. This results in the decoder performing soft-value merging during decoding, obtaining mostly soft values ​​with smaller absolute values, thus improving the overall system performance in certain scenarios.

[0029] In conjunction with the first aspect, in some possible implementations of the first aspect, t = r or r-1, where r is the order of the RM code.

[0030] The above scheme can be applied, for example, to scenarios where the decoder can begin decoding when r = 0 or 1. It is understood that when r takes other values ​​and the decoder can still decode, the value of t can also be changed accordingly. This application does not specifically limit the value of t.

[0031] Secondly, this application provides a communication method that can be executed by a second communication device. For example, it can be executed by the second communication device itself, or by a component (such as a processor, chip, chip system, etc.) configured in the second communication device, or by a logic module or software capable of implementing all or part of the functions of the second communication device. This application does not limit the scope of the method.

[0032] The second communication device may be, for example, a terminal or an access network device. This application does not limit the type of the second communication device.

[0033] For example, the method includes: demodulating the received modulation symbols to obtain a first sequence, the first sequence including an element with index x and an element with index x+Z, where x is an integer greater than or equal to 0; deinterleaving the first sequence to obtain a second sequence, the second sequence including an element with index a and an element with index b, wherein the element with index a in the second sequence corresponds to the element with index x in the first sequence, and the element with index b in the second sequence corresponds to the element with index x+Z in the first sequence, where a and b belong to the same coset of a subspace with dimension t, t≥1, t is an integer, and Z belongs to {1,…,2}. t-1}, or {-1,-2,…,1-2} t}, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the first sequence above.

[0034] In conjunction with the second aspect, in some possible implementations of the second aspect, the indices of any two bits in the second sequence described above are a and b.

[0035] In conjunction with the second aspect, in some possible implementations of the second aspect, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the aforementioned subspace in the second sequence.

[0036] In conjunction with the second aspect, in some possible implementations of the second aspect, the above-mentioned deinterleaving of the first sequence to obtain the second sequence includes: deinterleaving the first sequence based on the interleaved sequence to obtain the second sequence, wherein the interleaved sequence is used to indicate the correspondence between index x in the first sequence and index a in the second sequence, and the correspondence between index x+Z in the first sequence and index b in the second sequence.

[0037] In conjunction with the second aspect, in some possible implementations of the second aspect, when Z = nQ, the above-mentioned deinterleaving of the first sequence to obtain the second sequence includes: performing a first deinterleaving operation on the first sequence to obtain a third sequence, the third sequence including bits with index y and bits with index y+M, the bits with index y in the third sequence corresponding to the bits with index a in the second sequence, and the bits with index y+M in the third sequence corresponding to the bits with index b in the second sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t}; Perform a second deinterleaving operation on the third sequence to obtain the second sequence.

[0038] In conjunction with the second aspect, in some possible implementations of the second aspect, when Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} t When the first sequence is de-interleaved to obtain the second sequence, the above-mentioned process includes: performing a first interleaving operation on the first sequence to obtain the second sequence.

[0039] In conjunction with the second aspect, in some possible implementations of the second aspect, t = r or r-1, where r is the order of the RM code.

[0040] In conjunction with the second aspect, in some possible implementations of the second aspect, the sum of any two elements in the t-dimensional subspace S belongs to the t-dimensional subspace S.

[0041] In conjunction with the second aspect, in some possible implementations of the second aspect, for the entire space V, the set obtained by adding any element v in the entire space V to the elements in the t-dimensional subspace S is a coset of the aforementioned t-dimensional subspace S.

[0042] It should be understood that the second aspect of this application corresponds to the technical solution of the first aspect of this application, and the beneficial effects achieved by these two aspects and their corresponding feasible implementation methods are similar, and will not be described again.

[0043] Thirdly, this application provides a communication device that can implement the method described in the first aspect and any possible implementation thereof; or, can implement the method described in the second aspect and any possible implementation thereof. The device includes corresponding modules for performing the above-described methods. The modules included in the device can be implemented in software and / or hardware.

[0044] The communication device may be a first communication device for implementing the method described in the first aspect and any possible implementation of the first aspect. In one possible implementation, the communication device may include modules or units that perform the methods / operations / steps / actions described in the first aspect and any possible implementation of the first aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software.

[0045] The communication device may also be a second communication device for implementing the methods described in the second aspect and any possible implementation of the second aspect. In one possible implementation, the communication device may include modules or units that perform the methods / operations / steps / actions described in the second aspect and any possible implementation of the second aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software.

[0046] Fourthly, this application provides a communication device including a processor, which can be used to implement the method described in the first aspect and any possible implementation of the first aspect, or to implement the method described in the second aspect and any possible implementation of the second aspect, by executing a computer program in memory and / or by logic circuitry.

[0047] In one possible implementation, the device further includes a communication interface. The communication interface is used to receive signals from other communication devices outside the device and transmit them to the processor, or to send signals from the processor to other communication devices outside the device. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, pin, or other type of communication interface.

[0048] In one possible implementation, the device further includes a memory. The memory stores program instructions and data. The memory is coupled to the processor, which, when executing the instructions stored in the memory, can implement the methods described in the preceding aspects. Optionally, the memory and the processor can be integrated together; alternatively, the memory can be located outside the processor and exist independently.

[0049] Fifthly, this application provides a computer-readable storage medium storing a computer program (also referred to as code or instructions) that, when executed, implements the method described in the first aspect and any possible implementation thereof, or implements the method described in the second aspect and any possible implementation thereof.

[0050] In a sixth aspect, this application provides a computer program product comprising instructions (also referred to as code) that, when executed, implement the method described in the first aspect and any possible implementation thereof, or implement the method described in the second aspect and any possible implementation thereof.

[0051] In a seventh aspect, this application provides a chip system including at least one processor for supporting the implementation of the functions involved in the first aspect and any possible implementation of the first aspect, or for supporting the implementation of the functions involved in the second aspect and any possible implementation of the second aspect, such as receiving or processing data involved in the above methods.

[0052] In one possible design, the chip system also includes a memory for storing program instructions and data, which is located either inside or outside the processor.

[0053] The chip system can consist of chips or include chips and other discrete components.

[0054] Eighthly, this application provides a communication system comprising a first communication device and a second communication device, wherein the first communication device is used to implement the method described in the first aspect and any possible implementation thereof, and the second communication device is used to implement the method described in the second aspect and any possible implementation thereof.

[0055] It should be understood that the third to eighth aspects of this application correspond to the technical solutions of the first and second aspects of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the methods provided in the embodiments of this application;

[0057] Figure 2 This is a schematic diagram of a communication scenario applicable to the method provided in the embodiments of this application;

[0058] Figure 3 This is a schematic diagram of the decoding process provided in the embodiments of this application;

[0059] Figure 4 This is a schematic diagram of the 16QAM layered constellation diagram provided in the embodiments of this application;

[0060] Figure 5 This is a schematic flowchart of the communication method provided in the embodiments of this application;

[0061] Figure 6 This is a schematic diagram of the first interleaving operation provided in an embodiment of this application;

[0062] Figure 7 This is another schematic diagram of the first interleaving operation provided in the embodiments of this application;

[0063] Figure 8 This is a schematic diagram of the second interleaving operation provided in the embodiments of this application;

[0064] Figure 9 This is a schematic block diagram of the communication device provided in the embodiments of this application;

[0065] Figure 10 This is a schematic block diagram of another communication device provided in the embodiments of this application;

[0066] Figure 11 This is a schematic block diagram of another communication device provided in the embodiments of this application;

[0067] Figure 12 This is a schematic diagram of the communication chip system architecture provided in the embodiments of this application. Detailed Implementation

[0068] To facilitate understanding of the embodiments of this application, the following description is provided first:

[0069] First, to facilitate a clear description of the technical solutions provided in this application, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. For example, "first communication device" and "second communication device" are used only to distinguish different communication devices and do not limit their order of execution. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0070] Second, in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects, but it does not exclude the possibility of indicating an "and" relationship; the specific meaning can be understood in context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0071] Third, in this application, "when," "if," and "if" all refer to the device making a corresponding action under certain objective circumstances, and are not limited to a specific time, nor do they require the device to make a judgment action when it is implemented, nor do they imply any other limitations.

[0072] Fourth, in this application, "B corresponding to A" or "B corresponding to A" means that B is associated with A. "Determining B based on A" does not mean determining B solely based on A, but also determining B based on A and / or other information.

[0073] Fifth, in this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to the first communication device" can be understood as the destination of the information being the first communication device, which may include direct transmission via the air interface or indirect transmission via the air interface by other units or modules. "Receive information from the second communication device" can be understood as the source of the information being the second communication device, which may include direct reception from the second communication device via the air interface or indirect reception from the second communication device via the air interface by other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0074] In other words, sending and receiving can be performed between communication devices, such as between a second communication device and a first communication device; or they can be performed within a communication device, such as between components, modules, chips, software modules, or hardware modules within the communication device via a bus, wiring, or interface.

[0075] It is understandable that information may undergo necessary processing, such as encoding and modulation, before being sent from the source to the destination. Similarly, the destination, upon receiving information from the source, can also perform corresponding processing, such as decoding and demodulation, to interpret the valid information from the source. Similar expressions in this application can be understood in a similar way and will not be elaborated further.

[0076] Sixth, the technical solution provided in this application can be applied to encoding / decoding between communication devices. Encoding / decoding between communication devices can include: encoding / decoding between access network equipment and terminal equipment, encoding / decoding between access network equipment, and encoding / decoding between terminal equipment, etc. In the embodiments of this application, "encoding / decoding" can also be described as "encoding / decoding," "encoding / decoding," "network encoding / decoding," etc.

[0077] Seventh, the method provided in this application can be applied to fourth-generation (4G) communication systems, such as long-term evolution (LTE) communication systems, as well as fifth-generation (5G) communication systems, such as 5G new radio (NR) communication systems, and can also be applied to future communication systems, etc. This application does not limit it in this regard.

[0078] The following will combine Figure 1 The system architecture to which this application applies is described in detail.

[0079] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the methods provided in the embodiments of this application. Figure 1 The application scenarios applicable to this application are illustrated using the communication system architecture shown as an example. Figure 1 A possible, non-limiting system schematic diagram is shown. For example... Figure 1 As shown, the communication system includes RAN 100 and core network (CN) 200. Optionally, the communication system also includes Internet 300. RAN 100 includes at least one access network device (such as... Figure 1 110a and 110b (collectively referred to as 110) and at least one terminal device (such as Figure 1 RAN 100, denoted as RAN 120a-120j, is collectively referred to as RAN 120. RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 1(Not shown in the image). Terminal device 120 is connected to access network device 110 wirelessly. Access network device 110 is connected to core network 200 wirelessly or via wired connection. The core network device in core network 200 and access network device 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and wireless access network logical functions.

[0080] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future communication systems. RAN 100 can also be an open access network (open RAN, O-RAN, or ORAN). RAN 100 can also be a cloud radioaccess network (CRAN), etc. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0081] Understandable, Figure 1 This application only illustrates one possible communication system architecture that can be applied to an embodiment of the present application. In other possible scenarios, the communication system architecture may also include other devices.

[0082] In the aforementioned communication system, access network device 110 assists terminal devices in achieving wireless access. Multiple access network devices 110 in this communication system can be nodes of the same type or different types. In some scenarios, the roles of access network device 110 and terminal device 120 are relative, for example... Figure 1 Network element 120i can be a helicopter or a drone, and it can be configured as a mobile base station. For terminal devices 120j that access RAN 100 via network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal device. Access network device 110 and terminal device 120 are sometimes referred to as communication devices, for example... Figure 1 Network elements 110a and 110b can be understood as communication devices with base station functions, while network elements 120a-120j can be understood as communication devices with terminal functions.

[0083] In one possible scenario, access network equipment can be a base station, an evolved NodeB (eNodeB), a transmitting and receiving point (TRP), a transmitting point (TP), a next-generation NodeB (gNB), a base station in a future mobile communication system, a satellite, or an access point (AP) in a wireless fidelity (Wi-Fi) system, an integrated access and backhaul (IAB) node, or access network equipment in a mobile switching center non-terrestrial network (NTN) communication system; that is, it can be deployed on high-altitude platforms or satellites. Access network equipment can also be a macro base station (such as...). Figure 1 110a), micro base stations or indoor stations (such as Figure 1 Access network equipment can be 110b), relay nodes or donor nodes, or wireless controllers in CRAN scenarios. It can also function as a base station in device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, drone communication, or machine-to-machine (M2M) communication. Optionally, access network equipment can also be servers, wearable devices, vehicles, or in-vehicle equipment. For example, in vehicle-to-everything (V2X) technology, the access network equipment can be a roadside unit (RSU).

[0084] In another possible scenario, multiple access network devices collaborate to assist terminals in achieving wireless access, with each device performing a portion of the base station's functions. For example, access network devices can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs). CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio equipment or radio units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). It is understood that access network devices can be CU nodes, DU nodes, or devices comprising both CU and DU nodes. Furthermore, CUs can be classified as access network devices within the RAN (RAN) or the CN (CN), without limitation.

[0085] In this embodiment, the form of the access network device is not limited. The device used to implement the function of the access network device can be the access network device itself; or it can be a device that supports the access network device in implementing the function, such as a chip system. The device can be installed in the access network device or used in conjunction with the access network device.

[0086] In this application, the terminal device may also be referred to as a terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc., or a device used to provide voice or data connectivity to a user, or an Internet of Things (IoT) device. For example, terminal devices include handheld devices with wireless connectivity, vehicle-mounted devices, etc. Currently, terminal devices can include, for example: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, smart glasses, etc.), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), satellite terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability user equipment (REDCAP UE), wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, robotic arms, workshop equipment, wireless terminals in autonomous driving, wireless terminals in smart healthcare, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (such as smart robots, hot air balloons, drones, airplanes), etc. The terminal can also be a vehicle device, such as a vehicle unit, vehicle module, vehicle chip, on-board unit (OBU), or telematics box (T-BOX). The terminal device can also be other devices with terminal functions. For example, the terminal device can also be a device that plays the role of a terminal in D2D communication.

[0087] This application does not limit the form of the terminal device. The device used to implement the terminal's functions can be a terminal device itself, or it can be a device that supports the terminal in implementing those functions, such as a chip system. This device can be installed in the terminal or used in conjunction with the terminal. In this application, the chip system can be composed of chips, or it can include chips and other discrete components.

[0088] Figure 2 This is a schematic diagram of a communication scenario applicable to the method provided in the embodiments of this application.

[0089] like Figure 2 As shown in a), the method provided in this application can be applied to point-to-point single-connection communication scenarios, where two communication devices can communicate directly through a single communication link. For example, an access network device and a terminal device can communicate directly through a single communication link. In one possible scenario, the access network device can act as the receiver, and the terminal device can act as the transmitter, with the terminal device directly sending signals to the access network device through the communication link; however, this should not constitute any limitation on this application. For instance, in another possible scenario, the access network device can act as the transmitter, and the terminal device can act as the receiver, with the access network device directly sending signals to the terminal device through the communication link.

[0090] like Figure 2 As shown in b), the method provided in this application can also be applied to multi-hop single-connection communication scenarios, where multiple relay devices are included between the source device and the target device, and the connection between each pair of adjacent devices is a single point-to-point connection. For example, the access network device and the terminal device communicate through multiple relay devices.

[0091] like Figure 2 As shown in c), the method provided in this application can also be applied to dual connectivity (DC) communication scenarios, where the terminal device can connect to two different access network devices (such as base stations) at the same time. The cell provided by the macro base station can be called the master cell group (MCG), and the corresponding base station can be called the master base station (abbreviated as master station). The cell provided by the small base station or micro base station can be called the secondary cell group (SCG), and the corresponding base station can be called the secondary base station (abbreviated as secondary station).

[0092] like Figure 2 As shown in d), the method provided in this application can also be applied to multi-hop, multi-connection communication scenarios. This architecture combines the features of multi-hop routing and multi-connection, with data transmitted through multiple relay devices and each device able to establish connections with multiple other devices simultaneously.

[0093] More generally, the communication scenarios to which the method provided in this application is applicable include, but are not limited to: signal transmission (including uplink and downlink transmission) between access network devices and terminal devices, signal transmission between access network devices and relay devices, signal transmission between relay devices and terminal devices, signal transmission between multiple access network devices and one terminal device, or signal transmission between multiple access network devices and multiple terminal devices.

[0094] It should be understood that Figure 2 The communication scenarios shown are merely examples and should not be construed as limiting the methods provided in this application.

[0095] For future mobile communication networks, real-time high data rate applications are becoming increasingly common. These applications require the transmission of large amounts of data in a short period and are sensitive to latency, such as extended reality (XR), mixed reality (MR), and telemedicine. These applications place higher demands on the peak throughput and area efficiency of codecs, and also impose stricter requirements on decoder power consumption. Peak throughput refers to the highest data transmission rate that the network can achieve under ideal conditions, while area efficiency refers to the maximum amount of data transmission that can be supported per unit area. Currently, common codec technologies include low-density parity-check (LDPC) codes, polar codes, and RM codes. Further optimization of channel codecs for future mobile communication network chips is needed in these areas.

[0096] To better understand the methods provided in the embodiments of this application, the relevant technologies of RM codes are first briefly described below. It is understood that the methods provided in this application are applicable not only to RM codes but also to polar codes, and this application does not limit them in this regard.

[0097] 1. RM Code: Binary RM code contains multivariate polynomials in a binary field. The evaluation results are as follows. Consider a polynomial ring with m variables. For a polynomial and a binary vector Define Eval z (f)=f(z1,z2,…,z m Let f be the value of the polynomial f in the bivariate vector z. Define the evaluation vector of the polynomial f. That is, a coordinate of Eval(f) is the evaluation result of the polynomial f at a certain binary vector. Since The CCP has 2 m There are m-dimensional binary vectors, therefore, the evaluation vector Eval(f) has a total of 2... m Each dimension. For an RM code with parameters m and r, its codeword set can be defined as the set of evaluation vectors for all polynomials of order no higher than r, i.e.

[0098]

[0099] Here, deg(f) represents the order of the polynomial f. The parameter m can be called the code length parameter of the RM(m,r) code (or the first parameter of the RM code). The parameter m can be used to determine the code length; for example, the code length of the RM(m,r) code is equal to 2. m The parameter r can be called the order of the RM(m,r) code (or the second parameter of the RM code). The number of information bits k in the RM(m,r) code is equal to the number of m-ary binary monomials, i.e. in,

[0100] Based on the definition of RM(m,r) codes above, the generator matrix G of an RM(m,r) code can be determined. For example, with m=3 and r=2, the generator matrix of an RM(3,2) code is... A generator matrix can be used to encode an information bit sequence u into an encoded bit sequence x, for example, x = uG.

[0101] From the generator matrix G of the RM code, its inverse matrix G can be obtained. -1 Thus, for any valid RM codeword x∈RM(m,r), based on G -1 The corresponding information bits u = xG can be obtained. -1 .

[0102] The above method for determining the generator matrix of an RM(m,r) code based on the definition of the RM(m,r) code is merely an example and should not be construed as limiting this application. For example, another method for determining the generator matrix of an RM(m,r) code is given below.

[0103] For example, based on the recursive properties of RM codes, the generator matrix of RM codes can be obtained. The generator matrix defined in this way can be called a recursive generator matrix, and this application does not limit its name. For any valid codeword x of RM(m,r), the codeword can be divided into a first half and a second half: x = (x1,x2), where x1,x2∈RM(m-1,r), and Suppose that the generating matrix of RM(m,r) is G. m,r When the information sequence is u, the corresponding generated RM codeword sequence is x = u·G m,r Based on the aforementioned recursive properties of RM codes, the generator matrix G can be... m,r Decomposed into the following form:

[0104]

[0105] Where 0 represents a matrix of all zeros, and its dimension is the same as G. m-1,r-1 They have the same dimensions.

[0106] Specifically, when r = 0, the RM code corresponds to a 1-bit repeat code, which means repeating 1 bit of information twice.m Therefore, its generating matrix is ​​1 row 2. m A matrix of all 1s in each column. When r = m, the RM code corresponds to a code with a code rate of 1, therefore its generator matrix is ​​a matrix of size 2. m The identity matrix.

[0107] Based on the above generating matrix G m,r By defining the decomposition method and the generator matrices of the two special RM codes mentioned above, the generator matrix of RM codes of arbitrary length can be obtained. For example, an RM(3,1) code can be composed of RM(2,0) and RM(2,1) codes; and an RM(2,1) code can be composed of RM(1,0) and RM(1,1). Therefore, the generator matrix of RM(3,1) is...

[0108]

[0109] 2. The nature of RM codes

[0110] Automorphic permutation property of RM codes: For a valid codeword x of RM(m,r), its 2... m A bit codeword can be represented by an m-dimensional binary vector z = (z1, ..., zn). m Use ) as the index. For any binary full-rank matrix and vectors Define coordinate transformation That is, the bit at position z of codeword x is placed in... Position, thus obtaining a new length of 2 m The code

[0111] Decomposition property of RM codes: For any valid codeword x of an RM(m,r) (or any of its automorphic permutation codewords) (See the aforementioned properties), this codeword can be divided into a first half and a second half: x = (x1, x2). At this point, x1, x2 ∈ RM(m-1, r), and (for automorphic permutation codewords)

[0112] 3. Full Space: m-dimensional full space includes 2 m Each element.

[0113] 4. Subspace: For a binary field, any two elements in a k-dimensional subspace S, when added together, belong to that k-dimensional subspace S. For example, elements in this k-dimensional subspace satisfy: if a∈S, b∈S, then (a+b)∈S. Or, if a∈S, b∈S, c∈S, then (a+b)∈S, (b+c)∈S, (a+c)∈S, and (a+b+c)∈S. This k-dimensional subspace S includes 2... k 2 elements, the 2 k The elements include 0.

[0114] 5. Coset of a subspace: For the whole space V, the set obtained by adding any element v in the whole space V to the elements in the k-dimensional subspace S is a coset of the k-dimensional subspace S.

[0115] As can be seen from the definition of a subspace coset, the number of elements in each subspace coset of a k-dimensional subspace S is the same as the number of elements in the k-dimensional subspace S. Furthermore, each subspace coset is disjoint, meaning that the elements in each subspace coset are distinct.

[0116] For example, for 0 to 7, these 8 elements are represented in binary to form a space V, where space V is {{0,0,0}, {0,0,1}, {0,1,0}, {0,1,1}, {1,0,0}, {1,0,1}, {1,1,0}, {1,1,1}}. For the 1-dimensional subspaces {{0,0,0} and {1,0,0}}, these 1-dimensional subspaces are added to the elements in the vector space V respectively, resulting in:

[0117] +{0,0,0} = {{0,0,0}, {1,0,0}}, which corresponds to {0,4} in decimal;

[0118] +{0,0,1} = {{0,0,1}, {1,0,1}}, which corresponds to {1,5} in decimal;

[0119] +{0,1,0} = {{0,1,0}, {1,1,0}}, which corresponds to {2,6} in decimal;

[0120] +{0,1,1} = {{0,1,1}, {1,1,1}}, which corresponds to {3,7} in decimal;

[0121] +{1,0,0} = {{1,0,0}, {0,0,0}}, which corresponds to {4,0} in decimal.

[0122] +{1,0,1} = {{1,0,1}, {0,0,1}}, which corresponds to {5,1} in decimal;

[0123] +{1,1,0} = {{1,1,0}, {0,1,0}}, which corresponds to {6,2} in decimal;

[0124] +{1,1,1} = {{1,1,1}, {0,1,1}}, which corresponds to {7,3} in decimal;

[0125] Therefore, the cosets of the 1-dimensional subspaces {{0,0,0}, {1,0,0}} are {{0,0,0}, {1,0,0}}, {{0,0,1}, {1,0,1}}, {{0,1,0}, {1,1,0}}, and {{0,1,1}, {1,1,1}}. Corresponding to decimal, the cosets of the 1-dimensional subspace {0,4} are {0,4}, {1,5}, {2,6}, and {3,7}.

[0126] Similarly, we can obtain the cosets of the 2-dimensional subspace {0,4,2,6} as {0,4,2,6} and {1,5,3,7}.

[0127] 6. Decoding Method for RM Codes: This application mainly relates to the Dumer decoding algorithm. The Dumer decoding algorithm utilizes the decomposition and order reduction property of RM codes, solving the RM codes through a serial recursive approach. For example, suppose a log likelihood ratio (LLR) sequence L0,…,L is received. n This corresponds to the RM(m,r) code, where the code length or the length of the received LLR sequence is n = 2. m From the decomposition reduction property of RM codes, we know that for an RM codeword y∈RM(m,r)=(y l ,y r ), where y l It's the first half of the code, y r It's the second half of the code, with y l ∈RM(m-1,r), The Dumer decoding algorithm utilizes this property for decoding; it first decodes the first half L of the received sequence. l and the second half L r Element-by-element merging yields the merged LLR sequence:

[0128]

[0129] in, This represents the merging method for LLR fields, such as tanh merging, i.e.

[0130]

[0131] Where λ is an adjustable hyperparameter. Alternatively, it can be a min-sum merging algorithm, i.e.

[0132] L c =sign(L l )·sign(L r )·min(|L l |,|L r |),

[0133] Here, sign(·) is the sign operation. The merged sequence L c This corresponds to RM(m-1,r-1). Next, we utilize y... c The first half and the second half of the received sequence are merged a second time:

[0134] L d =L l +(1-2·y c )·L r ,

[0135] Furthermore, L d Corresponding to RM(m-1,r), it can be decoded by reducing its order. The above decoding process can be recursively repeated until some special RM nodes are reached. For example, RM(s,1) can be decoded using the fast Hadamard transform (FHT) algorithm, and RM(s,0), ​​RM(s,s), and RM(s,s-1) can be solved using the maximum likelihood (ML) decoding algorithm. In other words, the decoding device can decompose the received codeword based on the above method until m=r, or r=1, or r=0, etc., and then start decoding.

[0136] FHT decoding algorithm: Primarily designed for decoding first-order RM codes. For an RM(m,1) code, the information bit length is m+1. If the ML decoding algorithm is used, it would require enumerating 2... m+1 Given m+1 different information bit sequences, each is RM encoded. For each encoded sequence, the likelihood is calculated based on the LLR of each received bit, and all 2^m bits are used. m+1 The codeword with the highest likelihood value among the candidate information bit sequences is used as the decoding result. Even without considering encoding complexity, this method requires a certain number of floating-point additions. (That is, the complexity is approximately the square of the code length).

[0137] The FHT decoding algorithm utilizes the inherent characteristics of RM codes to accelerate the calculation of LLR in the aforementioned process. For a codeword sequence... Its likelihood is Where L zThis refers to the bit receiving LLR at coordinate z. Furthermore, for a first-order RM code, its codeword bits can be represented as... Therefore, maximizing the likelihood is equivalent to finding the information bits {u0,…,u m}, making

[0138]

[0139] Maximize. For binary variables. Can be defined

[0140]

[0141] If we take all Arranged into vectors It is essentially L z The Hadamard transform of the first-order RM code can be solved quickly using the FHT algorithm, thus completing the ML decoding of the first-order RM code.

[0142] Figure 3 This is a schematic diagram of the decoding process provided in the embodiments of this application. Figure 3 In this paper, we take the RM(3,2) code as an example to explain the Dumer decoding process, assuming that the decoding process will enter the 0th order node and the full order node for decoding.

[0143] like Figure 3 As shown, for the RM(3,2) code, the receiver can demodulate eight LLR soft values ​​L0,…,L7. First, the sequences {L0,L1,L2,L3} and {L4,L5,L6,L7} are combined using a tic-tac-toe addition method to obtain… It corresponds to the soft value sequence of the RM(2,1) code on the right. Further merging of this soft value sequence yields... This corresponds to the RM(1,0) code on the right. We have now reached the 0th-order RM code node, which can be decoded using the ML decoding method to obtain the decoding result of the RM(1,0) node. Based on this decoding result, the aforementioned L... d The merging formula yields the soft value corresponding to the middle RM(1,1) node, which is also a special node and can be decoded using ML. This completes the decoding of the right-hand RM(2,1) code. Continuing with L... d By combining the formulas, we can obtain the soft value of the left-hand RM(2,2), which is still a special node and can therefore be decoded using ML decoding. This completes the decoding process for the entire RM(3,2) code.

[0144] It should be noted that, due to the automorphic permutation property of RM codes, different automorphic permutations can be used to first permutate the RM codewords, and Dumer decoding can still be performed on this basis.

[0145] Additionally, the first decoded node, such as Figure 3 The rightmost RM(1,0) node shown in the diagram, each of its soft values ​​is essentially a 2 from the original soft value. r The result of merging the soft values ​​in a grid pattern. It can be proven that the indices corresponding to these soft values ​​are... An r-dimensional subspace coset (holds true for any permutation), the first decoding node can also be a first-order RM code, corresponding to the RM(2,1) node in the diagram, which corresponds to... (a coset in an r-1 dimensional subspace). Since it is the first decoding node, the decoding accuracy of it has a greater impact on the global accuracy.

[0146] 7. Constellation Diagram: In practical communication systems, codeword bits encoded through the channel are mapped to constellation points for subsequent channel transmission; this process is also called modulation. The receiving end also needs to calculate the soft value of each bit based on the constellation diagram and the received constellation points; this process is called demodulation. The mapping from bit flow to constellation symbols (also called constellation points) is generally represented visually by a constellation diagram. Commonly used constellation diagrams include Gray constellation diagrams and hierarchical constellation diagrams. In a constellation diagram, each constellation symbol (constellation point) can carry a certain number of bits. The bits carried by each constellation point can be called constellation bits. In a constellation diagram, the degree of protection for different types of constellation bits may vary, or in other words, the reliability of different constellation bits may differ.

[0147] For example, Figure 4 This is a schematic diagram of the 16QAM layered constellation diagram provided in the embodiments of this application.

[0148] like Figure 4 As shown, the constellation diagram has 16 selectable constellation points, each carrying 4 bits of information. The I-path (the variable on the horizontal axis) and Q-path (the variable on the vertical axis) each carry 2 bits. The constellation bits mapped to the first layer of the bitstream change frequently in the constellation diagram (e.g., for the I-path component, the constellation bits mapped to the first layer of the bitstream are 0101, which changes frequently), resulting in relatively low reliability. The absolute values ​​of the soft values ​​of these constellation bits calculated at the receiver are often small. Conversely, the constellation bits mapped to the second layer of the bitstream change slowly in the constellation diagram (e.g., for the I-path component, the constellation bits mapped to the second layer of the bitstream are 0011, which changes slowly), resulting in relatively high reliability. The absolute values ​​of the soft values ​​of these constellation bits calculated at the receiver are often small.

[0149] Currently, in wireless communication, the transmitting end encodes the control information and directly maps the channel-encoded codewords onto constellation points in the constellation diagram for subsequent channel transmission. In this way, the overall system performance is poor.

[0150] One example is that when using lower-order modulation schemes (such as QPSK), the degree of protection for the various constellation bits carried by each constellation point in a constellation diagram is relatively similar, or in other words, the reliability differences between different constellation bits are small. However, when using higher-order modulation schemes (such as 16QAM, 64QAM, etc.), the reliability differences of the various constellation bits carried by the same constellation point are significant. If the channel-coded codewords are directly mapped to constellation points, it may affect the reliability of decoding, and thus affect system performance.

[0151] like Figure 3 As shown, assuming c0, c4, c2, and c6 are mapped to constellation bits with different reliability, the receiver calculates that the absolute values ​​of the soft values ​​of these constellation bits are different. Therefore, the result after merging based on the merging algorithm is the soft value with the smallest absolute value. Similarly, assuming c1, c3, c5, and c7 are mapped to constellation bits with different reliability, the result after merging based on the merging algorithm is also the soft value with the smallest absolute value. In this way, the merged results are all soft values ​​with small absolute values, and the reliability is low, which affects the system performance.

[0152] Another example is that if c0, c4, c2, and c6 are mapped to constellation bits with the same reliability, and c1, c3, c5, and c7 are mapped to constellation bits with a different reliability, then the absolute values ​​of the combined soft values ​​at the receiver will vary greatly, resulting in a large dynamic range. In scenarios where precision is limited, the soft values ​​may even be unable to be fully represented, leading to significant performance loss.

[0153] It is easy to understand that different interleaving patterns will cause different codeword bits to map to different constellation bits, thus having a significant impact on the final performance. In view of this, this application provides a communication method that adjusts the order of bits in the coded bit sequence so that two elements with indices x and x+Z in the transposed bit sequence correspond to indices in the original bit sequence that belong to the same t-dimensional subspace coset, where Z belongs to {1,…,2}. t -1}, or, Z belongs to {-1,-2,…,1-2}. tWhen Z = nQ, it is beneficial to ensure that bits whose indices belong to the same t-dimensional subspace coset are mapped to constellation bits with different reliability. This results in the absolute values ​​of the soft values ​​after merging by the receiver using the merging algorithm being mostly small, making it suitable for scenarios with limited accuracy. When Z = nQ, it is beneficial to ensure that bits whose indices belong to the same t-dimensional subspace coset are mapped to constellation bits with the same reliability. This allows the receiver to merge larger soft values ​​with larger soft values ​​and smaller soft values ​​with smaller soft values, thus retaining the larger soft values ​​after merging, thereby improving reliability and system performance. This is suitable for scenarios where accuracy is not limited.

[0154] The communication method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments shown below describe the method from the perspective of the interaction between a first communication device and a second communication device, but should not constitute any limitation on the subject executing the method. The method provided in the embodiments of this application can be executed as long as a program containing the code of the method provided in the embodiments of this application is run. For example, the first communication device can also be replaced by a component (e.g., a chip, a chip system, etc.) configured in the first communication device, or other functional modules capable of calling and executing programs; similarly, the second communication device can be replaced by a component (e.g., a chip, a chip system, etc.) configured in the second communication device, or other functional modules capable of calling and executing programs. The embodiments of this application do not limit this.

[0155] Figure 5 This is a schematic flowchart of the communication method 500 provided in an embodiment of this application. The above method 500 can be applied, for example, to... Figure 1 or Figure 2 The communication system shown is described below. The steps of method 500 are explained in detail below.

[0156] In step 510, the first communication device acquires a first bit sequence, which includes a bit with index a and a bit with index b, where a and b belong to the same coset of the subspace.

[0157] The first communication device mentioned above can be considered as the information sending end, or the information encoding end. The first communication device can be a terminal (such as...). Figure 1 The terminal 120 shown can also be an access network device (such as...). Figure 1 The access network device 110 shown in the figure is not limited in this application.

[0158] It should be noted that in this application, the index of a bit in the bit sequence is used to indicate the position of the bit in the bit sequence. This index can also be called a position index, number, or sequence number, etc., and this application does not limit its name. For example, the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7}, where c0 represents the bit corresponding to index 0, c1 represents the bit corresponding to index 1, c2 represents the bit corresponding to index 2, c3 represents the bit corresponding to index 3, c4 represents the bit corresponding to index 4, and so on, and will not be listed here. It is understood that the above example of indices starting from 0 is merely an example and should not constitute any limitation on this application. For example, indices can also start from 1, etc.

[0159] The elements a and b mentioned above belong to the same coset of a subspace with dimension t, where t ≥ 1 and t is an integer. Based on the properties of cosets described above, if the subspace has dimension t, then a coset of this subspace also has dimension t. That is, a coset of this subspace contains 2^t elements. t The above a and b belong to the same coset of a subspace with dimension t. This can also be simply referred to as a and b belonging to the same t-dimensional subspace coset.

[0160] It can be understood that the aforementioned subspace can be a subspace of the full space composed of all indices in the first bit sequence.

[0161] For example, the first bit sequence mentioned above is {c0,c1,c2,c3,c4,c5,c6,c7}, with indices from 0 to 7. Indices 0 to 7 can form the full space V. The one-dimensional subspace of this full space V is {0,4}, and its corresponding cosets include {0,4}, {1,5}, {2,6}, and {3,7}. For example, the first bit sequence mentioned above includes bit c0 with index 0 and bit c4 with index 4, that is, a = 0, b = 4, and a and b belong to the same coset {0,4} of the one-dimensional subspace {0,4}. Similarly, the first bit sequence mentioned above includes bit c1 with index 1 and bit c5 with index 5, that is, a = 1, b = 5, and a and b belong to the same coset {1,5} of the one-dimensional subspace {0,4}. These are not listed individually here. The 2D subspace {0,4,2,6} of the full space V has cosets {0,4,2,6} and {1,5,3,7}. For example, the first bit sequence includes bit c0 with index 0 and bit c4 with index 4, meaning a = 0, b = 4, and a and b belong to the same coset {0,4,2,6} of the 2D subspace {0,4,2,6}. Similarly, the first bit sequence includes bit c1 with index 1 and bit c5 with index 5, meaning a = 1, b = 5, and a and b belong to the same coset {1,5,3,7} of the 2D subspace {0,4,2,6}.

[0162] Optionally, the first bit sequence is an encoded bit sequence or an encoded bit sequence after self-isomorphic permutation.

[0163] One possible design is that the first communication device directly performs step 520 on the encoded bit sequence (i.e., the encoded bit sequence), that is, directly interleaving the encoded bit sequence.

[0164] Another possible design is that after the first communication device encodes the encoded bit sequence, it performs an auto-isomorphic permutation on the encoded bit sequence to obtain an auto-isomorphic permuted encoded bit sequence, and then performs step 520 on the sequence, that is, interleaving the auto-isomorphic permuted encoded bit sequence.

[0165] In summary, this application does not limit whether the first communication device performs automorphic permutation on the coded bit sequence. The definition of automorphic permutation can be found above and will not be repeated here.

[0166] In step 520, the first communication device interleaves the first bit sequence to obtain a second bit sequence, which includes a bit with index x and a bit with index x+Z. The bit with index a in the first bit sequence corresponds to the bit with index x in the second bit sequence, and the bit with index b in the first bit sequence corresponds to the bit with index x+Z in the second bit sequence.

[0167] Where x is an integer greater than or equal to 0, and x is less than or equal to the maximum value of the index in the second bit sequence mentioned above. Z can be a positive integer or a negative integer. Correspondingly, when Z = nQ, nQ can be a positive integer or a negative integer. In other words, the above n can be a positive integer or a negative integer. For example, Z = Q or Z = -Q; or for example, Z = 2Q or Z = -2Q, etc.

[0168] Correspondingly, another case is that Z belongs to {1,…,2}. t -1} or Z belongs to {-1,-2,…,1-2} t}

[0169] The above Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the second bit sequence mentioned above. The above Q indicating the modulation order can also be understood as Q being determined based on the modulation order. Q represents the number of constellation bits carried by each constellation point, and Q satisfies the following relationship with the modulation order: Q = log₂(modulation order). For example, for 16QAM, Q = log₂16 = 4; and for 64QAM, Q = log₂64 = 6.

[0170] The first bit sequence contains the same bits as the second bit sequence, but the order of the bits is different, or in other words, the position indices of at least two bits are different.

[0171] The bit with index 'a' in the first bit sequence corresponds to the bit with index 'x' in the second bit sequence. This can be understood as the same bit, where the bit with index 'a' in the first bit sequence and the bit with index 'x' in the second bit sequence are simply different bits. The bit has index 'a' in the first bit sequence and index 'x' in the second bit sequence.

[0172] Similarly, the bit with index b in the first bit sequence corresponds to the bit with index x+Z in the second bit sequence. This can be understood as the bit with index b in the first bit sequence and the bit with index x+Z in the second bit sequence being the same bit, except that the index of this bit in the first bit sequence is b and the index of this bit in the second bit sequence is x+Z.

[0173] For example, if the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7} and the second bit sequence is {c0,c4,c2,c6,c1,c5,c3,c7}, taking a=0 and b=4 as an example, the bit c0 with index 0 in the first bit sequence has an index of 0 in the second bit sequence (i.e., x=0), and the bit c4 with index 4 in the first bit sequence has an index of 1 in the second bit sequence (i.e., x+{1,…,2}). t -1}=0+1=1). Alternatively, the second bit sequence above is {c0,c2,c4,c6,c1,c5,c3,c7}, and the index of bit c4, which is 4 in the first bit sequence, can also be 2 in the second bit sequence (that is, x+{1,…,2}). t -1}=0+2=2). Alternatively, if the second bit sequence is {c0,c2,c6,c4,c1,c5,c3,c7}, then the bit c4 with index 4 in the first bit sequence can also have an index of 2 in the second bit sequence (i.e., x+{1,…,2}). t -1}=0+(2 t -1)=0+3=3). These will not be listed individually here.

[0174] Another example is that the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7}, and the second bit sequence is {c0,c2,c1,c3,c4,c6,c5,c7}. Taking a=0 and b=4 as an example, the bit c0 with index 0 in the first bit sequence has an index of 0 in the second bit sequence (that is, x=0), and the bit c4 with index 4 in the first bit sequence has an index of 4 in the second bit sequence (that is, x+nQ=0+4=4).

[0175] In step 530, the first communication device modulates the second bit sequence to obtain a modulation symbol.

[0176] This application does not limit the modulation order of the above modulation. For example, the first communication device can use 16QAM modulation to modulate the second bit sequence. In other words, the first communication device can map the bits in the second bit sequence to constellation points in the constellation diagram. Each constellation point can carry 4 bits. That is, the first communication device can continuously read 4 bits and map them to a constellation point.

[0177] For example, the second bit sequence mentioned above is {c0,c4,c2,c6,c1,c5,c3,c7}. The first communication device can map c0, c4, c2, and c6 to different constellation bits of one constellation point, and map c1, c5, c3, and c7 to different constellation bits of another constellation point. In this way, the protection levels of c0, c4, c2, and c6 are different, and the protection levels of c1, c5, c3, and c7 are also different. In other words, for the decoding end, the absolute values ​​of the soft values ​​corresponding to the above bits are different. Therefore, after the decoding end performs soft value merging during the decoding process, it obtains mostly soft values ​​with smaller absolute values, which improves the overall performance of the system in some scenarios. For example, the above implementation can be applied to scenarios with limited precision, such as when the terminal is in power-saving mode. In scenarios where precision is limited, if the absolute values ​​of soft values ​​vary greatly, the numerical range is large. Due to the limited precision, there may be situations where soft values ​​cannot be fully represented, which may cause performance loss. However, through the above implementation, the soft values ​​obtained after merging are all soft values ​​with smaller absolute values, thereby improving the overall performance of the system.

[0178] For example, if the second bit sequence is {c0,c2,c1,c3,c4,c6,c5,c7}, the first communication device can map c0, c2, c1, and c3 to different constellation bits of one constellation point, and map c4, c6, c5, and c7 to different constellation bits of another constellation point. This ensures that c0 and c4 have the same level of protection, c2 and c6 have the same level of protection, c1 and c5 have the same level of protection, and c3 and c7 have the same level of protection. In other words, for the decoding end, the absolute values ​​of the soft values ​​corresponding to the bits with the same level of protection are the same. Therefore, after the decoding end performs soft value merging during the decoding process, the absolute values ​​of the soft values ​​obtained vary, allowing the soft values ​​with larger absolute values ​​to be retained, thereby improving decoding reliability and performance. This implementation can be applied to scenarios where precision is not limited, such as terminals not in power-saving mode.

[0179] In step 540, the first communication device sends modulation symbols to the second communication device. Correspondingly, the second communication device receives the modulation symbols.

[0180] The second communication device can be viewed as an information receiver or an information decoder. The second communication device can be an access network device (such as...). Figure 1 The access network device 110 shown can also be a terminal (such as...). Figure 1 The present application does not limit the terminal 120 shown in the figure.

[0181] In step 550, the second communication device demodulates the received modulation symbols to obtain a first sequence, which includes an element with index x and an element with index x+Z.

[0182] Where x is greater than or equal to 0, and x is less than or equal to the maximum value of the index in the first sequence, and x is an integer. Z can be a positive integer or a negative integer.

[0183] The elements in the first sequence mentioned above can be LLRs or probability values, and this application does not limit them.

[0184] The definition of the index of the above elements is similar to the definition of the index of bits. The index of an element in the first sequence indicates the position of the element in the first sequence. This index can also be called a position index, number, or sequence number, etc., and this application does not limit its name. For example, the first sequence is {L0,L1,L2,L3,L4,L5,L6,L7}, where L0 represents the element corresponding to index 0, L1 represents the element corresponding to index 1, L2 represents the element corresponding to index 2, L3 represents the element corresponding to index 3, L4 represents the element corresponding to index 4, and so on, and will not be listed here. It is understood that the index starting from 0 in the above example is only an example and should not constitute any limitation on this application. For example, the index can also start from 1, etc. The definitions of the indexes of elements in the second and third sequences described below are similar and will not be repeated below.

[0185] In step 560, the second communication device deinterleaves the first sequence to obtain a second sequence, which includes an element with index a and an element with index b. The element with index a in the second sequence corresponds to the element with index x in the first sequence, and the element with index b in the second sequence corresponds to the element with index x+Z in the first sequence. a and b belong to the same coset of the subspace.

[0186] Where Z belongs to {1,…,2} t -1}, or, Z belongs to {-1,-2,…,1-2}. t}, or, Z = nQ, the dimension of the above subspace is t-dimensional, t≥1, t is an integer, Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the above first sequence.

[0187] For explanations of subspaces, cosets, Q, and nQ, please refer to the encoding documentation; they will not be repeated here.

[0188] The element with index 'a' in the second sequence corresponds to the element with index 'x' in the first sequence. This can be understood as the element with index 'a' in the second sequence and the element with index 'x' in the first sequence being the same element, except that the element has index 'a' in the second sequence and index 'x' in the first sequence.

[0189] Similarly, the element with index b in the second sequence corresponds to the element with index x+Z in the first sequence. This can be understood as the element with index b in the second sequence and the element with index x+Z in the first sequence being the same element, except that the element has index b in the second sequence and index x+Z in the first sequence.

[0190] It is understandable that the above deinterleaving can be seen as the inverse operation of interleaving. After the second communication device obtains the first sequence, it deinterleaves it to obtain the second sequence. The second communication device can then decode the second sequence to obtain information bits.

[0191] As can be seen from the decoding process described above, when the second communication device performs soft-value merging during the decoding process, the soft values ​​of bits corresponding to the indices of the same subspace coset in the first bit sequence can be merged. For example... Figure 3 As shown, L0, L4, L2, and L6 were merged, and L1, L5, L3, and L7 were merged.

[0192] In the above method 500, one case is that Z belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t In other words, the bits corresponding to the indices of the same subspace coset in the first bit sequence can be sequentially arranged in the second bit sequence. Sequential arrangement means that bits corresponding to the indices of other subspace cosets are not added between these bits. Thus, when mapping the bits in the second bit sequence to constellation points, bits belonging to the same subspace coset can be mapped to constellation bits of different reliability. Therefore, after soft value merging during decoding, the decoder obtains mostly soft values ​​with smaller absolute values, thereby improving the overall system performance in certain scenarios. For example, the above implementation can be applied to precision-constrained scenarios, such as when the terminal is in power-saving mode. In precision-constrained scenarios, if the absolute values ​​of the soft values ​​vary greatly, the numerical range is large. Due to precision constraints, soft values ​​may not be fully represented, potentially causing performance loss. The above implementation ensures that the soft value merging results in soft values ​​with smaller absolute values, thereby improving the overall system performance.

[0193] Another scenario is where Z = nQ. This means that the bits corresponding to the indices of cosets belonging to the same subspace in the first bit sequence are spaced nQ-1 apart in the second bit sequence. Thus, when mapping the bits in the second bit sequence to constellation points, bits belonging to the same subspace coset can be mapped to constellation bits with the same reliability. Consequently, the absolute values ​​of the soft values ​​obtained after soft value merging during decoding vary, allowing the retention of soft values ​​with larger absolute values, thereby improving decoding reliability and performance. This implementation can be applied, for example, to scenarios where precision is not limited, such as terminals not in power-saving mode.

[0194] In the above scheme, the first bit sequence contains two bits belonging to the same coset within the same subspace that satisfy the aforementioned characteristic, such as indices x and x+Z in the second bit sequence. In one possible implementation, for the encoder, any two bits in the first bit sequence have indices a and b; that is, the bits corresponding to the indices of any coset within the aforementioned subspace satisfy the aforementioned characteristic. For the decoder, any two bits in the second sequence have indices a and b. The following example illustrates this using the encoder.

[0195] In this way, in scenarios where precision is limited, the soft values ​​obtained by the decoder after soft value merging during the decoding process are all soft values ​​with smaller absolute values, thereby improving the overall performance of the system; in scenarios where precision is not limited, the absolute values ​​of the soft values ​​obtained by the decoder after soft value merging during the decoding process vary in size, thus allowing the soft values ​​with larger absolute values ​​to be retained, thereby improving decoding reliability and thus decoding performance.

[0196] For example, the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7}, and the second bit sequence is {c0,c4,c2,c6,c1,c5,c3,c7}. Indices 0, 2, 4, and 6 belong to the same subspace coset, and indices 1, 3, 5, and 7 belong to the same subspace coset. It can be seen that for any two bits corresponding to indices 0, 2, 4, and 6, the above characteristics are satisfied, where Z belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t The above characteristics are satisfied for any two bits corresponding to indices 1, 3, 5, and 7.

[0197] Another example is the first bit sequence {c0,c1,c2,c3,c4,c5,c6,c7} and the second bit sequence {c0,c2,c1,c3,c4,c6,c5,c7}. Indices 0, 2, 4, and 6 belong to the same subspace coset, and indices 1, 3, 5, and 7 belong to the same subspace coset. It can be seen that any two bits corresponding to indices 0, 2, 4, and 6 satisfy the above characteristics, where Z = nQ and Q = 4. Any two bits corresponding to indices 1, 3, 5, and 7 satisfy the above characteristics.

[0198] In another possible implementation, for the encoding end, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the subspace in the first bit sequence. For the decoding end, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the subspace in the second sequence. That is, any two bits corresponding to the indices of one or more subspace cosets satisfy the above characteristics. The following example uses the encoding end for illustration.

[0199] For example, the first bit sequence is {c0,c1,c2,c3,c4,c5}, and the second bit sequence is {c0,c4,c1,c5,c2,c3}. Indices 0 and 4 belong to the same subspace coset, and indices 1 and 5 belong to the same subspace coset. It can be seen that the two bits corresponding to indices 0 and 4 satisfy the above characteristics, where Z belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t The two bits corresponding to indices 1 and 5 satisfy the above characteristics, while the bits corresponding to indices 2 and 3 do not satisfy the above characteristics.

[0200] Optionally, the interleaving of the first bit sequence to obtain the second bit sequence can be achieved using any of the following methods.

[0201] Implementation Method 1: A first communication device interleaves a first bit sequence based on an interleaved sequence to obtain a second bit sequence. The interleaved sequence indicates the correspondence between index x in the second bit sequence and index a in the first bit sequence, as well as the correspondence between index x+Z in the second bit sequence and index b in the first bit sequence. Correspondingly, a second communication device deinterleaves the first sequence based on the interleaved sequence to obtain a second sequence. This interleaved sequence indicates the correspondence between index x in the first sequence and index a in the second sequence, as well as the correspondence between index x+Z in the first sequence and index b in the second sequence.

[0202] For example, the interleaved sequence is {0,2,1,3,4,6,5,7}, where 0 indicates that the element with index 0 in the interleaved sequence is the same as the element with index 0 in the original sequence (the sequence before interleaving); 2 indicates that the element with index 1 in the interleaved sequence is the same as the element with index 2 in the original sequence; 1 indicates that the element with index 2 in the interleaved sequence is the same as the element with index 1 in the original sequence; 3 indicates that the element with index 3 in the interleaved sequence is the same as the element with index 3 in the original sequence; 4 indicates that the element with index 4 in the interleaved sequence is the same as the element with index 4 in the original sequence; 6 indicates that the element with index 5 in the interleaved sequence is the same as the element with index 6 in the original sequence; 5 indicates that the element with index 6 in the interleaved sequence is the same as the element with index 5 in the original sequence; and 7 indicates that the element with index 7 in the interleaved sequence is the same as the element with index 7 in the original sequence. For example, the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7}. Based on the above interleaving sequence, the first bit sequence is interleaved to obtain the second bit sequence {c0,c2,c1,c3,c4,c6,c5,c7}.

[0203] For the second communication device, the second communication device can de-interleave the first sequence based on the interleaved sequence to obtain the second sequence. The interleaved sequence is used to indicate the correspondence between index x in the first sequence and index a in the second sequence, as well as the correspondence between index x+Z in the first sequence and index b in the second sequence.

[0204] The above deinterleaving can be seen as the inverse operation of interleaving. For example, if the interleaving sequence is {0,2,1,3,4,6,5,7}, then the second communication device can, based on the above interleaving sequence, move the element with index 1 in the first sequence to the position of index 2, move the element with index 2 in the first sequence to the position of index 1, move the element with index 5 in the first sequence to the position of index 6, and move the element with index 6 in the first sequence to the position of index 5, thereby obtaining the second sequence.

[0205] Implementation Method 2: When Z = nQ, perform a first interleaving operation on the first bit sequence to obtain a third bit sequence. This third bit sequence includes a bit at index y and a bit at index y+M. The bit at index y in the third bit sequence corresponds to the bit at index a in the first bit sequence, and the bit at index y+M in the third bit sequence corresponds to the bit at index b in the first bit sequence. Here, M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t}; Perform a second interleaving operation on the third bit sequence to obtain the second bit sequence.

[0206] Through the first interleaving operation, the bits corresponding to the indices of the same t-dimensional subspace coset in the first bit sequence can be arranged in order. Then, through the second interleaving operation, the bits corresponding to the indices of the same t-dimensional subspace coset are spaced nQ-1 apart. In this way, when the bits in the second bit sequence are mapped to constellation points, the bits corresponding to the indices of the same t-dimensional subspace coset can be mapped to constellation bits with the same reliability, thereby improving the decoding reliability.

[0207] One possible implementation of the first interleaving operation is that it includes t interleaving operations, where the i-th interleaving operation is performed on the bit sequence obtained after the (i-1)-th interleaving operation, and the bit sequence after the (i-1)-th interleaving operation includes... The i-th interleaving operation for each sub-block includes: ... The bit sequences in each sub-block undergo a row-by-row interleaving operation, or a column-by-column interleaving operation, where i = 1, 2, ..., t, and X is the length of the first bit sequence. M-1 ≤X≤2 M .

[0208] For example, when t=2, the first interleaving operation includes: interleaving the first bit sequence including... The bit sequence in each sub-block is interleaved by row-to-row / column arrangement. The second interleaving operation includes: performing a row-to-row / column interleaving operation on the bit sequence obtained after the first interleaving operation.

[0209] For example, such as Figure 6 As shown, t=2, the first bit sequence is {c0,c1,c2,c3,c4,c5,c6,c7}, which includes There are two sub-blocks, one of which is {c0,c1,c2,c3} and the other is {c4,c5,c6,c7}. The first interleaving operation includes performing row-by-row interleaving on these two sub-blocks respectively. For example, the sub-block {c0,c1,c2,c3} is written row by row into the interleaver (taking interleaving with 2 rows as an example), and then read out column by column to obtain {c0,c2,c1,c3}. The sub-block {c4,c5,c6,c7} is written row by column into the interleaver. In the weaver (taking interleaving with 2 rows as an example), and read out column by column, we get {c4,c6,c5,c7}. Therefore, the sequence obtained after the first interleaving is {c0,c2,c1,c3,c4,c6,c5,c7}. The second interleaving operation includes performing a row-by-row interleaving operation (taking interleaving with 2 rows as an example) on the bit sequence obtained after the first interleaving operation, resulting in {c0,c4,c2,c6,c1,c5,c3,c7}.

[0210] Optionally, when the length of the first bit sequence is not a power of 2, for The length of each sub-block is not 2 M-t+i The interleaving operations for sub-blocks include: when writing by row, the last row includes empty elements, and when reading by column, empty elements are skipped; or, when writing by column, the last column includes empty elements, and when reading by row, empty elements are skipped.

[0211] For example, such as Figure 7 As shown, the sub-block is {c0,c1,c2,c3,c4,c5}. This sub-block is written to the interleaver in rows (with 2 rows and 2 columns). M-t+i-1 In the example of interleaving, the interleaver includes empty elements. When read out column by column, these empty elements are skipped, resulting in the sequence {c0,c4,c1,c5,c2,c3}.

[0212] Through the first interleaving operation, the bits corresponding to the indices of the same t-dimensional subspace coset have been sequentially arranged. During modulation, typically Q bits are continuously taken from the bit stream and mapped to a constellation point. Therefore, the second interleaving operation further maps the bits corresponding to the indices of the same subspace coset to constellation bits with the same reliability. The aforementioned second interleaving operation includes interleaving operations with Q rows or Q columns.

[0213] For example, such as Figure 8 As shown, an interleaving operation with Q rows is performed on {c0,c4,c2,c6,c1,c5,c3,c7} to obtain {c0,c2,c1,c3,c4,c6,c5,c7}. In this way, when mapping this sequence, the bits corresponding to the indices of the cosets belonging to the same subspace can be mapped to constellation bits with the same reliability.

[0214] Corresponding to the decoder, it receives the soft value corresponding to each bit after demodulation. It needs to perform a deinterleaving operation to restore the order of the soft values ​​back to the state corresponding to the bits input to the interleaver at the encoder. The deinterleaving operation can be understood as the inverse process of the interleaving operation. Corresponding to the second implementation method described above, the decoder deinterleaves the first sequence to obtain the second sequence, including: performing a first deinterleaving operation on the first sequence to obtain a third sequence. The third sequence includes bits with index y and bits with index y+M. The bit with index y in the third sequence corresponds to the bit with index a in the second sequence, and the bit with index y+M in the third sequence corresponds to the bit with index b in the second sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} tThe second deinterleaving operation is performed on the third sequence to obtain the second sequence. The first deinterleaving operation can be understood as the inverse of the second deinterleaving operation, and vice versa.

[0215] The first deinterleaving operation described above corresponds to the second interleaving operation described above. When the second interleaving operation uses an interleaving operation with Q rows in a row-to-column configuration, the first deinterleaving operation described above uses an interleaving operation with Q rows in a column configuration. When the second interleaving operation uses an interleaving operation with Q columns in a column configuration, the first deinterleaving operation described above uses an interleaving operation with Q columns in a row-to-column configuration.

[0216] The second deinterleaving operation corresponds to the first deinterleaving operation; that is, for the input soft-value sequence after the first deinterleaving operation, the inverse operation of the first deinterleaving operation is performed. The second deinterleaving operation involves t deinterleaving operations. The i-th deinterleaving operation in these t deinterleaving operations deinterleaves the sequence obtained after the (i-1)-th deinterleaving operation. The sequence after the (i-1)-th deinterleaving operation includes... For each sub-block, the i-th deinterleaving operation includes: ... The sequence in each sub-block undergoes column-wise deinterleaving (corresponding to row-wise interleaving at the encoding end), or row-wise deinterleaving (corresponding to column-wise interleaving at the encoding end), where i = 1, 2, ..., t, and X is the length of the first sequence. M-1 ≤X≤2 M .

[0217] Optionally, when the length of the first sequence is not a power of 2, for The length of each sub-block is not 2 M-t+i The interleaving operation for sub-blocks includes: 2 rows and 2 columns. M-i+1 The rows and columns are interwoven, and in the interleaver, following the order of traversing row by row from left to right, the last 2 M-i+1 -L positions are the positions where elements cannot be placed. Here, L is the actual length of the above sub-block. The L soft values ​​of the above sub-block are written column by column into the row-column deinterleaver. When an empty position is encountered during writing, it needs to be skipped. Then the sequence is read out row by row from the deinterleaver.

[0218] The above text provided a detailed explanation of the case where Z = nQ. The following text will discuss the case where Z belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t The following will explain the situation.

[0219] When Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} tWhen interleaving the first bit sequence to obtain the second bit sequence, the above includes: performing a first interleaving operation on the first bit sequence to obtain the second bit sequence.

[0220] By performing the first interleaving operation, the bits corresponding to the indices of the cosets of the same t-dimensional subspace in the first bit sequence can be arranged in order. In this way, when the bits in the second bit sequence are mapped to constellation points, the bits corresponding to the indices of the cosets of the same t-dimensional subspace in the first bit sequence can be mapped to constellation bits with different reliability. As a result, the soft values ​​obtained by the decoder after performing soft value merging during the decoding process are mostly soft values ​​with smaller absolute values, which can improve the overall performance of the system in some scenarios.

[0221] For a detailed explanation of the first interleaving operation mentioned above, please refer to the detailed explanation of the case where Z = nQ above, which will not be repeated here.

[0222] For the decoding end, Z corresponds to {1,…,2} in the second implementation method described above. t -1} or {-1,-2,…,1-2} t In the case of [missing information], the decoder deinterleaves the first sequence to obtain the second sequence, including: performing a first deinterleaving operation on the first sequence to obtain the second sequence. This first deinterleaving operation can be regarded as the inverse operation of the first interleaving operation in the encoder. For a detailed explanation of the above first deinterleaving operation, please refer to the detailed introduction of the second deinterleaving operation above, which will not be repeated here.

[0223] Optionally, t = r or r-1, where r is the order of the RM code.

[0224] like Figure 3 As can be seen, the first decoding node can be an RM(1,0) node, each of which is essentially a 2 from the original soft value. r The result of merging the soft values ​​in a grid pattern. It can be proven that the indices corresponding to these soft values ​​are... A coset of an r-dimensional subspace, where the first decoding node can also be a first-order RM code, such as... Figure 3 The RM(2,1) node in the diagram corresponds to... The first decoder node is an r-1 dimensional subspace coset, therefore t = r or r-1. It can be understood that when the order of the first decoder node is other values, the value of t can also change accordingly. This application does not specifically limit the value of t.

[0225] The methods provided in the embodiments of this application have been described in detail above with reference to the accompanying drawings. The apparatus provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0226] Figure 9This is a schematic block diagram of the communication device 900 provided in the embodiments of this application.

[0227] like Figure 9 As shown, the communication device 900 includes an acquisition module 910, an interleaving module 920, and a modulation module 930.

[0228] In one possible design, the aforementioned device 900 can be used to implement the above. Figure 5 The method embodiment shown may include the function of the first communication device, or the device 900 may include components for implementing the above. Figure 5 In the method embodiment shown, any function or operation of the first communication device can be implemented wholly or partially through software, hardware, firmware, or any combination thereof.

[0229] When device 900 is used to achieve Figure 5 In the method embodiment shown, when the first communication device functions, the acquisition module 910 is used to acquire a first bit sequence, which includes a bit with index a and a bit with index b, where a and b belong to the same coset of a subspace, and the subspace has a dimension of t, where t ≥ 1 and t is an integer; the interleaving module 920 is used to interleave the first bit sequence to obtain a second bit sequence, which includes a bit with index x and a bit with index x+Z. The bit with index a in the first bit sequence corresponds to the bit with index x in the second bit sequence, and the bit with index b in the first bit sequence corresponds to the bit with index x+Z in the second bit sequence, where x is an integer greater than or equal to 0, and Z belongs to {1,…,2}. t -1}, or, Z belongs to {-1,-2,…,1-2}. t}, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the second bit sequence; the modulation module 930 is used to modulate the second bit sequence to obtain the modulation symbol.

[0230] Optionally, any two bits in the first bit sequence described above are indexed as a and indexed as b.

[0231] Optionally, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the aforementioned subspace in the first bit sequence.

[0232] Optionally, the interleaving module 920 is specifically used to interleave the first bit sequence based on the interleaving sequence to obtain the second bit sequence. The interleaving sequence is used to indicate the correspondence between index x in the second bit sequence and index a in the first bit sequence, and the correspondence between index x+Z in the second bit sequence and index b in the first bit sequence.

[0233] Optionally, when Z = nQ, the interleaving module 920 is specifically used to perform a first interleaving operation on the first bit sequence to obtain a third bit sequence. The third bit sequence includes a bit with index y and a bit with index y+M. The bit with index y in the third bit sequence corresponds to the bit with index a in the first bit sequence, and the bit with index y+M in the third bit sequence corresponds to the bit with index b in the first bit sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t}; Perform a second interleaving operation on the third bit sequence to obtain the second bit sequence.

[0234] Optionally, when Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} t In this process, the interleaving module 920 is specifically used to perform a first interleaving operation on the first bit sequence to obtain the second bit sequence.

[0235] Optionally, t = r or r-1, where r is the order of the RM code.

[0236] Optionally, the first bit sequence is an encoded bit sequence or an encoded bit sequence after self-isomorphic permutation.

[0237] Optionally, the sum of any two elements in a t-dimensional subspace S belongs to that t-dimensional subspace S.

[0238] Alternatively, for the entire space V, the set obtained by adding any element v in the entire space V to the elements in the t-dimensional subspace S is a coset of the t-dimensional subspace S.

[0239] Optionally, the above-mentioned device 900 further includes an encoding module 940, which is used to encode the sequence to be encoded to obtain an encoded sequence.

[0240] Optionally, the above-mentioned device 900 further includes a rate matching module 950, which is used to perform rate matching on the encoded sequence.

[0241] Optionally, the device 900 further includes a storage module 960 for storing instructions and / or data.

[0242] Optionally, the device 900 further includes a control module 970, which is responsible for scheduling and control between the various modules.

[0243] Figure 10 This is a schematic block diagram of another communication device 1000 provided in the embodiments of this application.

[0244] like Figure 10As shown, the communication device 1000 includes a demodulation module 1010 and a deinterleaving module 1020.

[0245] In one possible design, the aforementioned device 1000 can be used to implement the above. Figure 5 The method embodiment shown may include the function of the second communication device, or the device 1000 may include components for implementing the above. Figure 5 In the method embodiment shown, any function or operation of the second communication device can be implemented wholly or partially through software, hardware, firmware, or any combination thereof.

[0246] When device 1000 is used to achieve Figure 5 In the method embodiment shown, the function of the second communication device is as follows: the demodulation module 1010 demodulates the received modulation symbols to obtain a first sequence, which includes an element with index x and an element with index x+Z, where x is an integer greater than or equal to 0; the deinterleaving module 1020 deinterleaves the first sequence to obtain a second sequence, which includes an element with index a and an element with index b. The element with index a in the second sequence corresponds to the element with index x in the first sequence, and the element with index b in the second sequence corresponds to the element with index x+Z in the first sequence. a and b belong to the same coset of a subspace, the subspace has a dimension of t, t≥1, t is an integer, and Z belongs to {1,…,2}. t -1}, or, Z belongs to {-1,-2,…,1-2}. t}, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the first sequence.

[0247] Optionally, any two bits in the second sequence described above are indexed as a and indexed as b.

[0248] Optionally, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the aforementioned subspace in the second sequence.

[0249] Optionally, the deinterleaving module 1020 is specifically used to deinterleave the first sequence based on the interleaving sequence to obtain the second sequence, wherein the interleaving sequence is used to indicate the correspondence between index x in the first sequence and index a in the second sequence, and the correspondence between index x+Z in the first sequence and index b in the second sequence.

[0250] Optionally, when Z = nQ, the deinterleaving module 1020 is specifically used to perform a first deinterleaving operation on the first sequence to obtain a third sequence. The third sequence includes bits with index y and bits with index y+M. The bits with index y in the third sequence correspond to the bits with index a in the second sequence, and the bits with index y+M in the third sequence correspond to the bits with index b in the second sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t}; Perform a second deinterleaving operation on the third sequence to obtain the second sequence.

[0251] Optionally, when Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} t Optionally, the deinterleaving module 1020 is specifically used to perform a first interleaving operation on the first sequence to obtain a second sequence.

[0252] Optionally, t = r or r-1, where r is the order of the RM code.

[0253] Optionally, the sum of any two elements in the t-dimensional subspace S belongs to the aforementioned t-dimensional subspace S.

[0254] Optionally, for the entire space V, the set obtained by adding any element v in the entire space V to the elements in the t-dimensional subspace S is a coset of the aforementioned t-dimensional subspace S.

[0255] Optionally, the above-mentioned device 1000 further includes a solution rate matching module 1030, which is used to perform solution rate matching.

[0256] Optionally, the above-mentioned device 1000 further includes a decoding module 1040, which is used to decode the sequence to be decoded to obtain information bits.

[0257] Optionally, the above-mentioned device 1000 further includes a storage module 1050 for storing instructions and / or data.

[0258] Optionally, the above-mentioned device 1000 further includes a control module 1060, which is responsible for scheduling and control between the various modules.

[0259] related Figure 9 and Figure 10 For a more detailed description of each module shown, please refer to [link / reference]. Figure 5 The relevant descriptions in the method embodiments shown are directly obtained and will not be repeated here.

[0260] It should be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0261] Figure 11 This is a schematic block diagram of another communication device 1100 provided in this application embodiment. The device 1100 can be a chip system, or it can be a device configured with a chip system to implement the above-described method embodiments. In this application embodiment, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0262] like Figure 11 As shown, the device 1100 may include a processor 1110, which can be used to execute computer programs or instructions stored in memory to achieve... Figure 5 The steps performed by the first communication device or the steps performed by the second communication device in the method embodiment shown.

[0263] Optionally, the device 1100 further includes a communication interface 1120. The communication interface 1120 can be used to communicate with other devices via a transmission medium, thereby enabling the device 1100 to communicate with other devices. The communication interface 1120 may be, for example, a transceiver, interface, bus, circuit, or a device capable of transmitting and receiving functions. The processor 1110 can utilize the communication interface 1120 to input and output data and to implement… Figure 5 The method described in the illustrated embodiment. Specifically, the device 1100 can be used to implement the functions of the first or second communication device in the above method embodiments.

[0264] Optionally, the device 1100 further includes at least one memory 1130 for storing program instructions and / or data. The memory 1130 is coupled to the processor 1110. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1130. The processor 1110 may execute program instructions stored in the memory 1130. At least one of the at least one memory may be included in the processor.

[0265] It should be understood that the coupling in the embodiments of this application is an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information interaction between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1130. The embodiments of this application do not limit the specific connection medium between the processor 1110, the communication interface 1120, and the memory 1130. The embodiments of this application... Figure 11 The processor 1110, communication interface 1120, and memory 1130 are connected via bus 1140. Bus 1140 is... Figure 11 The connections between other components are shown in bold lines only and are not intended to be limiting. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, Figure 11 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0266] It should be understood that when the communication device 1100 is a chip applied to a terminal, the chip implements the functions of the terminal in the above method embodiments. The terminal chip receives signals from other modules (such as radio frequency modules or antennas) in the terminal, and these signals may be sent to the terminal by network devices; or, the terminal chip sends signals to other modules (such as radio frequency modules or antennas) in the terminal, and these signals may be sent to the network by the terminal.

[0267] When the communication device 1100 is a chip used in a network device, the chip implements the functions of the network device in the above method embodiments. The chip of the network device receives signals from other modules (such as radio frequency modules or antennas) in the network device, and these signals may be sent by the terminal to the network device; or, the chip of the network device sends signals to other modules (such as radio frequency modules or antennas) in the network device, and these signals may be sent by the network device to the terminal.

[0268] It should be noted that when the communication device 1100 is a terminal or network device, the communication interface 1120 can be a transceiver, specifically including a transmitter and a receiver. The transmitter is used to send signals, and the receiver is used to receive signals. When the communication device 1100 is a chip applied to a terminal or network device, the communication interface 1120 can be an input / output circuit, a bus, a module, a pin, or other types of communication interface input / output circuit. The input circuit in the input / output circuit can be used for receiving, and the output interface can be used for sending.

[0269] Figure 12 This is a schematic diagram of the communication chip system architecture provided in the embodiments of this application.

[0270] like Figure 12 As shown, the communication chip system includes downlink processing and uplink processing. Downlink processing includes encoding, modulation, layer mapping, precoding, framing, and inverse fast Fourier transform (IFFT) of Layer 2 data, and finally processing it into an over-the-air signal via an intermediate frequency (IRF) module. Uplink processing includes processing the received signal through IRF to obtain baseband data, and then performing deframing, equalization, de-mapping, demodulation, and decoding via fast Fourier transform (FFT) to complete physical layer signal processing. The method provided in this application is mainly applicable to the encoding and decoding modules in the aforementioned communication system architecture. For example, Figure 5 In the method shown, step 530 can be specifically executed by the modulation module, and step 550 can be specifically executed by the demodulation module.

[0271] This application also provides a computer program product, which includes a computer program (also referred to as code or instructions) that, when executed, can achieve... Figure 5 The method described in the illustrated embodiment.

[0272] This application also provides a computer-readable storage medium storing a computer program (also referred to as code or instructions). When the computer program is executed, it can achieve... Figure 5 The method described in the illustrated embodiment.

[0273] It should be understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0274] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0275] The terms "unit," "module," etc., used in this specification can be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. In the embodiments of this application, "unit" and "module" have the same meaning and can be used interchangeably.

[0276] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. In the several embodiments provided in this application, it should be understood that the disclosed apparatus, devices, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0277] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0278] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0279] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0280] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the technology, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, include: Obtain a first bit sequence, which includes a bit with index a and a bit with index b, where a and b belong to the same coset of a subspace, and the subspace has a dimension of t, where t ≥ 1 and t is an integer. The first bit sequence is interleaved to obtain a second bit sequence, which includes a bit at index x and a bit at index x+Z. The bit at index a in the first bit sequence corresponds to the bit at index x in the second bit sequence, and the bit at index b in the first bit sequence corresponds to the bit at index x+Z in the second bit sequence. Here, x is an integer greater than or equal to 0, and Z belongs to {1,…,2}. t -1}, or, Z belongs to {-1,-2,…,1-2}. t }, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the second bit sequence; The second bit sequence is modulated to obtain a modulation symbol.

2. The method as described in claim 1, characterized in that, The indices of any two bits in the first bit sequence are a and b.

3. The method as described in claim 2, characterized in that, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the subspace in the first bit sequence.

4. The method according to any one of claims 1 to 3, characterized in that, The step of interleaving the first bit sequence to obtain the second bit sequence includes: Based on the interleaving sequence, the first bit sequence is interleaved to obtain the second bit sequence. The interleaving sequence is used to indicate the correspondence between index x in the second bit sequence and index a in the first bit sequence, and the correspondence between index x+Z in the second bit sequence and index b in the first bit sequence.

5. The method according to any one of claims 1 to 3, characterized in that, When Z = nQ, the step of interleaving the first bit sequence to obtain the second bit sequence includes: A first interleaving operation is performed on the first bit sequence to obtain a third bit sequence. The third bit sequence includes a bit with index y and a bit with index y+M. The bit with index y in the third bit sequence corresponds to the bit with index a in the first bit sequence, and the bit with index y+M in the third bit sequence corresponds to the bit with index b in the first bit sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t }; The third bit sequence is subjected to a second interleaving operation to obtain the second bit sequence.

6. The method according to any one of claims 1 to 3, characterized in that, When Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} t When interleaving the first bit sequence to obtain the second bit sequence, the process includes: The first bit sequence is subjected to a first interleaving operation to obtain the second bit sequence.

7. The method according to any one of claims 1 to 6, characterized in that, t = r or r-1, where r is the order of the Reid-Muller RM code.

8. The method according to any one of claims 1 to 7, characterized in that, The first bit sequence is an encoded bit sequence or an encoded bit sequence after self-isomorphic permutation.

9. The method according to any one of claims 1 to 8, characterized in that, The sum of any two elements in a t-dimensional subspace S belongs to the t-dimensional subspace S.

10. The method according to any one of claims 1 to 9, characterized in that, For a full space V, the set obtained by adding any element v in the full space V to the elements in the t-dimensional subspace S is a coset of the t-dimensional subspace S.

11. A communication method, characterized in that, include: The received modulation symbols are demodulated to obtain a first sequence, which includes an element with index x and an element with index x+Z, where x is an integer greater than or equal to 0. De-interleaving the first sequence yields a second sequence, which includes an element with index 'a' and an element with index 'b'. The element with index 'a' in the second sequence corresponds to the element with index 'x' in the first sequence, and the element with index 'b' in the second sequence corresponds to the element with index 'x+Z' in the first sequence. 'a' and 'b' belong to the same coset of a subspace, where the subspace has dimension 't', t ≥ 1, and t is an integer. Z belongs to {1, ..., 2}. t -1}, or, Z belongs to {-1,-2,…,1-2}. t }, or, Z = nQ, where Q indicates the modulation order, and nQ is less than or equal to the maximum value of the index in the first sequence.

12. The method as described in claim 11, characterized in that, The indices of any two bits in the second sequence are a and b.

13. The method as described in claim 12, characterized in that, a and b are the indices of any two bits corresponding to the indices of at least one coset belonging to the subspace in the second sequence.

14. The method according to any one of claims 11 to 13, characterized in that, The step of deinterleaving the first sequence to obtain the second sequence includes: Based on the interleaved sequence, the first sequence is de-interleaved to obtain the second sequence. The interleaved sequence is used to indicate the correspondence between index x in the first sequence and index a in the second sequence, as well as the correspondence between index x+Z in the first sequence and index b in the second sequence.

15. The method according to any one of claims 11 to 13, characterized in that, When Z = nQ, the step of deinterleaving the first sequence to obtain the second sequence includes: Perform a first deinterleaving operation on the first sequence to obtain a third sequence. The third sequence includes bits with index y and bits with index y+M. The bits with index y in the third sequence correspond to the bits with index a in the second sequence, and the bits with index y+M in the third sequence correspond to the bits with index b in the second sequence, where M belongs to {1,…,2}. t -1} or {-1,-2,…,1-2} t }; The third sequence is subjected to a second deinterleaving operation to obtain the second sequence.

16. The method according to any one of claims 11 to 13, characterized in that, When Z belongs to {1,…,2} t -1} or {-1,-2,…,1-2} t When the first sequence is de-interleaved to obtain the second sequence, the process includes: The first sequence is subjected to a first interleaving operation to obtain the second sequence.

17. The method according to any one of claims 11 to 16, characterized in that, t = r or r-1, where r is the order of the Reid-Muller RM code.

18. The method according to any one of claims 11 to 17, characterized in that, The sum of any two elements in a t-dimensional subspace S belongs to the t-dimensional subspace S.

19. The method according to any one of claims 11 to 18, characterized in that, For a full space V, the set obtained by adding any element v in the full space V to the elements in the t-dimensional subspace S is a coset of the t-dimensional subspace S.

20. A communication device, characterized in that, include: A module for performing the method as described in any one of claims 1 to 10, or the method as described in any one of claims 11 to 19.

21. A communication device, characterized in that, include: A processor, when invoked from a computer program in memory, causes the apparatus to perform the method as described in any one of claims 1 to 10, or the method as described in any one of claims 11 to 19.

22. A computer-readable storage medium, characterized in that, Used to store computer programs, which, when run on a computer, cause the computer to implement the method as described in any one of claims 1 to 10, or the method as described in any one of claims 11 to 19.

23. A computer program product, wherein the computer program product comprises a computer program, characterized in that, When the computer program is run on a computer, it causes the computer to implement the method as described in any one of claims 1 to 10, or the method as described in any one of claims 11 to 19.

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