Decoding method and signal receiving end

Abstract

Embodiments of the present specification relate to a decoding method and a signal receiving end. The method comprises demodulating a received signal to obtain a first log-likelihood ratio (LLR) sequence of the signal; removing LLR values corresponding to a placeholder x in the first LLR sequence to obtain a second LLR sequence; performing repetition merging on the second LLR sequence to obtain a decision value; and performing decision on the decision value by using a predetermined decision rule to obtain decoding. Embodiments of the present specification consider the characteristics of the placeholder, remove the LLR values corresponding to the placeholder x from the LLR sequence obtained by demodulation, the second LLR sequence after removing the LLR values corresponding to the placeholder x includes the LLR values corresponding to a placeholder y, and the second LLR sequence is subjected to repetition merging, so that the LLR values corresponding to the placeholder y are also subjected to merging and accumulation, thereby reducing the complexity and improving the decoding performance.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of communication technology, and in particular to a decoding method and a signal receiving end. Background Technology

[0002] There are generally two types of decoding methods in the existing technology: one is the method that makes a decision based on the quadrant of the modulation symbol, and the other is the method that makes a decision based on the demodulated LLR soft bits. However, the existing decoding methods have a large amount of decoding computation and low performance.

[0003] Therefore, how to reduce the computational load of decoding and improve decoding performance is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, this specification provides a decoding method and a signal receiver that takes into account the characteristics of placeholders. After receiving the signal sent by the transmitter, the receiver removes the LLR value corresponding to the placeholder x, and repeatedly merges the LLR values ​​after removing the LLR value corresponding to the placeholder x to obtain the final decision value. The decision value is then used to make a decision using a predetermined decision rule to complete the decoding.

[0005] The specific technical solutions of the embodiments in this specification are as follows:

[0006] On the one hand, embodiments of this specification provide a decoding method, the method comprising:

[0007] The received signal is demodulated to obtain the first log-likelihood ratio (LLR) sequence of the signal;

[0008] Remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence;

[0009] The second LLR sequence is repeatedly merged to obtain the decision value;

[0010] The predetermined decision rules are used to make a decision on the decision value to obtain the decoded result.

[0011] Furthermore, demodulating the received signal to obtain the first LLR sequence of the signal further includes:

[0012] The LLR values ​​obtained by demodulating the signal are stored according to a predetermined storage length to obtain the first LLR sequence. The predetermined storage length is determined according to the modulation order of the original signal corresponding to the signal.

[0013] Furthermore, storing the LLR values ​​according to a predetermined storage length to obtain the first LLR sequence further includes:

[0014] Determine whether the length of the signal exceeds the predetermined storage length;

[0015] If so, the first n LLR values ​​of the signal are stored to obtain the first LLR sequence, where n is the predetermined storage length; or

[0016] If not, the LLR value is stored and a padding sequence is generated. The stored LLR value is then padded with the padding sequence to obtain the first LLR sequence. The length of the padding sequence is the difference between the predetermined storage length and the length of the signal.

[0017] Furthermore, the second LLR sequence is repeatedly merged to obtain a decision value that further includes:

[0018] The LLR values ​​in the second LLR sequence are merged according to the length of the second LLR sequence corresponding to the number of bits of the original signal to obtain the decision value for each bit.

[0019] Further, when the number of bits is 1, merging the LLR values ​​in the second LLR sequence according to the length of the second LLR sequence corresponding to the number of bits of the original signal to obtain the decision value for each bit further includes:

[0020] The decision value of the bit is obtained by summing the LLR values ​​in the second LLR sequence according to the length of the second LLR sequence.

[0021] Further, when the number of bits is 2, the step of merging the LLR values ​​in the second LLR sequence according to the length of the second LLR sequence corresponding to the number of bits of the original signal to obtain the decision value of each bit includes:

[0022] According to the formula:

[0023]

[0024] The second LLR sequence is grouped and merged to obtain the LLR value of each merged group, where, Let N be the combined LLR value of the three groups of the second LLR sequence, where N represents the length of the second LLR sequence. This represents the 3i-th LLR value in the second LLR sequence;

[0025] Using the formula:

[0026]

[0027] The combined LLR value of the three groups of the second LLR sequence The calculation is performed to obtain the decision value for each bit, where llr0 and llr1 are the decision values ​​for the first and second bits, respectively, abs(·) is the absolute value function, and sign(·) is the sign function.

[0028] Furthermore, the decoding process, which involves applying predetermined decision rules to the decision value, further includes:

[0029] Check whether the highest bit of the decision value for each bit is 0;

[0030] If so, then the decoded value of that bit is 0; or

[0031] If not, the bit is decoded as 1. Furthermore, the method also includes:

[0032] Determine the validity of the decoded code.

[0033] Furthermore, determining the validity of the decoding further includes:

[0034] The actual number of repetitions of the second LLR sequence is determined based on the number of bits of the original signal and the modulation order.

[0035] The validity threshold is calculated based on the noise power of the signal, the threshold threshold, and the actual number of repeated mergings.

[0036] If the absolute value of the decision value corresponding to the decoding exceeds the validity threshold, then the decoding is valid.

[0037] Furthermore, when the number of bits is 2, determining the validity of the decoding also includes:

[0038] If at least one of the two bits has a decision value exceeding the validity threshold, then the decoding of each bit is valid.

[0039] On the other hand, embodiments of this specification also provide a signal receiving end, which includes: a signal receiving module, a demodulation module, and a decoding module;

[0040] The signal receiving module is used to receive signals;

[0041] The demodulation module is used to demodulate the signal described above to obtain the first LLR sequence of the signal;

[0042] The decoding module is used to remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence; to repeatedly merge the second LLR sequence to obtain the decision value; and to make a decision on the decision value using a predetermined decision rule to obtain the decoding.

[0043] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0044] Using the embodiments of this specification, the characteristics of placeholders are considered. The LLR value corresponding to placeholder x is removed from the demodulated LLR sequence. The second LLR sequence after removing the LLR value corresponding to placeholder x includes the LLR value corresponding to placeholder y. This embodiment repeats and merges the second LLR sequence according to the number of bits of the original signal, thereby merging and accumulating the LLR value corresponding to placeholder y as well. By utilizing the characteristics of the repeating code, the complexity is reduced while the decoding performance is improved. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 The diagram shows a flowchart of a small-block code encoding method in the prior art.

[0047] Figure 2 , Figure 3 and Figure 4 The diagram shown is a 1-bit encoding schematic.

[0048] Figure 5 The diagram shown is a flowchart of a decoding method in an embodiment of this specification.

[0049] Figure 6 The diagram shown is a flowchart illustrating the demodulation of the signal to obtain the first LLR sequence of the signal in an embodiment of this specification.

[0050] Figure 7 The diagram shown is a flowchart illustrating the process of determining and removing the LLR value corresponding to the placeholder x in the first LLR sequence based on the number of bits of the original signal corresponding to the signal and the modulation order in an embodiment of this specification, thereby obtaining the second LLR sequence.

[0051] Figure 8 The diagram shown is a flowchart illustrating the process of repeatedly merging the second LLR sequence according to the number of bits of the original signal to obtain the decision value of each bit in an embodiment of this specification.

[0052] Figure 9 The diagram shown is a structural schematic of a signal receiver in one embodiment of this specification.

[0053] [Explanation of Figure Markers]:

[0054] 901. Signal receiving module;

[0055] 902. Demodulation module;

[0056] 903. Decoding module. Detailed Implementation

[0057] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.

[0058] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0059] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.

[0060] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0061] In the hybrid Automatic Repeat Request (HARQ) and Acknowledgment (ACK / NACK) mechanisms used in 5G / 6G, IoT, and industrial automation, feedback signals are typically transmitted in the form of small code blocks. These small code blocks come in three types: 1 bit, 2 bits, and 3-11 bits. Taking 1 bit as an example, 0 can represent ACK (successful reception), and 1 can represent NACK (failure requiring retransmission). The sending end needs to encode and rate-match the small code blocks to obtain the signal and then transmit it. The receiving end receives the signal, decodes it, and obtains the original information of the small code blocks.

[0062] Figure 1 The diagram shows a flowchart of a prior art small-block code encoding method, where the encoding of the small-block code is performed by the transmitting end. The uplink control information (UCI) bit sequence input to the small-block code is defined as c0, c1, c2, c3, ..., c K-1 Where K is the number of bits to be encoded. The encoded bit sequence is defined as d0, d1, d2, ..., d... N-1 N is the number of bits after encoding, and the output bit sequence after rate matching is f0, f1, f2, ..., f E-1 , where E is the length of the rate-matched output sequence.

[0063] Existing technologies (such as the 3GPP protocol) specify that for K=1, it is encoded according to 1 bit information, and for different modulation orders Q... m The encoding can be performed according to Table 1 below, where x and y are placeholders. If d i =y, then d i =d i-1 If d i =x, then d i =1. The encoded output length is N = 3Q. m Q m It is the modulation order.

[0064] Table 1

[0065] <![CDATA[Q m ]]> <![CDATA[Encoded bit sequence d0, d1, d2, ..., d N-1 > 1 <![CDATA[[c0]]]> 2 <![CDATA[[c0 y]]]> 4 <![CDATA[[c0 y x x]]]> 6 <![CDATA[[c0 y x x x x]]]> 8 <![CDATA[[c0 y x x x x x x]]]>

[0066] For K=2, the information is encoded using 2 bits, according to Table 2 below, where c2=(c0+c1)mod2, and the output length after encoding is N=3Q. m Q m It is the modulation order, x is a placeholder, if d i =x, then d i =1.

[0067] Table 2

[0068] <![CDATA[Q m ]]> <![CDATA[Encoded bit sequence d0, d1, d2, ..., d N-1 > 1 <![CDATA[[c0 c1 c2] <!-- 4 -->]]> 2 <![CDATA[[c0 c1 c2 c0 c1 c2]]]> 4 <![CDATA[[c0 c1 x x c2 c0 x x c1 c2 x x]]]> 6 <![CDATA[[c0 c1 x x x x c2 c0 x x x x c1 c2 x x x x]]]> 8 <![CDATA[[c0 c1 x x x x x x c2 c0 x x x x x x c1 c2 x x x x x x]]]>

[0069] Because of the placeholders x and y, the Euclidean distance between symbols can be maximized. During constellation mapping, regardless of whether BPSK, QPSK, 16QAM, 64QAM, or 256QAM modulation is used, the constellation points can be located in the four corners. For example, using 1-bit encoding... Figure 2 , Figure 3 and Figure 4 The approach is the same for 2-bit encoding. The difference is that with 1-bit encoding, the modulated constellation mapping point has two possibilities: the upper right corner (corresponding to the encoded information 0) or the lower left corner (corresponding to the encoded information 1); while with 2-bit encoding, the modulated constellation mapping point has four possibilities: the upper left corner (corresponding to the encoded information 10), the upper right corner (corresponding to the encoded information 00), the lower left corner (corresponding to the encoded information 11), and the lower right corner (corresponding to the encoded information 01).

[0070] Then rate matching is performed, and the rate matching sequences are arranged in a cyclical manner until the length reaches the length E of the rate matching output sequence.

[0071] The embodiments in this specification improve the demodulation and decoding at the receiving end, reducing the computational load of decoding and improving decoding performance.

[0072] Specifically, the embodiments of this specification provide a decoding method applicable to the decoding of small block codes. Figure 5 The diagram shown is a flowchart illustrating the decoding method in an embodiment of this specification. This diagram depicts the process by which the receiving end demodulates and decodes the received encoded signal. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiment or the accompanying drawings can be executed sequentially or in parallel.

[0073] Specific examples Figure 5 As shown, the method, executed by the receiving end, may include:

[0074] Step 501: Demodulate the received signal to obtain the first log-likelihood ratio (LLR) sequence of the signal;

[0075] Step 502: Remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence;

[0076] Step 503: Repeatedly merge the second LLR sequence to obtain the decision value;

[0077] Step 504: Use the predetermined decision rules to make a decision on the decision value to obtain the decoded value.

[0078] In the embodiments of this specification, taking 1-bit and 2-bit small block codes as examples, according to the provisions of Tables 1 and 2, the position of the placeholder x in the signal can be determined by looking up the table. Therefore, the LLR value corresponding to the placeholder x in the first LLR sequence can be determined and removed to obtain the second LLR sequence, which includes the LLR value corresponding to the placeholder y.

[0079] Then, the second LLR sequence is repeatedly merged according to the number of bits in the original signal to obtain the decision value of the bit. If the number of bits in the original signal is 1, the decision value of 1 bit is obtained after repeated merging. If the number of bits in the original signal is 2, the decision value of the first and second bits of the 2-bit sequence is obtained after repeated merging.

[0080] Finally, the predetermined decision rules are used to determine the decision value of each bit, thus obtaining the decoded value of each bit.

[0081] Because different signals may have different lengths in practical applications, the first length of the first LLR sequence will also be different, resulting in different lengths of the second LLR sequence after removing the LLR value corresponding to the placeholder x. When receiving signals in batches, the dynamically changing length of the second LLR sequence will inevitably affect decoding performance. Therefore, in order to further improve decoding performance, such as... Figure 6 As shown, demodulating the signal to obtain the first LLR sequence of the signal further includes:

[0082] Step 601: Demodulate the signal to obtain the LLR value of each bit in the signal;

[0083] Step 602: Determine the predetermined storage length based on the number of bits in the original signal and the modulation order;

[0084] Step 603: Store the LLR value according to the predetermined storage length to obtain the first LLR sequence, wherein the first length of the first LLR sequence is equal to the predetermined storage length.

[0085] In the embodiments of this specification, in order to ensure that the lengths of the second LLR sequences corresponding to the same number of bits are the same, the embodiments of this specification pre-determine a predetermined storage length table corresponding to the number of bits and modulation order of the original signal. For example, the predetermined storage length table corresponding to 1 bit is shown in Table 3, and the predetermined storage length table corresponding to 2 bits is shown in Table 3.

[0086] Table 3

[0087] <![CDATA[Q m (Modulation order) <![CDATA[N max (Predetermined storage length) 1 256 2 256 4 512 6 768 8 1024

[0088] Table 4

[0089] <![CDATA[Q m (Modulation order) <![CDATA[N max (Predetermined storage length) 1 768 2 768 4 1536 6 2304 8 3072

[0090] In this embodiment of the specification, it is determined whether the length of the signal exceeds the predetermined storage length;

[0091] If so, the first n LLR values ​​in the signal are stored to obtain the first LLR sequence, where n is the predetermined storage length;

[0092] If not, the LLR values ​​of all bits of the signal are stored, and a padding sequence is generated. The length of the padding sequence is the difference between the predetermined storage length and the length of the signal. The stored LLR values ​​are padded with the padding sequence to obtain the first LLR sequence.

[0093] N max The transformation can be performed as needed, based on the principle that the buffer size N is for modulation orders 1 and 2. max The same, N with modulation order 4 max The buffer size N is for modulation orders 1 and 2. max Twice the size of the buffer N with a modulation order of 6 max N is a modulation order of 1 and 2 max Three times the size of the buffer N with a modulation order of 8. max The buffer size N is for modulation orders 1 and 2. max Four times that. The cache size N for storing 2 bits of information. max N is the cache size for storing 1 bit of information. max 3 times.

[0094] Based on this, such as Figure 7 As shown, the LLR value corresponding to the placeholder x in the first LLR sequence is determined and removed based on the number of bits of the original signal corresponding to the signal and the modulation order, to obtain the second LLR sequence, which further includes:

[0095] Step 701: Determine the position of the placeholder x in the signal based on the number of bits and the modulation order of the original signal;

[0096] Step 702: Remove the LLR value corresponding to the bit where the placeholder x is located in the first LLR sequence to obtain the second LLR sequence. The second length of the second LLR sequences with the same number of bits is the same.

[0097] In the embodiments described in this specification, the LLR values ​​corresponding to the bits containing placeholder x are sequentially removed, according to different modulation Q values ​​in the protocol. m The encoding requirements are extracted. For 1-bit decoding, only the LLR values ​​at the corresponding positions of c0 and y are retained. For 2-bit decoding, only the LLR values ​​at the corresponding positions of c0, c1, and c2 are retained.

[0098] Since placeholders x and y are added according to the encoding rules during encoding, the placeholders x are removed sequentially during decoding. For 1-bit decoding, only c0 and y are retained, i.e., according to the different modulation Q values ​​in Tables 1 and 2. m The encoding requirements are extracted; for 2-bit decoding, only c0, c1, and c2 are retained. Definition It is the first LLR sequence after limiting the cache size, and the sequence length is N. max . It is the second LLR sequence after removing the placeholder x. The sequence length N depends on the number of bits K being decoded. For example, when K=1, N=256; while when K=2, N=768.

[0099] The methods for removing the LLR value corresponding to the placeholder x in 1-bit decoding and 2-bit decoding are the same; the difference lies in the predetermined storage length N. max .

[0100] Because the encoded bit sequence is repeated cyclically during rate matching at the transmitting end, LLR repeating and combining is performed at the receiving end.

[0101] like Figure 8 As shown, the second LLR sequence is repeatedly merged according to the number of bits of the original signal to obtain a decision value for each bit, which further includes:

[0102] Step 801: Determine the second length corresponding to the number of bits;

[0103] Step 802: Merge the LLR values ​​in the second LLR sequence according to the second length to obtain the decision value for each bit.

[0104] This can be understood as follows: after storing the LLR values ​​according to the predetermined storage length and removing the LLR values ​​corresponding to the placeholder x, the length of the second LLR sequence corresponding to the same number of bits is the same. Therefore, during batch reception, there is no need to calculate the length of the second LLR sequence again. Instead, the length of the second LLR sequence can be determined directly based on the number of bits of the original signal corresponding to the received signal, thereby improving decoding performance.

[0105] Then, the LLR values ​​in the second LLR sequence are merged according to the second length to obtain the decision value for each bit.

[0106] Specifically, when the number of bits is 1, the LLR values ​​in the second LLR sequence are merged according to the second length, and the formula for obtaining the decision value of each bit is as follows:

[0107]

[0108] in, This represents the merged LLR value, which is a 1-bit decision value. N represents the second length corresponding to 1 bit. This represents the i-th LLR value in the second LLR sequence.

[0109] When the number of bits is 2, the step of merging the LLR values ​​in the second LLR sequence according to the second length to obtain the decision value of each bit includes:

[0110] According to the formula:

[0111]

[0112] The second LLR sequence is grouped and merged to obtain the LLR value of each merged group, where, The LLR value is the combined value of the three blocks of the second LLR sequence, where N represents the second length corresponding to 2 bits. This represents the 3i-th LLR value in the second LLR sequence;

[0113] Using the formula:

[0114]

[0115] The combined LLR value of the three groups of the second LLR sequence The calculation yields the decision value of the first and second bits in the 2-bit dataset, where llr0 and llr1 are the decision values ​​of the first and second bits, respectively. abs(·) is the absolute value function, and sign(·) is the sign function.

[0116] After obtaining the decision value for each bit, the decision value for each bit can be determined using the predetermined decision rules.

[0117] For example, when the number of bits is 1, it can be determined whether the highest bit of the decision value of 1 bit is 0; if yes, the decoding of 1 bit is 0; if no, the decoding of 1 bit is 1.

[0118] When the number of bits is 2, for any one of the 2 bits, determine whether the highest bit of the decision value of that bit is 0; if yes, then the decoding of that bit in the 2 bits is 0; if no, then the decoding of that bit in the 2 bits is 1.

[0119] Although merging is performed according to the second length each time, in reality, only when the number of LLR values ​​in the decoding input E>N is the merging process complete. max Only when the second length of points are valid values ​​will all be valid; otherwise, due to insufficient E in the LLR storage module, N will be invalid. maxIn the case of LLR values, only E LLR values ​​are stored, and the remaining bits are kept with an initial value of 0. Therefore, the bits after the second length of points are filled with 0, and the actual number of LLRs involved in the calculation does not correspond.

[0120] Therefore, the embodiments of this specification also determine the validity of the decoding.

[0121] Specifically, determining the validity of the decoding further includes:

[0122] The actual number of repeats in the second LLR sequence is determined based on the number of bits and the modulation order.

[0123] Based on the noise power of the signal, the threshold, and the actual number of repeated merges, the formula is used... Calculate the validity threshold, where H represents the validity threshold, thr represents the threshold limit, and num... merge σ represents the actual number of repeated merges. 2 Indicates noise power;

[0124] Determine whether the absolute value of the decision value exceeds the validity threshold;

[0125] If yes, the decoding is valid; otherwise, the decoding is invalid.

[0126] In the embodiments of this specification, the actual number of repeating merges (num) of the second LLR sequence can be determined based on the number of bits and the modulation order. merge For example, given the rate-matched output sequence length E of the transmitter, and combining it with Table 3 or Table 4, we can obtain the number of non-zero elements in the first LLR sequence. Then, based on Table 1 or Table 2, we can obtain the number of elements removed from the first LLR sequence, and finally obtain the actual number of LLRs participating in the calculation, num. merge .

[0127] For example, for 1 bit and 2 bits, this can be achieved with the following code:

[0128]

[0129]

[0130] The power of the measured noise is defined as σ. 2 ,num merge This represents the actual number of duplicate merges, and `thr` is the 1-bit and 2-bit threshold. The `thr` value is calculated as follows: if the false detection probability is defined as less than α, then the `thr` value is the value greater than the cumulative probability density table lookup value in the normal distribution. The value of α is usually 0.01.

[0131] If the absolute value of the decision value exceeds the validity threshold H, the decoding is valid; otherwise, the decoding is invalid.

[0132] When the number of bits is 2, determine whether the maximum value of the first and second decision values ​​of the 2 bits exceeds the validity threshold; if yes, the decoding of the first and second bits of the 2 bits is valid; if no, the decoding of the first and second bits of the 2 bits is invalid.

[0133] This can be understood as reducing the possibility of false detection and improving the reliability of decoding by using the above-mentioned methods to determine the validity of the decoding.

[0134] Based on the same inventive concept, embodiments of this specification also provide a signal receiving terminal. For example... Figure 9 As shown, it includes: a signal receiving module 901, a demodulation module 902, and a decoding module 903;

[0135] The signal receiving module 901 is used to receive signals;

[0136] The demodulation module 902 is used to demodulate the above signal to obtain the first LLR sequence of the signal;

[0137] The decoding module 903 is used to remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence; to repeatedly merge the second LLR sequence to obtain the decision value; and to make a decision on the decision value using a predetermined decision rule to obtain the decoding.

[0138] Since the principle of solving the problem in the above signal receiver is similar to that in the above method, the implementation of the above signal receiver can refer to the implementation of the above method, and the repeated parts will not be repeated.

[0139] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0140] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.

[0141] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0142] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0143] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.

[0144] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0145] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0146] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0147] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0148] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0149] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.

Claims

1. A decoding method, characterized in that, The method includes: The received signal is demodulated to obtain the first log-likelihood ratio (LLR) sequence of the signal; Remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence; The second LLR sequence is repeatedly merged to obtain the decision value; The predetermined decision rules are used to make a decision on the decision value to obtain the decoded result.

2. The method according to claim 1, characterized in that, Demodulating the received signal to obtain the first LLR sequence of the signal further includes: The LLR values ​​obtained by demodulating the signal are stored according to a predetermined storage length to obtain the first LLR sequence. The predetermined storage length is determined according to the modulation order of the original signal corresponding to the signal.

3. The method according to claim 2, characterized in that, The first LLR sequence is obtained by storing the LLR values ​​according to a predetermined storage length, and further includes: Determine whether the length of the signal exceeds the predetermined storage length; If so, the first n LLR values ​​of the signal are stored to obtain the first LLR sequence, where n is the predetermined storage length; or If not, the LLR value is stored and a padding sequence is generated. The stored LLR value is then padded with the padding sequence to obtain the first LLR sequence. The length of the padding sequence is the difference between the predetermined storage length and the length of the signal.

4. The method according to claim 2, characterized in that, Repeated merging of the second LLR sequence yields a decision value that further includes: The LLR values ​​in the second LLR sequence are merged according to the length of the second LLR sequence corresponding to the number of bits of the original signal to obtain the decision value for each bit.

5. The method according to claim 4, characterized in that, When the number of bits is 1, the LLR values ​​in the second LLR sequence are merged according to the length of the second LLR sequence corresponding to the number of bits of the original signal, and the decision value for each bit is further included: The decision value of the bit is obtained by summing the LLR values ​​in the second LLR sequence according to the length of the second LLR sequence.

6. The method according to claim 4, characterized in that, When the number of bits is 2, the step of merging the LLR values ​​in the second LLR sequence according to the length of the second LLR sequence corresponding to the number of bits of the original signal to obtain the decision value of each bit includes: According to the formula: The second LLR sequence is grouped and merged to obtain the LLR value of each merged group, where, Let N be the combined LLR value of the three groups of the second LLR sequence, where N represents the length of the second LLR sequence. This represents the 3i-th LLR value in the second LLR sequence; Using the formula: The combined LLR value of the three groups of the second LLR sequence The calculation is performed to obtain the decision value for each bit, where llr0 and llr1 are the decision values ​​for the first and second bits, respectively, abs(·) is the absolute value function, and sign(·) is the sign function.

7. The method according to claim 4, characterized in that, The decoding process further includes applying predetermined decision rules to the decision value, resulting in the following: Check whether the highest bit of the decision value for each bit is 0; If so, then the decoded value of that bit is 0; or If not, the bit is decoded as 1.

8. The method according to claim 2, characterized in that, The method further includes: Determine the validity of the decoded code.

9. The method according to claim 8, characterized in that, Determining the validity of the decoding further includes: The actual number of repetitions of the second LLR sequence is determined based on the number of bits of the original signal and the modulation order. The validity threshold is calculated based on the noise power of the signal, the threshold threshold, and the actual number of repeated mergings. If the absolute value of the decision value corresponding to the decoding exceeds the validity threshold, then the decoding is valid.

10. The method according to claim 9, characterized in that, When the number of bits is 2, determining the validity of the decoding further includes: If at least one of the two bits has a decision value exceeding the validity threshold, then the decoding of each bit is valid.

11. A signal receiver, characterized in that, include: Signal receiving module, demodulation module, and decoding module; The signal receiving module is used to receive signals; The demodulation module is used to demodulate the signal to obtain the first LLR sequence of the signal; The decoding module is used to remove the LLR value corresponding to the placeholder x in the first LLR sequence to obtain the second LLR sequence; to repeatedly merge the second LLR sequence to obtain the decision value; and to make a decision on the decision value using a predetermined decision rule to obtain the decoding.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 10.

Images