Communication method and communication apparatus

Abstract

The application discloses a communication method and a communication device. By arranging columns corresponding to at least one split group between two adjacent starting points, the split rows in the at least one split group can be sent in sequence, the generation of check equations can be reduced, the complexity of a decoder can be reduced, and the decoding performance can be improved.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to communication methods and communication apparatus. Background Technology

[0002] Channel coding is one of the core technologies in the field of wireless communication. The complete channel coding process includes: adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate adaptation, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is a crucial part. The purpose of error correction coding is to ensure that the receiving device can automatically correct errors that occur during data transmission with as little redundancy overhead as possible. At the same bit error rate, the smaller the redundancy overhead, the higher the coding efficiency.

[0003] Low-density parity check (LDPC) codes are one of the most mature and widely used coding schemes. LDPC codes are a channel coding scheme very close to Shannon lines, featuring good performance and low complexity. LDPC codes have been adopted by the 3rd Generation Partnership Project (3GPP) as a data channel coding scheme.

[0004] Currently, LDPC codes support a wide variety of parity check equations, which makes decoders complex and hinders decoding. Summary of the Invention

[0005] Embodiments of this application provide communication methods and communication devices to reduce decoder complexity and improve decoding performance.

[0006] Firstly, embodiments of this application provide a communication method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it.

[0007] The method includes: acquiring LDPC codewords, wherein the LDPC codewords are used for retransmission, the retransmission start point is one of a plurality of start points, the difference between the column number of the column adjacent to the retransmission start point and K is the row number of a row in a first row set, the first row set includes at least one split group, one split group corresponds to one first row, different split groups correspond to different first rows, the split group includes all second rows corresponding to the first row corresponding to the split group, the first row corresponds to a first column set, and the first column set includes the first n rows of the first row. c The column containing the non-zero elements of the n elements, the second row corresponds to the second column set, and the second column set includes the first n elements of the second row. c The column containing the non-zero elements of the n elements, the second column set is contained within the first column set, K is the number of information columns in the LDPC check matrix, and n c The sum of the number of information columns and core check columns of the LDPC check matrix; send the LDPC codeword.

[0008] For split LDPC codes, a splitting relationship between rows is introduced during low-rate extension. If a newly added row is related to a previous row, it can be eliminated using the related row, and the resulting matrix can be used for encoding or decoding. Different rows can have a splitting relationship with the same row. Due to this characteristic, if the initial transmission and retransmission are not continuous in the parity check equation, it may lead to more parity check equations. For example, with a boost value of 1, if row 5 of the base map is split from row 2, and row 9 is split from row 2, and the initial transmission transmits columns corresponding to rows 1 to 4, and the retransmission starts from the column corresponding to row 9, then row 9 will be used to eliminate rows 2 without using row 5 to eliminate rows 2. Compared to sending rows 2, 5, and 9 sequentially, this results in an additional parity check equation, complicating the decoder design. In the above method, by setting the column corresponding to at least one split group between two adjacent starting points, it can be ensured that the rows in at least one split group are sent in sequence, thereby reducing the generation of check equations, which helps to reduce the complexity of the decoder and thus helps to improve the decoding performance.

[0009] In conjunction with the first aspect, in some implementations, the at least one split group is all split groups.

[0010] Based on the above implementation method, it can be guaranteed that all the second lines are sent in sequence, which helps to reduce the number of generated check equations and further reduce the complexity of decoder implementation and control.

[0011] In conjunction with the first aspect or any of its implementations, in some other implementations, the row set corresponding to any two adjacent starting points other than the first two starting points includes at least one split group.

[0012] Based on the above implementation method, it helps to reduce the length of codewords in a single retransmission.

[0013] In conjunction with the first aspect or any of its implementations, in some other implementations, the first row set further includes at least one third row that is unrelated to the other rows of the LDPC check matrix.

[0014] Based on the above implementation method, on the one hand, it can avoid the distance between two adjacent starting points being too short, and on the other hand, it can make the row redesign of the parity matrix more flexible.

[0015] In conjunction with the first aspect or any of its implementations, in some other implementations, the first split group in the at least one split group includes a plurality of second rows, and some or all of the at least one third row is located between the plurality of second rows; and / or, the set of first rows includes a plurality of the split groups, and some or all of the at least one third row is located between the plurality of the split groups.

[0016] Based on the above implementation method, the design of the verification matrix (such as row redistribution) is more flexible.

[0017] In conjunction with the first aspect or any of its implementations, in some other implementations, the first row set includes multiple said split groups, with rows from different said split groups interspersed.

[0018] Based on the above implementation method, the design of the verification matrix (such as row redistribution) is more flexible.

[0019] Secondly, embodiments of this application provide a communication method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a network device, a terminal, a decoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it.

[0020] The method includes: obtaining retransmitted LDPC codewords, wherein the starting point for retransmitting the LDPC codewords is one of a plurality of starting points, the difference between the column number of the column between the starting point for retransmitting the LDPC codewords and the starting point adjacent to the starting point for retransmitting the LDPC codewords among the plurality of starting points and K is the row number of a row in a first row set, the first row set includes at least one split group, one split group corresponds to one first row, different split groups correspond to different first rows, the split group includes all second rows corresponding to the first row corresponding to the split group, the first row corresponds to a first column set, and the first column set includes the first n rows of the first row. c The column containing the non-zero elements of the n elements, the second row corresponds to the second column set, and the second column set includes the first n elements of the second row. c The column containing the non-zero elements of the n elements, the second column set is contained within the first column set, K is the number of information columns in the LDPC check matrix, and n c The sum of the number of information columns and core check columns of the LDPC check matrix; decoding is performed based on the LDPC codeword.

[0021] In the above method, by setting the column corresponding to at least one split group between two adjacent starting points, it can be ensured that the rows in at least one split group are sent in sequence, thereby reducing the generation of check equations, which helps to reduce the complexity of the decoder and thus helps to improve the decoding performance.

[0022] In conjunction with the second aspect, in some implementations, the at least one split group is all split groups.

[0023] Based on the above implementation method, it can be guaranteed that all the second lines are sent in sequence, which helps to reduce the number of generated check equations and further reduce the complexity of decoder implementation and control.

[0024] In conjunction with the second aspect or any of its implementations, in some other implementations, the row set corresponding to any two adjacent starting points other than the first two starting points includes at least one split group.

[0025] Based on the above implementation method, it helps to reduce the length of codewords in a single retransmission.

[0026] In conjunction with the second aspect or any of its implementations, in some other implementations, the first row set further includes at least one third row that is unrelated to the other rows of the LDPC check matrix.

[0027] Based on the above implementation method, on the one hand, it can avoid the distance between two adjacent starting points being too short, and on the other hand, it can make the row redesign of the parity matrix more flexible.

[0028] In conjunction with the second aspect or any of its implementations, in some other implementations, the first split group in the at least one split group includes a plurality of second rows, and some or all of the at least one third row is located between the plurality of second rows; and / or, the set of first rows includes a plurality of the split groups, and some or all of the at least one third row is located between the plurality of the split groups.

[0029] Based on the above implementation method, the design of the verification matrix (such as row redistribution) is more flexible.

[0030] In conjunction with the second aspect or any of its implementations, in some other implementations, the first row set includes multiple said split groups, with rows from different said split groups interspersed.

[0031] Based on the above implementation method, the design of the verification matrix (such as row redistribution) is more flexible.

[0032] Thirdly, embodiments of this application provide a communication device that has the function of implementing the method described in any of the above aspects or any of its implementations. For example, the communication device includes modules, units, or means corresponding to the operations involved in the method described in any of the above aspects or any of its implementations. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0033] Fourthly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer programs, code, or instructions for implementing the functions described in any of the above aspects or any of their implementations. The one or more processors can execute the computer programs, code, or instructions, causing the communication device to implement the methods described in any of the above aspects or any of their implementations when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0034] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0035] In one possible design, the communication device may also include the memory.

[0036] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0037] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0038] Fifthly, embodiments of this application provide a communication system including at least one of the first communication device or the second communication device described above.

[0039] Sixthly, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions, programs, or code, which, when read and executed by a computer, cause the computer to perform any of the above aspects or any implementation thereof.

[0040] In a seventh aspect, embodiments of this application provide a computer program product that, when read and executed by a computer, causes the computer to perform the methods described in any of the above aspects or any of their implementations.

[0041] Eighthly, embodiments of this application provide a computer program that, when run on a computer, causes the method provided in any of the above aspects or any of the implementations to be executed.

[0042] Ninthly, embodiments of this application provide a chip or chip system, including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory is used to store part or all of a computer program, code, or instructions necessary for implementing the functions involved in the methods described in any of the above aspects or any of their implementations. The one or more processors are executable to the computer program, code, or instructions, causing the communication device to implement the methods described in any of the above aspects or any of their implementations when the computer program, code, or instructions are executed. The interface circuit is used to implement communication functions within the communication device and / or communication functions between the communication device and other devices or components.

[0043] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0044] In one possible design, the chip or chip system may also include the memory. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the network architecture applicable to embodiments of this application.

[0046] Figure 2 This is a schematic diagram of the open access network architecture according to an embodiment of this application.

[0047] Figure 3 This is a schematic diagram of the information transmission process applicable to embodiments of this application.

[0048] Figure 4 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0049] Figure 5 This is a schematic diagram of the matrix structure of the base map of the 5th generation (5G) LDPC code.

[0050] Figure 6 This is another schematic diagram of the matrix structure of the base map of 5G LDPC code.

[0051] Figure 7 This is an example of an extension of a split LDPC code.

[0052] Figure 8 This is an example of the basis matrix of a split LDPC code.

[0053] Figure 9 This is a diagram illustrating the reading of code words.

[0054] Figure 10 This is a schematic flowchart of the communication method 1000 provided in this application.

[0055] Figure 11 This is an example where all the columns corresponding to the split rows are located between adjacent starting points.

[0056] Figure 12 This is an example of a split group between two adjacent starting points.

[0057] Figure 13 This is an example of multiple split groups between two adjacent starting points.

[0058] Figure 14 This is a schematic diagram of the structure of an apparatus provided in an embodiment of this application.

[0059] Figure 15 This is another schematic diagram of the device provided in the embodiments of this application.

[0060] Figure 16 This is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0061] Before introducing the embodiments of this application, the following description is provided.

[0062] "For indication" or "indication" can include both direct and indirect indication, or in other words, "for indication" or "indication" can be explicit and / or implicit. "System" and "network" are used interchangeably. "At least one" means one or more, and "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC. "At least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC, where A, B, and C can be single or multiple. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the order, timing, priority, or importance of multiple objects. The term "protocol" may refer to standard protocols in the field of communications, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as (another) example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design described as "exemplary" in this application should not be construed as being better or more advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0063] In this application, "sending information" can be understood as one device sending information to another device, or it can also be understood as one logic module within a device sending information to another logic module. For example, "the encoding device sending information" can be understood as the encoding device sending information to another device (such as a decoding device), or it can be understood as logic module 1 in the encoding device sending information to logic module 2 in the encoding device.

[0064] In this application, "receiving information" can be understood as one device receiving information from another device, or it can also be understood as a logic module within a device receiving information from another logic module. For example, "decoding device receiving information" can be understood as the decoding device receiving information from another device (such as an encoding device), or it can be understood as logic module 1 in the decoding device receiving information from logic module 2 in the decoding device.

[0065] In this application, the phrase "sending information to... (e.g., a decoding device)" or the related illustrations in the accompanying drawings can be understood as the destination of the information being a decoding device. This can include sending information directly or indirectly to a terminal. Similarly, the phrases "receiving information from... (e.g., an encoding device)," "receiving information from... (e.g., an encoding device)," or "receiving information sent (e.g., by an encoding device)," or the related illustrations in the accompanying drawings, can be understood as the source of the information being an encoding device. This can include receiving information directly or indirectly from an encoding device. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly, and will not be elaborated further here.

[0066] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0067] The following describes a communication system to which embodiments of this application can be applied.

[0068] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, long term evolution-vehicle (LTE-V) communication, long term evolution-machine (LTE-M) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrow band Internet of Things (NB-IoT) systems, or other communication systems. The embodiments of this application can also be applied to reconfigurable intelligent surface (RIS) communication systems, satellite communication systems, high altitude platform station (HAPS) communication systems, and non-terrestrial network (NTN) systems such as unmanned aerial vehicles (UAVs). Examples include integrated communication and navigation (ICAN) systems, global navigation satellite systems (GNSS), and ultra-dense low-Earth orbit (LEO) satellite communication systems. Furthermore, it can be extended to similar wireless communication systems, such as wireless local area networks (WLANs), wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and other 3GPP-related communication systems.

[0069] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminals. Optionally, both the transmitting device and the receiving device may be network devices.

[0070] In this application, the transmitting device can be understood as a device that transmits data or information, and may also be called an encoding device. The receiving device can be understood as a device that receives data or information, and may also be called a decoding device.

[0071] For example, Figure 1 A schematic diagram of a network architecture applicable to embodiments of this application is shown.

[0072] Figure 1 A possible, non-limiting system schematic diagram is shown. For example... Figure 1 As shown, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (e.g., ...). Figure 1 110a and 110b (collectively referred to as 110) and at least one terminal (such as Figure 1 RAN 100, denoted as RAN 120a-120j, is collectively referred to as RAN 120. RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 1 (Not shown in the image). Terminal 120 is connected to RAN node 110 wirelessly. RAN node 110 is connected to core network 200 wirelessly or via wired connection. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0073] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0074] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative, for example... Figure 1 Network element 120i can be a helicopter or a drone, and it can be configured as a mobile base station. For terminals 120j that access RAN 100 through network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes referred to as communication devices, for example... Figure 1 Network elements 110a and 110b can be understood as communication devices with base station functions, while network elements 120a-120j can be understood as communication devices with terminal functions.

[0075] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmit / receive point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system, etc. Figure 1 110a), micro base stations or indoor stations (such as Figure 1 The RAN node can be a relay node or donor node (as described in section 110b), or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions and corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node functions.

[0076] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with different RAN nodes each implementing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be set up separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0077] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0078] For ease of understanding, combined with Figure 2 This paper briefly introduces the O-RAN architecture of embodiments of this application. From Figure 2 As can be seen from this, the O-RAN architecture includes: the first network unit, the second network unit, the third network unit, O-eNB, O-CU-CP, O-CU-UP, O-DU, O-RU, and O-cloud.

[0079] Figure 2The network elements (also called nodes) can be interconnected. For example, the first network unit connects to the O-cloud via the O2 interface; the first network unit connects to the third network unit, O-eNB, O-CU-CP, O-CU-UP, O-DU, and O-RU via the O1 interface; the first network unit connects to the O-RU via the open fronthaul management plane (M-Plane) interface; the O-DU connects to the O-RU via the open fronthaul M-Plane interface and the open fronthaul control / user / synchronization plane (C / U / S-Plane) interface; the third network unit connects to the O-eNB, O-CU-CP, O-CU-UP, and O-DU via the E2 interface; the O-CU-CP connects to the O-DU via the F1-c interface; the O-CU-UP connects to the O-DU via the F1-u interface; and the O-CU-CP connects to the O-CU-UP via the E1 interface. Figure 2 For a detailed description of the interface shown, please refer to the existing standards; it will not be repeated here.

[0080] One possible example is that the first network unit could be a service management and orchestration framework (SMO), or a network unit with similar functionality to an SMO; there is no limitation on which one.

[0081] One possible example is that the second network element can be a Non-RT RIC, or a network element with similar functionality to a Non-RT RIC; there is no limitation on this.

[0082] One possible example is that the third network unit could be a Near-RT RIC, or a network unit with similar functionality to Near-RT RIC; there is no limitation on this.

[0083] O-RAN aims to achieve an intelligent and open access network. A key feature of the O-RAN architecture is the separation of hardware and software, enabling the virtualization of network functions and the standardization of hardware. Furthermore, O-RAN can incorporate artificial intelligence (AI).

[0084] In the embodiments of this application, the access network device may also be simply referred to as a network device.

[0085] A terminal is a device or module that connects to the aforementioned communication system and possesses corresponding communication functions. Terminals can also be called terminal equipment, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as D2D, V2X, MTC, IoT, virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. The terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle device (such as a complete vehicle device, vehicle module, vehicle chip, on-board unit (OBU) or telematics box (T-BOX)), flight equipment (e.g., drone, helicopter, airplane, hot air balloon), ship, robot, robotic arm, smart home device, transportation vehicle with wireless communication capabilities, communication module, smart point of sale (POS) machine, customer-premises equipment (CPE), light user equipment (light UE), reduced capability user equipment (REDCAP UE), vehicle-mounted equipment (e.g., car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), satellite terminal, etc. The embodiments of this application do not limit the device form of the terminal. The terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0086] Unless otherwise specified, the means for implementing the functions of a terminal or network device in this application can refer to the terminal or network device itself, or it can refer to a means that enables the terminal or network device to implement the function, such as a system-on-a-chip (SoC) or a chip, specifically a SoC or a modem. This means can be installed in the terminal or network device. In the embodiments of this application, the SoC can be composed of chips, or it can include chips and other discrete devices.

[0087] This document uses a 5G system as an example to illustrate specific solution details in some embodiments. It is understood that when this solution is used in other communication systems, such as LTE systems or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0088] Figure 3 This is a schematic diagram illustrating the information transmission process applicable to embodiments of this application. For example... Figure 3As shown, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Among these processes, Figure 3 The processing shown in the upper layer (including source coding, channel coding, and modulation) is performed on the coding side, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed on the decoding side.

[0089] The embodiments of this application can be implemented in hardware, such as through a dedicated chip or a programmable chip, or by a processor executing software instructions, and mainly involve... Figure 3 The channel coding and channel decoding are shown. The embodiments of this application can be used for the channel decoding part. The decoding method of the embodiments of this application is a general decoding means, effective for any coding scheme; therefore, the embodiments of this application do not limit the channel coding scheme.

[0090] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application will be briefly explained.

[0091] The concepts and terms described below are based on those specified in the agreement, but do not imply that the embodiments of this application can only be applied to existing systems. The concepts and terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms related to functional descriptions) may be adjusted as future systems develop.

[0092] 1. LDPC code

[0093] LDPC codes are linear block codes with sparse parity-check matrices. The proportion of non-zero elements in the parity-check matrix of an LDPC code is extremely small; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with K information bits and a code length of N, the dimension of its parity-check matrix H is (NK) × N, and the corresponding codeword c can be defined by the parity-check matrix H as follows:

[0094] c = {c|Hc} T =0, c∈{0,1} N}

[0095] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and the NK parity-check equations correspond to the NK parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,jThis indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0096]

[0097] Where v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0098] LDPC codes can be represented using graphical models. Commonly used graphical models include Tanner graphs, factor graphs, and tree graphs, among which Tanner graphs offer the most concise and intuitive representation. The Tanner graph of the parity-check matrix H mentioned above can be represented as follows: Figure 4 As shown, Figure 4 The degree in the graph corresponds to the definition of degree in the parity-check matrix H mentioned above; the degree of a node can be defined as the number of edges connected to it. In a Tanner graph, a cycle is defined as a structure that starts from a vertex, follows non-repeating edges, passes through non-repeating vertices, and finally returns to the starting point. Since a Tanner graph is a bipartite graph, the length of its cycles is an even number greater than 2, such as 4, 6, 8, etc. Short cycles are very detrimental to LDPC codes, mainly in the following two aspects: short cycles can form trap sets, which can significantly affect the code distance of LDPC codes; at the same time, short cycles can introduce correlations into the confidence propagation decoding algorithm, leading to inaccurate mutual information estimation. Therefore, in the design of LDPC codes, short cycles are generally avoided as much as possible.

[0099] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0100] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes.

[0101] QC-LDPC codes are represented using BG (Browser Group). Elements in BG are either 0 or 1, and a 1 in BG can be extended to Z. C ×Z C The cyclic displacement matrix BG, where 0 can be extended to Z C ×Z C The zero matrix is ​​expanded to obtain the parity matrix. Where Z... C Z is the lifting size.C It can also be referred to as boost size, expansion factor, boost value, expansion coefficient, or boost dimension, etc. Z C It can also be denoted as Z. The BG model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F represents the edge relationships. The boosted value is Z. C After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V are variable nodes, C are check nodes, and E are the edges between variable nodes and check nodes, corresponding to the number of columns in the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E| = Z. c |F|.

[0102] BG can also be expressed in matrix form, denoted as H. BG Based on the basis matrix H BG And the boost value Zc, which can transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. The lifting process involves... BG The element in the middle is promoted to a Z. C ×Z C A square matrix, where 0 is promoted to Z. C ×Z C A 0 matrix, promote the 1s to an identity matrix by cyclic shifting P (to the right). i,j The matrix, where P i,j The shifting value corresponding to the i-th row and j-th column. , SV). With Z C The results of cyclic shifting 4, -1, 0, 1, 2, 3 are shown below:

[0103]

[0104] 3. Base map of 5G LDPC code

[0105] The base map of 5G LDPC code includes BG1 and BG2, which share a common matrix structure.

[0106] Figure 5This is a schematic diagram of the matrix structure of the 5G LDPC code basemap. The 5G LDPC code basemap adopts a raptor-like structure and can be divided into four parts. The upper left part is the core matrix, also known as the high-rate part, which has a higher matrix density and corresponds to the base matrix of the highest code rate. The upper right and lower left parts belong to the extension part. The upper right part is an all-zero matrix, and the lower left part is also called the incremental redundancy region. These two parts have lower matrix densities. The lower right part is the identity matrix, also known as a diagonal matrix or region, used to adapt to different code rates.

[0107] Figure 6 This is another schematic diagram of the matrix structure of the 5G LDPC code basemap. As shown, the 5G LDPC code basemap can be divided into five regions: A, B, C, D, and E. Regions A and B correspond to the core matrix. Region A corresponds to system bits or information bits, and its columns are system or information columns. Region B corresponds to core parity bits, and its columns are core parity columns, which are columns with a degree of non-1 during the encoding process. Region C corresponds to the all-zero region, and its columns are extended parity columns, which are columns with a degree of 1 during the encoding process. Region D corresponds to the incremental redundancy region. Region E corresponds to a single diagonal matrix.

[0108] The elements of the base graph take values ​​of 0 or 1, where a value of 0 represents an empty element or a zero element, and a value of 1 represents an edge present at that position in the base graph or an association between the corresponding check node and the variable node.

[0109] In 5G LDPC codes, the protocol specifies a maximum-sized base map for storage. In practical applications, different matrix regions are selected based on the code rate. Specifically, rows 1 to M0 and columns 1 to N0 are selected. As the code rate decreases, M0 and N0 gradually increase, and the area of ​​the matrix used also gradually expands. For example... Figure 6 The dashed boxes containing high-bit-rate regions correspond to different bit-rates. The base map of 5G LDPC codes has a nested characteristic, meaning that low-bit-rate regions contain high-bit-rate regions.

[0110] The 5G LDPC code stores the following information regarding shift values: 1. A list of boost values; 2. A list of shift values ​​that corresponds one-to-one with each row of the boost value list. Table 1 shows an example of a boost value list.

[0111] Table 1

[0112]

[0113] The main characteristic of a list of promoted values ​​is that the j-th row of the list... Where a j∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}.

[0114] Table 2 is a list of edge connections and translation values ​​for a certain part of BG1, where the first two columns correspond to the basis matrix of that part, and the last eight columns correspond to the translation values ​​of that part.

[0115] Table 2

[0116]

[0117]

[0118] The row indices of the lift value list correspond one-to-one with the column indices of the shift values. That is, each row of the lift value list corresponds to a set of shift values, and multiple lift values ​​share the same set of shift values. For example, in Table 2, the set index i... LS The boost values ​​{2, 4, 8, 16, 32, 64, 128, 256} that equal 0 correspond to the shift values ​​{250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0}. During code rate matching, 5G LDPC first determines the boost values ​​and then selects the corresponding shift values ​​to construct the parity check matrix.

[0119] In the embodiments of this application, the base matrix can refer to a matrix with elements of 0 or 1, wherein elements represented as 0 can be replaced by a Z*Z all-zero matrix, and elements represented as 1 can be replaced by a Z*Z cyclic permutation matrix, as shown in the first two columns of Table 2.

[0120] The embodiments of this application are described based on code length, information length, and code rate, and these terms are explained herein. Information length refers to the number of information bits to be transmitted, which may or may not include cyclic redundancy check (CRC) bits. Code length refers to the length of the (to be) transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol. Code rate refers to the ratio of the number of information bits to the number of transmitted bits. Code length, information length, and code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, and can also be directly obtained and calculated by the transceiver. More specifically, code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0121] 3. Split LPDC codes

[0122] For split LDPC codes, row-to-row correlation is introduced during low-rate extension. Specifically, during low-rate extension, for partial or full extension, the newly added row eliminates a row preceding that row in the base matrix. The eliminated row and the newly added row, excluding the newly added check nodes, are orthogonal. That is, the newly added check equation eliminates the previous check equation, and the matrix after elimination is used as the decoding matrix.

[0123] The row being eliminated can be called the parent row, parent row, parent node, or parent node, while the row being eliminated is called the child row or child node.

[0124] The newly added row is obtained by eliminating a row in the base matrix preceding it. This can also be understood as the newly added row being split from a row preceding it in the base matrix. In this case, the newly added row can be called a split row. Rows not derived from splitting other rows can be called non-split rows.

[0125] Figure 7 This is an example of an extension of a split LDPC code.

[0126] Figure 7 Take splitting the second row as an example. Figure 7 In this matrix, "-1" corresponds to zero elements and can be expanded into a zero matrix. Non-"-1" values ​​correspond to non-zero elements and can be expanded into an identity matrix cyclically shifted (to the right) by the corresponding values. For example, "0" can be expanded into an identity matrix, and "37" can be expanded into an identity matrix cyclically shifted 37 times.

[0127] like Figure 7 As shown, adding the parity bit in column 29 adds a fifth parity row. It can be seen that the fifth parity row (excluding the extra parity bits, i.e., the last column) is a subset of the second parity row. Each parity node in the fifth parity row (excluding the extra parity bits, i.e., the last column) belongs to the second parity row before elimination, and the corresponding shift values ​​are the same.

[0128] During encoding, after encoding the check value of the core check matrix (columns 25-28), the check equation of the 5th check row is used to generate the check value of column 29.

[0129] During decoding, because the fifth parity row is a subset of the second parity row, many short loops are generated, resulting in very poor performance if decoded directly. Therefore, further processing can be performed during decoding: eliminating elements from the second parity row based on the fifth parity row to generate a new second parity row, as detailed below. Figure 7 As shown.

[0130] To simplify the description, we will use the check equation X2 of the second check row as V1+V2+V3+V4+V5+V6=0 and the check equation X5 of the fifth check row as V1+V3+V5+V7=0.

[0131] X2: V1+V2+V3+V4+V5+V6=0;

[0132] X5: V1+V3+V5+V7=0;

[0133] Therefore, by eliminating X2 based on X5, the newly generated check equation X2' is: V2+V4+V6+V7=0.

[0134] When decoding, replacing X2 with X2' can improve performance.

[0135] As the code rate decreases, the matrix weight of the split LDPC code (the number of check points, or the number of non-"-1" elements) increases less, thus resulting in lower complexity. For example... Figure 7 As shown, at a code rate of 24 / 28, the overall weight of the matrix is ​​106. At a code rate of 24 / 29, for a regular LDPC code, adding a 5th row results in a weight of 13, while for a split LDPC code, adding a 5th row results in a weight of 2 (the weight of the decoded matrix is ​​calculated using the equivalent decoding matrix). Therefore, if we compare performance while leveling the complexity, the decoding complexity of 10 iterations for a regular LDPC code is equivalent to the decoding complexity of 11 iterations for a split LDPC code. Thus, compared to a regular LDPC code, a split LDPC code offers a certain performance gain in decoding.

[0136] The splitting of a split LDPC code has a certain order and correlation. For example, in a split LDPC code, the correlation between rows can be represented by a sequence, which can be called a split sequence.

[0137] Figure 8 This is an example of the basis matrix of a split LDPC code.

[0138] like Figure 8As shown, column 1 represents the row number, and column 2 is a sequence representing the correlation between rows. In column 2, non-zero values ​​indicate split rows, and a value of 0 indicates a non-split row. For example, if column 1 of row 9 is 4, it means that row 9 splits from row 4. As another example, if column 2 of row 13 is 0, it indicates that row 13 is a non-split row. Of course, row numbers can also start counting from 0; for example, row 8 corresponds to 3 (i.e., column 1 of row 9 is 4), which also falls within the scope of this application.

[0139] The basis matrix of a split LDPC code can be as follows Figure 8 The data shown may include both split rows and non-split rows, or it may include split rows but exclude non-split rows.

[0140] This application does not limit the storage method of the sequence representing the correlation between rows in the embodiments; for example, it can be as follows: Figure 8 The sequence shown is a column of a matrix, and can also be stored independently of the base matrix. This sequence can also be in other forms, such as a mapping table or mapping pairs.

[0141] The matrix structure of the base graph and the description of the core check column of the split LDPC code can be found in the 5G LDPC code.

[0142] 4. Non-zero elements and zero elements

[0143] In the check matrix, zero elements indicate that there is no connection between the variable node and the check node, while non-zero elements indicate that there is a connection between the variable node and the check node.

[0144] In the basis matrix, the zero element represents Z. c A square matrix of order Z consisting entirely of zeros, where non-zero elements represent Z. c An identity matrix of order Z or based on Z c A cyclic permutation matrix of order identity matrix, where the values ​​of non-zero elements represent cyclic shift or offset values ​​relative to the identity matrix.

[0145] This application does not limit the specific representation of zero and non-zero elements. For example, such as Figure 2 In the parity check matrix H shown, "0" represents zero elements and "1" represents non-zero elements. Similarly, in the basis matrix, "-1" represents zero elements and "non-negative value" represents non-zero elements.

[0146] 5. Redundancy version (RV)

[0147] LDPC codes support incremental redundancy (IR) hybrid automatic repeat request (HARQ) functionality. The system specifies the starting point for retransmission codewords from a particular RV. Different RVs are used for the initial transmission and each subsequent retransmission to gradually accumulate redundant bits and complete the incremental redundancy HARQ operation.

[0148] Figure 9 This is a diagram illustrating the reading of codewords. For example... Figure 9 As shown, the encoded codeword sequence is placed sequentially in a circular buffer. For a specific code rate, codewords are read sequentially starting from a certain starting position in the circular buffer. If the codeword sequence is not completely read before reaching the end, it continues reading from the beginning. The number of codewords read conforms to the specific code rate. Here, RV represents the starting point for reading codewords in the circular buffer; different RV values ​​indicate different starting points.

[0149] The relevant terms used in the embodiments of this application have been described above, and will not be explained further below.

[0150] Currently, the parity check equations (PCEs) of the initial transmission and retransmission may not be continuous. For example, taking a boost value of 1 (i.e., the base matrix and the parity check matrix are the same), in the initial transmission, the information column and the core parity column of the PCE matrix are sent, where the core parity column consists of columns 1 to 4 of the PCE column. In the retransmission, the starting point for transmission is column 9 of the PCE column. In this case, columns 5 to 8 of the PCE column are not sent, and the codewords of the initial and retransmissions are not continuous. Correspondingly, the PCE equations of the initial and retransmissions are also not continuous. As can be seen from the above, the splitting of the split LDPC code has a certain order and correlation. If the PCE equations of the initial and retransmissions are not continuous, it may lead to more PCE equations than the scheme in this application, thus making the decoder more complex and detrimental to decoding.

[0151] To illustrate with a specific example, taking a boost value of 1, the core matrix of the check matrix has 4 rows and 26 columns. The first 22 columns are information columns, and the last 4 columns are core check columns. The 5th check row is derived from the 2nd check row, the 9th check row is derived from the 2nd check row, and the 13th check row is derived from the 5th check row. The check equations for each check row are as follows:

[0152] The check equation for the second check row is: V1+V2+V3+V4+V5+V6+V7+V8+V9+V10+V11+V12+V13+V14+V15=0;

[0153] The check equation for the 5th check row is: V2+V4+V6+V8+V10+V12+V14+V16=0;

[0154] The check equation for the 9th check row is: V1+V5+V9+V13+V20=0;

[0155] The check equation for the 13th check row is: V2+V6+V10+V14+V24=0.

[0156] When core verification is used, i.e., when sending the first to fourth verification columns (i.e., sending the core verification columns), the resulting verification equations include:

[0157] V1+V2+V3+V4+V5+V6+V7+V8+V9+V10+V11+V12+V13+V14+V15=0.

[0158] As the bit rate decreases, the 5th, 9th, and 13th check columns are all sent.

[0159] After the 5th check column is sent, the resulting check equation is:

[0160] V1+V3+V5+V7+V9+V11+V13+V15+V16=0:

[0161] V2+V4+V6+V8+V10+V12+V14+V16=0.

[0162] After the 9th check column is sent, the resulting check equation is:

[0163] V3+V7+V11+V15+V16+V20=0;

[0164] V2+V4+V6+V8+V10+V12+V14+V16=0;

[0165] V1+V5+V9+V13+V20=0.

[0166] After the 13th check column is sent, the resulting check equation is:

[0167] V3+V7+V11+V15+V16+V20=0;

[0168] V4+V8+V12+V16+V24=0;

[0169] V1+V5+V9+V13+V20=0;

[0170] V2+V6+V10+V14+V24=0.

[0171] In this case, the decoder supports the following seven types of check equations:

[0172] V1+V2+V3+V4+V5+V6+V7+V8+V9+V10+V11+V12+V13+V14+V15=0;

[0173] V1+V3+V5+V7+V9+V11+V13+V15+V16=0;

[0174] V2+V4+V6+V8+V10+V12+V14+V16=0;

[0175] V3+V7+V11+V15+V16+V20=0;

[0176] V1+V5+V9+V13+V20=0;

[0177] V4+V8+V12+V16+V24=0;

[0178] V2+V6+V10+V14+V24=0.

[0179] However, during the initial transmission, the information columns and core check columns of the parity check matrix (i.e., the first 26 columns) were sent. During retransmission, the starting point for transmission was the 9th column of the parity check matrix (i.e., the 31st column of all columns, or the 5th column of the extended parity check). The 5th column of the parity check matrix (i.e., the 27th column of all columns, or the 1st column of the extended parity check) was not sent. In this case, after eliminating the 2nd check column using the 5th check column, we directly eliminate the 2nd check column based on the 9th check column, resulting in the following parity check equation:

[0180] V2+V3+V4+V6+V7+V8+V10+V11+V12+V14+V15+V20=0;

[0181] V1+V5+V9+V13+V20=0.

[0182] Among them, V2+V3+V4+V6+V7+V8+V10+V11+V12+V14+V15+V20=0 does not belong to the previous 7 check equations. That is, because the check columns were not sent in order, an extra check equation was generated. If a check equation for a 13th check column is added, then another check equation will be added. Therefore, the number of check equations supported on the decoding side will increase.

[0183] Thus, depending on whether the check column is sent or not, more check equations will be generated, which will make the decoder design more complex.

[0184] To address this problem, this application provides a communication method and a communication device that can control the number of parity equations by limiting the transmission order of the split-related parity columns, thereby reducing the complexity of decoder control and design.

[0185] The method embodiments of this application are described below with reference to the accompanying drawings.

[0186] Figure 10 This is a schematic flowchart of the communication method 1000 provided in this application.

[0187] Understandably, method 1000 can be executed by a first communication device and a second communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component used in that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the "second communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, a decoding device, etc.), a component used in that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it.

[0188] Method 1000 may include at least a portion of the following:

[0189] Step 1001: The first communication device acquires the LDPC codeword.

[0190] The LDPC codeword is obtained by encoding the information to be encoded based on the LDPC parity check matrix. The LDPC codeword is the LDPC codeword for retransmission, or in other words, the LDPC codeword is the LDPC codeword used for retransmission.

[0191] The embodiments of this application do not limit the implementation method of the first communication device acquiring LDPC codewords. In some implementations, the first communication device can encode all the information bits to be encoded based on the LDPC parity check matrix to obtain all LDPC codewords. Then, in the event of a retransmission, it can obtain the LDPC codeword for retransmission from all the LDPC codewords according to the starting point corresponding to the RV specified by the system. In other implementations, the first communication device can also encode the portion transmitted each time. In this case, the first communication device can encode the portion of the LDPC parity check matrix corresponding to the LDPC codeword for retransmission based on the starting point corresponding to the RV specified by the system to obtain the LDPC codeword for retransmission. In other implementations, the first communication device can also receive the LDPC codeword for retransmission from other communication devices.

[0192] The starting point for this retransmission can be one of multiple starting points, with different starting points corresponding to different RVs. Multiple starting points can correspond to different columns of the parity check matrix. For ease of description, the starting point for this retransmission will be simply referred to as the first starting point.

[0193] In the embodiments of this application, the setting of the starting point is related to the distribution of the split rows. A split row can refer to a row obtained by splitting other rows, and the following relationship exists between the split row and the split row: the first n rows of the split row... c The columns containing the non-zero elements of the n elements form the first column set, and the first n elements of the split row are... c The columns containing the non-zero elements of n form the second column set, and the second column set is properly contained in the first column set, where n c The sum of the number of information columns and core check columns in the verification matrix, or in other words, n c This represents the number of columns in the core matrix.

[0194] In some implementations, the first starting point is adjacent to the second starting point, and the second starting point belongs to multiple starting points. The columns between the first and second starting points form a third column set, which corresponds to the first row set. The first row set includes at least one split group, and each split group corresponds to a first row (i.e., the parent row, such as a row in the core matrix). Different split groups correspond to different first rows. Each split group includes at least one second row, which is a split row. Each split group includes all the split rows obtained by splitting its corresponding first row.

[0195] Two adjacent starting points can be understood as follows: the RV numbers corresponding to the two starting points are adjacent. For example, there are four redundant versions: RV0, RV1, RV2, and RV3. Taking the starting point corresponding to RV1 as an example, the starting point corresponding to RV1 is adjacent to the starting point corresponding to RV2, and also adjacent to the starting point corresponding to RV0. However, the starting point corresponding to RV1 is not adjacent to the starting point corresponding to RV3. Two adjacent starting points can also be understood as follows: there are no other starting points between the two starting points. In the embodiments of this application, the second starting point can be a starting point adjacent to the first starting point after the first starting point. For example, in the above example, the starting point adjacent to the starting point corresponding to RV1 is the starting point corresponding to RV2.

[0196] The third column set corresponds to the first row set. It can be defined as follows: the difference between the column number of the third column set and K (or the column number minus K) equals the row number of the first row set, where K is the number of information columns in the parity check matrix, or the number of information bits, or the information length. For example, if the column numbers of the third column set are 27, 28, 29, and 30, and K is 22, then the row numbers of the first row set are 5, 6, 7, and 8.

[0197] A row split can include all the split rows obtained from a single row, including those directly derived from that row and those indirectly derived from it. Rows indirectly derived from a single row can refer to rows further split from those directly derived from that row. For example, row 36 is derived from row 4, row 39 from row 4, row 37 from row 36, row 41 from row 39, and row 68 from row 37. Rows 36, 37, 38, 39, and 68 can all be considered as derived from row 4, and all of them lie between two adjacent starting points. The parent row is typically the row included in the core matrix.

[0198] For example, the first set of rows may include all split groups (or split rows), that is, at least one of the aforementioned split groups is all the split groups. In other words, the columns corresponding to all split rows may be located between a set of adjacent starting points.

[0199] Figure 11 This is an example where all the columns corresponding to the split rows are located between adjacent starting points.

[0200] Figure 11The first column of the matrix shown represents the row numbers of the base matrix, the second column indicates the splitting relationship, and columns 3 through 70 represent the base matrix. A value in columns 3 through 70 represents a Zc×Zc matrix. For example, if Zc is 2, the first value in columns 3 through 70 can represent a 2×2 matrix. Each value represents a 2×2 matrix, which can be determined by the translation value at the corresponding position. A "0" in the second column indicates that the row is not a split row, and a non-"0" value in the second column indicates that the row is a split row, and is derived from the row with the non-"0" value. For example, if the 9th row in the second column is 4, it means that the 9th row is a split row and is derived from the 4th row.

[0201] The following explanation uses Zc as an example of 1. In this case... Figure 11 The matrix shown is the parity check matrix.

[0202] like Figure 11 As shown, rows 9, 10, 11, 12, 16, 18, 20, 21, 22, 23, 25, 26, 27, 28, 33, 36, and 37 are split rows. If Zc is not 1, then the Zc rows obtained by promoting these rows are also split rows. In this case, we can:

[0203] Set RV x The starting point is A, and A <= (22+8)*Zc+1 = (22+8)*1+1 = 31;

[0204] Set RV x+1 The starting point is B, B>=(22+37)*Zc+1=(22+37)*1+1=60;

[0205] Where Zc represents the boost value.

[0206] In this way, all split lines are between starting point A (which can correspond to the first starting point) and starting point B (which can correspond to the second starting point), and starting point A and starting point B are adjacent, thus ensuring that these split lines are sent in a fixed order.

[0207] For example, a split group may be included between two adjacent starting points. When there are multiple split groups, different split groups may be located between different adjacent starting points. In this case, the first row set includes a split group. For example, the row set corresponding to any two adjacent starting points other than the first two starting points includes a split group.

[0208] Figure 12 This is an example of a split group between two adjacent starting points.

[0209] Figure 12The first column of the matrix shown represents the row numbers of the base matrix, the second column indicates the splitting relationship, and columns 3 through 70 represent the base matrix. A value in columns 3 through 70 represents a Zc×Zc matrix. For example, if Zc is 2, the first value in columns 3 through 70 can represent a 2×2 matrix. Each value represents a 2×2 matrix, which can be determined by the translation value at the corresponding position. A "0" in column 2 indicates that the row is not a split row, while a non-"0" value in column 2 indicates that the row is a split row, derived from the row with that non-"0" value. For example, if row 9 in column 2 is 1, it means that row 9 is a split row, derived from row 1. If Zc is 1, then... Figure 12 The matrix shown is the parity check matrix, meaning that the base matrix before promotion is the same as the parity check matrix after promotion.

[0210] The following explanation uses Zc as an example of 1. In this case... Figure 12 The matrix shown is the parity check matrix.

[0211] like Figure 12 As shown, rows 9, 10, 11, 15, 17, 18, 19, 20, 22, 23, 24, 29, 32, 34, 36, 37, and 39 are split rows. Specifically, the second column of row 36 is 4, indicating that row 36 is split from row 4; the second column of row 39 is 4, indicating that row 39 is split from row 4; the second column of column 37 is 36, indicating that row 37 is split from row 36, and row 36 is itself split from row 4. Thus, row 4 is the parent row of rows 36, 39, and 37.

[0212] Since there are no splitting relationships between check rows related to different parent lines, exchanging the transmission order of check rows between different parent lines will not generate additional check equations (or decoding patterns). In this way, by setting rows split from the same parent line between two adjacent RV start points, it can be ensured that these rows are sent in a fixed order, avoiding the generation of additional check equations.

[0213] In this case, it is possible to:

[0214] Set RV x The starting point is A, and A≤(22+35)*Zc+1=(22+35)*1+1=58;

[0215] Set RV x+1 The starting point is B, and B≥(22+39)*Zc+1=(22+39)*1+1=62;

[0216] Where Zc represents the boost value.

[0217] In this way, all the split lines with the 4th line as the parent line are between the starting point A (which can correspond to the first starting point) and the starting point B (which can correspond to the second starting point). Since the starting point A and the starting point B are adjacent, it can be guaranteed that these split lines are sent in a fixed order.

[0218] If Zc is greater than 1, then Figure 12 One row in the matrix actually represents row Zc of the parity check matrix. Figure 12 In this context, a split group actually represents Zc split groups. For example, taking Zc as 2 as an example, Figure 12 The first line of the two lines obtained from the promotion of line 36, the first line of the two lines obtained from the promotion of line 37, and the first line of the two lines obtained from the promotion of line 39 form a split group. The second line of the two lines obtained from the promotion of line 36, the second line of the two lines obtained from the promotion of line 37, and the second line of the two lines obtained from the promotion of line 39 form a split group, for a total of two split groups.

[0219] For example, all split groups can be divided into several large groups, each large group comprising one or more split groups, and different large groups can be located between different adjacent starting points. In this case, the first row set comprises one large group. For example, the row sets corresponding to any two adjacent starting points other than the first two starting points comprise one large group.

[0220] Figure 13 This is an example of multiple split groups between two adjacent starting points.

[0221] Figure 13 The first column of the matrix shown represents the row numbers of the base matrix, the second column indicates the splitting relationship, and columns 3 through 70 represent the base matrix. A value in columns 3 through 70 represents a Zc×Zc matrix. For example, if Zc is 2, the first value in columns 3 through 70 can represent a 2×2 matrix. Each value represents a 2×2 matrix, which can be determined by the translation value at the corresponding position. A "0" in the second column indicates that the row is not a split row, and a non-"0" value in the second column indicates that the row is a split row, and is derived from the row with the non-"0" value. For example, if the 9th row in the second column is 1, it means that the 9th row is a split row and is derived from the 1st row.

[0222] The following explanation uses Zc as an example of 1. In this case... Figure 13 The matrix shown is the parity check matrix.

[0223] like Figure 13 As shown, rows 9, 10, 11, 15, 17, 18, 19, 20, 22, 23, 24, 29, 32, 34, 36, 37, and 39 are split rows.

[0224] In this row, the second column of row 9 is 1, indicating that row 9 is derived from row 1; the second column of row 17 is 1, indicating that row 17 is derived from row 1; the second column of column 20 is 9, indicating that row 20 is derived from row 9, which in turn is derived from row 1; the second column of column 34 is 9, indicating that row 34 is derived from row 9, which in turn is derived from row 1. Thus, row 1 is the parent row of rows 9, 17, 20, and 34.

[0225] The second column of row 10 is 3, indicating that row 10 is derived from row 3; the second column of row 15 is 3, indicating that row 15 is derived from row 3; the second column of column 22 is 10, indicating that row 22 is derived from row 10, and row 10 is derived from row 3. Thus, row 3 is the parent row of rows 10, 15, and 22.

[0226] The second column of row 11 is 2, indicating that row 11 is derived from row 2; the second column of row 19 is 2, indicating that row 19 is derived from row 2; the second column of column 18 is 11, indicating that row 18 is derived from row 11, and row 11 is derived from row 2. Thus, row 2 is the parent row of rows 11, 18, and 19.

[0227] In this case, it is possible to:

[0228] Set RV x The starting point is A, and A≤(22+8)*Zc+1=(22+8)*1+1=31;

[0229] Set RV x+1 The starting point is B, B≥(22+34)*Zc+1=(22+34)*1+1=57;

[0230] Where Zc represents the boost value.

[0231] In this way, the split lines with the first line as the parent line, the split lines with the second line as the parent line, and the split lines with the third line as the parent line are all between the starting point A (which can correspond to the first starting point) and the starting point B (which can correspond to the second starting point). Since the starting point A and the starting point B are adjacent, it can be guaranteed that these split lines are sent in a fixed order.

[0232] If Zc is greater than 1, then Figure 13 One row in the matrix actually represents row Zc of the parity check matrix. Figure 13 In this context, a split group actually represents Zc split groups. For example, taking Zc as 2 as an example, Figure 13The first line of the two lines obtained by promoting line 11, the first line of the two lines obtained by promoting line 18, and the first line of the two lines obtained by promoting line 19 form a split group. The second line of the two lines obtained by promoting line 11, the second line of the two lines obtained by promoting line 18, and the second line of the two lines obtained by promoting line 19 form a split group, for a total of two split groups.

[0233] For example, if combined Figure 12 and Figure 13 Then, three of the multiple starting points can be as follows:

[0234] RV x The starting point is A, and A≤(22+8)*Zc+1;

[0235] RV x+1 The starting point is B, and (22+34)*Zc+1≤B≤(22+35)*Zc+1;

[0236] RV x+2 The starting point is C, where C ≥ (22+34)*Zc+1.

[0237] In some implementations, if there are multiple split groups, rows from different split groups can be interspersed. For example, combining... Figure 13 The split groups consisting of Zc rows corresponding to rows 9, 17, 20, and 34, the split groups consisting of Zc rows corresponding to rows 10, 15, and 22, and the split groups consisting of Zc rows corresponding to rows 11, 18, and 19 are interspersed. This makes row redistribution more flexible.

[0238] In some implementations, the rows corresponding to the columns between two adjacent starting points (such as the first row set) can include not only split rows but also one or more third rows, where the third rows are non-split rows. This avoids the two adjacent starting points being too close together and allows for more flexible row redesign.

[0239] For example, if there are multiple split groups, some or all of the split groups can be separated by non-split rows, that is, non-split rows can be located between two split groups. For example, combining Figure 12 The split group consisting of Zc rows corresponding to rows 9, 17, 20 and 34 and the split group consisting of Zc rows corresponding to rows 36, 37 and 39 can be separated by the non-split row of row 35.

[0240] For example, split rows in a split group can also be separated by non-split rows; that is, non-split rows can be located between split rows included in the split group. For example, combining Figure 12The split group consisting of rows Zc corresponding to rows 36, 37, and 39 is separated by the non-split row of row 35.

[0241] In step 1002, the first communication device sends an LDPC codeword for retransmission, and correspondingly, the second communication device receives the LDPC codeword for retransmission from the first communication device.

[0242] Because LDPC codewords may introduce channel noise signals during transmission, the LDPC codeword sequence output or transmitted by the first communication device may be different from the LDPC codeword sequence received by the second communication device.

[0243] Step 1003: The second communication device decodes the retransmitted LDPC codeword.

[0244] During decoding, the second communication device uses the eliminated LDPC parity-check matrix to perform decoding based on the splitting relationship between rows.

[0245] For example, the second communication device decodes the LDPC codeword transmitted initially, the LDPC codeword transmitted retransmitted, and the start point of the retransmission. The descriptions of the LDPC codeword and the start point of the retransmission, etc., can be found above and will not be repeated here.

[0246] Thus, in method 1000, by setting the column corresponding to at least one split group between two adjacent starting points, it can be ensured that the split rows in at least one split group are sent in sequence, thereby reducing the generation of check equations, which helps to reduce the complexity of the decoder and thus helps to improve the decoding performance.

[0247] The starting points involved in the embodiments of this application can be defined based on the parity check matrix as described above, or they can be defined based on the base matrix. When the starting points are defined based on the base matrix, if the starting point is set to a column of the base matrix, the actual transmission starting point is the first column of column Zc obtained by column promotion. For example, if Zc is 3, the starting point is the 7th column of the base matrix, and the actual transmission starting point is the first column of the 3 columns obtained by promotion from the 7th column. Correspondingly, the split group mentioned above is also the grouping of rows in the base matrix.

[0248] The various embodiments of this application can be implemented independently or in combination. Descriptions of the same terms, steps, etc., in the various embodiments, examples, and implementations can be referenced or cited in relation to each other.

[0249] If an LDPC parity-check matrix can be obtained by performing a first transformation on the LDPC parity-check matrix provided in the embodiments of this application, then the LDPC parity-check matrix can be considered to be included within the protection scope of this application. Similarly, if an LDPC base matrix can be obtained by performing a first transformation on the LDPC base matrix provided in the embodiments of this application, then the LDPC base matrix can be considered to be included within the protection scope of this application. The first transformation includes at least one of the following operations: row permutation, column permutation, or translation value transformation. Row permutation may include permuting one or more rows. Column permutation may include permuting one or more columns. Translation value transformation may include simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more rows in the base matrix, and / or simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more columns in the base matrix.

[0250] Row permutations on the LDPC base matrix and its corresponding parity-check matrix are equivalent to swapping the order of the parity-check equations, without changing the parity relationship. Column permutations or shift transformations on the LDPC base matrix, its corresponding shift matrix, and its corresponding parity-check matrix are equivalent to swapping the order of the encoded bits, which can be considered as reordering the encoded result. Restoring the order during decoding yields the same effect as the matrix before the column transformation. Therefore, the LDPC base matrix obtained by the first transformation can be considered equivalent to the LDPC base matrix provided in the embodiments of this application, and the LDPC parity-check matrix obtained by the first transformation can be considered equivalent to the parity-check matrix corresponding to the LDPC base matrix provided in the embodiments of this application.

[0251] The above text combined Figures 1 to 13 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figures 14 to 16 This describes an embodiment of the apparatus described in this application.

[0252] It is understandable that, in order to achieve the functions described in the above embodiments, Figures 14 to 16 The apparatus includes hardware structures and / or software modules that perform various functions. These apparatuses can be used to implement the functions of the first or second communication device in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. Those skilled in the art will readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0253] Figure 14 This is a schematic diagram of the structure of an apparatus provided in an embodiment of this application.

[0254] In this application embodiment, the first communication device or the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a functional unit, or two or more functions can be integrated into one unit. Each function can be implemented in hardware or in the form of software functional modules. Figure 14 The division shown is illustrative and represents only one logical functional division. In actual implementation, there may be other division methods.

[0255] like Figure 14 As shown, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0256] When device 10 is used to implement the function of the first communication device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the first communication device, such as step 1002, and processing unit 12 is used to execute the processing steps of the first communication device, such as step 1001. When device 10 is used to implement the function of the second communication device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the second communication device, such as step 1002, and processing unit 12 is used to execute the processing steps of the second communication device, such as step 1003.

[0257] Optionally, the device 10 also includes a storage unit 13 for storing instructions and / or data.

[0258] When the first communication device or the second communication device does not perform the transmitting and receiving steps or the processing steps, the device 10 may also not include the transmitting and receiving unit 11 or the processing unit 12.

[0259] For a more detailed description of the transceiver unit 11 and the processing unit 12, please refer to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0260] Figure 15 This is another schematic diagram of the device provided in the embodiments of this application.

[0261] The device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, which stores instructions. When the device 20 is used to implement the method described above, the processing circuit 21 executes the instructions in the memory 23 to implement the function of the processing unit 12 described above.

[0262] Optionally, the device 20 further includes a memory 23 for implementing the functions of the aforementioned storage unit 13.

[0263] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 can be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 executes instructions to implement the function of the processing unit 12, and the transceiver circuit 22 implements the function of the transceiver unit 11.

[0264] Optionally, device 20 can be a first communication device or a second communication device, and correspondingly, the transceiver circuit can be a transceiver.

[0265] Optionally, device 20 can be a chip used in a first communication device or a second communication device, and correspondingly, the transceiver circuit can be an input / output interface.

[0266] For example, when device 20 is a chip applied to a first communication device or a second communication device, the chip implements the functions of the first communication device or the second communication device in the above method embodiments. The chip receives information from other modules (such as radio frequency modules or antennas) in the first communication device or the second communication device, which is sent to the first communication device or the second communication device by other devices; or, the chip sends information to other modules (such as radio frequency modules or antennas) in the first communication device or the second communication device, which is sent to other devices by the first communication device or the second communication device.

[0267] Figure 16 This is a schematic diagram of a chip system provided in an embodiment of this application. The chip system 30 (or may also be called a processing system) includes logic circuitry 31 and an input / output interface 32.

[0268] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 30 to implement the methods and functions of the embodiments of this application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting processed information from the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0269] As an alternative, the chip system 30 may also include a memory unit.

[0270] As one option, the chip system 30 is used to implement the operations performed by the first communication device or the second communication device in the various method embodiments described above.

[0271] For example, logic circuit 31 is used to implement processing-related operations performed by the first communication device or the second communication device in the above method embodiments; input / output interface 32 is used to implement sending and / or receiving-related operations performed by the first communication device or the second communication device in the above method embodiments.

[0272] This application also provides a communication device including a processing circuit coupled to a memory for storing computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or to read the data stored in the memory, to perform the methods in the above-described method embodiments. Optionally, the processing circuit may be one or more. Optionally, the communication device includes a memory. Optionally, the memory may be one or more. Optionally, the memory may be integrated with the processing circuit, or may be separately disposed.

[0273] This application also provides a chip including a processing circuit coupled to a memory. The memory stores computer programs or instructions, and the processing circuit executes the computer programs or instructions stored in the memory to implement the methods executed by the first or second communication device in the above-described method embodiments. The memory may be located within the chip or independently of the chip, and is not limited thereto.

[0274] This application also provides a computer-readable storage medium having stored thereon computer instructions for implementing the methods executed by the first communication device or the second communication device in the above-described method embodiments.

[0275] This application also provides a computer program product comprising instructions that, when executed by a computer, implement the methods performed by the first communication device or the second communication device in the above-described method embodiments.

[0276] This application also provides a computer program that, when executed by a computer, implements the methods performed by the first communication device or the second communication device in the above-described method embodiments.

[0277] This application also provides a communication system, which includes at least one of the first communication device or the second communication device in the above embodiments.

[0278] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0279] It is understood that the processing circuit in the embodiments of this application may be a processor or a circuit in a processor for performing processing operations. The processor may include one or more of the following: a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0280] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored in non-volatile memory, such as the aforementioned memory 23 or at least a portion of the storage cells (e.g., one or more of ROM, flash memory, EPROM, or hard disk).

[0281] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Furthermore, the ASIC can be located in a first communication device or a second communication device. Alternatively, the processor and storage medium can exist as discrete components in the first or second communication device.

[0282] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive.

[0283] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0284] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments and is not intended to limit the scope of this application. The above examples are merely illustrative and are intended to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments to the specific numerical values ​​or scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

Claims

1. A communication method, characterized in that, The method includes: Obtain low-density parity-check LDPC codewords, where, The LDPC codeword is used for retransmission. The retransmission start point is one of a plurality of start points. The difference between the column number of the column adjacent to the retransmission start point and K is the row number of the row in the first row set. The first row set includes at least one split group. One split group corresponds to one first row, and different split groups correspond to different first rows. Each split group includes all second rows corresponding to the first row corresponding to the split group. The first row corresponds to a first column set, which includes the first n rows of the first row. c The column containing the non-zero elements of the n elements, the second row corresponds to the second column set, and the second column set includes the first n elements of the second row. c The column containing the non-zero elements of the n elements, the second column set is contained within the first column set, K is the number of information columns in the LDPC check matrix, and n c The sum of the number of information columns and core check columns in the LDPC check matrix; Send the LDPC codeword.

2. The method according to claim 1, characterized in that, The at least one split group is all split groups.

3. The method according to claim 1, characterized in that, The row set corresponding to any two adjacent starting points other than the first two starting points includes at least one split group.

4. The method according to any one of claims 1 to 3, characterized in that, The first row set also includes at least one third row, which is unrelated to the other rows of the LDPC check matrix.

5. The method according to claim 4, characterized in that, The first split group in the at least one split group includes a plurality of second rows, and some or all of the at least one third row is located between the plurality of second rows; and / or, The first row set includes a plurality of said split groups, and some or all of the at least one third row is located between the plurality of said split groups.

6. A communication method, characterized in that, The method includes: Obtain retransmitted low-density parity-check (LDPC) codewords, wherein the starting point for retransmitting the LDPC codewords is one of a plurality of starting points, and the difference between the column number of the column adjacent to the starting point of the LDPC codewords and K is the row number of a row in a first row set. The first row set includes at least one split group, one split group corresponds to one first row, and different split groups correspond to different first rows. Each split group includes all second rows corresponding to the first row corresponding to the split group. The first row corresponds to a first column set, and the first column set includes the first n rows of the first row. c The column containing the non-zero elements of the n elements, the second row corresponds to the second column set, and the second column set includes the first n elements of the second row. c The column containing the non-zero elements of the n elements, the second column set is contained within the first column set, K is the number of information columns in the LDPC check matrix, and n c The sum of the number of information columns and core check columns in the LDPC check matrix; Decode according to the LDPC codeword.

7. The method according to claim 6, characterized in that, The at least one split group is all split groups.

8. The method according to claim 6, characterized in that, The row set corresponding to any two adjacent starting points other than the first two starting points includes at least one split group.

9. The method according to any one of claims 6 to 8, characterized in that, The first row set also includes at least one third row, which is unrelated to the other rows of the LDPC check matrix.

10. The method according to claim 9, characterized in that, The first split group in the at least one split group includes a plurality of second rows, and some or all of the at least one third row is located between the plurality of second rows; and / or, The first row set includes a plurality of said split groups, and some or all of the at least one third row is located between the plurality of said split groups.

11. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1 to 10.

12. A communication device, characterized in that, Including processor and interface circuitry; The interface circuit is used to receive signals and transmit them to the processor or to output signals from the processor. The processor is configured to implement the method as described in any one of claims 1 to 10 by means of logic circuits and / or by executing computer programs, code, or instructions.

13. The communication device according to claim 12, characterized in that, The communication device is a chip or chip system.

14. A computer-readable storage medium, characterized in that, The storage medium stores computer programs, code, or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1 to 10.

15. A computer program product, characterized in that, It includes computer programs, code, or instructions that, when run, implement the method as described in any one of claims 1 to 10.

16. A communication system, characterized in that, include: A first communication device for performing the method as described in any one of claims 1 to 5, and a second communication device for performing the method as described in any one of claims 6 to 10.

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