Pseudomorphically fail-safe baud rate admission method calibrated across polarity differential reference

Abstract

The application discloses a quasi-state fail-safe baud rate admission method based on cross-polarity differential reference calibration, which comprises the following steps: through the receiving end, based on the fail-single-polarity constraint, the micro-reference pulse width is extracted and updated through front-end filtering and first logical polarity minimum pulse width dynamic; through the sending end, the configuration guide symbol of the second logical polarity is sent, and the receiving end is used to update the feature verification pulse width as the macro-unique anchor point with the reservation priority strategy; through the sending end, the pre-defined integrity calibration sequence is sent, and through the receiving end, the feature verification pulse width is cross-polarity signed scale reference calibrated according to the reference window measurement pulse width of the reference guide symbol, and is closed interval arithmetic verified through the micro-reference pulse width. Compared with the traditional scheme, the application has higher problem definition, clearer fail-safe mechanism, more complete utilization of single-polarity physical failure, clearer quasi-state boundary and the like.

Description

Technical Field

[0001] This application relates to the field of communications, specifically to mimicking fail-safe baud rate acceptance for transpolar differential reference calibration. Background Technology

[0002] In distributed industrial control scenarios such as multi-unit cascaded high-power converters, frequency converters, and power conversion systems (PCS), high-speed fiber optic or isolated differential communication is typically used between master and slave controllers via asynchronous serial encoding without an independent clock line. To meet the requirements of "plug-and-play" functionality, parameter-free configuration, and rapid self-healing after a brief link failure, the underlying hardware of the receiving end usually needs to have automatic candidate baud rate acquisition, physical layer identification, and fail-safe acceptance capabilities.

[0003] In traditional solutions, automatic baud rate technology can generally be categorized into a common architecture: it estimates the absolute time scale corresponding to the target baud rate by using start bits, preset characters, synchronization characters, high and low level pulse widths, edge time intervals, or pulse statistical distributions; once a certain local pulse or local statistical result is deemed "reliable," the system updates the baud rate accordingly. The common feature of this type of solution is that its core task is always to "recover an absolute value."

[0004] While this type of solution can operate in normal environments, it suffers from the following common shortcomings in harsh industrial environments, such as high-frequency mechanical vibration, frequent fiber optic plugging and unplugging, intermittent terminal disconnections and reconnections, and intense electromagnetic interference: 1. Cross-layer unauthorized trial and error problem: Traditional solutions typically estimate candidate baud rates at the lower layer first, and then rely on upper-layer protocol headers, cyclic redundancy checks (CRC), or software trial and error to confirm their validity. Once the lower layer makes an incorrect judgment on the absolute width of a local pulse, subsequent erroneous candidate values ​​will often be uploaded along the system path, causing unnecessary interruption burden and real-time control risks.

[0005] 2. Failure polarity is not transformed into verification conditions: Traditional schemes usually treat physical failure as a pure interference source, and fail to transform the failure polarity itself into a constraint condition in the candidate baud rate acceptance mechanism, thus missing the opportunity to establish a fail-safe one-way defense.

[0006] 3. Slow statistical convergence: Statistical convergence schemes usually require a large number of samples to stably approximate the true value, which is not conducive to rapid recovery under transient fault conditions.

[0007] 4. Insufficient reliability of single-point absolute value: Traditional solutions mostly estimate the absolute value based on the starting position, local pulse, preset character, or statistical pulse width. However, in industrial environments with strong interference, local pulses are easily affected by loss of light, cutting, insertion and removal, fragmentation, and burrs. This makes it difficult for the system not to calculate the single-point absolute value, but to determine whether the single-point absolute value is an illusion caused by random disturbance. Summary of the Invention

[0008] To address the aforementioned issues, this application proposes a mimicry-based fail-safe baud rate acceptance method for transpolar differential reference calibration, comprising: At the receiving end, based on the failure unipolar constraint, the micro reference pulse width is dynamically extracted and updated through front-end filtering and the minimum pulse width of the first logic polarity; wherein, the first logic polarity is the bus level state presented by the communication medium when it fails physically. The transmitting end sends a configuration guide with a second logical polarity whose length meets the preset requirement, and the receiving end updates the feature verification pulse width with a retention priority strategy as a macroscopic unique anchor point; wherein, the second logical polarity is an effective strong drive level state opposite to the first logical polarity; the preset requirement is used to ensure that the length of the configuration guide is greater than the maximum natural length of consecutive second logical polarities appearing in the asynchronous serial communication word format; The transmitter sends a predefined integrity calibration sequence, and the receiver measures the pulse width and the micro-reference pulse width according to the reference window of the reference guide in the integrity calibration sequence. The feature verification pulse width is then subjected to cross-polarity signed scale reference calibration, and closed-interval arithmetic verification is performed using the micro-reference pulse width. The integrity calibration sequence includes a first logical polarity, a second logical polarity, and a first logical polarity reference guide whose length satisfies a preset requirement with respect to the length of the configuration guide. If the cross-polarity signed scale reference calibration and the closed interval arithmetic verification are passed, the system enters a locked state, stops sending the configuration guide and the integrity calibration sequence, resulting in the absence of a complete acceptance sequence. In the locked state, the longest continuous window of the first logical polarity formed by the service is strictly shorter than the length of the reference guide, so that the idle window cannot satisfy the reference calibration relationship, thereby preventing erroneous updates.

[0009] The mimicry-based failure-safe baud rate acceptance method for transpolar differential reference calibration proposed in this application can bring the following benefits: 1. Higher problem definition: Traditional solutions mainly address "how to estimate the baud rate from the absolute width of the local pulse", while this application mainly addresses "how to prove in layers whether a candidate baud rate is worth accepting under the premise of failed unipolar prior, and naturally suppress erroneous updates after locking".

[0010] 2. Clearer fail-safe mechanism: The present application does not generically describe that "configuring a boot flag plus multi-layer verification can improve reliability", but explicitly distinguishes that under the condition that the preset failure unipolar model and the measurement error budget are valid, the simple configuration of the boot flag and the closed-interval arithmetic verification can form deterministic rejection for disturbances where wf≥Tbit and actually change the candidate admission measurement quantity; for disturbances with 0<wf<Tbit, the cross-polarity differential reference calibration is used to eliminate and false closure formed by equal-proportion error scaling, so that erroneous candidates whose residuals exceed the preset tolerance boundary or whose sequence form is not closed are deterministically rejected.

[0011] 3. More thorough utilization of unipolar physical failures: The present application directly converts the fault unipolar physical phenomena caused by optical fiber loss of light, bus disconnection, pull-up / pull-down / Fail-Safe bias into mathematical monotonic constraints, which is not fully utilized by general automatic baud rate solutions.

[0012] 4. Faster reloading: The present application uses the controlled Rbit first logic polarity reference boot flag in the complete admission sequence as the calibration source. Since = , the receiving end can independently complete before capturing the edge closed capture; once the Kbit second logic polarity configuration boot flag is captured subsequently, the cross-polarity reference calibration can be quickly performed.

[0013] 5. Safer locked state: The present application is not only "cautious during admission", but further utilizes two mechanisms after "being locked": the first logic polarity window of normal service is shorter than the preferred Rbit reference boot flag, and the complete admission sequence is missing, to suppress the re-admission condition, so it is safer than solutions continuously exposed to update conditions.

[0014] 6. Lower cross-layer burden: The main screening process of candidate values is completed in the physical layer in a closed manner, without waking up the CPU, performing packet assembly, or CRC, which is beneficial to reducing the upper-layer interrupt burden and software trial-and-error overhead caused by the upward transmission of erroneous candidate values.

[0015] 7. Suitable for pure hardware implementation: The main functions of the present application can be implemented by FPGA / CPLD / ASIC state machines, comparators, counters, filters and latches, and are suitable for integration of underlying hardware transceiving links. Brief Description of the Drawings

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and the description thereof are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a schematic flowchart of the mimetic fail-safe baud rate acceptance method with cross-polarity differential reference calibration in the embodiments of the present application; Figure 2 is a schematic implementation flowchart of the fail-safe candidate baud rate acceptance overall state machine under a certain scenario in the embodiments of the present application; Figure 3 is a schematic path comparison diagram between the conventional solution and the present application under a certain scenario in the embodiments of the present application; Figure 4 is a schematic diagram of the relationship between the NRZ region and the configuration preamble length under normal conditions under a certain scenario in the embodiments of the present application; Figure 5 is a schematic diagram of a receiver using closed edge capture under a certain scenario in the embodiments of the present application; Figure 6 is a schematic diagram related to no idle acquisition state and locking state in the original frame under a certain scenario in the embodiments of the present application; Figure 7 is a schematic diagram of strict fail-safe for wf>=1bit using only the configuration preamble under a certain scenario in the embodiments of the present application; Figure 8 is a schematic diagram of isometrically scaled mimetic false closure and cross-polarity differential reference calibration in the 0<wf<1bit scenario under a certain scenario in the embodiments of the present application; Figure 9 is a schematic diagram of the mimetic boundary case under a certain scenario in the embodiments of the present application; Figure 10 is a schematic diagram related to the idle acquisition state and locking state with I bits existing in the original frame under a certain scenario in the embodiments of the present application; Figure 11 is a schematic diagram of morphological spatiotemporal interlock verification and temporal uniformity check of the acceptance constraint sequence under a certain scenario in the embodiments of the present application. DETAILED DESCRIPTION

[0017] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the specific embodiments of the present application and the corresponding accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of them. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present application.

[0018] The technical solutions provided by each embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0019] As Figure 1 shown, the embodiments of the present application provide a mimetic fail-safe baud rate acceptance method with cross-polarity differential reference calibration, including: S101: Based on the failure unipolar constraint, the micro reference pulse width is dynamically extracted and updated through front-end filtering and the minimum pulse width of the first logic polarity; wherein, the first logic polarity is the bus level state presented by the communication medium when it fails physically.

[0020] First, this application is based on the premise of unipolar failures that are common in industrial settings and have clear physical origins. This premise is not an abstract assumption, but rather stems directly from the failure manifestations of the receiving medium and the bus physical layer: (1) When the optical fiber loses light, the optical power suddenly drops, is plugged in or unplugged, the connector jitters, the optical module loses power, or the front-end comparator is out of normal operating range, the output of the receiver usually does not fluctuate symmetrically between the two logic polarities, but is more likely to collapse to a default logic state constrained by the comparator threshold, the bias network, or the subsequent recovery circuit. This default logic state is defined as the "first logic polarity" in this case, which can be adjusted to the desired physical polarity by an inverter.

[0021] (2) For differential / single-ended buses with fail-safe bias networks, pull-up / pull-down networks, or high-impedance bus constraints, when the transceiver loses active drive or the bus enters a high-impedance state, the bus potential will collapse to a default direction due to the constraints of pull-up, pull-down, resistor voltage division, or fail-safe bias. This default direction can also be logically defined as the "first logic polarity".

[0022] (3) In scenarios such as mechanical vibration, micro-interruption, pulse chopping, and poor contact, the direct consequence of physical faults is usually that the actively sent second logical polarity pulse (described in detail below) is locally shredded, cut off, shortened, or missing, rather than being stretched in the opposite direction. Therefore, logically, the first logical polarity is more likely to be inserted, maintained, or broadened, while the second logical polarity is more likely to be shortened, split, or missing.

[0023] Accordingly, this application limits the failure studied to a preset failure unipolar model after polarity normalization and front-end filtering: under the condition of excluding internal reverse failure of the receiver, bipolar high-energy interference, and reverse failure of the Fail-Safe bias network itself, the preset failure will not cause the continuous segment of the second logical polarity to increase, nor will it cause the controlled reference segment of the first logical polarity to shorten; the preset failure is more likely to manifest as the first logical polarity being injected, maintained, or broadened, and the second logical polarity being fragmented, shortened, or missing. Faults exceeding the preset failure unipolar model are not included in the deterministic rejection conclusion, but are enhanced by morphological interlocking, time consistency checks, and reacquisition mechanisms.

[0024] This set of monotonic constraints is not only the physical basis for constructing a rigorous fail-safe proof in this application, but also constitutes the primary source of constraints for the candidate baud rate acceptance order in this application. The fundamental gap in traditional schemes is not the lack of more valuation techniques, but the failure to elevate the aforementioned unipolar physical phenomena to the primary constraints in the acceptance order, and the failure to transform the fault space into a direction-governed, identifiable space that can be utilized in a fail-safe manner.

[0025] Specifically, such as Figure 2 As shown, the bus level state presented by the communication medium in the event of physical failure is defined as the first logic polarity. Asymmetric polarity physical layer binding is implemented, specifying the bus level state that the receiver is more likely to present when the communication medium experiences physical failure as the first logic polarity. Typically, the first logic polarity is also the same as the stop bit / idle state. If the first logic polarity is not the desired stop bit / idle state, an inverter can be added at the receiver to resolve this. The first logic polarity is not merely a passive observation object, but is explicitly introduced as a constraint source in the candidate baud rate acceptance mechanism.

[0026] In addition, to facilitate the interpretation of the parameters in the embodiments of this application, the parameters are defined in advance. The parameter symbols defined in this application are as follows: X: Total number of bits in a Non-Return to Zero (NRZ) word. X is determined by the protocol word format and includes a start bit, data bits, optional parity bit, and stop bit. Since a normal NRZ word starts with a second logical polarity start bit and the stop bit is a first logical polarity, the longest possible consecutive second logical polarity segment in a normal service word is X-1. Within a word excluding inter-frame idle time, if the data bits, optional parity bit, and stop bit are all of the first logical polarity, the longest possible consecutive first logical polarity segment in a normal NRZ word is also X-1.

[0027] K: Length of the second logical polarity configuration guide. K is preset or constructed by the sender and is used to form a macroscopically unique anchor point for the second logical polarity. To avoid consecutive segments of the second logical polarity in ordinary services being mistaken for configuration guides, K should satisfy: K>X-1.

[0028] I: Inter-frame idle length. I is determined by the inter-frame idle rules of the original service protocol; if the inter-frame idle length is variable, then I is taken from the receiver. The maximum number of inter-frame idle bits that may occur in normal services within the capture range.

[0029] R: Length of the first logical polarity reference window. R is determined by the original physical layer stop bits, inter-frame idle time, extended idle time, protocol harmless idle time, or the first logical polarity window actively constructed by the sender, and is used to form... Reference window. Since the longest possible first logical polarity continuous window that can naturally form when all first logical polarity data / check bits, stop bits, and 1-bit inter-frame idle overlap in normal services is I + X - 1, the theoretical range of R is R ≥ I + X. In this embodiment, R = I + X is preferred, making the controlled R-bit first logical polarity reference guide 1 bit longer than the naturally longest first logical polarity window in normal services, thus forming a strict length distinction. In other embodiments, R can be greater than I + X.

[0030] D: Signed differential bit length. D is determined by the length R of the first logical polarity reference window and the length K of the second logical polarity configuration guide: D = RK. In the embodiments of this application, it is preferred that R = I + X: D = I + XK. In other embodiments, D is determined according to the actual value of R.

[0031] When D>0 Strength When D=0, and Isoscale; when D < 0, Shorter than As long as K satisfies the second logical polarity unique anchor point requirement, R satisfies the first logical polarity reference window maximality requirement, and the preset scale relationship of D=RK can be combined All calibrations can be used as implementation methods in this application.

[0032] Microscopic reference pulse width. This is the candidate 1-bit micro-reference pulse width extracted by the receiving end from the continuous pulse width of the first logic polarity. Unable to / K or Instead of being obtained by reverse calculation of / R, the receiver counts and measures the bus level using a high-speed sampling clock Ts. For the first logic polarity continuous pulse width after filtering, the receiver can use sliding minimum, minimum hold with confidence counting, lower envelope tracking, or equivalent hardware counting methods to form a signal. .

[0033] Configure the guide to measure the pulse width (also known as the feature verification pulse width). This refers to the duration measured by the receiving end for configuring the second logical polarity of the K-bit bootstrap. The scaling relationship is as follows: ≈K* .

[0034] : The pulse width is measured by the reference window (also known as the duration of the reference guide). This is the duration measured by the receiver for the first logical polarity reference window of Rbit. Its scaling relationship is: ≈R* ,and and The two satisfy a preset signed difference relationship: - ≈D* That is: |( - )-D* |≤ΔD.

[0035] The periodicity of idle positions between original service frames. This indicates the period at which available inter-frame idle positions appear within the original service frame. This period can be given by protocol presets, system initialization parameters, transmitter broadcast parameters, or fixed hardware conventions.

[0036] : Complete admission sequence cycle. In the deterministic admission process, The complete acceptance sequence is a strictly controlled repetition period at the transmitting end, and simultaneously constitutes the maximum occurrence interval of the controlled R-bit first logical polarity reference guide. The complete acceptance sequence includes at least a K-bit second logical polarity configuration guide, a 1-bit first logical polarity controlled unit, a 1-bit second logical polarity controlled unit, and an R-bit first logical polarity reference guide.

[0037] When there is available inter-frame idle space in the original service frame, the transmitter can replace the idle space with a complete admission sequence in the open admission state, using the original inter-frame idle position as the anchor point. If every available idle position is replaced, then... = If the substitution is performed every N empty positions, then =N* This setting indicates that the complete admission sequence appears according to the original idle rhythm or an integer multiple thereof, and maintains compatibility with the original service sequence by utilizing the idle-compatible semantics of the Rbit first logical polarity reference guide.

[0038] When there is no available inter-frame free space in the original service frame, the sending end can, at the frame boundary where the stop bit at the end of a frame is located, press... Periodic insertion of complete acceptance sequence; A complete acceptance sequence can be inserted once for every N service frames, without requiring it to be inserted at the end of each frame.

[0039] : Capture period. Indicates that the receiving end executes The reference period used for periodic edge-closed capture. When the transmitter is in the accept open state and periodically transmits the complete accept sequence, the receiver independently captures using a periodic window. hour, A macroscopic time base, pre-agreed upon by the transmitting and receiving ends and independent of the candidate baud rate and service frame decoding results, is adopted, and satisfies... = .

[0040] When the complete acceptance sequence replaces the original empty position Can be equal to It can also be equal to N* When there is no available idle space in the original service frame, To ensure the complete acceptance sequence, the insertion period at the stop bit boundary of the frame end can be inserted once every N service frames. This is the period for these N service frames. The receiver starts timing from a valid edge; the timing exceeds... Then, continue waiting for the next edge-closing capture window, and select the largest complete first logic polarity pulse width within that edge-closing window as... Candidate values. Press at the sending end. Under the condition of sending the complete accept sequence, the receiver timer exceeds [time limit]. After the next edge closes, at least one controlled R-bit first logic polarity reference leader should be fully included within the edge closure window. If a first logic polarity fault causes the reference leader to widen, the receiver obtains a larger complete first logic polarity pulse width candidate value containing the reference leader. Subsequent updates are determined by the scale calibration closure condition. .

[0041] Therefore, the core parameter constraints of this application are: K>X-1, R≥I+X, and preferably R=I+X and D=RK. ≈K* , ≈R* , - ≈D* Where K is used to ensure the uniqueness of the second logical polarity configuration bootstrap; R is used to ensure that the first logical polarity reference window is within... Maximum capture; this application preferably takes R=I+X, making it 1 bit longer than the longest first logical polarity continuous window I+X-1 of ordinary business logic, thus forming strict length uniqueness; D is used to establish and The transpolarity between them has a sign-scale relationship.

[0042] By continuously monitoring the bus signal at the receiving end, narrow pulses with a width less than a preset threshold are filtered out using a digital filter. For the filtered pulses belonging to the first logic polarity, the minimum confident pulse width is extracted as the microscopic reference pulse width. A microscopic reference scale is then established. The continuous extraction of the micro-reference pulse width (also known as the micro-reference pulse width) is achieved using a high-speed oversampling clock in the receiver's underlying hardware. Continuously monitor the bus, extract and dynamically update the candidate unit bit width of the first logic polarity, and denot it as the micro reference pulse width. Preferably, the system extracts the minimum duration of the first logical polarity, the minimum credible duration after digital filtering, or their equivalent lower envelope to form a 1-bit candidate scale, which is the microscopic reference pulse width.

[0043] Preset confidence conditions are used to avoid direct updates of the microscopic reference pulse width by a single, sporadic narrow pulse. In different implementations, the preset confidence conditions may include at least one of the following: the candidate pulse width appears a preset number of times within a preset observation window; the candidate pulse width remains stable within multiple consecutive observation windows; the candidate pulse width matches the measured pulse width of the 1-bit first logic polarity unit in the integrity calibration sequence; the candidate pulse width is confirmed by a minimum hold or lower envelope tracking mechanism with confidence counting.

[0044] To prevent electromagnetic interference (EMI) spikes from causing Abnormally shrunk, in The system extracts a purely hardware digital filter at the front end, which filters out channel signals exceeding the bandwidth limit of the hardware medium. The system presets a minimum physical pulse width threshold; any transitions with a duration less than this threshold are silently filtered out and do not participate in the signal processing. renew.

[0045] at the same time, The anomaly may manifest not only as a decrease, but also as an increase when the first logical polarity is continuously injected with an anomaly. Therefore, subsequent acceptance judgments cannot only consider the offset on one side, but also... Abnormal shrinkage and abnormal enlargement provide defensive capabilities.

[0046] S102: The transmitting end sends a configuration guide with a second logical polarity whose length meets the preset requirement, and the receiving end updates the feature verification pulse width with a retention priority strategy as a macroscopic unique anchor point; wherein, the second logical polarity is an effective strong drive level state opposite to the first logical polarity; the preset requirement is used to ensure that the length of the configuration guide is greater than the maximum natural length of the consecutive second logical polarities appearing in the asynchronous serial communication word format.

[0047] like Figure 3As shown, traditional schemes lack an acceptance order oriented towards the mimicry boundary. Traditional schemes often interpret fail-safe as a fixed threshold switch, but strong interference samples may gradually approach the true bit pattern. If the system relies solely on a single long segment, equal-length comparison, fixed ratio, or single difference relationship, mimicry false closures may occur, such as "incorrect but proportionally correct" or "incorrect but differentially correct." Therefore, the acceptance boundary needs to be jointly defined by a microscopic scale, a unique anchor point, a transpolar controlled reference window, and a controlled short bit sequence. This ensures that samples deviating from the boundary are rejected, while samples entering the boundary are accepted as candidate baud rates. Whether the source is a fault is not used as a direct criterion at the physical layer; further discrimination is then carried out by higher-level frame structures, semantics, or verification mechanisms when necessary.

[0048] Meanwhile, traditional solutions lack a lock-state anti-error update mechanism. Even if many solutions successfully estimate or accept the correct baud rate on the first try, they are still exposed to the conditions for refitting, which may cause the system to be pulled back into the update chain due to abnormal pulses after locking.

[0049] Therefore, when performing physical layer binding with asymmetric polarity, in addition to the first logic polarity, the opposite effective strong drive level can be defined as the second logic polarity. Generally speaking, the second logic polarity is the same as the start bit.

[0050] During the link initialization or recovery phase, the sending end actively sends a continuous second logical polarity of length K as a configuration guide; where the value of K satisfies K>X-1; and where X represents the total number of bits in a single word, including start bit, data bits, optional parity bit, and stop bit.

[0051] The feature verification pulse width is obtained by the receiver based on the maximum sustained pulse width of the second logical polarity and used as the macroscopic unique anchor point; whenever a larger second logical polarity is obtained, the feature verification pulse width is updated.

[0052] The transmitting end actively sends a continuous second logical polarity of length Kbit as a configuration guide in any preset state among the power-on initialization phase, network formation phase, safe state, and link recovery phase. For example... Figure 4 As shown, under the Non-Return to Zero (NRZ) encoding format, the maximum natural length of a consecutive second logical polarity in normal business data does not exceed X-1. Therefore, a long segment of consecutive second logical polarities satisfying K>X-1 constitutes a macroscopically unique anchor point. The receiver monitors and updates the maximum duration of consecutive second logical polarities, denoted as the feature verification pulse width. .

[0053] Under the pre-defined failure unipolar model, a fault will not increase the measured continuous segment of the second logical polarity, but will more easily cause the continuous segment of the second logical polarity to be fragmented, shortened, or missing. Therefore, a long pulse of the second logical polarity that satisfies the unique length condition can be preferentially used as a candidate for the transmitter's configuration guide. Therefore, the receiver preferably implements a retention update strategy for the maximum candidate duration of the continuous second logical polarity: when a candidate value of a long pulse of the second logical polarity that satisfies the unique condition has been obtained, the candidate value will not be immediately cleared due to a single subsequent verification failure before the anchor timeout condition is triggered. Thus, while maintaining the constraint that "fault unipolarity is biased towards the first logical polarity", the retention probability of the unique anchor point and the convergence efficiency of the subsequent acceptance chain can be improved.

[0054] S103: The transmitter sends a predefined integrity calibration sequence, and the receiver measures the pulse width according to the reference window of the reference guide in the integrity calibration sequence, performs transpolar signed scale reference calibration on the feature verification pulse width, and performs closed interval arithmetic verification through the microscopic reference pulse width; wherein, the integrity calibration sequence includes a first logical polarity, a second logical polarity, and a first logical polarity reference guide whose length and the length of the configuration guide satisfy a preset requirement.

[0055] Pre-defined: The reference guide in this paper refers to a controlled-length, first logical polarity continuous window sent, constructed, or multiplexed by the sender during the accept / open phase. When this window is semantically compatible with stop bits and idle bits, it is also called an idle-compatible reference window. The reference window length is uniformly denoted as R, and the reference window measurement pulse width measured by the receiver for this R-bit first logical polarity reference window is denoted as... .

[0056] The reference window is not limited to being directly concatenated from the actual stop bits and the actual inter-frame space. It can be formed from the original protocol stop bits, the equivalent stop bits, the inter-frame space, the extended space, the protocol harmless space, or a first logical polarity window actively constructed by the sender. Its length, polarity, and protocol semantics are subject to the aforementioned parameter definitions and acceptance constraints.

[0057] The measurement or overload is not a direct value taken from any continuous segment of the first logic polarity, nor is it a pre-selection of the absolute time of Rbit at an unknown baud rate. The specific capture method is based on the aforementioned complete reception sequence period. (This includes the Kbit second logical polarity configuration guide and integrity calibration sequence) and edge closure capture mechanism. Normal inter-frame idle time is not directly written. Only the first logical polarity reference guide of the controlled Rbit in the complete acceptance sequence, after being constrained by preset scale and calibrated by cross-polarity reference, constitutes a valid sequence.

[0058] Specifically, the integrity calibration sequence includes a reference guide with 1 bit of first logical polarity, 1 bit of second logical polarity, and R bits of first logical polarity. To extract the true 1-bit width with high determinism under controlled conditions, the transmitter preferably inserts a 1-bit first logical polarity unit and a 1-bit second logical polarity unit after configuring the guide. The receiver checks these two short units to help confirm the true width scale and compare it with... The updates form a closed relationship.

[0059] Bit-width extraction units can also be used to assist in morphological verification. If a certain extraction yields... Corresponding to a true 1-bit width, when the complete acceptance sequence appears subsequently, this... Capable of being measured with the Kbit second logical polarity configuration bootstrap The closed interval relationship is satisfied, thus proceeding to the subsequent 1-bit+1-bit auxiliary morphological verification and transpolar reference calibration process.

[0060] Additionally, this section addresses the first logical polarity controlled reference leader and... based on The edge closure capture is explained.

[0061] In this embodiment, the first logic polarity is simultaneously the same as both the stop bit and the idle bit. If this condition is not met, it can be adjusted using an inverter. Normally, the stop bit or equivalent stop bit can be 1 bit, 2 bits, or other first logic polarity bits as agreed in the protocol.

[0062] This application will accept the open-state controlled formation of the first logical polarity continuous window of Rbit as the idle-compatible reference guide, and as... The calibration source. For example... Figure 5 As shown, The capture employs a periodic approach based on the complete admission sequence. Edge closure mechanism: The receiver starts timing from the valid edge, exceeding... Then wait for the next edge to close the window, and take the maximum complete first logic polarity pulse width within that window as... Candidate values; where = The capture window should cover at least one complete admission sequence period; at the sending end, press... When transmitting the complete accept sequence, a complete controlled R-bit first logical polarity reference leader is included within the edge-closed window. If a first logical polarity fault causes this reference leader to widen, the receiver obtains a larger complete first logical polarity pulse width candidate value containing this reference leader, and subsequent transmissions are still processed through the corresponding protocol. ≈R· and - ≈D· Perform a scale closure test.

[0063] If there is available inter-frame free space in the original frame, the transmitter can replace the free space with a complete acceptance sequence in the open acceptance state, using the original inter-frame free space position as the anchor point. This replacement can occur at every available free space position, or it can occur once every N free space positions; correspondingly, Can be equal to It can also be equal to N* The first logical polarity reference guide in the complete accept sequence is compatible with the original idle structure in terms of length, polarity, and protocol semantics, and serves as... Controlled reference sources.

[0064] like Figure 6 As shown, if there is no available inter-frame gap in the original frame or the inter-frame gap has no specific pattern, the sending end can press the stop bit at the frame boundary where the end of a frame is located. Periodically insert the complete admission sequence. This insertion can be performed once every N service frames, and is not required to be inserted at the end of each frame.

[0065] This complete acceptance sequence is used to organize the K-bit second logical polarity configuration pilot, the 1-bit + 1-bit controlled short bit, and the R-bit first logical polarity controlled reference pilot into a single state machine-resolvable acceptance chain.

[0066] Regardless of whether the idle replacement method or the frame tail boundary insertion method is used, the complete acceptance sequence includes at least a K-bit second logical polarity configuration guide, a 1-bit first logical polarity controlled unit, a 1-bit second logical polarity controlled unit, and an R-bit first logical polarity reference guide.

[0067] Assuming that there is an available inter-frame idle space of length I bits in the original service frame, the following is an illustration of an implementation method with the preferred value of R, i.e., R=I+X; the physical layer encoding of the locked state with idle space is as follows: the first logical polarity stop bit of the previous frame data + I bits of the first logical polarity idle + the second logical polarity start bit of the next frame data, or, (I+1) bits of the first logical polarity level (stop bit + idle) + the second logical polarity start bit of the next frame data.

[0068] Under the above conditions, the acquisition state acceptance sequence can be represented as: the first logical polarity stop bit of the previous frame data + Kbit second logical polarity configuration guide + 1 bit first logical polarity unit + 1 bit second logical polarity unit + R bit first logical polarity idle compatibility reference guide (R=I+X) + the second logical polarity start bit of the next frame data.

[0069] Among them, the Rbit first logical polarity idle compatible reference guide is compatible with the stop bit and idle window semantics in the original protocol in terms of polarity and protocol semantics, and satisfies the aforementioned Rbit reference guide conditions in terms of length. Therefore, it can maintain compatibility with the original service frame boundary, idle identification and bus reset mechanism to the greatest extent.

[0070] The physical layer encoding for a locked state with no free space is as follows: the first logical polarity stop bit of the previous frame data + the second logical polarity start bit of the next frame data.

[0071] In the implementation where there is no inter-frame idle time in the original service frame, the sending end actively constructs an open acceptance sequence in the acquisition state: the first logical polarity stop bit of the previous frame data + Kbit second logical polarity configuration guide (K>X-1 to form a unique anchor point) + 1 bit first logical polarity unit + 1 bit second logical polarity unit + R bit first logical polarity reference guide (R=I+X) + the second logical polarity data start bit of the next frame.

[0072] The Rbit first logical polarity reference guide can be represented as an artificial idle, placeholder idle, safe idle, or protocol-harmless idle window, used to form an idle window when there is no native inter-frame idle. A complete measurement basis.

[0073] The controlled reference guide is compatible with stop bits or inter-frame idle in terms of level polarity and idle semantics, and can be recognized by the receiver of this application or a compatible upgraded receiver within a specified admission window. For traditional asynchronous serial receivers without the admission state machine of this application, the K-bit second logic polarity configuration guide may be identified as an abnormal start bit or frame error. Therefore, it is necessary to prevent it from entering the normal service channel through maintenance window, admission enable condition, silent discarding of erroneous frames, or device isolation mechanism. The compatibility analysis is as follows: Generally, the configuration preamble sequence is inserted after the stop bit of the last word in a frame. When the configuration preamble sequence is introduced into a traditional NRZ coding system, if the system does not enforce inter-frame gaps, the receiver hardware state machine will perform the following process: Start bit mismatch: Traditional devices will recognize the configuration guide as the start bit of the next frame; Data anomaly: K consecutively sampled data bits (K>X-1) all exhibit the second logical polarity corresponding to the configuration guide, or do not meet the normal NRZ word format, and no valid stop bit is detected; At this point, a traditional device might throw a standard error: "Frame Error" or "Bus Open Circuit". Low-level driver behavior: Silently discard the erroneous data packet and report errors such as FE; For the receiving end of this application or a compatible receiving end, the controlled reference guide of length R can be identified. In ordinary services, when all first logical polarity data / parity bits, stop bits, and 1-bit inter-frame idle bits are concatenated, the longest possible continuous window of the first logical polarity is I+X-1 bits; however, in this application, there is a preset signed bit difference D between the length R of the reference guide and the length K of the configuration guide, and D=RK. When the original service protocol stipulates that the continuous window of the first logical polarity of ordinary services has a finite maximum value, let the maximum number of bits of inter-frame idle bits in ordinary services be... Then, the maximum length of the first logical polarity continuous window that can be naturally formed by ordinary business operations is +X-1, with reference to the length R of the leading symbol satisfying R> +X-1; when R is an integer, R≥ +X.

[0074] The length of the controlled reference guide is preferably R = I + X. Therefore, this controlled reference guide is 1 bit longer than the naturally longest first logical polarity window of a normal service, and will not be naturally formed by a normal service. At the same time, it is the first logical polarity and is semantically compatible with stop bits, equivalent stop bits, and inter-frame idle time. Therefore, it can be identified as an idle-compatible controlled long segment, thereby enabling the bus state machine to have the conditions for reset, resynchronization, or entering the next frame start decision.

[0075] If the system forces a timeout between frames, the receiver hardware state machine will perform the following process: Forced Idle Lock: Traditional devices will continuously capture idle time after the end of a frame, which is used as the starting condition for the next frame. The level sequence of the configuration guide + 1 bit first logic polarity unit + 1 bit second logic polarity unit can be treated as an abnormal frame, non-idle segment or invalid segment by the compatible receiver, and will not be entered into the subsequent data channel as a valid service frame; some strict systems may also report the existence of non-idle time between frames. For receivers configured with the acceptance state machine of this application, after capturing a controlled reference guide with a bit width of R, it is treated as an idle compatible controlled long segment according to the aforementioned R condition. The complete acceptance sequence is not submitted to the upper layer as a valid service frame, and then the next frame is received normally. For traditional asynchronous serial receivers without the acceptance state machine of this application, the configuration guide may still trigger frame errors or BREAK detection, which should be handled through acceptance enable, silent discarding of underlying errors, or device isolation mechanisms.

[0076] Using the above sequence, the receiver can follow the complete acceptance sequence period sent by the sender. Perform edge-closing capture to refresh Note that the transmitter is currently in the acquire state. It should be clarified that the acquire state, accept open state, and locked state mentioned in this article all refer to the transmission mode adopted by the transmitter for the complete accept sequence. The receiver's baud rate acceptor continuously performs bus signal acquisition, candidate pulse width extraction, and accept verification, and does not stop working, disable the accept function, or switch to the receiver locked state because the transmitter enters the locked state. When the transmitter is in the locked state, the receiver cannot form a new valid baud rate accept result because the transmitter stops transmitting the complete accept sequence, preventing the actual received signal from simultaneously meeting all accept conditions, rather than because the receiver actively prohibits updates.

[0077] After the transmitting end enters the locked state and stops transmitting the complete acceptance sequence, the receiving end's baud rate acceptor continues to perform bus signal acquisition, candidate pulse width extraction, and acceptance verification. It does not switch to the locked state, nor does it actively close the acquisition and verification process of candidate quantities. Since a normal service sequence cannot simultaneously form a Kbit second logical polarity configuration guide, a 1-bit first logical polarity unit, a 1-bit second logical polarity unit, and an Rbit first logical polarity reference guide, all acceptance conditions cannot be closed, and therefore no new valid baud rate acceptance result will be formed.

[0078] Specifically, this includes two aspects: First, when R=I+X is preferably selected in this application, the longest continuous window of the first logical polarity formed by the data bits, optional parity bits, stop bits, and inter-frame idle overlap in ordinary services is I+X-1 bit, which is strictly smaller than the bit width R of the controlled reference guide. Therefore, the first logical polarity window in ordinary services cannot satisfy the requirement. ≈R· The reference calibration relationship; secondly, the sending end no longer sends the Kbit second logical polarity configuration guide and the subsequent 1bit first logical polarity unit and 1bit second logical polarity unit, so that the ordinary service signal lacks a macroscopic unique anchor point and a controlled short bit sequence, and the complete acceptance evidence chain cannot be closed.

[0079] Through the receiving end, determine the signed bit difference D between the length R of the reference guide and the length K of the configuration guide, and D=RK, and measure the reference window measurement pulse width of the reference guide; determine the pulse width difference between the reference window measurement pulse width and the feature verification pulse width, and verify whether the residual between the pulse width difference and D times the microscopic reference pulse width is within the preset differential tolerance range. Closed-interval arithmetic verification is performed on the feature verification pulse width and the reference window measurement pulse width respectively; specifically, for the feature verification pulse width, it is verified whether the residual between it and K times the microscopic reference pulse width is within the first preset tolerance range; for the reference window measurement pulse width, it is verified whether the residual between it and R times the microscopic reference pulse width is within the second preset tolerance range. If both the transpolar signed scale reference calibration and the closed interval arithmetic verification pass, the feature verification pulse width is determined as the verified configuration guide measurement pulse width.

[0080] This section explains the principles of transpolar signed scale reference calibration and closed interval arithmetic verification from both a holistic and specific perspective to ensure the credibility of the verification process.

[0081] Overall, this application provides a mimicry-based fail-safe candidate baud rate acceptance method based on failure polarity binding and unique anchor point integrity calibration. This method is applicable to NRZ-coded asynchronous serial communication in highly disruptive industrial scenarios. Its core task is not "how to directly obtain an absolute baud rate value from the local pulse width" in traditional automatic baud rate technology, but rather "how to determine whether a candidate baud rate is eligible for acceptance within the physical layer in industrial environments with high random disturbances, high mechanical damage, and high noise, and to default to rejecting updates and re-acquiring when the evidence chain is not closed."

[0082] Therefore, the main architecture of this application is a candidate baud rate acceptance mechanism, rather than a traditional absolute value valuation mechanism.

[0083] The "mimicry boundary acceptance" referred to in this application does not protect the idea that "the closer a fault is to a real bit, the harder it is to distinguish" as a natural law or scientific discovery, nor does it aim to identify whether a pulse is a fault. Instead, it constructs an engineering acceptance boundary in the NRZ physical layer. In other words, the object of this application is not "whether the pulse source is a fault," but "whether the candidate baud rate sample formed by the pulse is qualified to be accepted."

[0084] The boundary is formed by , , The acceptance criteria are jointly defined by the transpolar differential reference calibration relationship, the 1-bit+1-bit controlled short sequence, and the absence of a complete lock-state acceptance sequence. Therefore, this application does not use a single pulse width, a single ratio, or a single threshold as the acceptance criterion, but rather uses whether the candidate sample can simultaneously fall within the above-mentioned multidimensional constraint boundaries as the acceptance criterion.

[0085] Candidate samples are accepted by the physical layer only if they simultaneously satisfy the above constraints; if any constraint is not closed, the system refuses to update and recaptures the sample. Therefore, the fail-safe mechanism in this application is not a threshold switch of fixed strength, but rather an acceptance order that converges towards the mimicry boundary: the further a sample deviates from this boundary, the less likely it is to be accepted, and the stronger the fail-safe mechanism becomes.

[0086] It should be noted that a sample entering the mimetic boundary is not necessarily determined by the physical layer as a "fault-free source". If a fault pulse exactly provides evidence in the observable dimension of the current physical layer that is of the same scale and sequence as a real bit and can close with the admission constraint sequence, this fault pulse may probabilistically assist in convergence; at this time, the physical layer admits the candidate baud rate sample formed with its participation, rather than making a "non-fault" determination on the source of the pulse.

[0087] Further, the present application does not take the fault pulse's own width as a sufficient condition for deterministic rejection, but takes the residual formed by each measured quantity relative to the preset scale relationship after the fault acts as the criterion. For a first logical polarity fault with a width greater than or equal to 1 bit, the preset failure unipolar model can only determine the non-increasing change direction and the non-shortening change direction of the first logical polarity controlled reference segment; only when at least one of | -K· |, | -R· | or |( - )-D· | exceeds the corresponding tolerance, the candidate baud rate is deterministically rejected. When the fault width is greater than or equal to 1 bit but its actual intrusion into the measurement edge is still within the tolerance, the sample belongs to the sample within the mimetic boundary, and no separate rejection judgment is made based solely on the fault width.

[0088] In the second category, for the first logical polarity narrow disturbance with 0<wf<Tbit, and may be scaled down proportionally, causing a false closure of the standalone ≈K· relationship. To address this, the present application introduces an R-bit first logical polarity controlled reference guide and sequential constraints of 1 bit of the first logical polarity and 1 bit of the second logical polarity. Let =βTbit, =βKTbit, =γRTbit, where 0<β<1, γ≥1, then both the reference scale residual and the differential residual are R(γ-β)Tbit. Only when the residual exceeds the corresponding tolerance, the candidate baud rate is deterministically rejected; when the residual is still within the tolerance and the morphology and sequence of the complete sequence are closed at the same time, the sample enters the mimetic boundary, and the physical layer admits the candidate baud rate formed with the participation of this sample, without making a non-fault determination on the disturbance source.

[0089] The third type is the locked state after the system has completed baud rate acceptance. This application further proposes that after successful baud rate adaptation, the transmission of the configuration guide and the subsequent 1-bit first logical polarity unit and 1-bit second logical polarity unit can be stopped, retaining only the stop bit, idle, and normal service. After the transmitting end enters the locked state, the receiving end's baud rate acceptor continues to operate and continues to perform microscopic reference extraction, candidate long segment acquisition, reference window acquisition, and acceptance relationship verification on the received signal. On the one hand, in this application, when R=I+X is preferably chosen, the longest continuous first logical polarity window formed by the data bits, optional parity bits, stop bits, and inter-frame idle overlap in normal service is I+X-1 bit, which is strictly smaller than the controlled reference guide bit width R. Therefore, the first logical polarity window in normal service cannot satisfy... ≈R· The reference calibration relationship; on the other hand, the sending end no longer sends the Kbit second logical polarity configuration guide and the subsequent 1bit+1bit controlled unit, so ordinary services cannot form a complete acceptance constraint sequence.

[0090] Therefore, after the transmitter locks, the receiver does not exit or close the candidate baud rate acceptance chain. Rather, with the receiver continuing to operate, ordinary service signals cannot close the complete acceptance evidence chain, thus preventing the formation of a new valid baud rate acceptance result. Therefore, this application addresses "how to form a valid acceptance result" in the open acceptance state, and in the transmitter-locked state, it addresses "how to avoid ordinary services triggering new baud rate acceptance" through the combined solutions of "ordinary services not satisfying the R-scale relationship" and "the lack of a complete acceptance sequence."

[0091] Furthermore, this application does not investigate whether a sample is faulty on the ontology, but rather whether the sample disrupts the candidate baud rate acceptance order. The more a perturbation deviates from the true bit width, the more it disrupts the unique anchor point, the microscale, and the integrity calibration relationship, the less likely it is to be accepted by the system; the closer a perturbation is to the true bit width and the closer it is to the mimicry boundary, the more likely it is to converge with the true sample in the current physical layer dimension; when a certain type of perturbation is equivalent to a true 1 bit in the current dimension and contributes to… During convergence, it can exhibit a neutral or even convergence-enhancing effect on the system. Therefore, this application does not focus on "identifying what the fault is," but rather on "whether the candidate baud rate should be accepted," and establishes a monotonic fail-safe order in which the more severe the fault, the less likely it is to be mistakenly accepted.

[0092] Specifically, firstly, the construction and related explanations for closed interval verification: When detected , Subsequently, the underlying hardware does not wake up the CPU, perform packet assembly, or CRC check; instead, it treats the current result as a candidate baud rate and enters the physical layer for internal verification. First, it performs closed-interval arithmetic verification: ; R* -ΔR<= <=R* +ΔR; D* -ΔD<= - <=D* +ΔD, or written as: |( - )-D* |<=ΔD; Where Δ is the configuration guide scale tolerance, ΔR is the reference window scale tolerance, and ΔD is the transpolarity differential tolerance. Let the normal measurements be respectively... =Tbit+εb、 =K·Tbit+εp、 =R·Tbit+εr, then the three normal residuals are εp-Kεb, εr-Rεb, and εr-εp-(RK)εb, respectively. Δ, ΔR, and ΔD should each be no less than the maximum absolute value of the corresponding normal residual under the combined effects of sampling quantization error, minimum statistical deviation, transmit and receive clock errors, edge jitter, rising and falling edge asymmetry, and front-end filtering delay. Faulty samples are deterministically rejected only when at least one residual exceeds the corresponding tolerance or sequence shape, or the sequence is not closed; samples within all tolerances and with a closed chain of evidence constitute the mimicry boundary of this application.

[0093] This closed-interval arithmetic verification proves the necessity of using the first logical polarity as the measurement polarity. If the second logical polarity is mistakenly used... Measurement source, then physical failure is more likely to lead to and As values ​​shrink in the same direction, spurious values ​​are more likely to fall into the valid range. Therefore, the first logical polarity is used as... Measurement sources are an important prerequisite for building a two-way defense mechanism.

[0094] Furthermore, not to / K or / R is directly used as the estimate of the major bit width. Longer measurement windows typically have better relative quantization resolution under the same counting clock, but in fail-safe acceptance scenarios... It may be truncated by a fault and mixed with BREAK or abnormally long segments. It may be confused with ordinary idle, widening fault, or unclosed window; neither, when used alone, can provide complete evidence of transpolar sequence. Therefore, Used to form the macroscopic anchor point of the second logical polarity. Used to form a first logic polarity controlled reference Used to provide a microscale; candidate baud rates are only accepted when all three are closed together with a 1-bit + 1-bit controlled short sequence.

[0095] Second, provide a mathematical proof for baud rate acceptance calculation under ideal, undisturbed conditions: Known conditions at the receiver (obtained through real-time hardware measurements and preset conditions at the receiver) include: 1. Receive single word width X.

[0096] 2. Hardware continuously measures the minimum pulse width of the first logic polarity. (Assuming) If the actual bit width is 1, then any effective level width is... multiples of integers, therefore =m* (where m is a positive integer).

[0097] 3. Hardware continuously measures the maximum pulse width of the second polarity. (Configuring only the guide pulse width can reach or exceed X*) The maximum pulse width in the NRZ coding region is (X-1)* ).

[0098] Core derivation formula: The following example uses a convenient value of K=X. The derivation follows the same logic for any pre-defined value of K that satisfies K>X-1. The derivation occurs if and only if the leading symbol appears. The true value = K* ;at this time, / =(K* ) / (m* =K / m; Note that when m=1, = The sampled at this time The actual width is 1 bit. As above, closed interval verification: K* -Δ<= <=K* +Δ, which is equivalent to: K-Δ / <= / <=K+Δ / .

[0099] Since m is a positive integer, therefore: if m=1, then the ratio = K, which falls exactly within the closed interval, thus the verification passes; if m≥2, then the ratio ≤ K / 2, which is much smaller than K-Δ / The lower limit was breached, and the verification failed.

[0100] The conclusion is then reached: only when... Exactly equal to 1 bit of actual width Only then will the verification pass. At this point, under the ideal conditions described above, the system can accept a candidate baud rate of 1 / .

[0101] Third, such as Figure 7 As shown, a rigorous fail-safe mathematical proof is provided for configuring the bootstrap character to ensure that the fault width is greater than or equal to 1 bit.

[0102] It is now rigorously proven that, under the premise of fault unipolarity, if the fault is injected only in the form of the first logical polarity, and its width is denoted as wf, and wf>=Tbit, then simply configuring the bootstrap can provide strict fail-safety. Here, Tbit represents the duration of a single bit, which corresponds to the actual 1-bit width.

[0103] The proof is as follows: Under this premise, a fault will only insert, maintain, or widen the first logic polarity in the bus, but will not expand the second logic polarity. Therefore: no fault can cause the duration of the continuous second logic polarity corresponding to the second logic polarity configuration bootstrap to exceed its fault-free value K*Tbit, i.e. <= K*Tbit.

[0104] Any first logic polarity fault with an arbitrary width satisfying wf>=Tbit cannot produce a first logic polarity minimum duration shorter than a real 1 bit. >=Tbit.

[0105] Therefore: / <= (K*Tbit) / Tbit = K.

[0106] If the fault affects the current candidate acceptance... or For the measurement to have a real impact, at least one of the following two conditions must be met: First, the second logical polarity configuration guide is shredded, shortened, or missing, causing: <K·Tbit。

[0107] Secondly, the first logic polarity unit, which could originally form the minimum bit width, is merged, expanded, or replaced, resulting in: >Tbit.

[0108] In any case, we have: <K·

[0109] Under the ideal integer bit-width model, the above change will cause -K· to generate a non-zero negative residual. When the configured pilot scale tolerance Δ can cover normal sampling quantization error, edge jitter and propagation delay error, and is smaller than the minimum resolvable residual caused by a fault, the closed-interval arithmetic verification: K· -Δ≤ ≤K· +Δ; no longer holds, and the candidate value is rejected. Therefore, simply configuring the pilot and the closed-interval condition can deterministically reject unipolar disturbances where wf≥Tbit and which actually undermine the candidate acceptance measurement.

[0110] In addition, it can also be concluded that, in the above case, the wider the disturbance injected in the first logical polarity form, the smaller the average probability of passing the verification. In the acceptance order of the present application, whether a disturbance is accepted does not depend on its source label, but on whether it can still simultaneously satisfy , , and the 1bit+1bit morphological constraint. The more the disturbance undermines the above relationship, the further the sample is away from the mimic boundary, the less likely it is to meet the acceptance condition, and the system tends to reject the update; only when the disturbance is already self-consistent with the real bit behavior in the current physical layer dimension and enters the mimic boundary, can it possibly not be further distinguished by the physical layer.

[0111] It should be emphasized that the fault pulse does not necessarily exist only as a rejection object; when it exactly provides available scale information consistent with the real bit in the observable dimension of the physical layer, and promotes , or to fall into the acceptance boundary faster, this fault pulse can assist the convergence of the candidate baud rate in a probabilistic sense. What the system finally accepts is still the candidate baud rate that meets the acceptance boundary, rather than making an affirmative judgment on the fault source itself.

[0112] Fourth, the proportional scaling counterexample under strictly less than 1bit disturbance and its mathematical description: As Figure 8 shown, for a narrow disturbance of the first logical polarity with 0<wf<Tbit (this disturbance is injected in the second logical polarity through vibration or the like), the situation is different from the above. At this time, may be abnormally reduced, and the long pilot of the second logical polarity may also be fragmented. If no additional constraints are imposed on itself, a proportional scaling counterexample will occur.

[0113] Assume there is a certain scaling factor α, where 0<α<1, such that the high-frequency narrow disturbance exactly causes: =α*K*Tbit, =α*Tbit; Then we have: / =(α*K*Tbit) / (α*Tbit)=K.

[0114] Although and are both incorrect, the ratio still remains K. In this case, simply configuring the pilot symbol and the closed interval condition cannot independently constitute a strict rejection proof.

[0115] Therefore, the rigorous conclusion of the present application on this point needs to be clearly stated as: For wf>=Tbit, simply configuring the pilot symbol can already achieve strict fail-safe; For 0<wf<Tbit, if is not subjected to independent integrity calibration, a proportional scaling counterexample exists, so simply configuring the pilot symbol cannot independently complete the strict proof.

[0116] To eliminate the aforementioned proportional scaling ambiguity, the present application continues to transmit after configuring the pilot symbol: a 1-bit first logic polarity unit, a 1-bit second logic polarity unit, and an R-bit first logic polarity reference pilot (which forms an integrity calibration sequence).

[0117] Wherein, when the stop bit, equivalent stop bit, inter-frame idle, extended idle or protocol-harmless idle in the original service frame can carry or form the R-bit first logic polarity idle compatible window in the admission open state, the R-bit reference pilot is preferably compatible with the window in terms of length, polarity and protocol semantics; when there is no available inter-frame idle in the original service frame, the transmitting end actively constructs the R-bit first logic polarity reference pilot.

[0118] After the receiving end completes the 1-bit+1-bit short unit detection and optional morphological verification, it reads the candidate value obtained in advance by the independent capture process based on the complete admission sequence period and the edge-closed capture mechanism, and requires and to simultaneously satisfy: K* -Δ<= <=K* +Δ; corresponding to the closed interval arithmetic verification of the feature verification pulse width; R* -ΔR<= <=R* +ΔR; corresponding to the closed interval arithmetic verification of the reference window measurement pulse width;​ |( - )-D* |<=ΔD; where D=R−K, which is the signed digit difference between the reference pilot length R and the configured pilot length K; - is the pulse width difference between the reference window measurement pulse width and the feature verification pulse width.

[0119] The physical meaning of the above relationship is not simply "adding one more long section", but to promote from "the second logical polarity candidate long section" to "an effective configured pilot measurement pulse width that has been calibrated by the reference pilot".

[0120] The strict proof is as follows: Under ideal conditions, it can be determined that: =K*Tbit, =R*Tbit, - =D*Tbit.

[0121] On the premise of fault unipolarity, a fault cannot increase the continuous long section of the second logical polarity, nor can it shorten the reference window of the first logical polarity. If a fault injects into the first logical polarity reference pilot to make the reference pilot wider, it will cause >R*Tbit. If a first logical polarity fault cuts into the section where the second logical polarity configured pilot is located, it will cause <K*Tbit, at this time either increases, or decreases, the integrity calibration condition: |( - )-D* |<=ΔD will jump out of the interval and be falsified. That is, if a fault causes the corresponding measurement residual to exceed the preset tolerance, and the integrity calibration condition formed cannot be closed, and the candidate value is rejected.

[0122] It should be emphasized that, the capture period takes the complete acceptance sequence period , the determination method of which is subject to the aforementioned parameter definitions. The receiving end starts timing from a valid edge, and when the timing exceeds then continue to wait for the next edge closing window, so that the edge closing window covers at least one complete admission sequence period and fully incorporates the controlled Rbit first logic polarity reference guide symbol therein. If the first logic polarity fault causes the reference guide symbol to be widened, the receiving end obtains the maximum complete first logic polarity pulse width candidate value after being widened, and whether to update it is subsequently determined by the scale calibration condition .

[0123] Specifically, the receiving end starts from the valid edge to perform capture timing; when the timing exceeds , the sampling window is not truncated immediately, but continues to wait for the next edge to close the current capture window, and the maximum complete first logic polarity pulse width within the edge closing window is selected as the candidate value.

[0124] Therefore, the integrity of is not guaranteed solely by "the window exceeding the period", but is jointly guaranteed by " defining the maximum repetition interval of the complete admission sequence and the controlled reference guide symbol", "waiting for the next edge closing window after exceeding ", "the edge closing window fully incorporating the controlled Rbit first logic polarity reference guide symbol", "selecting the maximum complete first logic polarity pulse width within the edge closing window", and "the maximum complete pulse width continuing to satisfy ≈R* and - ≈D* scale closure".

[0125] Only when and pass the integrity calibration, can be identified as the measured pulse width of the Kbit configuration guide symbol that meets the admission condition. At this point, has been promoted from the "candidate second logic polarity long segment" to the "configuration anchor point that has passed the reference window calibration".

[0126] For the first logic polarity narrow disturbance where 0<wf<Tbit, let the true single-bit duration be Tbit. When the narrow disturbance causes the microscopic reference pulse width and the configuration guide symbol measured pulse width to shrink in equal proportion incorrectly, it can be expressed as: ; ; where: .

[0127] Under the preset failure unipolar model, the first logic polarity controlled reference guide symbol will not be shortened due to the first logic polarity fault, so its reference window measured pulse width can be expressed as: ; where, .

[0128] Let D = R − K, then the differential residual of the transpolar signed scale reference calibration is: ; ; .

[0129] Since R>0, γ≥1 and 0<β<1, therefore >0. When: At that time, candidate baud rates generated by proportionally incorrect scaling are deterministically rejected.

[0130] when If the sample is still within the preset differential tolerance range, and the configuration of the guide scale, reference window scale, 1-bit first logic polarity unit, 1-bit second logic polarity unit, and sequence arrangement all meet the acceptance conditions, the sample belongs to the sample within the pseudo-boundary and can participate in the candidate baud rate convergence; the physical layer accepts the candidate baud rate formed by the sample, without making a negative determination on whether the sample comes from a fault.

[0131] Therefore, transpolar signed scale reference calibration excludes spurious closures of proportional scaling that could cause erroneous candidate baud rates and cause residuals to exceed preset tolerance boundaries, rather than unconditionally rejecting all sources of physical faults.

[0132] Alternatively, we can conclude that in the above circumstances, if For calibration, the higher the frequency vibration injected in the form of the first logic polarity, the narrower the pulse that can pass through the hardware bandwidth-level filter, i.e., the more effectively it is latched. The smaller the value, the lower the average probability of passing the verification. In other words, the system also naturally implements a strong fail-safe filtering strategy: "The further the sample is from the mimicry boundary, the less likely it is to pass the acceptance condition, and the more the system tends to refuse to update."

[0133] Fifth, the engineering implications of mimicry-based failure safety boundaries and transpolar differential reference calibration: The fail-safe mechanism in this application is not a fixed-strength switch, nor does it simply determine whether a pulse is a fault. Instead, it constructs a mimicry-based candidate baud rate acceptance boundary within the physical layer through an acceptance constraint sequence. This boundary determines whether a candidate baud rate sample can be accepted, rather than the fault source label of a single pulse. This boundary is defined by… , , The cross-polarity differential reference calibration relationship, the 1-bit+1-bit controlled short sequence, and the missing complete acceptance sequence in the locked state are jointly defined. In other words, the acceptance constraint sequence is not a set of conditions, but the engineering structure itself that forms the pseudo-boundary; its role is to place candidate samples into an acceptance space jointly defined by polarity, timing, scale, and state machine for judgment.

[0134] When a fault disturbance disrupts the above relationships, the candidate sample cannot simultaneously satisfy the unique anchor scale, the controlled reference scale, the preset signed difference scale, and the morphological order constraint. The system will refuse to update and recapture by default. The more the disturbance deviates from the true bit scale or the more it disrupts the controlled sequence, the farther the sample is from the mimicry boundary, and the less likely it is to be accepted by the system. Therefore, the stronger the fail-safe condition, the better.

[0135] When a perturbation is equivalent to a real 1 bit in the current physical layer observable dimension, the perturbation enters the mimetic boundary defined in this application. If it participates in the formation... , , When the 1-bit + 1-bit morphological relationship can be closed together, the perturbation is no longer treated as a source of rejection by the physical layer, but may become one of the valid pieces of evidence in the candidate baud rate convergence process.

[0136] This mechanism can be understood heuristically using mimicry: the closer the mimicry is to the target object, the more difficult it is to distinguish within the same observation dimension; to continue distinguishing, it is usually necessary to introduce features of higher or more dimensions. However, in this application, "mimicry" does not mean that the system attempts to identify whether a pulse is a fault masquerading, but rather whether the candidate baud rate sample has already met the engineering acceptance boundary in the current physical layer observation dimension. Faults that meet the engineering acceptance boundary do not disrupt the self-consistency of the acceptance order results; the fault itself needs to be identified by the link layer using features such as semantic analysis or verification, rather than being decided at the physical layer.

[0137] It should be noted that the aforementioned mimicry boundary is not proposed as a natural law, scientific discovery, or biological law, but rather is derived from the transmission sequence, receiving state machine, and periodically guided edge-closing mechanism of this application. capture, / / The engineering decision boundary is jointly defined by the comparison relationship and the rejection update mechanism. This application claims protection for the specific technical means of forming this boundary, rather than the abstract understanding that "the closer the fault is to the real bit, the harder it is to distinguish".

[0138] like Figure 9As shown, when the first logical polarity perturbation is equivalent to a real 1 bit in the current physical layer's observable dimension, and the candidate baud rate samples it participates in forming do not violate the acceptance constraint sequence, the perturbation can probabilistically assist in the convergence of candidate baud rates. The physical layer accepts candidate baud rate samples that satisfy the mimicry boundary, rather than making a non-fault determination of the perturbation's source. If it is necessary to further distinguish the source, the higher-level frame structure or verification mechanism will continue to identify it.

[0139] Sixth, transpolar signed scale reference relationships cannot stand alone; they must be combined with other relationships. To prevent candidate baud rate mimicry false closure: also, Before participating in the signed scale reference calibration process, it was During independent acquisition, the receiver starts timing from a valid edge, waits for the next edge closing window after the selected acquisition period has elapsed, and selects the candidate value obtained after the largest complete first logic polarity pulse width within that edge closing window. If If the segment is a random first logical polarity long segment, a half-empty segment, an unclosed long segment, or a segment spliced ​​across a window, it will not be included in the judgment of proportional relationship or difference relationship.

[0140] Special Note: and The preset scale relationship cannot be used as a single convergence criterion. This ratio is expressed as K / R, where K is the length of the second logic polarity configuration guide and R is the length of the first logic polarity reference window. In this application, R is preferably set to I+X, in which case the ratio is expressed as K / (I+X). In other embodiments, the ratio is based on the actual bit width of R. This is because, in the initial stage of power-on, the clock is not yet stable, the transmit and receive ends have not yet converged, the analog front-end bias drifts, and the comparator threshold transient shifts or... When a valid candidate value has not yet been obtained through edge closure, relying solely on / The proportional relationship may still result in false closure.

[0141] In other words, only: However, the possibility of erroneous proportional false closure cannot be ruled out; therefore, it is still necessary to combine [the analysis with other methods]. And jointly verify the logical polarity and permutation order of the complete acceptance sequence. Let: ; .

[0142] The transpolar difference residual is: .

[0143] This relationship is used to perform a consistency check on two heteropolar measurement residuals under the same signed scale, ensuring that the configuration guide measurement results not only satisfy their own K-fold scale relationship but also close together with the first logical polarity controlled reference window. When and When using a common counter, a common sampling clock, a common edge reference, or a shared fixed delay, the differential residuals can also cancel out or reduce the corresponding common measurement errors. Therefore, the three scale relationships together constitute a joint chain of evidence formed by the microscale, the second logic polarity configuration anchor point, and the first logic polarity controlled reference window.

[0144] S104: If the cross-polarity signed scale reference calibration and the closed interval arithmetic verification are passed, then enter the locked state, stop sending the configuration guide and the integrity calibration sequence, so that the complete acceptance sequence is missing, and in the locked state, the longest continuous window of the first logical polarity formed by the service is strictly shorter than the length of the reference guide, so that the idle window cannot satisfy the reference calibration relationship, thereby preventing erroneous updates.

[0145] like Figure 10 As shown, once the system has successfully adapted to and locked the current baud rate, the sending end can stop sending the configuration guide and the subsequent 1-bit first logical polarity unit and 1-bit second logical polarity unit, retaining only the stop bit, idle bit, and normal service bit.

[0146] After the transmitter enters the locked state, the receiver's baud rate acceptor continues to perform signal acquisition, candidate extraction, and acceptance verification. Because the longest first logical polarity continuous window formed by ordinary services is strictly smaller than the controlled reference pilot bit width R, the first logical polarity window in ordinary services cannot satisfy... ≈R· The reference calibration relationship is established; at the same time, the sending end no longer sends the Kbit second logical polarity configuration guide and the subsequent 1bit first logical polarity unit and 1bit second logical polarity unit, so ordinary services cannot form a complete admission constraint sequence.

[0147] Therefore, although the receiver baud rate acceptor is always working, ordinary service signals in the locked state cannot close the acceptance evidence chain, will not form a new valid baud rate acceptance result, and will not be triggered by ordinary services to replace the currently accepted baud rate.

[0148] 1. Higher problem definition: Traditional solutions mainly address "how to estimate the baud rate from the absolute width of the local pulse", while this application mainly addresses "how to prove in layers whether a candidate baud rate is worth accepting under the premise of failed unipolar prior, and naturally suppress erroneous updates after locking".

[0149] 2. Clearer fail-safe mechanism: The present application no longer generally describes that "configuring a guide symbol plus multi-layer verification can improve reliability", but clearly distinguishes that under the conditions that the preset failure unipolar model and the measurement error budget are valid, the simple configuration of the guide symbol and the closed-interval arithmetic verification can deterministically reject disturbances where wf≥Tbit and which actually change the candidate admission measurement quantity; for disturbances with 0<wf<Tbit, the false closure formed by proportional error scaling is eliminated through cross-polarity differential reference calibration and , so that erroneous candidates whose residuals exceed the preset tolerance boundary or whose sequence form is not closed are deterministically rejected.

[0150] 3. More thorough utilization of unipolar physical failures: The present application directly converts the fault unipolar physical phenomena caused by fiber-optic loss of light, bus disconnection, pull-up / pull-down / Fail-Safe bias into mathematical monotonicity constraints, which is not fully utilized by general auto-baud rate schemes.

[0151] 4. Faster reloading: The present application uses the controlled Rbit first logic polarity reference guide symbol in the complete admission sequence as the calibration source. Since = , the receiving end can independently complete before capturing the edge closed capture; once the Kbit second logic polarity configuration guide symbol is captured subsequently, the cross-polarity reference calibration can be quickly executed.

[0152] 5. Safer locked state: The present application is not only "cautious during admission", but further uses two mechanisms after "being already locked": the window of the first logic polarity of normal service is shorter than the preferred Rbit reference guide symbol, and the complete admission sequence is missing, to suppress the re-admission condition, so it is safer than schemes that are continuously exposed to update conditions.

[0153] 6. Lower cross-layer burden: The main screening process of candidate values is completed in the physical layer in a closed manner, without waking up the CPU, assembling packets, or performing CRC, which is beneficial to reducing the upper-layer interrupt burden and software trial-and-error overhead caused by the upward transmission of erroneous candidate values.

[0154] 7. Suitable for pure hardware implementation: The main functions of the present application can be implemented by FPGA / CPLD / ASIC state machines, comparators, counters, filters and latches, and are suitable for integration in underlying hardware transceiver links.

[0155] In one embodiment, due to the constraint that "fault unipolarity is biased towards the first logical polarity," the maximum value of the second logical polarity is scarce. Therefore, during the verification process, possible anchor points of the second logical polarity are preferentially retained. Furthermore, the receiver does not completely blindly wait for the unique anchor point of the second logical polarity to reappear; instead, it can continuously update the micro-reference pulse width based on the first logical polarity. This ensures the reliability of subsequent closed-range verification and morphological examination.

[0156] Specifically, such as Figure 11 As shown, whenever the feature verification pulse width is updated, a closed-interval arithmetic verification is attempted using the micro-reference pulse width. If the closed-interval arithmetic verification passes, the transpolar signed scale reference calibration continues; if the closed-interval arithmetic verification fails, the updated feature verification pulse width is retained, and the locked state is not entered.

[0157] This application preferably employs a greedy search strategy prioritizing the second logical polarity anchor point. The receiving end first determines whether the width of consecutive second logical polarity pulses is greater than the current one. If it is greater, then update. And then proceed to candidate acceptance verification.

[0158] Candidate acceptance verification is preferably performed in the following order: 1) According to right Perform closed interval arithmetic verification; 2) Perform morphological pulse width check on the first logical polarity unit 1 bit after configuring the bootstrap; 3) Perform morphological pulse width check on the subsequent 1-bit second logic polarity unit; 4) Use Candidate values ​​are subjected to transpolar differential reference calibration.

[0159] If captured hour If convergence has already occurred in the normal data stream, the above 1-bit + 1-bit morphological check can be performed directly. Differential calibration. To avoid Occasional abnormal over-widening can lead to deadlock; the system can be configured with anchor point timeout reload. Preferably, when a single candidate acceptance verification fails, already captured candidates are not immediately cleared. Instead, it retains the second logical polarity candidate anchor point and reloads or continues updating. Only when the anchor point timeout condition, the condition of not refreshing for a long time, or the condition of continuous failure is met will the [anchor point] be refreshed. Restored to the minimum value. It can be restored to the maximum value when the overload condition is triggered; Only based on the complete admission sequence period The edge closure capture process is refreshed.

[0160] The implementation includes a timeout reload mechanism. If, after a preset time has elapsed since the feature verification pulse width update, the closed-interval arithmetic verification or transpolar signed scale reference calibration has not yet been passed, a reload is triggered, resetting the feature verification pulse width to its minimum value, the reference window measurement pulse width to its minimum value, and the microscopic reference pulse width to its maximum value. The greedy search strategy in this embodiment requires a timeout reload to prevent... In an extreme, intermittent situation, a wider level than the normal configuration bootstrap was acquired, resulting in a deadlock that consistently failed the closed-interval arithmetic verification. Recovery during reload. , For the minimum value, The maximum value is sufficient. This strategy reduces computation and accelerates convergence.

[0161] Of course, besides the greedy search strategy, another alternative implementation is to initiate a candidate calculation each time a complete second logic polarity continuous pulse width is detected. If, theoretically, a continuous second logic polarity pulse width not less than the current value is detected at a position theoretically located within the 1-bit second logic polarity morphological verification region... If this happens, the segment will no longer be processed as a 1-bit morphological unit, but should be reclassified as a new second logical polarity configuration bootstrap candidate. The receiving end updates or maintains the pulse width of this continuous second logical polarity. And re-initiate candidate acceptance verification; where the pulse width is greater than the current Update with this larger pulse width. The candidate acceptance verification is then re-initiated. This scheme requires more computation than the anchor-first retention strategy, but it reduces the risk of deadlock caused by improper selection of candidate anchors.

[0162] In one embodiment, morphological spatiotemporal interlock verification, temporal uniformity check, and anchor point retention priority / timeout reload can also be performed as an enhancement layer.

[0163] Example 1: Determine the first matching result between 1 bit of the first logic polarity and the micro reference pulse width; determine the second matching result between 1 bit of the second logic polarity and the micro reference pulse width; if both the first and second matching results are a match, then pass the morphological verification; otherwise, reject the current candidate baud rate and re-capture.

[0164] It should be noted that the failure safety referred to in this application means that, under the conditions that the preset failure unipolar model after polarity normalization and front-end filtering is valid and the measurement error does not exceed the preset error budget, candidate samples whose sequence morphology or scale residuals exceed the mimicry boundary are deterministically rejected; for samples whose residuals are still within the tolerance boundary and whose sequence evidence is completely closed, the physical layer accepts the candidate baud rate without determining whether the sample originates from a fault. This conclusion does not mean that it is unconditionally valid under arbitrary physical damage, arbitrary front-end internal failure, or arbitrary bipolar anomaly perturbation; external operating conditions are enhanced by morphological interlocking, time consistency checks, timeout overload, and higher-level verification mechanisms.

[0165] Configure the bootstrap character in Kbit, 1 bit + 1 bit controlled unit, and first logic polarity controlled reference bootstrap character. based on After the edge-closed capture mechanism, transpolar differential reference calibration and closed interval review have been combined to form the main acceptance system, the system can still further perform morphological spatiotemporal interlock verification, that is, detect whether the local short units after the guide appear in a predetermined order and with a predetermined width, in order to exclude erroneous candidate values ​​of "local ratios are accidentally true but local bit morphology is inconsistent".

[0166] Example 2: The complete admission constraint sequence is repeatedly transmitted at a preset period by the transmitting end. The admission constraint sequence includes a K-bit second logical polarity configuration guide and an integrity calibration sequence. The preset period is determined based on the period of occurrence of the inter-frame idle position of the service frame or an integer multiple thereof, or based on a fixed insertion period at the stop bit boundary at the end of the frame. If a single admission constraint sequence passes the cross-polarity signed scale reference calibration and closed interval arithmetic verification, it enters a pre-locked state. If a preset number of consecutive admission constraint sequences enter the pre-locked state, the timestamp Ti corresponding to the same preset reference edge in each admission constraint sequence is recorded, and the time interval between two adjacent preset reference edges is determined to satisfy: If so, it enters the locked state; where the preset reference edge is any one of the start edge of the configuration guide, the end edge of the configuration guide, or the end edge of the reference guide. The timestamp corresponding to the preset reference edge in the i-th acceptance constraint sequence. To accommodate the repetition period of the constraint sequence, This is the preset tolerance threshold.

[0167] To address complex chaotic scenarios such as hard failure of the fail-safe bias network, high-energy second-logic-polarity EMI pulses breaking down the fail-safe bias network, leading to unstable reception of the configuration guide and occasional passage of local random fragments through the aforementioned verification, the receiver can further introduce a macroscopic time consistency check. The transmitter then uses custom macroscopic rhythm parameters... Repeatedly transmit a complete admission sequence or its equivalent configuration sequence; the receiving end does not immediately open the data channel upon a single successful verification, but enters a pre-locked state and records a local timestamp. The pre-locked state referred to herein is only an internal pre-confirmation state adopted by the receiving end when performing multiple time consistency checks, is not equivalent to the transmitting end's locked state, nor does it indicate that the baud rate acceptor at the receiving end stops capturing, calculating or verifying. This time uniformity check does not change the necessary conditions of the main admission chain, but performs enhanced confirmation on the macroscopic rhythm consistency of admission events under complex chaotic working conditions. Only after the candidate baud rate meeting the conditions is independently identified for multiple consecutive times, the system calculates the time interval between adjacent identification events, and determines whether the absolute value of the difference is less than a preset macroscopic time domain tolerance threshold.

[0168] Embodiment 3 is provided with a timeout overload mechanism, which has been described in the foregoing embodiments and will not be repeated here.

[0169] In one embodiment, a fail-safe hardware interception defense mechanism and a probabilistic fallback formula are provided.

[0170] The fail-safe feature is divided into two layers: The first layer: deterministic rejection layer. Under the condition that the preset failure unipolar model is established and the measurement error does not exceed the preset error budget, for the first logical polarity fault where wf≥Tbit and actually changes the candidate admission measurement, the configuration descriptor and closed interval arithmetic verification can form deterministic rejection for unclosed candidate samples; for the first logical polarity narrow disturbance with 0<wf<Tbit, through configuration descriptor integrity calibration and upper and lower boundary review, candidate samples with proportionally scaled errors and residuals exceeding the tolerance boundary are deterministically rejected. For samples whose residuals are still within the tolerance boundary and whose complete admission sequence evidence is closed, they are processed according to samples within the mimetic boundary.

[0171] The second layer: probabilistic fallback layer. When the ideal unipolar condition is damaged by working conditions such as extreme high-energy pulse impact, medium collapse, strong common-mode breakdown or severe mechanical damage, the system can still rely on enhancement layers such as morphological space-time interlocking verification, time uniformity check, anchor reservation priority / timeout overload to form an additional probabilistic defense line.

[0172] From the perspective of engineering probability, let: E1: abnormal narrow pulse passes through the front-end filter; E2: Integrity calibration and closed interval arithmetic verification pass simultaneously; E3: morphological space-time interlocking verification passes; E4: time uniformity check passes.

[0173] In the implementation manner where the front-end filter, configuration descriptor integrity calibration, morphological space-time interlocking verification and time uniformity check are enabled at the same time, the final acceptance of an erroneous candidate baud rate requires E1, E2, E3 and E4 to occur simultaneously, that is =E1∩E2∩E3∩E4. This expression is only used to determine the event chain that needs to be observed for fault injection test, simulation or field statistics, and does not directly give the value or upper bound of the error acceptance probability; only after obtaining the conditional probability, correlation data or conservative upper bound of each event, can P( be further calculated or estimated |fault).

[0174] In one embodiment, the present application is generally and inductively described as follows: In view of the shortcomings in the conventional solutions, the purpose of the present application is not to provide another baud rate algorithm centered on single-point absolute value estimation, but to provide: establishing a microscopic scale through first logical polarity binding; establishing a macroscopic unique anchor point through a second logical polarity configuration guide; forming an acceptance constraint sequence with 1 bit of first logical polarity + 1 bit of second logical polarity + controlled R bit of first logical polarity referring to the guide; wherein the length of the second logical polarity configuration guide is denoted as K bits, the length of the first logical polarity reference guide is denoted as R bits, the two satisfy D=R−K, and the value of R is subject to the aforementioned parameter definition; with ≈K* , ≈R* and − ≈D* The cross-polarity reference calibration relationship embodied in completes high-reliability acceptance; wherein D=R−K; by stopping sending the K-bit second logical polarity configuration guide and the subsequent 1-bit + 1-bit controlled unit in the locked state, the complete acceptance sequence is missing, thereby suppressing erroneous re-updating.

[0175] Further, the present application does not merely list the above structures, but develops around three core vulnerabilities: first, the conventional solutions do not establish the order of "acceptance rather than estimation"; second, the conventional solutions do not reveal the key vulnerability of proportional scaling in the scenario of 0<wf<1 bit and ; third, the conventional solutions do not break the re-entry condition from the transmission mode in the locked state. To this end, the purpose of the present application is to establish a fail-safe acceptance order that is governed by unipolar failure constraints, takes vulnerability patching as the advancement path, takes the mimetic boundary as the identification limit, and takes whether the candidate baud rate is accepted as the only evaluation target.

[0176] The difference between the present application and the conventional solutions does not lie in "how to estimate the absolute bit width of a certain pulse more accurately", but in: how to construct a fail-safe candidate baud rate acceptance chain inside the physical layer, and further construct a set of transmission-reception coordinated acceptance constraint sequence and locked state suppression mechanism, so that the system refuses to update by default when the evidence chain is not closed.

[0177] In the specific implementation of this application, a failure-safe non-return to zero (NRZ) candidate baud rate acceptance method based on failure polarity binding, cross-polarity differential reference calibration, and mimicry boundary acceptance is provided. Its core does not lie in directly measuring the absolute bit width corresponding to a local pulse, but rather in: forming a microscopic measurement scale through failure polarity binding, forming a macroscopic unique anchor point through a second logic polarity configuration guide, extracting a bit-level scale through a controlled 1-bit short sequence following the guide, and forming cross-polarity signed scale circumstances through a first logic polarity controlled reference guide; this reference guide can be compatible with stop bits or idle semantics in usable scenarios and only accepts candidate baud rates when the above information is collectively closed; otherwise, it defaults to rejecting updates and re-acquiring. This method can be implemented using low-level hardware state machines such as Field-Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and Application-Specific Integrated Circuits (ASICs).

[0178] It should be noted that the acceptance constraint sequence is not a simple list of several independent verification conditions, nor is it a passive waiting at the receiver for multiple pulse widths to coincidentally meet the threshold simultaneously. Rather, it is a systematic chain of evidence actively constructed at the sender and parsed by the receiver according to a state machine. In this chain of evidence, Provide a microscopic scale, It provides a unique anchor point for the second logical polarity, and a 1-bit+1-bit controlled short bit sequence provides local true bit width and morphological order constraints. It provides a first logical polarity-controlled reference window and cross-polarity signed scale circumstances. These elements mutually limit and calibrate each other, together forming a pseudo-boundary acceptance system. Only when the entire system is closed is a candidate baud rate accepted; if any part is not closed, the system defaults to refusing to update.

[0179] In one embodiment, alternatives to some solutions are provided: 1. Alternatives to Closed Interval Verification: Besides using multipliers to implement the closed interval relationship described above, equivalent alternatives include implementations based on division, table lookup, proportional threshold mapping, or interval comparator arrays, as long as the essence remains the same: using the relationship between microscale and macroscopic pulse widths to determine whether candidate baud rates meet the acceptance criteria. These equivalent implementations do not change the fundamental nature of this application's candidate acceptance based on the relationship between microscale and macroscopic anchor points.

[0180] 2. Replacement of K / R length and acceptance sequence position: The theoretical lower bound of R is I+X. This application preferably adopts: R=I+X, so that the controlled reference pilot is 1 bit longer than the natural longest first logical polarity continuous window of ordinary traffic.

[0181] When existing service protocols naturally contain available inter-frame idle periods, the sender can replace the idle period with a complete acceptance sequence in the open acceptance state, using the original idle period position as an anchor point. This replacement can occur at every available idle period position, or it can occur once every N idle periods; correspondingly, Can be equal to It can also be equal to N* The first logical polarity reference guide in the complete acceptance sequence is compatible with the original stop bit / inter-frame idle structure in terms of length, polarity, and protocol semantics, and can be recognized by the receiver as an idle compatibility window, thereby maintaining compatibility with the original service frame boundaries and idle mechanism to the greatest extent.

[0182] When there is no available inter-frame free space in the existing service protocol, the sending end can press the stop bit at the frame boundary where the end of a frame is located. Periodic insertion of complete acceptance sequence. It can be inserted once every N service frames, and it is not required to insert it at the end of every frame.

[0183] In other embodiments, the target length of the second logical polarity configuration guide can be denoted as Cbit, and the target length of the first logical polarity reference guide or idle compatibility reference window can be denoted as Rbit. R can be equal to C, or greater than or less than C; however, R should satisfy the idle compatibility and maximization requirements of the first logical polarity reference window, with a theoretical lower limit of I+X. Corresponding to the main implementation method in the text, R can be I+X; in other alternative implementation methods, R can also be a value greater than I+X. There is a preset signed scale relationship between R and C, denoted as D=RC. Such alternative implementation methods still need to satisfy: First, the reference guide and the configuration guide are in different logical polarities; Second, the configuration guide length C satisfies the unique anchor point requirement, i.e., C>X-1; Third, the reference window length R satisfies the idle compatibility, bus reset, or inter-frame idle identification requirements; Fourth, there is a preset signed scale relationship between R and C, denoted as D=RC; Fifth, this signed scale relationship can be combined with right Complete independent integrity calibration.

[0184] 3. Subsequent replacement of controlled units: In addition to 1 bit first logic polarity + 1 bit second logic polarity + R bit first logic polarity referencing the bootstrap, other methods capable of simultaneously achieving "real bit width extraction" can also be used. Controlled cell sequence of "independent integrity calibration" and "multiplexing with idle with the same polarity".

[0185] 4. Replacement of the reference bootstrap: The reference bootstrap can be implemented by an artificial idle word, placeholder word, safe state word, control word, or other protocol-innocent unit. Any reference bootstrap that essentially forms the first logical polarity of the controlled Rbit and is used for... All schemes for transpolar signed scale reference calibration are alternative embodiments of the present invention; the scale relationship is expressed as the D-bit signed difference component between Rbit and Kbit, where D=RK.

[0186] 5. Alternative to the locked-state suppression of re-acceptance: In one implementation, the transmitter stops transmitting the K-bit second logical polarity configuration guide and the subsequent 1-bit+1-bit controlled unit in the locked state, resulting in the absence of a complete acceptance constraint sequence. In other implementations, the transmitter may also stop transmitting any necessary component of the complete acceptance constraint sequence, or change the preset order of the necessary components, so that the receiver cannot obtain a complete and closed chain of acceptance evidence from the actual received signal. The receiver's baud rate acceptor continues to operate in the aforementioned transmitter-locked state, without closing the acceptance window or prohibiting... Updating or stopping candidate verification is a necessary means to suppress re-admission in a locked state. Any scheme that essentially changes or omits the complete admission constraint sequence at the sending end, preventing normal services from forming new valid admission results, belongs to the alternative implementation methods of this application.

[0187] 6. Alternatives to time uniformity checks: In addition to comparing whether the time interval difference between adjacent identified events is less than a preset threshold, multiple periodic deviation accumulation, sliding window consistency judgment, windowed rhythm scoring, or other macroscopic rhythm consistency algorithms can also be used, as long as their essence is still to further enhance the judgment of the macroscopic time consistency of identified events.

[0188] 7. Configuration of alternatives between guide sign retention and timeout reload: During the recapture phase, unique anchors can be preserved using methods such as second logical polarity candidate maximum value retention, sliding retention, retention with timeout, retention with refresh threshold, or retention by priority. Furthermore, configuration guide reloading can be triggered by methods such as fixed timeout, reload cycle counting, verification chain closure failure count, or anchor point not being refreshed for a long period of time. Any scheme that essentially achieves "prioritizing the retention of the unique anchor point of the second logical polarity and then performing cleanup and reloading after the timeout condition is met" is an alternative implementation of this application.

[0189] 8. Alternative Communication Media: Although this application uses optical fiber communication as an example, it can also be extended to communication media with asymmetric physical failure polarity characteristics, such as RS-485 and single-ended bus. For the differential electrical signal physical layer, a Fail-Safe bias network can be added to clamp the high-impedance state of the disconnected wire to the first logic polarity.

[0190] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A mimicry-based fail-safe baud rate acceptance method for transpolar differential reference calibration, characterized in that, include: At the receiving end, based on the failure unipolar constraint, the micro reference pulse width is dynamically extracted and updated through front-end filtering and the minimum pulse width of the first logic polarity; wherein, the first logic polarity is the bus level state presented by the communication medium when it fails physically. The transmitting end sends a configuration guide with a second logical polarity whose length meets the preset requirement, and the receiving end updates the feature verification pulse width with a retention priority strategy as a macroscopic unique anchor point; wherein, the second logical polarity is an effective strong drive level state opposite to the first logical polarity; the preset requirement is used to ensure that the length of the configuration guide is greater than the maximum natural length of consecutive second logical polarities appearing in the asynchronous serial communication word format; The transmitter sends a predefined integrity calibration sequence, and the receiver measures the pulse width and the micro-reference pulse width according to the reference window of the reference guide in the integrity calibration sequence. The feature verification pulse width is then subjected to cross-polarity signed scale reference calibration, and closed-interval arithmetic verification is performed using the micro-reference pulse width. The integrity calibration sequence includes a first logical polarity, a second logical polarity, and a first logical polarity reference guide whose length satisfies a preset requirement with respect to the length of the configuration guide. If the cross-polarity signed scale reference calibration and the closed interval arithmetic verification are passed, the system enters a locked state, stops sending the configuration guide and the integrity calibration sequence, resulting in the absence of a complete acceptance sequence. In the locked state, the longest continuous window of the first logical polarity formed by the service is strictly shorter than the length of the reference guide, so that the idle window cannot satisfy the reference calibration relationship, thereby preventing erroneous updates.

2. The method according to claim 1, characterized in that, At the receiving end, based on the failed unipolar constraint, the micro-reference pulse width is dynamically extracted and updated through front-end filtering and the minimum pulse width of the first logic polarity. Specifically, this includes: The bus level state exhibited by the communication medium when it fails physically is defined as the first logic polarity; The receiver continuously monitors the bus signal and uses a digital filter to filter out narrow pulses with a width less than a preset threshold. For the duration of the filtered level that belongs to the first logic polarity, the minimum confident pulse width is extracted as the micro reference pulse width.

3. The method according to claim 1, characterized in that, The sending end transmits a configuration guide with a second logical polarity whose length meets the preset requirements, specifically including: During the link initialization or recovery phase, the sending end actively sends a continuous second logical polarity of length K bits as a configuration guide. Wherein, the value of K satisfies K>X-1; where X represents the total number of bits in a single word, including start bit, data bits, optional parity bit and stop bit.

4. The method according to claim 1, characterized in that, At the receiving end, the pulse width is updated using a retention-first strategy to verify the feature, serving as a unique macroscopic anchor point. Specifically, this includes: The feature verification pulse width is obtained from the maximum sustained pulse width of the second logical polarity at the receiving end and used as the macroscopic unique anchor point. Whenever a larger second logical polarity is obtained, the feature verification pulse width is updated.

5. The method according to claim 4, characterized in that, The method further includes: Whenever the feature verification pulse width is updated, an attempt is made to perform closed interval arithmetic verification using the micro-reference pulse width; If the closed-interval arithmetic verification is passed, then the transpolar signed scale reference calibration continues. If the closed interval arithmetic verification fails, the updated feature verification pulse width is retained, and the locked state is not entered.

6. The method according to claim 5, characterized in that, The method further includes: A timeout reload mechanism is set up so that if the feature verification pulse width fails to pass the closed interval arithmetic verification or the transpolar signed scale reference calibration after a preset time has elapsed since the update, a reload is triggered to reset the feature verification pulse width to the minimum value, the reference window measurement pulse width to the minimum value, and the microscopic reference pulse width to the maximum value.

7. The method according to claim 3, characterized in that, The integrity calibration sequence includes a 1-bit first logical polarity, a 1-bit second logical polarity, and an R-bit first logical polarity reference guide; At the receiving end, the pulse width is measured according to the reference window of the reference guide in the integrity calibration sequence. Transpolar signed scale reference calibration is performed on the feature verification pulse width, and closed-interval arithmetic verification is performed using the microscopic reference pulse width. Specifically, this includes: The receiving end determines the signed bit difference D between the length R of the reference guide and the length K of the configuration guide, where D = RK, and measures the reference window measurement pulse width of the reference guide. The reference window measurement pulse width is obtained by the receiving end through edge closure capture based on a preset complete admission sequence period. The receiving end uses a capture period equal to the complete admission sequence period for the reference window measurement pulse width, starts timing from the valid edge, and continues to wait for the next edge closure capture window after the timing reaches or exceeds the capture period. The maximum complete first logic polarity pulse width is selected as the candidate value of the reference window measurement pulse width within the edge closure capture window. Determine the pulse width difference between the reference window measured pulse width and the feature verification pulse width, and verify whether the residual between the pulse width difference and D times the microscopic reference pulse width is within the preset differential tolerance range; Closed-interval arithmetic verification is performed on the feature verification pulse width and the reference window measurement pulse width, respectively; wherein, for the feature verification pulse width, it is verified whether the residual between it and K times the micro-reference pulse width is within a first preset tolerance range; for the reference window measurement pulse width, it is verified whether the residual between it and R times the micro-reference pulse width is within a second preset tolerance range. If both the transpolar signed scale reference calibration and the closed interval arithmetic verification pass, then the feature verification pulse width is determined as the verified configuration guide measurement pulse width.

8. The method according to claim 7, characterized in that, The method further includes: Determine the first matching result between the measured pulse width of the 1-bit first logic polarity unit and the microscopic reference pulse width; Determine a second matching result between the measured pulse width of the 1-bit second logic polarity unit and the microscopic reference pulse width; If both the first and second matching results are a match, then morphological verification is passed; otherwise, the current candidate baud rate is rejected and re-capture is performed.

9. The method according to claim 7, characterized in that, The method further includes: The complete admission constraint sequence is repeatedly transmitted through the transmitting end at a preset period; wherein, the admission constraint sequence includes a configuration guide with Kbit second logical polarity and the integrity calibration sequence; the preset period is determined according to the occurrence period of the inter-frame idle position of the service frame or an integer multiple thereof, or according to the fixed insertion period at the stop bit boundary of the frame end; If a single acceptance constraint sequence passes the transpolar signed scale reference calibration and the closed interval arithmetic verification, it enters the pre-locked state. If the acceptance constraint sequence enters the pre-locked state for a predetermined number of consecutive times, then the timestamp corresponding to the same predetermined reference edge in each acceptance constraint sequence is recorded, and the time interval between two adjacent predetermined reference edges is determined to satisfy: Then it enters a locked state; where, This refers to the timestamp corresponding to the preset reference edge in the i-th acceptance constraint sequence. For a complete admission sequence period, A preset tolerance threshold is defined; the preset reference edge is any one of the starting edge of the configuration guide, the ending edge of the configuration guide, or the ending edge of the reference guide.

10. The method according to claim 7, characterized in that, When the original service protocol stipulates that the continuous window of the first logical polarity of ordinary services has a finite maximum value, let the maximum number of bits of idle space between ordinary service frames be . Then, the maximum length of the first logical polarity continuous window that can be naturally formed by ordinary business operations is +X-1, the length R of the reference guide symbol satisfies: R> When R is an integer, R≥Imax+X.

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