A segmented interleaving error correction method for multi-core NoC interposer

Abstract

The application discloses a segmented interleaving error correction method for a multi-core particle NoC interlayer, and relates to the fields of network-on-chip link reliability and error correction coding technology. Temperature samples, error position data, interleaving depth, frame serial numbers and in-transit frame counts are obtained to form trusted temperature and error trajectory; adjacent temperature differences, boundary threshold values and residence state update logic interleaving sections are updated; residual error code rates and cache delays are predicted to determine a section level depth lower bound when error aggregation is within an error correction range; a coordinated depth meeting end-to-end error code and delay constraints is formed according to risk contribution and delay increment; a target depth is formed through fluctuation bands and adjustment amplitudes; segmented, depth and applicable frame ranges are bound to form a configuration epoch; after preloading and confirmation, consistency is submitted at a frame boundary; old epochs are reserved until in-transit frames are cleared; and a performance table is corrected according to actual and predicted residual error code rate deviations for determining a depth lower bound in a next period. The application improves the stability of segmented error correction control.

Description

Technical Field

[0001] This invention relates to the field of on-chip network link reliability and error correction coding technology, and in particular to a segmented interleaving error correction method for multi-core NoC intermediary layers. Background Technology

[0002] Multi-chip integrated systems typically achieve data transmission between chips via on-chip network links on the interposer layer, and utilize error correction coding and interleaving to reduce data errors caused by link noise, crosstalk, and thermal disturbances. Due to differences in chip power density, heat dissipation paths, and communication loads, the interposer layer is prone to uneven temperature distribution along the link direction, which varies with operating conditions. This results in differences in timing margins, noise tolerance, and burst error characteristics across different link regions. Existing error correction methods often determine fixed parameters based on link conditions during the design phase, or adopt uniform parameters based on the overall state of the entire link, making it difficult to simultaneously address the error correction needs of high-risk local areas and the transmission delay requirements of other areas.

[0003] Existing link monitoring typically collects temperature status and receiver error statistics separately. These two types of data may have different sampling locations, statistical periods, and time bases, and are often aggregated into core-level or link-level state variables. Because temperature data and error data lack a direct correspondence to the same transmission process, errors observed at the receiver are not easily correlated accurately with the local thermal state during the data's passage through the link. Longer statistical windows can smooth out local burst errors, while shorter windows are more susceptible to transient noise. Furthermore, when using a fixed monitoring area, thermal distribution migration can cause different electrical characteristics of adjacent areas to be mixed, leading to distorted link risk estimation or delayed response.

[0004] At the error correction decision-making stage, existing technologies typically select a uniform interleaving depth based on the average or worst-case link state. An excessively large interleaving depth can increase buffer usage and transmission latency, while an excessively small interleaving depth may fail to adequately disperse continuous errors generated in localized areas. Adjusting error correction parameters separately for each link region without unified end-to-end reliability and latency verification can lead to situations where local judgments meet requirements while residual errors accumulate across the entire link. Inconsistencies between the sending and receiving sides during parameter updates, or confusion between old and new parameters, can also cause deinterleaving misalignment. Furthermore, the lack of effective correction to existing error prediction relationships after changes in operational status can cause subsequent judgments to gradually deviate from actual link characteristics, affecting the stability of multi-core communication. Summary of the Invention

[0005] To address the issues of uneven spatial thermal state in multi-core NoC interposers, the difficulty in simultaneously balancing local error correction capability and transmission delay with a uniform interleaving depth, and the potential inconsistency between old and new parameters during dynamic adjustment, this invention provides a segmented interleaving error correction method for multi-core NoC interposers.

[0006] This invention provides a segmented interleaving error correction method for multi-core NoC interposer layers, comprising:

[0007] Configurable link relay nodes are set along the physical links between core particles. Temperature samples, error location data, current interleaving depth, frame number and in-transit frame count are obtained for each node. A reliable temperature sequence and an error run length sequence are formed according to the link position and frame number.

[0008] The logical interleaving segment set is updated based on the temperature difference between adjacent reliable temperatures, the boundary establishment threshold, the boundary cancellation threshold, and the boundary dwell status, and error correction encoding / decoding and cross-weaving functions are enabled at both ends of each logical interleaving segment.

[0009] Based on the temperature representative value of each logical interleaving segment and the target quantile length of the error run, the predicted residual bit error rate and buffer latency of each depth level are obtained from the candidate depth performance table. The lower bound of the segment-level depth is determined with the condition that the single codeword error clustering degree is within the error correction capability range.

[0010] Starting from the lower bound of the segment-level depth, a coordinated depth set is formed based on the risk contribution of each logical interleaving segment and the latency increment of the depth level to satisfy the end-to-end target residual bit error rate and the upper limit of total cache latency.

[0011] Compare the coordination depth set with the current interleaving depth, form a target depth set according to the allowable fluctuation band and single-cycle adjustment range, bind the logical interleaving segment set, the target depth set and the applicable frame range as a new configuration epoch and preload them into the spare parameter buffer;

[0012] After the parameters are confirmed to be consistent, a new configuration epoch is submitted at the frame boundary of the applicable first frame, and the old configuration epoch is retained until the corresponding in-transit frame count is cleared to zero. Obtain the actual residual bit error rate of each logical interleaving segment, correct the candidate depth performance table based on the deviation between the actual residual bit error rate and the predicted residual bit error rate, and use the corrected result to determine the lower bound of the segment-level depth in the next control cycle.

[0013] In summary, the present invention has at least one of the following beneficial technical effects: This invention aligns temperature samples and error location data according to frame sequence number and link propagation period, and combines valid flags, range flags, and spatial residuals to form a reliable temperature sequence, making the local thermal state comparable to the error performance in the same transmission process. Based on the alignment result, according to the temperature difference between adjacent reliable temperatures and the set of interleaved segments updated by establishing and canceling dual thresholds and dwell state, it can suppress repeated boundary migrations caused by temperature measurement fluctuations and make each segment a continuous link interval with similar temperature characteristics. Furthermore, it matches the candidate depth performance table with the segment-level temperature representative value and the target quantile length of the error run, and forms a lower bound for the segment-level depth by constraining the error clustering degree of the error run falling into a single codeword after interleaving to be within the error correction capability range. This makes the interleaving depth constrained by local thermal risk, sudden error morphology, and actual error correction capability, thereby reducing the situation where the link average state masks local sudden errors, and avoiding unnecessary interleaving depth in low-risk segments while ensuring the error dispersion capability of high-risk segments.

[0014] This invention uses the aforementioned set of logically interleaved segments, the lower bound of segment-level depth, and the predicted residual bit error rate and buffer latency given in the candidate depth performance table as continuous inputs. Under the constraints of the end-to-end target residual bit error rate, the upper limit of total buffer latency, and the difference in adjacent segment levels, it coordinates the depth of each segment. This ensures that local configuration adjustments are jointly verified by the overall link reliability and latency budget, reducing the possibility that a single segment may meet the requirements while the overall link residual error still accumulates and exceeds the limit. The coordination result is then constrained by the allowable fluctuation band and the single-cycle adjustment amplitude limit to form a target depth set, which is bound to the segment boundary and the applicable frame range to form a new configuration epoch. This is buffered by backup parameters. Preloading of the region, confirmation of consistent parameters, submission of frame boundaries, and emptying of frames in transit from the old epoch ensure that both the transmitting and receiving ends interpret data according to the same epoch when the depth and boundary gradually change, reducing deinterleaving misalignment caused by parameter mutations and mixing of old and new configurations; the actual residual bit error rate obtained after the handover is further narrowed and corrected to the corresponding candidate depth performance table entry when the deviation and sample quantity meet the conditions, and used to redetermine the lower bound of the segment-level depth in the next control cycle, thus forming a closed loop from risk identification, configuration coordination, safe handover to model correction, suppressing the continuous shift of the prediction relationship caused by changes in the link thermal state and improving the stability of segmented error correction control. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a segmented interleaving error correction method for multi-core NoC intermediary layers provided by an embodiment of the present invention.

[0017] Figure 2 This is a flowchart of the coordination and configuration sub-flow of a segmented interleaving error correction method for multi-core NoC intermediary layers provided in an embodiment of the present invention. Detailed Implementation

[0018] The following description, in conjunction with the implementation of the present invention, is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the concept of the invention, and all such modifications and additions should fall within the protection scope of the present invention.

[0019] Example This application discloses a segmented interleaving error correction method for multi-core NoC intermediary layers.

[0020] Reference Figure 1-2 A segmented interleaving error correction method for multi-core NoC intermediary layers, specifically including: This embodiment uses an active silicon interposer as the carrier structure for the multi-core NoC. The physical links between cores are formed by connecting continuous wiring sections and configurable link relay nodes. The configurable link relay nodes include a temperature sampling interface, a frame sequence number register, an error syndrome interface, a bypassable error correction encoding / decoding circuit, a cross-weaving address generator, an active parameter buffer, and a spare parameter buffer. Dynamic segmentation changes which existing relay nodes assume the responsibility of logical interleaving segment endpoints, without changing the physical breakpoints of the metal wiring. Therefore, each logical interleaving segment has a hardware endpoint that can actually perform interleaving, deinterleaving, error correction, and re-encoding.

[0021] Configurable link relay nodes are set along the physical links between core particles. Temperature samples, error location data, current interleaving depth, frame number and in-transit frame count are obtained for each node. A reliable temperature sequence and an error run length sequence are formed according to the link position and frame number. Specifically, a physical link is pre-configured with eight to sixty-four configurable link relay nodes according to signal integrity and pipeline timing requirements, with the center-to-center spacing between adjacent nodes ranging from 0.2 mm to 2 mm. Temperature sensors utilize on-chip PN junction temperature sensors, ring oscillator temperature sensors, or other digital temperature sensors co-located with the relay nodes, with sampling periods ranging from 1 s to 100 s. The above values ​​are for illustrative purposes only; the actual spacing and sampling period are determined by the interposer process, link length, and hotspot migration time constant.

[0022] Each downstream relay node stores the error bit position corresponding to the error syndrome during the error correction decoding process. For BCH codes or Reed-Solomon codes that can provide the error correction position, the corrected position is directly registered; for codewords that only provide an uncorrectable flag, the error event exceeding the error correction capability is also registered. The error position data carries the physical link identifier, logical interleaving segment identifier, frame sequence number, codeword sequence number, and error bit index. The segmented error correction controller uses a unified clock as a reference and utilizes the pipeline cycle number of the relay nodes to push back the temperature sampling time to the time window when the target frame passes through the corresponding position, ensuring that temperature data and error data belong to the same transmission object. Specifically, the frame... At the node The starting point of the time window is The destination is ;in, A unified clock count for frames entering the link. To reach the node The required number of flow cycles, For a single flow cycle, The sampling and holding period for each node is determined, and all four use the same time scale. If any input count overflows or becomes non-finite, the corresponding time window is not formed, and the alignment failure flag is set.

[0023] Temperature reliability is determined by the sensor's validity flag, range flag, and spatial consistency between adjacent points. This indicates that the valid label for the temperature sample is valid and the range label is within the calibrated range; if either condition is not met, When there are two effective neighbors, the spatial residual is... Take the absolute value of the difference between the node temperature and the median temperature of its two effective neighboring nodes; when there is only one effective neighboring node, Take the absolute value of the temperature difference with the neighboring point; if there are no valid neighboring points, then... Set to zero and set the adjacent point insufficient flag. To freeze the unique execution rule, this example sets... The confidence level of the sample is set to zero; for the remaining samples, if the spatial residual does not reach the spatial residual threshold, the confidence level is set to one; if it reaches the spatial residual threshold but does not reach the upper limit of the spatial residual, the confidence level is set to half; if it reaches the upper limit of the spatial residual, the confidence level is set to zero. The spatial residual threshold is taken as the maximum deviation of the factory constant temperature repeated test, and the upper limit of the spatial residual is taken as twice the maximum deviation. The confidence level is uniquely obtained in this way. The representative value of the segment-level temperature is calculated using the following formula: in, This is the set of indices for valid temperature nodes within the logically interleaved segment s. For nodes Temperature in Celsius within the alignment time window. For dimensionless temperatures ranging from zero to one, This represents the segment-level temperature value. The lower limit of the confidence weight is denoted as... Its range is from one to the total number of temperature nodes in that segment. The initial value is the minimum number of fully reliable samples required in repeated constant-temperature tests at the factory to ensure that the segment-level temperature error does not exceed twice the temperature measurement repeatability error. The current full window contains... When the temperature values ​​of a given segment are reliable, the segment-level temperature variance is: ,in Only in Calculate immediately; otherwise, record the window as a high-variance window. Set continuous high-variance counting at runtime. and low variance continuous count When the segment-level temperature variance of the current complete window exceeds the upper limit of the factory-set repeated test variance, Add one and Clear to zero; otherwise Add one and Reset to zero. When At that time, Add one but not more than And clear the count; when At that time, Decrease the count by one, but not below one, and reset it to zero; otherwise, retain the original value. Only when... Non-empty and If the nearest trusted temperature is not available during a cold start, the logical interleaving boundary will not be updated, and the reduction in depth and the submission of a new configuration epoch will be prohibited until the first trusted weight is obtained and the threshold is reached. The full window.

[0024] Error locations are listed in ascending order of intra-frame index. Adjacent error locations satisfy... If the error occurs, it is classified into the same incorrect run; otherwise, it is classified from... Start a new run; the current run is forcibly terminated at the end of the frame. The length of each run is equal to the difference between its last error location and its first error location plus one. A run length sequence is generated and online quantile calculation is prohibited. The controller registers the length of each run and obtains a sequence of erroneous run lengths. The recent statistics window can contain 16 to 4096 frames, and the historical window can be set to 4 to 32 times the size of the recent window. Expanding the window can reduce quantile statistics fluctuations, but it will delay the response to thermal state transitions, so it is jointly calibrated by the target reliability and the allowable response time.

[0025] The logical interleaving segment set is updated based on the temperature difference between adjacent reliable temperatures, the boundary establishment threshold, the boundary cancellation threshold, and the boundary dwell status, and error correction encoding / decoding and cross-weaving functions are enabled at both ends of each logical interleaving segment. Specifically, the controller generates a temperature gradient between adjacent nodes: in, For nodes The temperature difference between node i+1 and node i+1 is expressed in degrees Celsius. The boundary establishment threshold can be calibrated between 2°C and 15°C, and the boundary revocation threshold, which is lower than the corresponding establishment threshold, can be calibrated between 1°C and 12°C. The difference between the two thresholds should be higher than the repeatability error of the temperature sampling link. Candidate nodes establish boundaries only when the establishment threshold is reached for two to twenty consecutive control cycles; existing boundaries are revoked only when the threshold is reached for two to twenty consecutive control cycles and the holding time reaches the shortest holding period. Cases equal to the threshold are assigned to the trigger side, ensuring a unique state transition result.

[0026] The controller also checks the minimum number of link units between boundaries. If a logical interleaving segment cannot accommodate the data pipeline corresponding to a complete interleaving block after establishing a new boundary, the temperature difference between the two boundaries of the short segment is compared, and the boundary with the smaller temperature difference is canceled; if the temperature differences on both sides are equal, the boundary located downstream along the data transmission direction is canceled; for short segments located at the end of the physical link, only their internal boundaries are canceled. This yields a unique segment merging direction. Relay nodes identified as segment endpoints enable deinterleaving, error correction, recoding, and interleaving paths, while relay nodes within the segment use pipelined bypass paths; this method ensures that dynamic logical boundaries always fall on physical nodes with processing resources.

[0027] Based on the temperature representative value of each logical interleaving segment and the target quantile length of the error run, the predicted residual bit error rate and buffer latency of each depth level are obtained from the candidate depth performance table. The lower bound of the segment-level depth is determined with the condition that the single codeword error clustering degree is within the error correction capability range. Specifically, the interleaving depth uses discrete levels, such as 2, 4, 8, 16, and 32 codewords. The candidate depth performance table is established based on factory hot-box calibration and link error injection testing. Table entry keys include temperature range, error run length range, error correction code type, and depth level. Table entry data includes predicted residual bit error rate, buffer latency, and sample size. The controller sorts the error run length sequence in ascending order and obtains the target quantile length using the following formula: in, Let s be the number of valid erroneous runs within the logically interleaved segment, and p be the target quantile level in the range of 0.9 to 0.9999. Let be the length of the i-th erroneous run in the ascending sequence. denoted as the target quantile length of the erroneous run, in bits; D is the set of positive integer interleaving depths supported by the hardware. The number of error-correctable bits per codeword registered in the error correction capability register. This is the lower bound for segment-level depth. The lower bound for erroneous run quantile samples is denoted as... , and feedback update sample lower limit Register separately. The index starts at the beginning; if it is exactly an integer, take that integer index; otherwise, take only the integer index. Online quantile calculation is performed when the time is right; otherwise, the factory default entries are used, provided the historical window exists and the sample size reaches a certain threshold. Historical window results are only used when necessary. The error correction capability register is written to by the hardware configuration word of the selected error correction code during link initialization, and the configuration word is simultaneously tested by both the encoder and decoder.

[0028] For each depth level, this example sends the same-position data from d codewords in a round-robin fashion according to their codeword indices, so that consecutive transmission positions are sequentially mapped to different codewords; the receiving end writes back in reverse order according to the same codeword index. Therefore, the length is... The upper bound for the number of erroneous runs falling into any codeword is . If the clustering degree does not exceed the value in the error correction capability register... If the depth level passes the error correction capability check, then the controller iterates upwards from the lowest level, and the first level that passes the check becomes the lower bound of the segment-level depth. If the set... If D is empty, the minimum value operation is not performed, the segment is set to the highest protection depth in D, an insufficient capacity flag is output, and the segment depth reduction is prohibited; if D is empty or If the codec self-check fails, the current depth is maintained, committing a new epoch is prohibited, and a configuration table anomaly warning is issued. This mapping and the anomaly branch together provide a directly implementable rule for round-robin address occurrence.

[0029] Starting from the lower bound of the segment-level depth, a coordinated depth set is formed based on the risk contribution of each logical interleaving segment and the latency increment of the depth level to satisfy the end-to-end target residual bit error rate and the upper limit of total cache latency. Specifically, the predicted residual bit error rate corresponding to each candidate depth is summed, and any result exceeding one is restricted to one, forming an upper bound on the end-to-end residual bit error rate that does not depend on the inter-segment independence assumption: Where S is the number of logical interleaving segments. The interlacing depth setting for segment 's'. The predicted residual bit error rate is given by the candidate depth performance table. The upper bound for the end-to-end residual bit error rate is given, where all values ​​are dimensionless probabilities. The total buffer latency is... The unit is nanoseconds; summation is only performed on valid logically interleaved segments; when s=0, coordination is not initiated and the topology anomaly flag is set. Empty segment sets are physically excluded by boundary validity checks; if any entry is missing, the corresponding segment is set to the highest depth level and the missing entry flag is set.

[0030] when When the residual bit error rate is higher than the end-to-end target bit error rate, the controller calculates the enhancement gain for each segment that still has higher bit levels: in, For segment s, which is the adjacent gear that is higher than the current gear, This is the buffer latency, in nanoseconds. The unit is the decrease in bit error rate per nanosecond. When the candidate depth performance table is built, the cache latency of adjacent high-order bits is forced to increase strictly, thus keeping the denominator positive; when the measured latency increment is equal to or less than zero, division is not performed, and the pair of entries is marked as having latency monotonicity anomalies and transferred to the recalibration queue; risk is poor. If the value is less than zero, division is not performed; the paired entries are marked as risky monotonicity anomalies and moved to the recalibration queue; if any entry is not finite, the segment depth is frozen and the entry anomaly flag is set. Each selection... The largest segment increases in depth by one level, update. and This process continues until reliability meets standards, latency reaches its limit, or no further segments can be added. When there are equal maximum values, the segment with the higher temperature representative value is selected first; if the temperature representative values ​​are still equal, the upstream segment along the data transmission direction is selected to ensure a unique selection. It is still higher than the end-to-end target residual bit error rate, and the next candidate deepening will make... If the total cache latency limit is exceeded, or if there are no valid segments that can be deepened, no set of coordination depths that can be committed is formed, the current depth is maintained, and a no-feasibility-configuration flag is output; if all logical interleaving segments are at the highest depth level, a link degradation flag is output separately.

[0031] Compare the coordination depth set with the current interleaving depth, form a target depth set according to the allowable fluctuation band and single-cycle adjustment range, bind the logical interleaving segment set, the target depth set and the applicable frame range as a new configuration epoch and preload them into the spare parameter buffer; Specifically, the allowable fluctuation range can be set to zero to one depth level, and the single-cycle adjustment range can be set to one to two depth levels. The controller converts both the coordination depth and the current interleaving depth into a level index, and forms the next cycle level using the following formula: in, This is the index for the current gear. To coordinate the gear index, h represents the number of gears allowed for fluctuation bands. Here, K represents the maximum gear change in a single cycle, K is the set of hardware-allowed gear indices, and 1 represents an indicator that takes one if the condition is true and zero if the condition is false. The unclamped results are restricted to the range between the minimum and maximum indices of set K. Therefore, the target gear remains unchanged when the gear difference does not exceed the allowable fluctuation range, and changes by a maximum of [missing information] when it does. The controller sets the gears and performs outer hardware clamping at the highest and lowest gears. The controller also saves the results before the outer clamping and the clamping flags.

[0032] The new configuration epoch must include at least an incrementing epoch number, a logical interleaving segment boundary table, a target depth set, a node role table, an applicable first frame sequence number, parameter checksums, and a timeout period. The controller first writes to the backup parameter buffer, without modifying the active parameter buffer; the frame boundary commit phase is only allowed after all participating nodes return the same checksum.

[0033] After the parameters are confirmed to be consistent, a new configuration epoch is submitted at the frame boundary of the applicable first frame, and the old configuration epoch is retained until the corresponding in-transit frame count is cleared to zero. Specifically, the sending side writes a new epoch number to the applicable first frame and subsequent frames; nodes along the route select either the active parameter buffer or the backup parameter buffer based on the frame header epoch number. Old frames that have entered the link before the applicable first frame continue to use the old epoch deinterleaving rules. Frame sequence numbers use a fixed-width unsigned counter, and the valid condition for comparison is that the difference in magnitude between two sequence numbers falls within half of the counting space; when the difference in magnitude is exactly equal to half of the counting space, it is judged as a sequence number conflict and the old epoch is retained. When each old frame leaves the endpoint of the last old epoch segment, the count of frames in transit in the old epoch is decremented. Only after the count is cleared and all endpoints return and confirm emptying is confirmed, does the controller reclaim the old parameters. In case of parameter inconsistency, confirmation timeout, or frame sequence number conflict, all participating nodes retain the old active parameters, clear uncommitted epochs, and record the reason for failure for re-initiation in the next control cycle.

[0034] Obtain the actual residual bit error rate of each logical interleaving segment, correct the candidate depth performance table based on the deviation between the actual residual bit error rate and the predicted residual bit error rate, and use the correction result to determine the segment-level depth lower bound in the next control cycle. Specifically, let the number of erroneous bits in segment S after error correction within window n be . The number of bits received is The actual residual bit error rate is Only in Division is performed during the interval; no observation is generated and updates are prohibited when the number of received bits is zero. Table entries are updated only when the statistical window is complete, the corresponding epochs are consistent, and the number of received bits reaches the update lower limit. A limiting index correction is applied to predicted values ​​matching the same temperature range, run range, and depth level. in, To correct the residual bit error rate before prediction, This represents the actual residual bit error rate for the current full window. is a dimensionless correction coefficient between 0.01 and 0.2, and b is the model correction band determined by the upper limit of the predicted residual from repeated factory tests. Let be the number of currently valid feedback samples for segment s within window n. To ensure that the statistical resolution of the bit error rate is not lower than the lower sample limit required for the model correction band, and These are the lower and upper monotonic bounds for the corresponding entries. The lower monotonic bound is the larger of the value between an entry at a higher depth level in the same temperature range and an entry at the same depth in the next lower temperature range; if neither is available, it is zero. The upper monotonic bound is the smaller of the value between an entry at a lower depth level in the same temperature range and an entry at the same depth in the next higher temperature range; if neither is available, it is one. If the obtained lower bound is higher than the upper bound, the update is stopped and the adjacent entries are sent to the recalibration queue. Correction is only performed when the deviation exceeds the model correction band and the sample size reaches the lower limit; otherwise, the old predicted value is retained. Before each update, the unclamped value is calculated and the input is verified to be between zero and one; abnormal input invalidates the update. The corrected entry replaces the original entry and is used in the next control cycle for segment-level depth lower bound and end-to-end coordination calculation.

[0035] Furthermore, a reliable temperature sequence and an error run length sequence are formed, including: Based on the sampling time carried by the temperature sample and the propagation period corresponding to the smallest link unit, the time window for each frame to pass through each sampling position is determined, and the temperature sample falling into the time window is matched with the error position data of the same frame. Temperature confidence is determined based on the valid identifier, range identifier and spatial residual of temperature samples and adjacent temperature samples. Temperature samples are then screened and sorted according to their confidence to form a reliable temperature sequence. The number of consecutive error locations within the same logical interleaving segment is recorded sequentially to form an error run length sequence.

[0036] In one specific embodiment, the starting point of the time window is determined by the unified clock count of the frame entering the physical link plus the pipeline cycle required to reach the target relay node, and the ending point is the starting point plus the hold cycle of that node. Repeated temperature samples retain the one with the best quality flag; when samples are out of order, they are reordered according to the sampling time; if there are no temperature samples in the target time window, a missing sample is marked and not filled with data from future windows. Error runs that cross frame boundaries terminate at the end of the frame to prevent the merging of errors from different interleaved transactions.

[0037] Furthermore, the set of logically interleaved segments is updated based on the temperature difference between adjacent reliable temperatures, the boundary establishment threshold, the boundary cancellation threshold, and the boundary dwell state, including: For configurable link relay nodes that have not yet been designated as boundaries, boundaries are established when the temperature difference between adjacent trusted temperatures reaches the boundary establishment threshold and the establishment dwell period is continuously met. For the configurable link relay node that currently serves as the boundary, the boundary is revoked when the temperature difference between adjacent trusted temperatures drops to the boundary revocation threshold, the revocation dwell period is continuously met, and the boundary retention time reaches the shortest retention period. Divide the continuous minimum link units according to the updated boundaries, and delete logical interleaving segments whose length does not reach the link length corresponding to an interleaving block.

[0038] In one specific embodiment, the threshold is determined based on the lower edge of the temperature difference when the bit error rate reaches a stable transition during the factory heating test, and the cancellation threshold is determined based on the upper edge of the temperature difference when the bit error rate recovers to stability during the cooling test. If the distance between the two is less than twice the temperature measurement repeatability error, the hysteresis distance is increased. The shortest hold period is not less than the control period required for the preloading, committing, and old frame emptying of a single configuration transaction, to prevent the boundary from migrating again before the old epoch is reclaimed.

[0039] Furthermore, based on the temperature representative value and the target quantile length of the error run of each logical interleaving segment, the predicted residual bit error rate and buffer latency for each depth level are obtained from the candidate depth performance table. The lower bound of the segment-level depth is determined under the condition that the single codeword error clustering is within the error correction capability range, including: A candidate depth performance table is established based on the temperature range, error run length range and interleaving depth level in the factory calibration data, so that each table entry carries the corresponding predicted residual bit error rate and buffer latency. Temperature samples within the same logical interleaving segment are weighted according to the confidence level of each temperature sample to form a representative temperature value. The error run length sequence is sorted by length, and the target quantile length of the error run is obtained based on the quantile level determined by the end-to-end target residual bit error rate. By matching the temperature range and the error run length range in the candidate depth performance table with the representative temperature value and the target quantile length of the error run, segment-level candidate entries are formed according to the interlacing depth level. Starting from the lowest interleaving depth level, the predicted residual bit error rate and buffer latency corresponding to each segment-level candidate entry are obtained sequentially. The first interleaving depth level that makes the single codeword error clustering after error runs dispersed within the error correction capability range is determined, and this interleaving depth level is taken as the lower bound of the segment-level depth.

[0040] In one specific embodiment, the candidate depth performance table is stored in on-chip static random access memory. Its header includes a version number, error correction code identifier, temperature range boundaries, run interval boundaries, and depth level index. Entries with a temperature value equal to the upper boundary of an interval are assigned to the adjacent higher temperature range, and entries with a run length equal to the upper boundary of an interval are assigned to the adjacent longer run interval, thus employing more protective entries. When the number of entries falls below the update lower limit, the factory default value is retained, and online sample overwriting is prohibited.

[0041] Furthermore, starting from the lower bound of the segment-level depth, based on the risk contribution of each logically interleaved segment and the latency increment of the depth level, a coordinated depth set is formed that satisfies the end-to-end target residual bit error rate and the upper limit of total buffer latency, including: Each logical interleaving segment is set as the lower bound of the corresponding segment-level depth, and the upper bound of the full-link residual bit error rate is formed according to the predicted residual bit error rate of each logical interleaving segment. When the upper bound of the end-to-end residual bit error rate exceeds the target residual bit error rate, the risk reduction and delay increment caused by adding a depth level to each logical interleaving segment are determined respectively. The logical interleaving segment with the largest ratio of risk reduction to delay increment is selected to add a depth level, and the upper bound of the end-to-end residual bit error rate is updated. Repeat the selection until the upper bound of the end-to-end residual bit error rate reaches the target residual bit error rate, and the sum of the buffer latency of all logical interleaving segments is within the upper limit of the total buffer latency.

[0042] In one specific embodiment, the end-to-end target residual bit error rate can be given by the NoC link service level register, for example, set to the order of ten to the power of negative twelve per bit in high-reliability services; the total buffer latency limit is jointly determined by the router credit return cycle and the service latency budget. Each deepening only changes one level of a segment, so the number of loops is at most equal to the sum of the number of available deepening levels for each segment. At the end of the loop, the achievement flag, the final risk upper bound, and the total buffer latency are output simultaneously and written to the configuration transaction log.

[0043] Furthermore, after forming a coordinated depth set, the depth level difference between adjacent logical interleaving segments is compared; when the depth level difference exceeds the upper limit of the adjacent segment level difference, the logical interleaving segment with the smaller depth level is promoted, and the upper limit of the residual bit error rate of the entire link and the total buffer latency are re-verified; when all logical interleaving segments reach the highest depth level but still fail to reach the end-to-end target residual bit error rate, the highest depth level is maintained and a link degradation flag is output.

[0044] In one specific embodiment, the upper limit of the adjacent segment gap can be set to one or two levels, which limits the buffer occupancy and frame phase difference of adjacent segments. If upgrading a shallower segment causes the total buffer latency to exceed the upper limit, the coordination depth set is not submitted, the current configuration is maintained, and a "no feasible configuration" state is output. After receiving the link degradation flag, the NoC router can reduce the routing priority of the link; this linkage does not change the protection depth already determined by this method.

[0045] Furthermore, by comparing the coordinated depth set with the current interleaving depth, a target depth set is formed according to the allowable fluctuation range and single-cycle adjustment amplitude, including: Determine the gear difference between the coordination depth and the current interlacing depth; When the gear difference is within the allowable fluctuation range, the current interlacing depth is written into the target depth set; When the difference between the gears exceeds the allowable fluctuation range, the depth gear is changed along the direction corresponding to the coordinated depth by no more than the adjustment range of a single cycle, and the changed depth gear is written into the target depth set.

[0046] In one specific embodiment, the fluctuation band is allowed to be determined based on the maximum round-trip fluctuation of the coordinated depth level under a stable thermal state, and the single-cycle adjustment range is determined based on the spare buffer capacity and acceptable latency variation. The reduction operation also requires that the actual residual bit error rate be lower than the risk budget allocated to that segment for multiple consecutive full windows; if this condition is not met, only maintaining or increasing the depth is permitted.

[0047] Furthermore, the new configuration epoch is also bound to the node identifiers and parameter verification values ​​at both ends of the logical interleaving segment; each configurable link relay node writes the new configuration epoch into the spare parameter buffer and returns the parameter verification value. When all return values ​​are consistent, the new configuration epoch is submitted; in-transit frames whose applicable frame range belongs to the old configuration epoch continue to call the old parameter buffer, and frames whose applicable frame range belongs to the new configuration epoch call the spare parameter buffer; when any of the following states occurs, such as parameter verification inconsistency, submission confirmation timeout, or frame sequence number conflict, the unsubmitted new configuration epoch is cleared and the old configuration epoch is maintained.

[0048] In one specific embodiment, the parameter checksum covers the epoch number, boundary node identifier, depth level, interleaving address seed, and applicable first frame sequence number. The commit confirmation timeout value is not shorter than the worst round-trip time of the control message. If an confirmation message is lost midway, the sender does not send the applicable first frame, and the receiver does not exchange active buffer pointers, thereby ensuring that both parties still use the old epoch.

[0049] Furthermore, when any of the following states occur: temperature sample missing, temperature sample exceeding range, data overflow at erroneous location, or temperature sample and erroneous location data not corresponding to frame number, the boundary of the affected location is frozen and the interleaving depth of the corresponding logical interleaving segment is prohibited from being reduced; the boundary freezing is lifted after obtaining a reliable temperature sequence and erroneous run length sequence that reach the number of recovery windows consecutively; when the deviation between the actual residual bit error rate and the predicted residual bit error rate exceeds the model correction band and the number of effective samples reaches the update lower limit, the single correction amplitude is limited and the corresponding entry in the candidate depth performance table is replaced.

[0050] In one specific embodiment, data anomalies are handled according to priority: epoch conflicts take precedence over bit error count overflow, and bit error count overflow takes precedence over temperature sample loss. Anomaly windows are not included in model correction. The number of recovery windows can be three to thirty-two control windows; increasing this number reduces the probability of false recovery but prolongs the recovery time. The model correction band is determined by the confidence range of the predicted residuals from repeated factory tests, and the correction magnitude is limited by the monotonic relationship between adjacent temperature ranges and adjacent depth levels.

[0051] The following four sets of data are used to verify the complete data chain from perception, segmentation, depth determination, coordination, gradual adjustment, epoch switching and feedback correction. The values ​​are example values ​​selected for ease of recalculation and do not constitute a limitation on the scope of protection.

[0052] The first group represents a normal scenario. Let the two reliable temperature samples in segment 1 be 70℃ and 72℃, with confidence levels of 1% and 1 / 2 respectively. The confidence weight sum is 1.5, and the segment-level temperature representative value is... ℃. When the temperatures of adjacent nodes are 70 ℃ and 76 ℃, the temperature difference is 6 ℃; when the establishment threshold is 5 ℃ and the establishment dwell count reaches the requirement, the boundary is established, thus obtaining three logical interleaving segments. The 99th item of the 100 ascending error run samples in segment 1 is 9 bits and p=0.99, therefore Bit; for depth set and The single-codeword clustering degrees corresponding to depths of 2, 4, and 8 are 5, 3, and 2 bits respectively, therefore the lower bound of segment 1's depth is 8. Let the predicted risks of the three segments at their respective lower bounds be... , and The cache latency is 10 ns, 10 ns, and 10 ns respectively, then initially... The total delay is 30 ns. The end-to-end target is... The total latency limit is 40 ns; the risk decreases when segment 1's depth is increased from 8 to 16. The delay increased to 14 ns, therefore the And the returns are higher than the other two segments. The results after backcalculation of segment 1 are... The total delay is 34 ns, both of which meet the target, and the coordination iteration terminates. Let the current depth index of segment 1 be 2, the coordination index be 3, and h=0. , If the parameters of the new epoch are consistent and the frame sequence number difference is within half the space, then the old epoch is committed at the first frame boundary and reclaimed after the old frame is emptied. After the commit, the old predicted value of the corresponding entry in segment 1 is... The observation value of the complete feedback window of the same era is , , , Monotonic intervals are Therefore, the value not clamped and updated is Located within the monotonic interval, it is written back to the 16th entry of the depth table to form the input for the next control cycle.

[0053] The second group represents zero or minimum value scenarios. Assume a link retains only one fully reliable temperature sample of 60°C. The weights sum to the lower limit, and the segment temperature is 60 ℃; all comparable adjacent temperatures are 60 ℃, therefore... The threshold for establishing the fault was not reached, the boundary state remained zero, and a single logical interleaving segment was formed. The faulty run had only one 1-bit sample. , ,at this time It does not perform online quantile calculation, but instead uses the values ​​given in the factory-issued table entries. Position; to and A depth of 1 corresponds to a clustering degree of 1, and the lower bound of the segment-level depth is 1. The prediction risk for this single segment is zero, and the cache latency is 1 ns. The total latency is 1 ns, eliminating the need for revenue division. The current index and coordination index are both zero, h=0, and the next index remains zero. The target configuration is identical to the activity configuration; the controller does not create a new epoch and continues to use the activity parameters. Feedback window observations are zero, predictions are zero, bias is zero and does not exceed b, and entries remain zero. The final output of this chain is a single segment, depth 1, with no reconfiguration and unchanged prediction entries.

[0054] The third group represents extreme scenarios. Assume adjacent reliable temperatures are 100℃ and 115℃, with a temperature difference of 15℃ continuously reaching the conditions for establishing a dwell point, thus establishing a hotspot boundary; the target quantile length of the erroneous run for the corresponding hotspot segment is... Position. To and The clustering degrees of the three levels are 50, 25, and 13 bits respectively, satisfying the condition that the set is empty. Therefore, the minimum value of the empty set is not calculated. Instead, the hotspot segment is set to the maximum protection depth of 8, an insufficient output capability flag is displayed, and depth reduction is prohibited. Assuming that the sum of predicted risks for each segment at the maximum protection depth is still 1.4, the total delay is 38 ns, and the delay upper limit is 40 ns, then the clamp is 1. Since there are no segments that can be deepened, the coordination result is that the reliability does not meet the standard, all maximum depths are maintained, and a link degradation flag is output. Hardware depth 8 corresponds to index 4, and both the current index and the coordination output index are 4; h=0, , F06 output index 4, thus maintaining the highest depth continuously. The controller attempts to bind the insufficient capacity and link degradation flags to the new epoch, but the modulus difference between the applicable first frame number and the current baseline number in the frame number space M=256 is 128, so it is judged as a half-space conflict, uncommitted epochs are cleared and the old activity parameters are maintained; the old activity parameters themselves are already depth 8. Subsequently, only the old epoch full feedback window is used, with old prediction risk set at 0.8, observation risk at 0.9, b=0.01, and sample size meeting the target. The monotonic interval is [0.7, 0.85], the unclamped value is 0.81, and the write-back value is 0.81. The final output of this chain is depth 8, insufficient capacity and link degradation, epoch rollback, and the old epoch table entry updated to 0.81. The independent adverse recalculation of the outer hardware out-of-bounds clamping is shown in the F06 access control record. The out-of-bounds diagnostic quantity is not mixed with the coordinated output of this scenario.

[0055] The fourth group represents a data anomaly scenario. Assume that the valid flag for all temperature samples in a given segment is zero, such that... If the sum of the trusted weights is zero, then temperature division is not performed; the most recent trusted temperature of 75°C is used; the affected boundary is frozen and depth reduction is prohibited; the logical interleaving segment set retains the two segments from the previous cycle. Furthermore, due to an overflow in the error location buffer, the number of valid online runs is reduced. Therefore, quantile calculation is not performed; instead, the two lower depth bounds of 8 and 4 given in the factory entry are adopted. The current predicted risks given in the factory entry are respectively... and The current cache latency is 12 ns and 8 ns respectively, therefore The total delay is 20 ns; the end-to-end target is... If the total latency limit is 40 ns, then the risk has not yet met the standard. In the candidate table, the latency of segment 1 remains 12 ns when the depth increases from 8 to 16, and the predicted risk increases from 4 to 8 when the depth of segment 2 increases. Rise to Therefore, segment 1 is not calculated because the delay difference is zero, and segment 2 is not calculated because the risk difference is negative. Two pairs of entries are added to the recalibration queue. The risk is then output. The following conditions are met: a 20 ns delay, no valid depth increase candidates, maintaining the current depths 8 and 4 with a no-feasibility configuration flag; the asymptotic grading input equals the current index, and no new epoch is created. Since the observations in the feedback window are non-finite and the epochs are inconsistent, F07 is not executed, and two old entries are retained. The final output of this chain is: boundary frozen, depth reduction prohibited, risk not met but no valid candidates, depths 8 and 4 maintained, no new epoch, old entries maintained. The freeze is only lifted after a continuous stream of valid data reaching the recovery window size.

[0056] The above content is merely an example and illustration of the concept of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described or use similar methods to replace them, as long as they do not deviate from the concept of the invention, they should all fall within the protection scope of the present invention.

[0057] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0058] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention.

Claims

1. A segmented interleaving error correction method for multi-core NoC interposer layers, characterized in that, include: Configurable link relay nodes are set along the physical links between core particles. Temperature samples, error location data, current interleaving depth, frame number and in-transit frame count are obtained for each node. A reliable temperature sequence and an error run length sequence are formed according to the link position and frame number. The logical interleaving segment set is updated based on the temperature difference between adjacent reliable temperatures, the boundary establishment threshold, the boundary cancellation threshold, and the boundary dwell status, and error correction encoding / decoding and cross-weaving functions are enabled at both ends of each logical interleaving segment. Based on the temperature representative value of each logical interleaving segment and the target quantile length of the error run, the predicted residual bit error rate and buffer latency of each depth level are obtained from the candidate depth performance table. The lower bound of the segment-level depth is determined with the condition that the single codeword error clustering degree is within the error correction capability range. Starting from the lower bound of the segment-level depth, a coordinated depth set is formed based on the risk contribution of each logical interleaving segment and the latency increment of the depth level to satisfy the end-to-end target residual bit error rate and the upper limit of total cache latency. Compare the coordination depth set with the current interleaving depth, form a target depth set according to the allowable fluctuation band and single-cycle adjustment range, bind the logical interleaving segment set, the target depth set and the applicable frame range as a new configuration epoch and preload them into the spare parameter buffer; After the parameters are confirmed to be consistent, a new configuration epoch is submitted at the frame boundary of the applicable first frame, and the old configuration epoch is retained until the corresponding in-transit frame count is cleared to zero. Obtain the actual residual bit error rate of each logical interleaving segment, correct the candidate depth performance table based on the deviation between the actual residual bit error rate and the predicted residual bit error rate, and use the corrected result to determine the lower bound of the segment-level depth in the next control cycle.

2. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 1, characterized in that, Forming a reliable temperature sequence and an error run length sequence includes: Based on the sampling time carried by the temperature sample and the propagation period corresponding to the smallest link unit, the time window for each frame to pass through each sampling position is determined, and the temperature sample falling into the time window is matched with the error position data of the same frame. Temperature confidence is determined based on the valid identifier, range identifier and spatial residual of temperature samples and adjacent temperature samples. Temperature samples are then screened and sorted according to their confidence to form a reliable temperature sequence. The number of consecutive error locations within the same logical interleaving segment is recorded sequentially to form an error run length sequence.

3. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 2, characterized in that, The set of logically interleaved segments is updated based on the temperature difference between adjacent reliable temperatures, the boundary establishment threshold, the boundary cancellation threshold, and the boundary dwell state, including: For configurable link relay nodes that have not yet been designated as boundaries, boundaries are established when the temperature difference between adjacent trusted temperatures reaches the boundary establishment threshold and the establishment dwell period is continuously met. For the configurable link relay node that currently serves as the boundary, the boundary is revoked when the temperature difference between adjacent trusted temperatures drops to the boundary revocation threshold, the revocation dwell period is continuously met, and the boundary retention time reaches the shortest retention period. Divide the continuous minimum link units according to the updated boundaries, and delete logical interleaving segments whose length does not reach the link length corresponding to an interleaving block.

4. The segmented interleaving error correction method for multi-core NoC intermediary layers according to claim 1, characterized in that, Based on the temperature representative value of each logical interleaving segment and the target quantile length of the error run, the predicted residual bit error rate and buffer latency for each depth level are obtained from the candidate depth performance table. The lower bound of the segment-level depth is determined under the condition that the single codeword error clustering is within the error correction capability range, including: A candidate depth performance table is established based on the temperature range, error run length range and interleaving depth level in the factory calibration data, so that each table entry carries the corresponding predicted residual bit error rate and buffer latency. Temperature samples within the same logical interleaving segment are weighted according to the confidence level of each temperature sample to form a representative temperature value. The error run length sequence is sorted by length, and the target quantile length of the error run is obtained based on the quantile level determined by the end-to-end target residual bit error rate. By matching the temperature range and the error run length range in the candidate depth performance table with the representative temperature value and the target quantile length of the error run, segment-level candidate entries are formed according to the interlacing depth level. Starting from the lowest interleaving depth level, the predicted residual bit error rate and buffer latency corresponding to each segment-level candidate entry are obtained sequentially. The first interleaving depth level that makes the single codeword error clustering after error runs dispersed within the error correction capability range is determined, and this interleaving depth level is taken as the lower bound of the segment-level depth.

5. The segmented interleaving error correction method for multi-core NoC intermediary layers according to claim 4, characterized in that, Starting from the lower bound of the segment-level depth, based on the risk contribution of each logically interleaved segment and the latency increment of the depth level, a coordinated depth set is formed that satisfies the end-to-end target residual bit error rate and the upper limit of total buffer latency, including: Each logical interleaving segment is set as the lower bound of the corresponding segment-level depth, and the upper bound of the full-link residual bit error rate is formed according to the predicted residual bit error rate of each logical interleaving segment. When the upper bound of the end-to-end residual bit error rate exceeds the target residual bit error rate, the risk reduction and delay increment caused by adding a depth level to each logical interleaving segment are determined respectively. The logical interleaving segment with the largest ratio of risk reduction to delay increment is selected to add a depth level, and the upper bound of the end-to-end residual bit error rate is updated. Repeat the selection until the upper bound of the end-to-end residual bit error rate reaches the target residual bit error rate, and the sum of the buffer latency of all logical interleaving segments is within the upper limit of the total buffer latency.

6. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 5, characterized in that, After forming a coordinated depth set, compare the depth level difference between adjacent logical interleaving segments; when the depth level difference exceeds the upper limit of the adjacent segment level difference, increase the logical interleaving segment with the smaller depth level, and re-verify the upper limit of the residual bit error rate of the entire link and the total buffer latency; when all logical interleaving segments reach the highest depth level but still fail to reach the end-to-end target residual bit error rate, maintain the highest depth level and output the link degradation flag.

7. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 6, characterized in that, Compare the coordinated depth set with the current interleaving depth, and form a target depth set according to the allowable fluctuation range and single-cycle adjustment amplitude, including: Determine the gear difference between the coordination depth and the current interlacing depth; When the gear difference is within the allowable fluctuation range, the current interlacing depth is written into the target depth set; When the difference between the gears exceeds the allowable fluctuation range, the depth gear is changed along the direction corresponding to the coordinated depth by no more than the adjustment range of a single cycle, and the changed depth gear is written into the target depth set.

8. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 7, characterized in that, The new configuration epoch also binds the node identifiers and parameter verification values ​​at both ends of the logical interleaving segment; each configurable link relay node writes the new configuration epoch into the spare parameter buffer and returns the parameter verification value. When all return values ​​are consistent, the new configuration epoch is submitted; in-transit frames whose applicable frame range belongs to the old configuration epoch continue to call the old parameter buffer, and frames whose applicable frame range belongs to the new configuration epoch call the spare parameter buffer; when any of the following states occurs, such as parameter verification inconsistency, submission confirmation timeout, or frame sequence number conflict, the unsubmitted new configuration epoch is cleared and the old configuration epoch is maintained.

9. The segmented interleaving error correction method for multi-core NoC interposer layers according to claim 8, characterized in that, When any of the following states occur: temperature sample missing, temperature sample exceeding range, data overflow at erroneous location, or temperature sample and erroneous location data not corresponding to frame number, the boundary of the affected location is frozen and the interleaving depth of the corresponding logical interleaving segment is prohibited from being reduced; the boundary is unfrozen after obtaining a reliable temperature sequence and erroneous run length sequence that reach the number of recovery windows consecutively; when the deviation between the actual residual bit error rate and the predicted residual bit error rate exceeds the model correction band and the number of effective samples reaches the update lower limit, the single correction amplitude is limited and the corresponding entry in the candidate depth performance table is replaced.

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